Fault analysis method, fault analysis device, storage medium and electronic equipment

Abstract

The invention provides a fault analysis method, a fault analysis device, a storage medium and electronic equipment, and relates to the technical field of semiconductors. The fault analysis method comprises the following steps: determining the number of fault points on each fault line in a fault area of the memory to obtain a number range, and determining a division parameter value of the fault area from a data range; dividing the fault area into at least two fault groups by using the division parameter values; and respectively matching fault solutions for each fault group. According to the invention, the time consumption of fault analysis can be reduced on the premise of ensuring the fault recovery rate.

Description

Background Art

[0002] In the field of semiconductor technology, research on redundancy analysis (RA) algorithms for memory repair has a long history. Redundancy analysis algorithms can better solve fault problems existing in memories.

[0003] At present, under the premise of ensuring the fault repair rate, there is a problem of long analysis time.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to provide a fault analysis method, a fault analysis device, a storage medium and an electronic device, thereby overcoming the problem that fault analysis takes a long time at least to a certain extent.

[0006] According to a first aspect of the present disclosure, a fault analysis method is provided, including: determining the number of fault points on each fault line in a fault area of ​​a memory to obtain a number range, and determining a partition parameter value of the fault area from the data range; dividing the fault area into at least two fault groups using the partition parameter value; and matching a fault solution to each fault group respectively.

[0007] Optionally, the fault line includes column fault lines extending in the column direction of the fault area; wherein, using the division parameter value to divide the fault area into at least two fault groups includes: comparing the number of fault points of each column fault line in the fault area with the division parameter value; determining the area corresponding to the column fault lines whose number of fault points in the fault area is greater than or equal to the division parameter value as the first fault group; determining a first target area composed of column fault lines whose number of fault points in the fault area is less than the division parameter value, and determining at least a second fault group based on the first target area.

[0008] Optionally, determining at least a second fault group based on the first target area includes: determining a fault distribution sub-area within the first target area; comparing the size of the fault distribution sub-area with the size of a predetermined area in the solution library; if the size of the fault distribution sub-area is less than or equal to the size of the predetermined area in the solution library, determining the fault distribution sub-area as the second fault group; if the size of the fault distribution sub-area is larger than the size of the predetermined area in the solution library, taking the fault distribution sub-area as the fault area to determine at least a second fault group from the fault distribution sub-area.

[0009] Optionally, the fault line includes a row fault line extending in the row direction of the fault area; wherein, using the division parameter value to divide the fault area into at least two fault groups includes: comparing the number of fault points of each row fault line in the fault area with the division parameter value; determining the area corresponding to the row fault points in the fault area where the number of fault points is greater than or equal to the division parameter value as the third fault group; determining a second target area consisting of row fault lines in the fault area where the number of fault points is less than the division parameter value, and determining at least a fourth fault group based on the second target area.

[0010] Optionally, determining at least the fourth fault group based on the second target area includes: determining a fault distribution sub-area within the second target area; comparing the size of the fault distribution sub-area with the size of a predetermined area in the solution library; if the size of the fault distribution sub-area is less than or equal to the size of the predetermined area in the solution library, determining the fault distribution sub-area as the fourth fault group; if the size of the fault distribution sub-area is larger than the size of the predetermined area in the solution library, taking the fault distribution sub-area as the fault area to determine at least the fourth fault group from the fault distribution sub-area.

[0011] Optionally, matching a fault solution to each fault group includes: determining at least one fault solution corresponding to the fault group according to a distribution state of fault points in the fault group; wherein the fault solution includes the number of spare rows and the number of spare columns.

[0012] Optionally, the fault analysis method further includes: merging the fault solutions of the fault groups to determine a fault solution for the fault area of ​​the memory.

[0013] According to a second aspect of the present disclosure, a fault analysis device is provided, including: a parameter value determination module, used to determine the number of fault points on each fault line in a fault area of ​​a memory to obtain a number range, and determine a partition parameter value of the fault area from the data range; a fault group partition module, used to divide the fault area into at least two fault groups using the partition parameter value; and a solution matching module, used to match a fault solution to each fault group respectively.

[0014] Optionally, the fault line includes a column fault line extending in the column direction of the fault area. In this case, the fault group division module is configured to perform: comparing the number of fault points of each column fault line in the fault area with the division parameter value; determining the area corresponding to the column fault line whose number of fault points in the fault area is greater than or equal to the division parameter value as the first fault group; determining a first target area consisting of column fault lines whose number of fault points in the fault area is less than the division parameter value, and determining at least a second fault group based on the first target area.

[0015] Optionally, the fault group division module is also configured to perform: determining a fault distribution sub-area within the first target area; comparing the size of the fault distribution sub-area with the size of a predetermined area in the solution library; if the size of the fault distribution sub-area is less than or equal to the size of the predetermined area in the solution library, determining the fault distribution sub-area as a second fault group; if the size of the fault distribution sub-area is larger than the size of the predetermined area in the solution library, using the fault distribution sub-area as a fault area to determine at least a second fault group from the fault distribution sub-area.

[0016] Optionally, the fault line includes a row fault line extending in the row direction of the fault area. In this case, the fault group division module is configured to perform: comparing the number of fault points of each row fault line in the fault area with the division parameter value; determining the area corresponding to the row fault points in the fault area where the number of fault points is greater than or equal to the division parameter value as the third fault group; determining a second target area consisting of row fault lines in the fault area where the number of fault points is less than the division parameter value, and determining at least a fourth fault group based on the second target area.

[0017] Optionally, the fault group division module is also configured to perform: determining a fault distribution sub-area within the second target area; comparing the size of the fault distribution sub-area with the size of a predetermined area in the solution library; if the size of the fault distribution sub-area is less than or equal to the size of the predetermined area in the solution library, determining the fault distribution sub-area as a fourth fault group; if the size of the fault distribution sub-area is larger than the size of the predetermined area in the solution library, using the fault distribution sub-area as a fault area to determine at least a fourth fault group from the fault distribution sub-area.

[0018] Optionally, the solution matching module is configured to execute: determining at least one fault solution corresponding to the fault group according to the distribution state of the fault points in the fault group; wherein the fault solution includes the number of spare rows and the number of spare columns.

[0019] Optionally, the solution matching module is further configured to execute: merging the fault solutions of each fault group to determine a fault solution for the fault area of ​​the memory.

[0020] According to a third aspect of the present disclosure, a storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any of the above-mentioned fault analysis methods is implemented.

[0021] According to a fourth aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; the processor is configured to implement any of the above-mentioned fault analysis methods by executing the executable instructions.

[0022] In the technical solutions provided by some embodiments of the present disclosure, the fault area is divided into at least two fault groups, and a fault solution is matched to each fault group. On the one hand, by segmenting the fault area, the processing speed of fault analysis can be improved and the analysis time can be reduced while ensuring the repair rate; on the other hand, the basis for dividing the fault area is the number range of fault points on each fault line in the fault area. The solution is adaptive to the fault area being targeted, and dynamic analysis of different fault areas can be achieved, which helps to ensure the accuracy and efficiency of fault analysis.

[0023] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0025] Figure 1 The flowchart of the fault analysis method according to the exemplary embodiment of the present disclosure is schematically shown.

[0026] Figure 2 A trend chart showing the relationship between the partition parameter value and the repair rate according to an embodiment of the present disclosure is shown.

[0027] Figure 3 A schematic diagram of a column-based partitioning method for a fault area according to an embodiment of the present disclosure is shown.

[0028] Figure 4 A schematic diagram of a row-based division method for a fault area according to an embodiment of the present disclosure is shown.

[0029] Figure 5 A schematic diagram showing simultaneous division by rows and by columns in an embodiment of the present disclosure is shown.

[0030] Figure 6 A schematic diagram of dividing fault groups in the present disclosure using a size of 4×4 as an example is shown.

[0031] Figure 7 Shown with Figure 3 Schematic diagram of the fault solution corresponding to area a.

[0032] Figure 8 Shown with Figure 3 Schematic diagram of the fault solution corresponding to area b.

[0033] Fig. 9 A schematic diagram showing the overall fault solution after partitioning by column.

[0034] Fig.10 Shown with Figure 4 Schematic diagram of the fault solution corresponding to area c.

[0035] Fig.11 Shown with Figure 4 Schematic diagram of the fault solution corresponding to area d.

[0036] Fig.12 A schematic diagram showing the overall fault solution after partitioning by row.

[0037] Fig.13 A schematic diagram showing the overall fault solution after combining the results of column-based partitioning and row-based partitioning.

[0038] Fig.14 A block diagram of a fault analysis device according to an exemplary embodiment of the present disclosure is schematically shown.

[0039] Fig.15 A block diagram of an electronic device according to an exemplary embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0040] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0041] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0042] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the steps. For example, some steps may be decomposed, while some steps may be combined or partially combined, so the actual execution order may change according to the actual situation. In addition, all the terms "first", "second", "third", "fourth", etc. below are only for the purpose of distinction and should not be used as limitations of the present disclosure.

[0043] The goal of redundancy analysis is to achieve a high repair rate to ensure yield, and a high repair speed to reduce testing costs. However, current algorithms have difficulty in achieving a balance between repair rate and analysis time. Redundancy analysis algorithms with high repair rates often have a large time overhead, while redundancy analysis algorithms with fast repair speeds often cannot guarantee repair rates.

[0044] In addition, the existing redundancy analysis algorithm cannot adjust the repair rate and analysis time according to the demand to adapt to different possible application scenarios. In other words, the existing redundancy analysis algorithm cannot dynamically adjust the analysis performance of FBM (Fail Bit Map).

[0045] In order to solve or at least alleviate the above problems to a certain extent, the embodiments of the present disclosure provide a new fault analysis solution.

[0046] The fault analysis scheme can be implemented by an electronic device, that is, the electronic device can perform each step of the fault analysis method of the embodiment of the present disclosure, and the following fault analysis device can be configured in the electronic device. The present disclosure does not limit the type of electronic device, for example, including memory test equipment, servers, personal computers, etc.

[0047] In this fault analysis solution, the fault area is segmented, and further, the fault area can be segmented by recursive segmentation, thereby ensuring a faster analysis speed. On the one hand, for the segmented small-scale fault groups, a fault solution library (Solution Library) can be constructed, thereby not only being able to quickly match the fault solution, but also having a very high normalized repair rate. On the other hand, for the segmented large-scale fault groups, they can be recursively segmented to a size that is consistent with or less than the size corresponding to the solution in the fault solution library. In this case, the fault solution can be directly determined, which guarantees the repair rate to a certain extent and also improves the analysis speed.

[0048] The fault analysis method according to the embodiment of the present disclosure is described below with reference to the accompanying drawings.

[0049] Figure 1 The flowchart of the fault analysis method according to the exemplary embodiment of the present disclosure is schematically shown. Figure 1, the fault analysis method may include the following steps:

[0050] S12. Determine the number of fault points on each fault line in the fault area of ​​the memory to obtain a number range, and determine a partition parameter value of the fault area from the data range.

[0051] In the exemplary embodiment of the present disclosure, the fault area may also be referred to as a fault distribution, and may be an area corresponding to a real fault point. The present disclosure does not limit the size of the fault area, the number of fault points included, the location in the memory, etc. In addition, the fault area may also be an area obtained by preprocessing the area of ​​the real fault point, and the present disclosure does not limit this.

[0052] For the fault region, each column and / or each row is recorded as a fault line. That is, the fault line of the embodiment of the present disclosure may include a column fault line extending in the column direction of the fault region, or may include a row fault line extending in the row direction of the fault region.

[0053] The number of fault points on each fault line in the fault area can be determined, and the number range can be determined from these numbers. The number range is the interval range from the minimum number of fault points to the maximum number of fault points. For example, the fault area includes fault line 1, fault line 2, fault line 3 and fault line 4, and the number of fault points corresponding to them is 2, 3, 1, and 5, respectively, then the determined number range is [1,5].

[0054] The electronic device can determine the partition parameter value of the fault area from the number range. The partition parameter value is usually a positive integer within the data range. The selection method of the partition parameter value is related to the fault repair requirements, that is, the repair rate and / or the analysis time consumption. The present disclosure does not limit the specific value of the partition parameter value.

[0055] Figure 2 The relationship trend diagram between the partition parameter value and the repair rate of the embodiment of the present disclosure is shown. The experiment found that within the above-mentioned numerical range, the partition parameter value affects the repair rate and shows a monotonic change trend. The larger the partition parameter value, the longer the analysis time; the smaller the partition parameter value, the shorter the analysis time. Therefore, the balance between the repair rate and the analysis time can be achieved by controlling the selection of the partition parameter value.

[0056] S14. Divide the fault area into at least two fault groups using the division parameter value.

[0057] After the partition parameter value is determined, the fault area can be divided into multiple fault groups using the partition parameter value.

[0058] According to some embodiments of the present disclosure, the electronic device may divide the fault area into a plurality of fault groups along a column direction.

[0059] Specifically, the electronic device may compare the number of fault points of each column fault line in the fault area with the above-mentioned division parameter value. The electronic device may determine the area corresponding to the column fault line whose number of fault points in the fault area is greater than or equal to the division parameter value as the first fault group. It can be understood that the first fault group is a group with more faults, that is, relative to other fault groups divided under this division mode, the first fault group has more fault points.

[0060] In addition, the electronic device can determine a first target area composed of column fault lines in which the number of fault points in the fault area is less than the partition parameter value, and determine at least a second fault group based on the first target area. The second fault group can be understood as a group with fewer fault points than the first fault group.

[0061] In one embodiment, the electronic device may directly determine the first target area as the second fault group.

[0062] In another embodiment, the electronic device may perform further processing based on the fault distribution in the first target area to at least determine a second fault group.

[0063] First, a fault distribution sub-area may be determined within the first target area. The present disclosure does not limit the number of the determined fault distribution sub-areas, which may be one or more, depending on the actual distribution of the fault points within the first target area. In addition, the size of the determined fault distribution sub-area may be, for example, 2*3, 4*4, 3*5, etc., and the present disclosure does not limit its size either.

[0064] Next, the size of the fault distribution sub-area can be compared with the size of the predetermined area in the solution library. The solution library can also be called a fault solution library (Solution Library), and the solution library is pre-configured with fault solutions for the predetermined area size. For example, the predetermined area can be 4*4. In this case, the solution library is pre-configured with a solution set for the 4*4 fault area, which can include solutions for all possible fault distribution situations in the 4*4 area.

[0065] It should be noted that there may be one or more fault solutions for a predetermined area in the solution library. The above-mentioned size of 4*4 is only an exemplary description of the size of the predetermined area. The size of the predetermined area involved in the solution library may also be 3*3, 5*5, etc., and the present disclosure does not limit this. In some embodiments of the present disclosure, the size of the predetermined area may be the square of n, where n may be a positive integer greater than 1.

[0066] If the size of the fault distribution sub-area is less than or equal to the size of a predetermined area in the solution library, it means that the distribution of fault points in the fault distribution sub-area has a solution in the solution library. In this case, the fault distribution sub-area can be determined as the second fault group, so that the corresponding fault solution in the solution library can be directly used to match the fault distribution sub-area.

[0067] If the size of the fault distribution sub-area is larger than the size of all pre-defined areas in the solution library, it means that the distribution of fault points in the fault distribution sub-area exceeds the pre-configured solution in the solution library. In this case, the fault distribution sub-area can be used as the above-mentioned fault area to determine at least the second fault group from the fault distribution sub-area.

[0068] It can be understood that the operation of using the fault distribution sub-region as the above-mentioned fault region refers to re-executing the process of determining the partition parameter value of step S12 and the process of partitioning the fault group of step S14 with the fault distribution sub-region as the fault region. It can be seen that, except for the first fault group divided, the recursive partitioning process of the embodiment of the present disclosure ends when the size of the fault group is less than or equal to the size of the predetermined area in the solution library. In addition, given that the size of the area targeted by the partitioning operation is constantly decreasing, the corresponding partition parameter value may also change.

[0069] Figure 3 FIG. 1 is a schematic diagram showing a column-based partitioning method for a fault area according to an embodiment of the present disclosure. Figure 3 In the example, a 5*5 fault area is given, where the position with a black dot is the fault point, and the position without a black dot is the non-fault point. Figure 3 For the fault area on the left, the number of fault points in the row direction and the column direction can be counted, and the statistical results are shown in the "Row Direction Statistics" and "Column Direction Statistics" in the figure. Subsequently, when the partition parameter value is determined to be 4, if there is a fault resolution strategy for a predetermined area with a size greater than or equal to 5*3 in the solution library, the fault area can be divided into two fault groups, corresponding to area a and area b, respectively, where area a corresponds to the first fault group mentioned above, and area b corresponds to the second fault group mentioned above.

[0070] According to some other embodiments of the present disclosure, the electronic device may divide the fault area into a plurality of fault groups along a row direction.

[0071] Specifically, the electronic device may compare the number of fault points of each row fault line in the fault area with the above-mentioned division parameter value. The electronic device may determine the area corresponding to the row fault line whose number of fault points in the fault area is greater than or equal to the division parameter value as the third fault group. It can be understood that the third fault group is a group with more faults, that is, relative to other fault groups divided under this division mode, the third fault group has more fault points.

[0072] In addition, the electronic device can determine a second target area composed of row fault lines with a number of fault points less than the partition parameter value in the fault area, and determine at least a fourth fault group based on the second target area. The fourth fault group can be understood as a group with fewer fault points than the third fault group.

[0073] In one embodiment, the electronic device may directly determine the second target area as the fourth fault group.

[0074] In another embodiment, the electronic device may perform further processing based on the size of the fault distribution in the second target area to determine at least a fourth fault group.

[0075] First, a fault distribution sub-area can be determined in the second target area. The present disclosure does not limit the number of the determined fault distribution sub-areas, which can be one or more, depending on the actual distribution of the fault points in the second target area. In addition, the size of the determined fault distribution sub-area can be, for example, 2*3, 4*4, 3*5, etc., and the present disclosure does not limit its size either.

[0076] Next, the size of the fault distribution sub-area can be compared with the size of the predetermined area in the solution library. The solution library has the same concept as the above solution library and will not be described in detail. For example, the predetermined area can be 4*4. In this case, the solution library is pre-configured with a solution set for a 4*4 fault area, which can include solutions for all possible fault distribution situations in the 4*4 area.

[0077] It should be noted that there may be one or more fault solutions for a predetermined area in the solution library. The above-mentioned size of 4*4 is only an exemplary description of the size of the predetermined area. The size of the predetermined area involved in the solution library may also be 3*3, 5*5, etc., and the present disclosure does not limit this. In some embodiments of the present disclosure, the size of the predetermined area may be the square of n, where n may be a positive integer greater than 1.

[0078] If the size of the fault distribution sub-area is less than or equal to the size of a predetermined area in the solution library, it means that the distribution of fault points in the fault distribution sub-area has a solution in the solution library. In this case, the fault distribution sub-area can be determined as the fourth fault group, so that the corresponding fault solution in the solution library can be directly used to match the fault distribution sub-area.

[0079] If the size of the fault distribution sub-area is larger than the size of all the predetermined areas in the solution library, it means that the distribution of the fault points in the fault distribution sub-area exceeds the pre-configured solution in the solution library. In this case, the fault distribution sub-area can be used as the above-mentioned fault area to determine at least the fourth fault group from the fault distribution sub-area.

[0080] It can be understood that the operation of taking the fault distribution sub-area as the above-mentioned fault area refers to re-executing the process of determining the partition parameter value of step S12 and the process of partitioning the fault group of step S14 with the fault distribution sub-area as the fault area. It can be seen that, except for the third fault group divided, the recursive partitioning process of the embodiment of the present disclosure ends when the size of the fault group is less than or equal to the size of the predetermined area in the solution library. In addition, given that the size of the area targeted by the partitioning operation is constantly decreasing, the corresponding partition parameter value may also change.

[0081] Figure 4 FIG. 2 shows a schematic diagram of a row-based division method for a fault area according to an embodiment of the present disclosure. Figure 4 In the example, a 5*5 fault area is given, where the position with a black dot is the fault point, and the position without a black dot is the non-fault point. Figure 4 For the fault area on the left, the number of fault points in the row direction and the column direction can be counted, and the statistical results are shown in the "Row Direction Statistics" and "Column Direction Statistics" in the figure. Subsequently, when the partition parameter value is determined to be 4, if there is a fault resolution strategy for a predetermined area with a size greater than or equal to 3*5 in the solution library, the fault area can be divided into two fault groups, corresponding to area c and area d, respectively, where area d corresponds to the third fault group mentioned above, and area c corresponds to the fourth fault group mentioned above.

[0082] According to some other embodiments of the present disclosure, the electronic device can divide the fault area into multiple fault groups along the column direction and the row direction respectively. That is, the electronic device can execute the above-mentioned division scheme along the column direction and the above-mentioned division scheme along the row direction at the same time, and each fault group obtained can be applied to the following process.

[0083] Figure 5 FIG. 1 is a schematic diagram showing a method of dividing by rows and columns simultaneously in an embodiment of the present disclosure. Figure 5, the electronic device can divide the fault area in the row direction and the column direction respectively, and no matter the result of the row direction division or the column direction division, a group with more faults and a group with fewer faults can be obtained. In addition, as described above, in some embodiments of the present disclosure, for a group with fewer faults and a larger scale of fault points, it can also be used as a fault area and the division operation is repeated. The result of this recursive division is helpful for subsequent matching of fault solutions.

[0084] For the region size corresponding to the solutions in the above solution library, the number of rows or columns can be configured to be no more than 4, such as Figure 6 As shown, the configuration is in the form of 4×4. In fact, in the fault distribution of redundant analysis, such a configuration already includes most of the possible situations, which can achieve a higher repair analysis speed and ensure a higher repair rate. In addition, within the fault group, it is not necessary to ensure the address association relationship between the fault points. In other words, the addresses between the fault points can be associated and be continuous addresses. However, the addresses between the fault points can also have no relationship and be incompletely continuous addresses or completely discontinuous addresses.

[0085] S16. Match a fault solution to each fault group.

[0086] When multiple fault groups are determined, the electronic device can match a fault solution for each fault group, that is, the process of matching a fault solution for each fault group can be understood as an independent process. In an exemplary embodiment of the present disclosure, the fault solution can include the number of spare rows and the number of spare columns.

[0087] According to some embodiments of the present disclosure, the electronic device can determine at least one fault solution corresponding to the fault group according to the distribution state of the fault points in the fault group. It is understandable that for multiple fault solutions for the same fault group, in actual application, only any one of the fault solutions can be used to achieve the effect of fault repair.

[0088] refer to Figure 7 ,against Figure 3 For area a in FIG. 1 , the fault solution may include 4 solutions, namely, 3 spare rows, 2 spare rows and 1 spare column, 1 spare row and 2 spare columns, and 3 spare columns.

[0089] refer to Figure 8 ,against Figure 3 For area b in FIG. 1 , the fault solution can be 2 spare columns.

[0090] You can Figure 7 The results and Figure 8The results of are superimposed to obtain the fault solution that matches the fault groups divided by the columns. Fig. 9 After dividing by columns, the total fault solution includes 4 solutions: 3 spare rows and 2 spare columns, 2 spare rows and 3 spare columns, 1 spare row and 4 spare columns, and 5 spare columns.

[0091] refer to Fig.10 ,against Figure 4 For area c in FIG. 1 , the fault solution may include 4 solutions, namely, 3 spare rows, 2 spare rows and 1 spare column, 1 spare row and 2 spare columns, and 3 spare columns.

[0092] refer to Fig.11 ,against Figure 4 For area d in the example, the failure solution can be 2 spare rows.

[0093] You can Fig.10 The results and Fig.11 The results of are superimposed to obtain the fault solution that matches the fault groups divided by the rows. Fig.12 After dividing by rows, the total fault solution includes 4 solutions: 5 spare rows, 4 spare rows and 1 spare column, 3 spare rows and 2 spare columns, and 2 spare rows and 3 spare columns.

[0094] In addition, the electronic device can combine the results of the column division and the row division to obtain a total fault solution, wherein the combination can be understood as a combination, which only includes combining the results together and does not involve a quantitative superposition operation.

[0095] refer to Fig.13 ,Will Fig. 9 and Fig.12 The results are combined, and the total fault solution includes 6 solutions: 5 spare rows, 4 spare rows and 1 spare column, 3 spare rows and 2 spare columns, 2 spare rows and 3 spare columns, 1 spare row and 4 spare columns, and 5 spare columns.

[0096] It should be noted that although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0097] Furthermore, this exemplary embodiment also provides a fault analysis device.

[0098] Fig.14 FIG. 1 schematically shows a block diagram of a fault analysis device according to an exemplary embodiment of the present disclosure. Fig.14 According to an exemplary embodiment of the present disclosure, the fault analysis device 14 may include a parameter value determination module 141 , a fault group division module 143 , and a solution matching module 145 .

[0099] Specifically, the parameter value determination module 141 can be used to determine the number of fault points on each fault line in the fault area of ​​the memory to obtain a number range, and determine the partition parameter value of the fault area from the data range; the fault group partition module 143 can be used to divide the fault area into at least two fault groups using the partition parameter value; the solution matching module 145 can be used to match fault solutions to each fault group respectively.

[0100] According to an exemplary embodiment of the present disclosure, the fault line includes a column fault line extending in the column direction of the fault region. In this case, the fault group division module 143 can be configured to perform: comparing the number of fault points of each column fault line in the fault region with the division parameter value; determining the area corresponding to the column fault line whose number of fault points in the fault region is greater than or equal to the division parameter value as the first fault group; determining a first target area consisting of column fault lines whose number of fault points in the fault region is less than the division parameter value, and determining at least a second fault group based on the first target area.

[0101] According to an exemplary embodiment of the present disclosure, the fault group division module 143 can also be configured to perform: determining a fault distribution sub-area within the first target area; comparing the size of the fault distribution sub-area with the size of a predetermined area in the solution library; if the size of the fault distribution sub-area is less than or equal to the size of the predetermined area in the solution library, determining the fault distribution sub-area as a second fault group; if the size of the fault distribution sub-area is larger than the size of the predetermined area in the solution library, using the fault distribution sub-area as a fault area to determine at least a second fault group from the fault distribution sub-area.

[0102] According to an exemplary embodiment of the present disclosure, the fault line includes a row fault line extending in the row direction of the fault area. In this case, the fault group division module 143 can be configured to perform: comparing the number of fault points of each row fault line in the fault area with the division parameter value; determining the area corresponding to the row fault points in the fault area where the number of fault points is greater than or equal to the division parameter value as the third fault group; determining a second target area consisting of row fault lines in the fault area where the number of fault points is less than the division parameter value, and determining at least a fourth fault group based on the second target area.

[0103] According to an exemplary embodiment of the present disclosure, the fault group division module 143 can also be configured to perform: determining a fault distribution sub-area within the second target area; comparing the size of the fault distribution sub-area with the size of a predetermined area in the solution library; if the size of the fault distribution sub-area is less than or equal to the size of the predetermined area in the solution library, determining the fault distribution sub-area as a fourth fault group; if the size of the fault distribution sub-area is larger than the size of the predetermined area in the solution library, using the fault distribution sub-area as a fault area to determine at least a fourth fault group from the fault distribution sub-area.

[0104] According to an exemplary embodiment of the present disclosure, the solution matching module 145 may be configured to execute: determining at least one fault solution corresponding to the fault group according to the distribution state of the fault points in the fault group; wherein the fault solution includes the number of spare rows and the number of spare columns.

[0105] According to an exemplary embodiment of the present disclosure, the solution matching module 145 may also be configured to perform: merging the fault solutions of each fault group to determine a fault solution for the fault region of the memory.

[0106] Since the functional modules of the fault analysis device in the embodiment of the present disclosure are the same as those in the above method embodiment, they will not be described in detail here.

[0107] In an exemplary embodiment of the present disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the above method of the present specification is stored. In some possible implementations, various aspects of the present disclosure may also be implemented in the form of a program product, which includes a program code, and when the program product is run on a terminal device, the program code is used to enable the terminal device to execute the steps according to various exemplary implementations of the present disclosure described in the above "Exemplary Method" section of the present specification.

[0108] The program product for implementing the above method according to the embodiment of the present disclosure can adopt a portable compact disk read-only memory (CD-ROM) and include program code, and can be run on a terminal device, such as a personal computer. However, the program product of the present disclosure is not limited thereto, and in this document, a readable storage medium can be any tangible medium containing or storing a program, which can be used by or in combination with an instruction execution system, an apparatus or a device.

[0109] The program product may use any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical disk, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0110] Computer readable signal media may include data signals propagated in baseband or as part of a carrier wave, in which readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Readable signal media may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0111] The program code embodied on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination of the foregoing.

[0112] Program code for performing the operations of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., through the Internet using an Internet service provider).

[0113] In an exemplary embodiment of the present disclosure, an electronic device capable of implementing the above method is also provided.

[0114] Those skilled in the art will appreciate that various aspects of the present disclosure may be implemented as systems, methods or program products. Therefore, various aspects of the present disclosure may be specifically implemented in the following forms, namely: complete hardware implementation, complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software, which may be collectively referred to herein as "circuits", "modules" or "systems".

[0115] Refer to the following Fig.15 15 to describe the electronic device 1500 according to this embodiment of the present disclosure. Fig.15 The electronic device 1500 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0116] like Fig.15 As shown, the electronic device 1500 is in the form of a general computing device. The components of the electronic device 1500 may include, but are not limited to: the at least one processing unit 1510, the at least one storage unit 1520, a bus 1530 connecting different system components (including the storage unit 1520 and the processing unit 1510), and a display unit 1540.

[0117] The storage unit stores program codes, which can be executed by the processing unit 1510, so that the processing unit 1510 executes the steps according to various exemplary embodiments of the present disclosure described in the above “Exemplary Method” section of this specification. For example, the processing unit 1510 can execute various steps of the fault analysis method of the embodiment of the present disclosure.

[0118] The storage unit 1520 may include a readable medium in the form of a volatile storage unit, such as a random access storage unit (RAM) 15201 and / or a cache storage unit 15202 , and may further include a read-only storage unit (ROM) 15203 .

[0119] The storage unit 1520 may also include a program / utility 15204 having a set (at least one) of program modules 15205, such program modules 15205 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0120] Bus 1530 may represent one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0121] The electronic device 1500 may also communicate with one or more external devices 1600 (e.g., keyboards, pointing devices, Bluetooth devices, etc.), may also communicate with one or more devices that enable a user to interact with the electronic device 1500, and / or communicate with any device that enables the electronic device 1500 to communicate with one or more other computing devices (e.g., routers, modems, etc.). Such communication may be performed via an input / output (I / O) interface 1550. In addition, the electronic device 1500 may also communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via a network adapter 1560. As shown, the network adapter 1560 communicates with other modules of the electronic device 1500 via a bus 1530. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 1500, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0122] Through the description of the above implementation, it is easy for those skilled in the art to understand that the example implementation described here can be implemented by software, or by software combined with necessary hardware. Therefore, the technical solution according to the implementation of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the implementation of the present disclosure.

[0123] In addition, the above-mentioned figures are only schematic illustrations of the processes included in the method according to the exemplary embodiments of the present disclosure, and are not intended to be limiting. It is easy to understand that the processes shown in the above-mentioned figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.

[0124] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0125] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and embodiments are to be considered merely as exemplary, and the true scope and spirit of the present disclosure are indicated by the claims.

[0126] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A fault analysis method, characterized in that: include: Determine the number of fault points on each fault line in a fault area of ​​the memory to obtain a number range, and determine a partition parameter value of the fault area from the data range; Dividing the fault area into at least two fault groups using the division parameter value; A fault solution is matched to each of the fault groups.

2. The fault analysis method according to claim 1, characterized in that: The fault line includes a column fault line extending in the column direction of the fault area; wherein dividing the fault area into at least two fault groups using the division parameter value includes: Comparing the number of fault points of each of the columns of fault lines in the fault area with the partition parameter value; Determine the area corresponding to the column fault line in which the number of fault points in the fault area is greater than or equal to the partition parameter value as the first fault group; A first target area consisting of column fault lines in the fault area whose number of fault points is less than the partition parameter value is determined, and at least a second fault group is determined based on the first target area.

3. The fault analysis method according to claim 2, characterized in that: Determining at least a second fault group based on the first target area includes: Determining a fault distribution sub-area within the first target area; comparing the size of the fault distribution sub-area with the size of a predetermined area in a solution library; If the size of the fault distribution sub-region is smaller than or equal to the size of the predetermined region in the solution library, determining the fault distribution sub-region as the second fault group; If the size of the fault distribution sub-region is larger than the size of the predetermined region in the solution library, the fault distribution sub-region is used as the fault region to determine at least the second fault group from the fault distribution sub-region.

4. The fault analysis method according to claim 1 or 2, characterized in that: The fault line includes a row fault line extending in the row direction of the fault area; wherein dividing the fault area into at least two fault groups using the division parameter value includes: Comparing the number of fault points of each of the row fault lines in the fault area with the division parameter value; Determine the area corresponding to the row fault points in which the number of fault points in the fault area is greater than or equal to the partition parameter value as a third fault group; A second target area consisting of row fault lines in which the number of fault points in the fault area is less than the partition parameter value is determined, and at least a fourth fault group is determined based on the second target area.

5. The fault analysis method according to claim 4, characterized in that: Determining at least a fourth fault group based on the second target area includes: determining a fault distribution sub-area within the second target area; comparing the size of the fault distribution sub-area with the size of a predetermined area in a solution library; If the size of the fault distribution sub-region is smaller than or equal to the size of the predetermined region in the solution library, determining the fault distribution sub-region as the fourth fault group; If the size of the fault distribution sub-region is larger than the size of the predetermined region in the solution library, the fault distribution sub-region is used as the fault region to determine at least the fourth fault group from the fault distribution sub-region.

6. The fault analysis method according to claim 1, characterized in that: Matching fault solutions to each of the fault groups includes: Determine at least one fault solution corresponding to the fault group according to the distribution state of the fault points in the fault group; The fault solution includes the number of spare rows and the number of spare columns.

7. The fault analysis method according to claim 1 or 6, characterized in that: The fault analysis method further comprises: The fault solutions of the fault groups are combined to determine a fault solution of the fault area of ​​the memory.

8. A fault analysis device, characterized in that: include: A parameter value determination module, used to determine the number of fault points on each fault line in the fault area of ​​the memory to obtain a number range, and determine the partition parameter value of the fault area from the data range; A fault group division module, used to divide the fault area into at least two fault groups using the division parameter value; The solution matching module is used to match the fault solution to each of the fault groups.

9. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the fault analysis method according to any one of claims 1 to 7 is implemented.

10. An electronic device, characterized in that: include: processor; as well as A memory, configured to store executable instructions of the processor; The processor is configured to implement the fault analysis method according to any one of claims 1 to 7 by executing the executable instructions.

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