Semiconductor packaging chip mounter and precision test method thereof

Abstract

The invention provides a semiconductor packaging chip mounter and a precision testing method thereof, and relates to the technical field of semiconductor packaging, and the testing method comprises the steps that a first positioning module positions a first surface of a chip, obtains first position information of the first surface, and stores the first position information; the mounting head picks up the chip according to the first position information; the second positioning module is used for positioning the second surface of the chip, acquiring second position information of the second surface and storing the second position information; mounting a chip by the semiconductor packaging chip mounter according to the second position information; the first positioning module is used for measuring the actual mounting position of the first surface of the chip; calculating an actual mounting position and a theoretical mounting position of the second surface; and calculating the chip mounting deviation according to the actual mounting position and the theoretical mounting position of the second surface. According to the detection method provided by the invention, the mounting precision can be detected after mounting, and the semiconductor packaging chip mounter can be adjusted in time, so that the subsequent mounting deviation is reduced, and the production yield is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor packaging technology, and in particular to a semiconductor packaging placement machine and a precision inspection method thereof. Background Art

[0002] Semiconductor packaging and placement machines are devices that pick up tiny semiconductor components (such as chips, passive components, etc.) and place them on a predetermined packaging substrate or mount them to a specified location. For example, during the chip reassembly process, it can pick up extremely small chips from the chip carrier and place them at a predetermined location according to design requirements.

[0003] During the chip placement and reorganization process, there is a risk of chip offset exceeding the standard. Therefore, how to test the placement accuracy and adjust the equipment placement accuracy in time has become one of the technical problems that need to be solved urgently at this stage. Summary of the invention

[0004] In order to solve the above technical problems, the present disclosure provides a semiconductor packaging placement machine and an accuracy inspection method thereof, which are used to inspect the placement accuracy and adjust the equipment placement accuracy in time.

[0005] In a first aspect, the present disclosure provides a method for inspecting the accuracy of a semiconductor packaging placement machine, comprising:

[0006] The first positioning module positions the first surface of the chip, obtains first position information of the first surface, and saves the first position information;

[0007] The placement head picks up the chip;

[0008] The second positioning module positions the second surface of the chip, obtains second position information of the second surface, and saves the second position information; the first surface and the second surface are arranged opposite to each other;

[0009] A semiconductor packaging mounter mounts the chip according to the second position information;

[0010] The first positioning module measures the actual mounting position of the first surface of the chip, and calculates the actual mounting position of the second surface according to the actual mounting position of the first surface, the first position information and the second position information;

[0011] Calculate a theoretical mounting position of the second surface according to the second position information;

[0012] The chip mounting deviation is calculated according to the actual mounting position of the second surface and the theoretical mounting position of the second surface.

[0013] Optionally, where:

[0014] Before the first positioning module positions the first surface of the chip, the method further includes: coaxially calibrating the first positioning module and the second positioning module.

[0015] Optionally, where:

[0016] The coaxial calibration comprises:

[0017] The first positioning module takes a picture of the marking point on the glass substrate to obtain a first position of the marking point;

[0018] The second positioning module takes a photo of the marking point on the glass substrate to obtain a second position of the marking point; wherein the first positioning module and the second positioning module are respectively located on two sides of the glass substrate;

[0019] The first positioning module and the second positioning module are calibrated according to the first position and the second position.

[0020] Optionally, where:

[0021] Also includes:

[0022] Acquiring chip position deviation data of the semiconductor packaging placement machine;

[0023] Processing and analyzing the chip position deviation data;

[0024] The semiconductor packaging placement machine is adjusted according to the analysis results.

[0025] Optionally, where:

[0026] The step of obtaining chip position deviation data of the semiconductor packaging placement machine includes:

[0027] Establishing the cutting position coordinates of the chip;

[0028] Establishing the chip placement position coordinates and recording the number of the placement head used to place the chip;

[0029] The actual mounting position of the chip after mounting is completed is measured, and the position offset between the actual mounting position and the theoretical mounting position is calculated.

[0030] Optionally, where:

[0031] The processing and analyzing of the chip position deviation data includes:

[0032] According to the cutting position coordinates, the average value of the cutting errors of the chips in the same row along the column direction is calculated and recorded as the first average error e1.

[0033] Optionally, where:

[0034] The processing and analyzing of the chip position deviation data further includes:

[0035] According to the cutting position coordinates, the average cutting error of the chips in the same column along the row direction is calculated and recorded as the second average error e2.

[0036] Optionally, where:

[0037] The processing and analyzing of the chip position deviation data further includes:

[0038] Calculate the mounting offset according to the first average error and the second average error;

[0039] The placement offset is analyzed according to the number of the placement head, and the placement head whose placement offset is greater than a preset error range is controlled.

[0040] Optionally, where:

[0041] The calculation of the mounting offset includes calculating a row mounting offset m1 of the chips in the same row, and calculating a column mounting offset m2 of the chips in the same column;

[0042] The row position offset of the chips in the same row is s1, m1=s1-e1;

[0043] The column position offset of the chips in the same column is s2, m2=s2-e2.

[0044] In a second aspect, based on the same inventive concept, the present disclosure further provides a semiconductor packaging placement machine, which uses the semiconductor packaging placement machine accuracy inspection method described in the first aspect to inspect the placement accuracy.

[0045] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0046] The present disclosure provides a semiconductor packaging placement machine and its precision inspection method, wherein the inspection method includes a first positioning module positioning the first side of a chip, obtaining the first position information of the first side, and saving the first position information; a placement head picking up the chip according to the first position information; a second positioning module positioning the second side of the chip, obtaining the second position information of the second side, and saving the second position information; the first side and the second side are arranged relatively; the semiconductor packaging placement machine places the chip according to the second position information; the first positioning module measures the actual placement position of the first side of the chip, and calculates the actual placement position of the second side according to the actual placement position of the first side, the first position information and the second position information; calculates the theoretical placement position of the second side according to the second position information; and calculates the chip placement deviation according to the actual placement position of the second side and the theoretical placement position of the second side. The inspection method provided by the present disclosure can inspect the placement accuracy after placement, which is conducive to timely adjustment of the semiconductor packaging placement machine to reduce subsequent placement deviations, thereby helping to improve production yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0048] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0049] Figure 1 Shown is a schematic diagram of a chip reorganization process in the prior art;

[0050] Figure 2 The figure is a flow chart of a method for precision inspection of a semiconductor packaging placement machine provided by an embodiment of the present disclosure;

[0051] Figure 3 It is a schematic flow chart of another method for precision inspection of semiconductor packaging placement machine provided by an embodiment of the present disclosure;

[0052] Figure 4 Shown is a schematic diagram of a coaxial calibration process provided by an embodiment of the present disclosure;

[0053] Figure 5 Shown is a schematic diagram of a coaxial calibration structure provided by an embodiment of the present disclosure;

[0054] Figure 6 It is a schematic flow chart of another method for precision inspection of semiconductor packaging placement machine provided by an embodiment of the present disclosure;

[0055] Figure 7 The figure is a schematic diagram of a process for obtaining chip position deviation data of a semiconductor packaging placement machine provided by an embodiment of the present disclosure;

[0056] Figure 8 The figure shows a schematic diagram of chip positions after cutting provided by this embodiment;

[0057] Fig. 9 The figure shows a schematic diagram of chip position after mounting provided by this embodiment;

[0058] Fig.10 Shown is a chip mounting deviation summary chart provided by an embodiment of the present disclosure;

[0059] Fig.11 Shown is a summary chart of a placement head deviation provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0060] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0061] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0062] The inventors found in their research that there is a risk of chip deviation exceeding the standard during the chip reorganization process. The relevant technology includes two inspection methods: one is to regularly check the equipment accuracy management mechanism, which cannot detect problems in time; the other is to set up a product inspection mechanism in the back-end process, which is far away from the inspection station and cannot detect problems in time. For example, Figure 1 The figure shows a schematic diagram of a chip reorganization process in the prior art. Figure 1 , Figure 1 A chip reorganization process is shown in the figure. In step S10', the semiconductor packaging mounter mounts and reorganizes the chip. Steps S20' to S30' perform plastic sealing and baking on the mounted device. The chip position is inspected in step S40' after baking. At this time, the plastic sealing and baking steps are performed after the chip is reorganized, and the inspection is not timely. At the same time, the inspection result also includes the errors in the plastic sealing and baking steps, and the inspection result is inaccurate.

[0063] Therefore, how to test the mounting accuracy and adjust the equipment mounting accuracy in time has become one of the technical problems that need to be solved urgently at this stage.

[0064] In order to solve the above technical problems, the present disclosure provides a semiconductor packaging placement machine and an accuracy inspection method thereof, which are used to inspect the placement accuracy and adjust the equipment placement accuracy in time.

[0065] Figure 2 FIG. 1 is a flow chart of a method for precision inspection of a semiconductor packaging placement machine provided by an embodiment of the present disclosure. Please refer to FIG. Figure 2 The present disclosure provides a method for inspecting the accuracy of a semiconductor packaging placement machine, comprising:

[0066] Step S01: A first positioning module positions a first surface of a chip, obtains first position information of the first surface, and saves the first position information;

[0067] Step S02, the placement head picks up the chip;

[0068] Step S03: The second positioning module positions the second surface of the chip, obtains second position information of the second surface, and saves the second position information; the first surface and the second surface are arranged opposite to each other;

[0069] Step S04: the semiconductor packaging mounter mounts the chip according to the second position information;

[0070] Step S05: The first positioning module measures the actual mounting position of the first surface of the chip, and calculates the actual mounting position of the second surface according to the actual mounting position of the first surface, the first position information and the second position information;

[0071] Step S06, calculating the theoretical mounting position of the second surface according to the second position information;

[0072] Step S07: Calculate the chip mounting deviation according to the actual mounting position of the second surface and the theoretical mounting position of the second surface.

[0073] It should be noted that the semiconductor packaging placement machine precision inspection method provided by the present disclosure includes but is not limited to steps S01 to S07. The inspection method provided by the present disclosure is applied to the chip reassembly process, and timely inspection after mounting is more conducive to timely inspection of mounting deviations in the mounting and reassembly process. At the same time, the mounting accuracy and the plastic sealing accuracy are inspected separately, which will be more conducive to separately controlling the accuracy of mounting and plastic sealing, thereby improving the overall accuracy level of the reassembled chip.

[0074] Specifically, in step S01, the first side of the chip is positioned by a first positioning module. It should be noted that the first positioning module may be a camera having a function of obtaining chip position information, and the first side may be the back side of the chip. The present disclosure is only described by this example and is not limited thereto. The first side of the chip is positioned by the first positioning module, first position information of the first side is obtained, and the obtained first position information is saved.

[0075] In step S02, the placement head picks up the chip and moves to a designated position.

[0076] In step S03, the second side of the chip is positioned by a second positioning module. It should be noted that the second positioning module may also be a camera having a function of obtaining chip position information. The second side may be the front side of the chip. The first side and the second side are two sides of the chip that are arranged opposite to each other. The present disclosure is only described by taking this as an example and is not limited thereto. The second side of the chip is positioned by the second positioning module to obtain second position information of the second side, and the obtained second position information is saved.

[0077] In step S04, the semiconductor packaging placement machine controls the placement head to place the chip at a designated position according to the second position information.

[0078] In step S05, the actual mounting position of the first surface of the chip is measured by the first positioning module. It should be noted that the chip usually has a marking point, which is located on the front of the chip. After mounting, the marking point information on the front cannot be obtained. Therefore, in step S05, the actual mounting position of the first surface of the chip is measured by the first positioning module, that is, the actual mounting position of the back of the chip. According to the actual mounting position of the first surface, the first position information obtained in step S01, and the second position information obtained in step S03, the actual mounting position of the second surface is calculated.

[0079] In step S06, in order to subsequently calculate the mounting deviation, it is necessary to calculate the theoretical mounting position of the second surface. The position deviation between the first surface and the second surface of the chip is calculated based on the second position information obtained in step S03, thereby calculating the theoretical mounting position of the second surface.

[0080] In step S07, the chip mounting deviation can be calculated according to the actual mounting position and the theoretical mounting position of the second surface of the chip.

[0081] It should be noted that in the above embodiment, the chip mounting deviation is calculated by calculating the actual mounting position and the theoretical mounting position of the second surface. In some other embodiments, the chip mounting deviation can also be calculated by calculating the actual mounting position and the theoretical mounting position of the first surface. The present disclosure provides another optional implementation method, which is to measure the actual mounting position of the first surface in step S05; calculate the theoretical mounting position of the first surface according to the first position information and the second position information in step S06; and calculate the chip mounting error according to the actual mounting position and the theoretical mounting position of the first surface of the chip in step S07.

[0082] The semiconductor packaging placement machine accuracy inspection method provided by the present disclosure can inspect the placement accuracy after placement, which is conducive to timely adjustment of the semiconductor packaging placement machine to reduce subsequent placement deviations, thereby helping to improve production yield.

[0083] It should also be noted that after the chip mounting deviation is detected, the mounting deviation is compared with the preset deviation. If the mounting deviation is within the preset deviation range, normal production can be carried out. If the mounting deviation exceeds the preset deviation range, production is stopped and the equipment alarm operation is performed. Exemplarily, the preset acceptable deviation range (preset deviation range) of the center of the front and back of the chip is ±6μm. When the center of the front and back of the chip deviates by 5μm, it is a normal value and normal production can be carried out; when the center of the front and back of the chip deviates by -7μm, it exceeds the preset deviation range and the equipment alarms.

[0084] Figure 3 FIG. 1 is a flow chart of another semiconductor packaging placement machine accuracy inspection method provided by the embodiment of the present disclosure. Please refer to FIG. Figure 3 In an optional embodiment of the present disclosure, before the first positioning module positions the first surface of the chip, it also includes: step S00, coaxially calibrating the first positioning module and the second positioning module.

[0085] Specifically, before the precision inspection of the semiconductor packaging placement machine is performed, in order to improve the accuracy of the inspection, the present embodiment performs coaxial calibration on the first positioning module and the second positioning module, the first positioning module is used to locate the first surface of the chip, and the second positioning module is used to locate the second surface of the chip, the first surface and the second surface are two surfaces of the chip that are arranged opposite to each other, that is, the first positioning module and the second positioning module are respectively located on both sides of the chip. Coaxial calibration of the first positioning module and the second positioning module is conducive to improving the accuracy of chip positioning, thereby helping to improve the accuracy of precision inspection of the semiconductor packaging placement machine.

[0086] It should be noted that step S00 of coaxially calibrating the first positioning module and the second positioning module can be performed periodically, and does not need to be performed before each inspection. This is beneficial to improving the inspection accuracy and saving production time. For example, the period of performing coaxial calibration can be 15 days, 1 month, 2 months, etc.

[0087] It should also be noted that in step S06, when calculating the theoretical mounting position, the coaxial calibration data can also be combined, which is helpful to improve the accuracy of the theoretical mounting position, thereby helping to improve the accuracy of the inspection.

[0088] Figure 4 FIG. 1 is a schematic diagram of a coaxial calibration process provided by an embodiment of the present disclosure. Figure 5 FIG. 1 is a schematic diagram of a coaxial calibration structure provided by an embodiment of the present disclosure, please refer to Figure 3 to Figure 5 Optionally, the coaxial calibration comprises:

[0089] Step S001, the first positioning module 10 takes a photo of the marking point 00 on the glass substrate 30 to obtain a first position of the marking point 00;

[0090] Step S002: the second positioning module 20 takes a photo of the mark point 00 of the glass substrate 30 to obtain a second position of the mark point 00; wherein the first positioning module 10 and the second positioning module 20 are respectively located on both sides of the glass substrate 30;

[0091] Step S003 , calibrating the first positioning module 10 and the second positioning module 20 according to the first position and the second position.

[0092] Specifically, the present disclosure provides an implementation method of coaxial calibration, wherein a glass substrate 30 is arranged between a first positioning module 10 and a second positioning module 20, and the glass substrate 30 includes a marking point 00. The first positioning module 10 and the second positioning module 20 are respectively used to take photos of the glass substrate 30. The first positioning module 10 takes photos to obtain the position of the marking point 00 on the glass substrate 30, which is recorded as the first position, and the second positioning module 20 takes photos to obtain the position of the same marking point 00 on the glass substrate 30, which is recorded as the second position. Since the photos are taken of the same marking point 00 on the same glass substrate 30, theoretically, the first position and the second position coincide. The first positioning module 10 and the second positioning module 20 are calibrated according to the first position and the second position so that their shooting centers coincide. Such an arrangement is conducive to improving the accuracy of chip positioning, thereby facilitating improving the accuracy of precision inspection of semiconductor packaging placement machines.

[0093] Figure 6 FIG. 1 is a flow chart of another semiconductor packaging placement machine accuracy inspection method provided by the embodiment of the present disclosure. Please refer to FIG. Figure 2 and Figure 6 In an optional embodiment of the present disclosure, the semiconductor packaging placement machine accuracy inspection method further includes steps S81 to S83:

[0094] S81, obtaining chip position deviation data of a semiconductor packaging placement machine;

[0095] S82, analyzing chip position deviation data;

[0096] S83. Adjust the semiconductor packaging placement machine according to the analysis results.

[0097] Specifically, the semiconductor packaging placement machine accuracy inspection method provided in this embodiment is to obtain the chip position deviation data of the semiconductor packaging placement machine after placement, and screen out the placement heads with large placement errors in the semiconductor packaging placement machine through classification, statistics and analysis of the chip position deviation data. This is beneficial to discover placement head problems in advance through reasonable control of placement deviations. At the same time, deviation trend analysis can also be performed on the same placement head, which is further beneficial to early intervention in placement deviations, and then to improving production line yield.

[0098] It should be noted that the semiconductor packaging placement machine precision inspection method provided in this embodiment implements the intervention and control of chip placement deviation by classifying the data of chip cutting rules and statistically analyzing the data after placement. This implementation requires certain data and does not need to be executed after each placement. It should also be noted that the semiconductor packaging placement machine precision inspection method corresponding to steps S81 to S83 provided in this embodiment and the calculation of chip placement deviation according to the actual placement position and theoretical placement position after placement (the semiconductor packaging placement machine precision inspection method corresponding to steps S01 to S07) can be used separately, and both are conducive to the control of placement deviation. Among them, steps S01 to S07 are conducive to more timely inspection of the current chip. It is only necessary to add the corresponding module to the software part of the semiconductor packaging placement machine, and the inspection can be carried out through the inspection method provided by the present disclosure; steps S81 to S83 are conducive to reducing the error of subsequent products on the production line. This method does not require changes to the hardware and software of the equipment, and only requires obtaining chip position deviation data. When actually inspecting the mounting accuracy, after using steps S01 to S07 for inspection, steps S81 to S83 may no longer be executed; when the actual inspection is not suitable for using steps S01 to S07 for inspection, steps S81 to S83 may be used alone for inspection. This disclosure is only used as an example for illustration and is not limited to this.

[0099] Figure 7 FIG. 1 is a flow chart of obtaining chip position deviation data of a semiconductor packaging placement machine provided by an embodiment of the present disclosure. Figure 8 FIG. 1 is a schematic diagram of chip positions after cutting provided in this embodiment. Fig. 9 The figure shows a schematic diagram of chip position after mounting provided in this embodiment. Figure 6 to Figure 9 In an optional embodiment of the present disclosure, step S81, obtaining chip position deviation data of a semiconductor packaging placement machine, includes:

[0100] Step S081, establishing the cutting position coordinates of the chip 50;

[0101] Step S082, establishing the chip placement position coordinates of the chip 50, and recording the number of the placement head used to place the chip;

[0102] Step S083, measuring the actual mounting position of the chip 50 after the mounting is completed, and calculating the position offset between the actual mounting position and the theoretical mounting position.

[0103] It should be noted that, in the chip reassembly process, a chip substrate 40 includes a plurality of chips 50 arranged in an array. The chip substrate 40 needs to be cut before mounting. The cut chips 50 are picked up by a mounting head and mounted to a specified position. For example, the chips 50 are mounted to Fig. 9 The reconstitution substrate 60 is shown.

[0104] In this embodiment, during the cutting process of the chip substrate 40, the cutting position coordinates of the chip 50 are established; after the chip 50 is picked up by the mounting head and mounted to the specified position, the chip position coordinates of the chip 50 are established, and the number of the mounting head used to mount the chip is recorded, so as to facilitate the subsequent identification of the mounting head with a large mounting deviation, and to perform mounting deviation error trend analysis for the same mounting head. After the mounting is completed, the mounting error between the actual mounting position and the theoretical mounting position of the chip 50 after the mounting is completed is measured and calculated, so that the position offset of multiple chips 50 is obtained. By analyzing and processing the position offset of the chip, it is helpful to find the mounting head problem in advance through reasonable control of the mounting deviation. At the same time, the deviation trend analysis can also be performed for the same mounting head, which is further conducive to early intervention of the mounting deviation, and thus helps to improve the production line yield.

[0105] Please refer to Figure 6 The present disclosure provides an optional implementation method, in which, when analyzing and controlling the placement deviation through the semiconductor packaging placement machine accuracy inspection method corresponding to steps S81 to S83, step S82, processing and analyzing the chip position deviation data, includes:

[0106] According to the cutting position coordinates, the average value of the cutting errors of the chips in the same row along the column direction is calculated and recorded as the first average error e1.

[0107] Specifically, one of the main reasons why the final position of the chip after mounting is offset from the theoretical deviation position is that the chip cutting position is offset when the chip substrate is cut. Therefore, the cutting position offsets of the chips in the same row or column are the same. In this embodiment, the cutting offset errors of the chips in the same row are extracted according to the cutting position coordinates, and the average cutting error of the chips in the same row is calculated and recorded as the first average error e1. For the chips in the same row, the row mounting offset m1 of the chips in the same row can be calculated according to the first average error e1. The present disclosure provides an optional implementation, m1=s1-e1, wherein s1 is the row position offset of the chips in the same row.

[0108] Similarly, the present disclosure provides another optional implementation mode, in which, when analyzing and controlling the placement deviation through the semiconductor packaging placement machine accuracy inspection method corresponding to steps S81 to S83, step S82, processing and analyzing the chip position deviation data, further includes:

[0109] According to the cutting position coordinates, the average value of the cutting errors of the chips in the same column along the row direction is calculated and recorded as the second average error e2.

[0110] Specifically, this embodiment extracts the cutting offset error of chips in the same column according to the cutting position coordinates, calculates the average cutting error of chips in the same column, and records it as the second average error e2. For chips in the same column, the column mounting offset m2 of chips in the same column can be calculated according to the second average error e2. The present disclosure provides an optional implementation method, m2=s2-e2, wherein s2 is the column position offset of chips in the same column.

[0111] It should be noted that the cutting error refers to the difference between the distance between the actual cutting edge and the chip edge and the distance between the theoretical cutting edge and the chip edge. When calculating the first average error e1 and the second average error e2, 5% to 10% of extreme data can be removed, which is beneficial to further improve the accuracy of the first average error e1 and the second average error e2, thereby improving the accuracy of the row mounting offset m1 and the column mounting offset m2.

[0112] Please refer to Figure 6 In an optional implementation of the present application, when analyzing and controlling the placement deviation through the semiconductor packaging placement machine accuracy inspection method corresponding to steps S81 to S83, step S82, processing and analyzing the chip position deviation data, also includes:

[0113] Calculate the placement offset according to the first average error and the second average error;

[0114] The placement offset is analyzed according to the number of the placement head, and the placement heads whose placement offset is greater than the preset error range are controlled.

[0115] Specifically, the main reasons for the deviation between the final position of the chip after mounting and the theoretical deviation position include: first, the chip cutting position is offset when the chip substrate is cut; second, the mounting head is offset when mounting the chip. This embodiment is to manage the mounting accuracy by analyzing and controlling the offset generated by the mounting head. Therefore, it is necessary to calculate the mounting offset generated when the mounting head mounts the chip. The present disclosure provides an optional embodiment in which the calculation of the mounting offset includes calculating the row mounting offset m1 of the chips in the same row, and calculating the column mounting offset m2 of the chips in the same column; the row position offset of the chips in the same row is s1, m1=s1-e1; the column position offset of the chips in the same column is s2, m2=s2-e2. In this way, the mounting offset generated by the mounting head when mounting the chip can be calculated. Analyze the placement offset according to the number of the placement head, and optionally use SPC to analyze and control the placement offset. This setting is conducive to reasonable control of placement deviation, early detection of placement head problems, and reduction of placement deviation in subsequent production processes, thereby improving production yield.

[0116] It should be noted that SPC (Statistical Process Control) is a process control tool that uses mathematical statistics methods. It collects, analyzes and monitors data in the production process to determine whether the process is in a stable state, promptly discover abnormal fluctuations in the process, and take corresponding measures to make adjustments, thereby ensuring the stability and consistency of the production line.

[0117] It should also be noted that when establishing the chip placement position coordinates, the present disclosure records the number of the placement head used to place the chip, and obtains the placement error of the chip placed by the same placement head for the chip placed by the same placement head. By statistics and analysis of the placement error of the same placement head, it is helpful to timely discover and adjust the error of the placement head to reduce the placement deviation in subsequent production. Optionally, when it is found that the placement error of the placement head is large or has an increasing trend, the machine is stopped in time and the semiconductor packaging placement machine is calibrated.

[0118] Please refer to Figure 8 and Fig. 9 , the present disclosure provides an optional implementation as follows: Figure 8A chip position diagram after cutting is shown, a chip substrate 40 after cutting, each row includes 10 chips 50, each column includes 10 chips 50, and cutting position coordinates are established for the chips 50 in the chip substrate 40, the cutting position coordinates of the chip 50 in the first row and the first column are (1, 1), the cutting position coordinates of the chip 50 in the first row and the second column are (1, 2), the cutting position coordinates of the chip 50 in the second row and the first column are (2, 1), and so on, to establish the cutting position coordinates of all chips. Fig. 9 The chip position diagram after mounting is shown. The mounting head picks up the chip from the chip substrate 40 and mounts it to the reorganized substrate 60. The mounting position coordinates of the chip 50 after mounting are established. The mounting position coordinates of the chip 50 in the first row and the first column are (1, 1), the mounting position coordinates of the chip 50 in the first row and the second column are (1, 2), and the mounting position coordinates of the chip 50 in the second row and the first column are (2, 1). By analogy, the mounting position coordinates of all chips 50 are established. At the same time, the number of the mounting head used to mount the chip is recorded. It should be noted that Fig. 9 The number in the chip 50 indicates the number of the placement head. This embodiment is described by taking a semiconductor package placement machine including 5 placement heads as an example, but is not limited to this. Figure 8 and Fig. 9 When cutting, there are 10 chips 50 in each row, and the cutting position coordinates of the 10 chips 50 in the first row are (1, 1) to (1, 10); there are 10 chips 50 in each column, and the cutting position coordinates of the 10 chips 50 in the first column are (1, 1) to (10, 1). After mounting, there are 8 chips 50 in each row, and the mounting position coordinates of the 8 chips 50 in the first row are (1, 1) to (1, 8); there are 8 chips 50 in each column, and the mounting position coordinates of the 8 chips 50 in the first column are (1, 1) to (8, 1). The number of the mounting head used is shown on each chip 50.

[0119] Fig.10 The figure shows a chip mounting deviation summary chart provided by the embodiment of the present disclosure. Please refer to Fig.10 , Fig.10 It is shown in Figure 8 The first and second rows of chips 50 mounting deviation data in the same row of chips 50 have the same or substantially the same cutting deviations in the first direction Y. Therefore, the average chip positions of the first and second rows of chips 50 after cutting in the first direction Y are calculated and recorded as the first average error e1. Along the first direction Y, according to the row position offset s1 after mounting the same row of chips, after subtracting the first average error e1, the row mounting position offset m1 of the chip can be obtained. Similarly, if the cutting deviations of the same column of chips 50 in the second direction X are the same or substantially the same, the column mounting offset m2 after mounting the same column of chips can be calculated in the same way.

[0120] Fig.11 The figure shows a summary chart of the placement head deviation provided by the embodiment of the present disclosure, please refer to Fig.11 , Fig.11 Part of the placement deviation data of placement heads 1 to 5 is shown in the figure. The average value of the placement offset of the same placement head is calculated, and the placement head with a larger offset is tracked. This is conducive to timely control of the placement offset of the placement head, thereby facilitating the identification of abnormal situations in the production process, and further facilitating the improvement of product yield.

[0121] It should be noted that this disclosure only Figure 8 and Fig. 9 The embodiments shown are described by way of example only and are not intended to be limiting.

[0122] Based on the same inventive concept, the present disclosure provides a semiconductor packaging placement machine, and uses the semiconductor packaging placement machine accuracy inspection method provided by the embodiment of the present disclosure to inspect the placement accuracy.

[0123] It should be noted that the embodiment of the semiconductor packaging and placement machine provided in the embodiment of the present application can refer to the embodiment of the semiconductor packaging and placement machine accuracy inspection method mentioned above, and will not be repeated here.

[0124] It can be seen from the above embodiments that the conductor package placement machine and the accuracy inspection method thereof provided by the present disclosure achieve at least the following beneficial effects:

[0125] The present disclosure provides a semiconductor packaging placement machine and its precision inspection method, wherein the inspection method includes a first positioning module positioning the first side of a chip, obtaining the first position information of the first side, and saving the first position information; a placement head picking up the chip according to the first position information; a second positioning module positioning the second side of the chip, obtaining the second position information of the second side, and saving the second position information; the first side and the second side are arranged relatively; the semiconductor packaging placement machine places the chip according to the second position information; the first positioning module measures the actual placement position of the first side of the chip, and calculates the actual placement position of the second side according to the actual placement position of the first side, the first position information and the second position information; calculates the theoretical placement position of the second side according to the second position information; and calculates the chip placement deviation according to the actual placement position of the second side and the theoretical placement position of the second side. The inspection method provided by the present disclosure can inspect the placement accuracy after placement, which is conducive to timely adjustment of the semiconductor packaging placement machine to reduce subsequent placement deviations, thereby helping to improve production yield.

[0126] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0127] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for testing the accuracy of a semiconductor packaging placement machine, characterized in that: include: The first positioning module positions the first surface of the chip, obtains first position information of the first surface, and saves the first position information; The placement head picks up the chip; The second positioning module positions the second surface of the chip, obtains second position information of the second surface, and saves the second position information; the first surface and the second surface are arranged opposite to each other; A semiconductor packaging mounter mounts the chip according to the second position information; The first positioning module measures the actual mounting position of the first surface of the chip, and calculates the actual mounting position of the second surface according to the actual mounting position of the first surface, the first position information and the second position information; Calculate a theoretical mounting position of the second surface according to the second position information; The chip mounting deviation is calculated according to the actual mounting position of the second surface and the theoretical mounting position of the second surface.

2. The semiconductor packaging placement machine accuracy inspection method according to claim 1, characterized in that: Before the first positioning module positions the first surface of the chip, the method further includes: coaxially calibrating the first positioning module and the second positioning module.

3. The semiconductor packaging placement machine accuracy inspection method according to claim 2, characterized in that: The coaxial calibration comprises: The first positioning module takes a picture of the marking point on the glass substrate to obtain a first position of the marking point; The second positioning module takes a photo of the marking point on the glass substrate to obtain a second position of the marking point; wherein the first positioning module and the second positioning module are respectively located on two sides of the glass substrate; The first positioning module and the second positioning module are calibrated according to the first position and the second position.

4. The semiconductor packaging placement machine accuracy inspection method according to claim 1, characterized in that: Also includes: Acquiring chip position deviation data of the semiconductor packaging placement machine; Processing and analyzing the chip position deviation data; The semiconductor packaging placement machine is adjusted according to the analysis results.

5. The semiconductor packaging placement machine accuracy inspection method according to claim 4, characterized in that: The step of obtaining chip position deviation data of the semiconductor packaging placement machine includes: Establishing the cutting position coordinates of the chip; Establishing the chip placement position coordinates and recording the number of the placement head used to place the chip; The actual mounting position of the chip after mounting is completed is measured, and the position offset between the actual mounting position and the theoretical mounting position is calculated.

6. The semiconductor packaging placement machine accuracy inspection method according to claim 5, characterized in that: The processing and analyzing of the chip position deviation data includes: According to the cutting position coordinates, the average value of the cutting errors of the chips in the same row along the column direction is calculated and recorded as the first average error e1.

7. The semiconductor packaging placement machine accuracy inspection method according to claim 6, characterized in that: The processing and analyzing of the chip position deviation data further includes: According to the cutting position coordinates, the average value of the cutting errors of the chips in the same column along the row direction is calculated and recorded as the second average error e2.

8. The semiconductor packaging placement machine accuracy inspection method according to claim 7, characterized in that: The processing and analyzing of the chip position deviation data further includes: Calculate the mounting offset according to the first average error and the second average error; The placement offset is analyzed according to the number of the placement head, and the placement head whose placement offset is greater than a preset error range is controlled.

9. The semiconductor packaging placement machine accuracy inspection method according to claim 8, characterized in that: The calculation of the mounting offset includes calculating a row mounting offset m1 of the chips in the same row, and calculating a column mounting offset m2 of the chips in the same column; The row position offset of the chips in the same row is s1, m1=s1-e1; The column position offset of the chips in the same column is s2, m2=s2-e2.

10. A semiconductor packaging mounter, characterized in that: The semiconductor packaging placement machine accuracy inspection method described in any one of claims 1 to 9 is used to inspect the placement accuracy.

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