Interposer and manufacturing method thereof, three-dimensional packaging structure and manufacturing method thereof

Abstract

The invention discloses an interposer and a manufacturing method thereof, and a three-dimensional packaging structure and a manufacturing method thereof, and relates to the technical field of semiconductor devices. The substrate is provided with a plurality of through holes penetrating from the first surface to the second surface, and each through hole is filled with a conductive material to form a conductive through hole; the substrate is provided with a groove penetrating from the first surface to the second surface, the groove divides the substrate into a plurality of connecting areas spaced by the groove, one connecting area is configured to be connected with one chip, and the chip is electrically connected with the conductive through hole in the corresponding connecting area; the rewiring layer is arranged on the second surface, has flexibility and is electrically connected with the conductive through holes; and the conductive through holes in one connection area are electrically connected with the conductive through holes in the other connection area through the re-wiring layer, so that interconnection between the chip corresponding to one connection area and the other chip corresponding to the other connection area is realized. According to the invention, the stress problem between the interposer and the chip or the packaging substrate can be overcome.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to an intermediate layer and a manufacturing method thereof, a three-dimensional packaging structure and a manufacturing method thereof. Background Art

[0002] With the development of technologies such as artificial intelligence and high-performance computing, the requirements for chip computing power are increasing, and high-performance chips generally adopt 2.5D packaging. In order to reduce power consumption and improve performance, 2.5D packaging usually integrates multiple HBMs (High Bandwidth Memory) and XPUs. The development of multi-chip sealing technology has caused the size of the interposer to increase continuously, and the height and bump pitch of the solder joints / bumps at the bottom of the interposer have continued to decrease, and the requirements for the TTV (total thickness variation) of the interposer, the uniformity of the bump height, and the matching of the thermal expansion coefficient (CTE) of the material have become increasingly higher. The oversized interposer also has problems such as CTE mismatch with the IC Substrate (package substrate), which is very prone to reliability problems such as bump welding failure, which will seriously affect the subsequent process, resulting in a decrease in the qualified rate. Summary of the invention

[0003] The main technical problem solved by the present invention is the problem of stress in the existing packaging structure due to mismatch in thermal expansion coefficients between the interposer and the bottom bump of the interposer and the packaging substrate material.

[0004] According to a first aspect, an interposer is provided in one embodiment, and in one embodiment, includes: a substrate and a redistribution layer;

[0005] The substrate has a first surface and a second surface opposite to each other, and the substrate has a plurality of through holes extending from the first surface to the second surface, each through hole being filled with a conductive material to form a conductive through hole;

[0006] The substrate has a groove extending from the first surface to the second surface, the groove dividing the substrate into a plurality of connection areas separated by the groove, one connection area being configured to connect one chip, and the chip being electrically connected to a conductive through hole in a corresponding connection area;

[0007] The rewiring layer is arranged on the second surface, the rewiring layer is flexible and is electrically connected to the conductive through hole;

[0008] The conductive via in one connection area is electrically connected to the conductive via in another connection area through the rewiring layer, so as to interconnect a chip corresponding to one connection area with another chip corresponding to another connection area.

[0009] In one embodiment, the rewiring layer includes a metal layer and a dielectric layer, the dielectric layer is flexible, the metal layer is electrically connected to the conductive through hole, and the dielectric layer is made of resin.

[0010] In one embodiment, the interposer further includes a plurality of first solder joints;

[0011] The first solder joint is disposed on the first surface and electrically connected to the conductive through hole. The first solder joint is configured to be electrically connected to the chip.

[0012] In one embodiment, the interposer further includes a plurality of second solder joints;

[0013] The second solder joint is disposed on a surface of the redistribution layer away from the substrate. The second solder joint is electrically connected to the redistribution layer. The second solder joint is configured to be electrically connected to the packaging substrate.

[0014] According to the second aspect, an embodiment provides a three-dimensional packaging structure, including a plurality of chips and the interposer described in the first aspect;

[0015] The plurality of chips include at least a first chip and a second chip;

[0016] The first chip and the second chip are respectively mounted on corresponding connection areas on the interposer, and the first chip and the second chip are electrically connected to the rewiring layer through conductive through holes on the interposer.

[0017] In one embodiment, the first chip is a storage chip and the second chip is a processing chip.

[0018] In one embodiment, the three-dimensional packaging structure further includes a packaging substrate;

[0019] The interposer also includes a plurality of second solder joints;

[0020] The second solder joint is arranged on a surface of the rewiring layer away from the substrate, the second solder joint is electrically connected to the rewiring layer, and the second solder joint is electrically connected to the packaging substrate.

[0021] In one embodiment, the three-dimensional packaging structure further includes insulating glue, which is disposed between the substrate and the chip, and wraps the solder joints electrically connected between the substrate and the chip.

[0022] According to a third aspect, an embodiment provides a method for manufacturing an interposer, including:

[0023] A substrate is provided; wherein the substrate has a first surface and a second surface opposite to each other; the substrate has a plurality of through holes extending from the first surface to the second surface, each through hole is filled with a conductive material to form a conductive through hole; a rewiring layer is arranged on the second surface, the rewiring layer is flexible, and the rewiring layer is electrically connected to the conductive through hole;

[0024] The substrate is patterned to form a groove, wherein the groove runs from the first surface to the second surface, and the groove divides the substrate into a plurality of connection areas separated by the groove, and one connection area is configured to connect a chip, and the chip is electrically connected to the conductive through hole in the corresponding connection area.

[0025] According to a fourth aspect, an embodiment provides a method for manufacturing a three-dimensional packaging structure, including:

[0026] Using the method for manufacturing an intermediary layer described in the third aspect to prepare an intermediary layer;

[0027] Mounting at least two chips to corresponding connection areas, the at least two chips include a first chip and a second chip, the first chip and the second chip are electrically connected to the redistribution layer through conductive vias;

[0028] The interposer with the chip is mounted on the package substrate, and the package substrate is electrically connected to the rewiring layer.

[0029] According to the interposer and its manufacturing method, three-dimensional packaging structure and its manufacturing method of the above-mentioned embodiments, the substrate is provided with conductive through holes along its thickness direction, and the conductive through holes are electrically connected to the chip; the rewiring layer is provided on the second surface of the interposer, the rewiring layer is flexible, and the rewiring layer is connected to the packaging substrate; multiple chips are stacked on the first surface of the interposer, and are interconnected through the conductive through holes and the rewiring layer; the groove runs through the first surface of the interposer to the second surface along the gap between the chips, that is, it is cut from the front of the interposer to the rewiring layer, and the rewiring layers of each connection area are connected. By making a groove in the middle of the substrate, the substrate can be provided with a stress buffer, reducing the stress caused by the mismatch of thermal expansion coefficients between the substrate, the bottom bump and the packaging substrate, and thus reducing the problems such as welding failure and material delamination, and the flexible rewiring layer can further eliminate most of the stress and solve the warping problem of large-size packaging structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of the structure of an interposer provided in one embodiment of the present application;

[0031] Figure 2 A schematic structural diagram of a three-dimensional packaging structure provided by an embodiment of the present application;

[0032] Figure 3 for Figure 1 A top view of

[0033] Figure 4 A schematic diagram of a method for manufacturing an interposer provided in one embodiment of the present application (I);

[0034] Figure 5 A schematic diagram of a method for manufacturing an interposer provided in one embodiment of the present application (II);

[0035] Figure 6 A schematic diagram of a process of manufacturing a three-dimensional packaging structure provided in another embodiment of the present application.

[0036] Figure markings: 001-three-dimensional packaging structure; 1-intermediary layer; 2-groove; 3-chip; 11-substrate; 12-rewiring layer; 121-metal layer; 122-dielectric layer; 111-conductive through hole; 13-first solder joint; 14-second solder joint; 4-packaging substrate; 131-first conductive bump; 132-first solder ball; 141-second conductive bump; 142-second solder ball; 52-temporary bonding glue; 51-carrier board; 53-photoresist; 54-photolithography groove; 55-V-shaped groove. DETAILED DESCRIPTION

[0037] The present invention is further described in detail below by specific embodiments in conjunction with the accompanying drawings. Wherein similar elements in different embodiments adopt associated similar element numbers. In the following embodiments, many detailed descriptions are for making the present application better understood. However, those skilled in the art can easily recognize that some features can be omitted in different situations, or can be replaced by other elements, materials, methods. In some cases, some operations related to the present application are not shown or described in the specification, this is to avoid the core part of the present application being overwhelmed by too much description, and for those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations according to the description in the specification and the general technical knowledge in the art.

[0038] In addition, the features, operations or characteristics described in the specification can be combined in any appropriate manner to form various implementations. At the same time, the steps or actions in the method description can also be interchanged or adjusted in a manner that is obvious to those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a required sequence, unless otherwise specified that a certain sequence must be followed.

[0039] The serial numbers of the components in this document, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings).

[0040] With the development of multi-chip sealing technology, the size of the interposer will continue to increase, while the height and spacing of the bumps / solder joints at the bottom of the interposer will continue to decrease, and the requirements for the total thickness change of the interposer, the uniformity of the bump height, and the matching of the thermal expansion coefficient of the material will become increasingly higher. The oversized interposer will also have problems such as mismatching the thermal expansion coefficient with the packaging substrate material, which is very likely to cause reliability problems such as solder joint welding failure, which will seriously affect the subsequent process, resulting in a reduction in product yield.

[0041] In the present application, an interposer 1 and a three-dimensional packaging structure 001 are proposed, specifically, grooves are opened on the interposer 1. This structure can effectively solve reliability problems such as solder joint welding failure caused by the mismatch in thermal expansion coefficients between the interposer 1 and the solder joint and the packaging substrate 4 materials due to the increasing size of the interposer 1.

[0042] Embodiment 1

[0043] like Figure 1 As shown, in the embodiment of the present application, an interposer 1 is provided, which may include: a substrate 11 and a re-distribution layer 12 (ReDistribution Layer ， RDL layer).

[0044] The substrate 11 has a first surface ( Figure 1 The upper surface, or front surface) and the second surface ( Figure 1 The substrate 11 has a plurality of through holes extending from the first surface to the second surface, and each through hole is filled with a conductive material to form a conductive through hole 111.

[0045] The substrate 11 has a groove 2 extending from the first surface to the second surface, and the groove 2 divides the substrate 11 into a plurality of connection areas (or sub-interposers) separated by the groove. One connection area is configured to connect a chip 3, and the chip 3 is electrically connected to the conductive through hole 111 in the corresponding connection area.

[0046] The rewiring layer 12 is disposed on the second surface. The rewiring layer 12 is flexible and electrically connected to the conductive via 111 .

[0047] The conductive via 111 in one connection region is electrically connected to the conductive via 111 in another connection region through the rewiring layer 12, so as to interconnect the chip 3 corresponding to one connection region with another chip 3 corresponding to another connection region.

[0048] For example, the interposer 1 may be provided with a first solder joint 13 on the front side and a second solder joint 14 on the back side, and the interposer 1 is composed of a substrate 11 and a rewiring layer 12. The substrate 11 is provided with a conductive via 111 along its thickness direction, and the front side is bonded to the chip 3 through the first solder joint 13; the rewiring layer 12 is provided on the back side of the interposer 1, and the rewiring layer 12 is connected to the package substrate 4 through the second solder joint 14; multiple chips 3 are stacked on the front side of the interposer 1, and are interconnected through the front side line of the substrate 11 (such as the conductive via 111 and the first solder joint 13) and the rewiring layer 12 on the back side of the substrate 11; the groove 2 is cut from the front side of the interposer 1 to the rewiring layer 12 along the gap between the chips 3, and the interposer 1 is divided into multiple sub-interposers by the groove 2, and the bottom RDL layers of each sub-interposer are connected. The bottom RDL layer is electrically connected to the conductive via 111 and the chip 3.

[0049] Among them, along the thickness direction of the intermediate layer 1 ( Figure 1 Conductive through holes 111 are provided in the upper and lower directions to realize vertical interconnection of the interposer 1 and reduce the package height.

[0050] For example, the material of the substrate 11 can be silicon, or inorganic materials such as glass, SiC, GaN, etc. When the substrate 11 is a silicon wafer, the conductive via 111 can be called a through silicon via (TSV). The substrate 11 is provided with conductive vias 111 along its thickness direction, and the front side is bonded to the chip 3; the rewiring layer 12 can be connected to the packaging substrate 4 (such as a PCB board) to form an electrical interconnection. The chip 3 is stacked on the front side of the interposer 1, and the interconnection is achieved through the front line of the substrate 11 and the back rewiring layer 12.

[0051] By making a groove in the middle of the substrate 11, the substrate 11 can be used as a stress buffer, reducing the CTE mismatch problem caused by the oversized substrate 11 and the PCB interconnection and reliability process. Even if there is still stress caused by the mismatch of thermal expansion coefficient, the flexible rewiring layer 12 can further eliminate most of the stress and solve the warping problem of large-size packaging structure.

[0052] like Figure 1 and Figure 3 As shown, the groove 2 is cut from the front side of the interposer 1 to the rewiring layer 12 along the gap between the chips 3, so that the substrate 11 is cut into various sub-blocks, and the groove 2 becomes a stress buffer of the interposer 1 to the substrate 11 / package substrate 4. The shape of the groove 2 can be a straight groove or a V groove / trapezoidal groove.

[0053] like Figure 1 As shown, in one embodiment, the rewiring layer 12 may include a metal layer 121 or a metal conductive line and a dielectric layer 122 . The dielectric layer 122 is flexible. The metal layer 121 is electrically connected to the conductive via 111 . The material of the dielectric layer 122 may be resin.

[0054] The rewiring layer 12 is disposed on the back of the interposer 1, and its material includes metal conductive lines such as silver, copper, aluminum, gold, etc. and resin polyimide, epoxy resin, acrylic resin, etc. In the embodiment of the present application, resin material is used as the dielectric layer 122 to make the dielectric layer 122 flexible, and the metal layer 121 itself has ductility and elasticity, and can be combined with the dielectric layer 122, so that the rewiring layer 12 is flexible as a whole.

[0055] like Figure 1 As shown, in one embodiment, the interposer 1 may further include a plurality of first solder joints 13; the first solder joints 13 are disposed on the first surface and electrically connected to the conductive vias 111, and the first solder joints 13 are configured to be electrically connected to the chip 3. The front side of the interposer 1 may be bonded to the chip 3 via the first solder joints 13.

[0056] For example, the first solder joint 13 may include a first conductive bump 131 and a first solder ball 132. By providing the first solder ball 132 on the first conductive bump 131, the flexible interposer 1 and the chip 3 packaging module can be electrically connected through the first solder ball 132, and the connection between the interposer 1 and the chip 3 can be made more secure.

[0057] In some embodiments, the number of conductive vias 111 on each connection area is N, and the number of corresponding first solder joints 13 is M, and the ratio of N to M can be 1:1, n:1 or 1:n. According to the actual setting of the solder joints or pins of the connection chip 3, generally the first solder joints 13 and the solder joints of the chip 3 are one-to-one corresponding, but the conductive vias 111 and the first solder joints 13 may not be one-to-one corresponding. In this case, a connection layer such as an interconnection layer can be set to achieve the connection. Therefore, the interposer 1 may also include an interconnection layer, which is arranged on the first surface and located between the first solder joint 13 and the substrate 11, and the first solder joint 13 is electrically connected to the conductive via 111 through the interconnection layer. The interconnection layer may also include a metal layer and a dielectric layer, and the metal layer realizes the electrical connection between the first solder joint 13 and the conductive via 111.

[0058] like Figure 1 As shown, in one embodiment, the interposer 1 may further include a plurality of second solder joints 14; the second solder joints 14 are disposed on the surface of the rewiring layer 12 away from the substrate 11, the second solder joints 14 are electrically connected to the rewiring layer 12, and the second solder joints 14 are configured to be electrically connected to the package substrate 4. The rewiring layer 12 may be connected to the package substrate 4 through the second solder joints 14 to form electrical interconnection.

[0059] For example, the second solder joint 14 may include a second conductive bump 141 and a second solder ball 142 . The second solder joint 14 is formed on the back side of the redistribution layer 12 . The second solder ball 142 is disposed on the second conductive bump 141 . The interposer 1 and the packaging substrate 4 can be electrically connected via the second solder ball 142 .

[0060] The substrate 11 is provided with conductive through holes 111 along its thickness direction, and the front side is bonded to the chip 3; the rewiring layer 12 is provided on the back side of the flexible interposer 1, and the rewiring layer 12 can be connected to the package substrate 4; multiple chips 3 can be stacked on the front side of the interposer 1, and interconnected through the front line of the substrate 11 (such as the conductive through hole 111, the first solder joint 13) and the rewiring layer 12 on the back side of the substrate 11; the groove 2 is cut from the front side of the interposer 1 to the rewiring layer 12 along the gap between the chips 3, and the bottom RDL layer of each sub-interposer is connected. By making a groove in the middle of the substrate 11, the substrate 11 can be used as a stress buffer, reducing the problems such as welding failure or material delamination caused by the oversized substrate 11 in the interconnection and reliability process with the PCB. Even if there is still stress caused by the mismatch of thermal expansion coefficients, most of the stress can be further eliminated through the flexible rewiring layer 12 to solve the warping problem of large-size packaging structures.

[0061] Embodiment 2

[0062] like Figure 2 As shown, the embodiment of the present application further provides a three-dimensional packaging structure 001, which may include a plurality of chips 3 and the intermediate layer 1 described in the first embodiment.

[0063] The plurality of chips 3 at least include a first chip and a second chip; the first chip and the second chip are respectively mounted on corresponding connection areas on the interposer, and the first chip and the second chip are electrically connected to the rewiring layer through conductive vias 111 on the interposer.

[0064] The interposer 1 is composed of a substrate 11 and a rewiring layer 12. The substrate 11 is provided with conductive vias 111 along its thickness direction, and the front side can be bonded to the chip 3 through a first solder joint 13; the rewiring layer 12 is provided on the back side of the interposer 1, and the rewiring layer 12 is connected to the package substrate 4 through a second solder joint 14; multiple chips 3 are stacked on the front side of the interposer 1, and are interconnected through the front side line of the substrate 11 and the rewiring layer 12 on the back side of the substrate 11; the groove 2 is cut from the front side of the interposer 1 to the rewiring layer 12 along the gap between the chips 3, and the interposer 1 is divided into multiple sub-interposers (connection areas) by the groove 2, and the bottom surface RDL layers of each sub-interposer are connected. The bottom surface RDL layer is electrically connected to the conductive vias 111 and the chip 3, and the chips 3 are interconnected through the front side line of the substrate 11 and the back side rewiring layer 12, thereby maintaining signal transmission between the chips 3.

[0065] It should be noted that the three-dimensional packaging structure 001 provided in the embodiment of the present application may also include other chips such as a third chip and a fourth chip. Taking the third chip as an example, the third chip may be interconnected with any one of the first chip and the second chip; or interconnected with both the first chip and the second chip; or the third chip is not interconnected with the first chip and the second chip, or the third chip is interconnected with the fourth chip. Therefore, the three-dimensional packaging structure 001 does not limit the number of specific chips 3, nor does it limit the interconnection conditions therein, and at least ensures that the first chip is interconnected with the second chip.

[0066] In one embodiment, the first chip may be a memory chip, and the second chip may be a processing chip. The memory chip may be a memory chip using HBM, DRAM (Dynamic Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), etc.; the processing chip may be an XPU. The concept of XPU covers a variety of different processor technologies, including CPU, GPU, FPGA, ASIC, etc. These technologies are integrated into a unified architecture to meet specific computing needs.

[0067] like Figure 2 As shown, in one embodiment, the three-dimensional packaging structure 001 may further include a packaging substrate 4; the packaging substrate 4 may be made of an organic substrate or a glass substrate, such as a commonly used PCB (Printed Circuit Board). The packaging substrate 4 may be printed or deposited with a circuit, and solder joints / pads may be formed on the upper and lower surfaces. The interposer 1 may further include a plurality of second solder joints 14; the second solder joints 14 are disposed on the surface of the rewiring layer 12 away from the substrate 11, and the rewiring layer 12 is electrically connected to the packaging substrate 4 through the second solder joints 14.

[0068] In one embodiment, the three-dimensional packaging structure 001 may further include an insulating glue, which is disposed between the substrate 11 and the chip 3, and the insulating glue wraps the solder joints / pads electrically connected between the substrate 11 and the chip 3. The bottom filler layer can protect the pads / solder joints on the one hand, and can make the connection between the chip 3 and the interposer 1 more secure on the other hand.

[0069] The groove 2 is cut from the front side of the interposer 1 to the rewiring layer 12 along the gap between the chips 3, so that the substrate 11 is cut into various sub-blocks, and the groove 2 becomes a stress buffer of the interposer 1 to the substrate 11. There is a flexible metal conductive rewiring layer 12 between the substrate 11 and the package substrate 4. The flexible metal conductive rewiring layer 12 can electrically interconnect multiple substrates 11, and at the same time, the stress caused by CTE mismatch can be reduced.

[0070] The interposer 1 is electrically connected to the chip 3 by welding the first solder joint 13 to the chip 3, and the connection between the interposer 1 and the chip 3 is more secure. The interposer 1 and the chip 3 can be filled with glue. The glue can protect the pads and make the connection between the chip 3 and the interposer 1 more secure. The interposer 1 can be electrically connected to the package substrate 4 by the second solder joint 14. The interposer 1 is provided with conductive through holes 111 along its thickness direction. The conductive through holes 111 can realize the vertical electrical interconnection of the flexible interposer 1 and effectively reduce the package height.

[0071] In addition, the three-dimensional packaging structure 001 of this embodiment also corresponds to the technical effect of the intermediate layer 1 of the first embodiment, which will not be described again here.

[0072] Embodiment 3

[0073] like Figure 4 and Figure 5 As shown, the embodiment of the present application further provides a method for manufacturing an interposer 1, which can be used to manufacture the interposer 1 described in the first embodiment, and may include:

[0074] Step 1: Figure 4 (A) and Figure 5 As shown in (A), a substrate 11 is provided; wherein the substrate 11 has a first surface and a second surface opposite to each other; the substrate 11 has a plurality of through holes extending from the first surface to the second surface, each through hole is filled with a conductive material to form a conductive through hole 111; a rewiring layer 12 is arranged on the second surface, the rewiring layer 12 is flexible, and the rewiring layer 12 is electrically connected to the conductive through hole 111.

[0075] Step 2, patterning the substrate 11 to form a groove 2; wherein the groove 2 runs from the first surface to the second surface, and the groove 2 divides the substrate 11 into a plurality of connection areas separated by the grooves, and one connection area is configured to connect a chip 3, and the chip 3 is electrically connected to the conductive through hole 111 in the corresponding connection area.

[0076] In step 1, the substrate 11 may be prefabricated with conductive vias 111 and a rewiring layer 12, and may also be prefabricated with first solder joints 13 and second solder joints 14. The substrate 11 may also be prefabricated using the following steps:

[0077] Step 100 : providing a substrate 11 , and performing patterning on the substrate 11 to form a plurality of through holes penetrating from a first surface to a second surface.

[0078] Step 101 : Fill the through hole with a conductive material to form a conductive through hole 111 .

[0079] Step 102 : forming a plurality of first solder joints 13 on the first surface of the substrate 11 .

[0080] Step 103 : forming a redistribution layer 12 on the second surface of the substrate 11 .

[0081] Step 104: forming a plurality of second solder joints 14 on the surface of the redistribution layer 12 away from the substrate 11. The order of step 102 and step 103 is not limited.

[0082] In step 2, if Figure 4 (C) and Figure 5 As shown in (C), according to different requirements, the groove 2 can be formed into a straight groove or a V groove. For example, a straight groove can be formed by dry etching / laser grooving / mechanical grooving / wet etching, etc. A V groove can be formed by wet etching.

[0083] The following provides two specific implementation methods for different groove 2 forms; the process scheme for straight groove is as follows Figure 4 As shown, the specific steps are as follows:

[0084] Step 310 , using a temporary bonding method, the interposer 1 is bonded to the carrier board 51 by a temporary bonding adhesive 52 .

[0085] Step 320, such as Figure 4 As shown in (A) and (B) in FIG. 1 , a photoresist 53 is coated on the interposer 1 , and the photoresist 53 where the photolithography groove 54 is required is removed by exposure and development.

[0086] Step 330, such as Figure 4 As shown in (C) in FIG. 1 , the depth of the groove is opened to the redistribution layer 12 by dry etching / laser grooving / mechanical grooving / wet etching or the like.

[0087] Step 340, such as Figure 4 As shown in (D) in FIG. 1 , the photoresist 53 on the surface of the interposer 1 is removed by wet cleaning.

[0088] The process scheme for opening V groove is as follows: Figure 5 As shown, the specific steps are as follows:

[0089] Step 410 , using a temporary bonding method, the interposer 1 is bonded to the carrier board 51 by a temporary bonding adhesive 52 .

[0090] Step 420, such as Figure 5 As shown in (A) and (B) in FIG. 1 , a photoresist 53 is coated on the interposer 1 , and the photoresist 53 where the photolithography groove 54 is required is removed by exposure and development.

[0091] Step 430, such as Figure 5As shown in (C) in FIG. 1 , the groove is opened to the depth of the rewiring layer 12 in the form of a V-shaped groove 55 by wet etching.

[0092] Step 440, such as Figure 5 As shown in (D) in FIG. 1 , the photoresist 53 on the surface of the interposer 1 is removed by wet cleaning.

[0093] The manufacturing method of this embodiment can prepare the interposer 1 of the first embodiment, and has the corresponding technical effects of the interposer 1 of the first embodiment, which will not be described again here.

[0094] Embodiment 4

[0095] like Figure 6 As shown, the embodiment of the present application further provides a method for manufacturing a three-dimensional packaging structure 001, which can be used to prepare the three-dimensional packaging structure 001 described in the second embodiment, and may include:

[0096] Step 10: Prepare the intermediary layer 1 by using the method for manufacturing the intermediary layer 1 described in the third embodiment.

[0097] Step 20, mount at least two chips 3 to the connection area, the at least two chips 3 include a first chip and a second chip, the first chip and the second chip are electrically connected to the redistribution layer 12 through the conductive through-hole 111, for example, by welding to connect the chip solder joints to the conductive through-hole 111, such as welding the chip solder joints to the first solder joints 13.

[0098] Step 30, mount the interposer 1 with the chip 3 to the packaging substrate 4, and electrically connect the packaging substrate 4 to the rewiring layer 12, for example, by welding to connect the solder joints of the packaging substrate 4 to the rewiring layer 12, such as welding the second solder joints 14 to the solder joints of the packaging substrate 4.

[0099] A specific implementation method is provided below. Figure 5 As shown, the manufacturing method of the above-mentioned three-dimensional packaging structure 001 may include:

[0100] Step 510, such as Figure 4 (A) and Figure 5 As shown in (A) of FIG. 5 , the interposer 1 is bonded to the carrier board 51 by a temporary bonding adhesive 52 in a temporary bonding manner.

[0101] Step 520, such as Figure 6 As shown in (A) in the figure, Figure 4 or Figure 5 In the manner shown in FIG. 1 , grooves are opened in the interposer 1 so that the interposer 1 is divided into different sub-blocks (connection areas).

[0102] Step 530, such as Figure 6As shown in (B) in FIG. 1 , the chip 3 is mounted on each sub-interposer (connection area) through the first solder joint 13 on the front side of the interposer 1 .

[0103] Step 540, such as Figure 6 As shown in (C), the carrier plate 51 is removed by debonding, and the temporary bonding adhesive 52 is removed by wet cleaning. After the interposer 1 is cleaned, the substrate 11 is diced.

[0104] Step 550, such as Figure 6 As shown in (D) in FIG. 1 , the sliced ​​substrate 11 is mounted on the packaging substrate 4 through the second solder joint 14 on the back side of the interposer 1 .

[0105] The manufacturing method of this embodiment can prepare the three-dimensional packaging structure 001 of the second embodiment, and has the corresponding technical effects of the three-dimensional packaging structure 001 of the second embodiment, which will not be described again here.

[0106] In summary, the interposer 1 and its manufacturing method, the three-dimensional packaging structure 001 and its manufacturing method provided by the present application are that the substrate 11 is provided with a conductive through hole 111 along its thickness direction, and the front side is bonded to the chip 3 through a solder joint; the rewiring layer 12 is provided on the back side of the flexible interposer 1, and the rewiring layer 12 is connected to the packaging substrate 4 through a solder joint; a plurality of chips 3 are stacked on the front side of the interposer 1, and are interconnected through the front line of the substrate 11 and the rewiring layer 12 on the back side of the substrate 11; the groove 2 is cut from the front side of the interposer 1 to the rewiring layer 12 along the gap between the chips 3, and the bottom RDL layer of each sub-interposer is connected. By making a groove in the middle of the substrate 11, the substrate 11 can be provided with a stress buffer, and the stress caused by the mismatch of the thermal expansion coefficients between the substrate 11, the bottom bump and the packaging substrate 4, and the welding failure and material delamination caused by the stress, etc., can be reduced. Even if there is still stress caused by the mismatch of the thermal expansion coefficient, most of the stress can be further eliminated through the flexible rewiring layer 12, and the warping problem of the large-size packaging structure can be solved.

[0107] Those skilled in the art will appreciate that all or part of the functions of the various methods in the above-mentioned embodiments can be implemented by hardware or by computer programs. When all or part of the functions in the above-mentioned embodiments are implemented by computer programs, the program can be stored in a computer-readable storage medium, and the storage medium can include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to implement the above-mentioned functions. For example, the program is stored in the memory of the device, and when the program in the memory is executed by the processor, all or part of the above-mentioned functions can be implemented. In addition, when all or part of the functions in the above-mentioned embodiments are implemented by computer programs, the program can also be stored in a storage medium such as a server, another computer, disk, optical disk, flash disk or mobile hard disk, and can be downloaded or copied and saved in the memory of the local device, or the system of the local device is updated, and when the program in the memory is executed by the processor, all or part of the functions in the above-mentioned embodiments can be implemented.

[0108] This document is described with reference to various exemplary embodiments. However, those skilled in the art will recognize that changes and modifications may be made to the exemplary embodiments without departing from the scope of this document. For example, various operating steps and components for performing the operating steps may be implemented in different ways (e.g., one or more steps may be deleted, modified, or incorporated into other steps) depending on the specific application or considering any number of cost functions associated with the operation of the system.

[0109] Although the principles of this invention have been shown in various embodiments, many modifications of structures, arrangements, proportions, elements, materials and components particularly suitable for specific environments and operational requirements can be used without departing from the principles and scope of this invention. The above modifications and other changes or amendments will be included in the scope of this invention.

[0110] The foregoing specific description has been described with reference to various embodiments. However, those skilled in the art will recognize that various modifications and changes can be made without departing from the scope of the present disclosure. Therefore, the consideration of the present disclosure will be illustrative rather than restrictive, and all these modifications will be included in its scope. Similarly, the advantages, other advantages and solutions to the problems of various embodiments have been described above. However, the benefits, advantages, solutions to the problems and any elements that can produce these, or make them more clear, should not be interpreted as critical, necessary or necessary. The term "include" and any other variants used in this article are all non-exclusive inclusions, so that the process, method, article or device including the list of elements not only includes these elements, but also includes other elements that are not explicitly listed or do not belong to the process, method, system, article or device. In addition, the term "coupled" and any other variants used in this article refer to physical connections, electrical connections, magnetic connections, optical connections, communication connections, functional connections and / or any other connections.

[0111] Those skilled in the art will appreciate that many changes may be made to the details of the above-described embodiments without departing from the basic principles of the invention. Therefore, the scope of the present invention should be determined solely by the claims.

Claims

1. An interposer, characterized in that: include: A substrate (11) and a redistribution layer (12); The substrate (11) has a first surface and a second surface opposite to each other, and the substrate (11) has a plurality of through holes extending from the first surface to the second surface, each of the through holes being filled with a conductive material to form a conductive through hole (111); The substrate (11) has a groove (2) extending from the first surface to the second surface, the groove (2) dividing the substrate (11) into a plurality of connection areas separated by the groove, one of the connection areas being configured to connect a chip (3), the chip (3) being electrically connected to the conductive through hole (111) in the corresponding connection area; The rewiring layer (12) is arranged on the second surface, the rewiring layer (12) is flexible, and is electrically connected to the conductive through hole (111); The conductive via (111) in one of the connection areas is electrically connected to the conductive via (111) in another of the connection areas through the rewiring layer (12), so as to interconnect the chip (3) corresponding to one of the connection areas with another chip (3) corresponding to another of the connection areas.

2. The interposer according to claim 1, wherein: The rewiring layer (12) comprises a metal layer (121) and a dielectric layer (122); the dielectric layer (122) is flexible; the metal layer (121) is electrically connected to the conductive through hole (111); and the material of the dielectric layer (122) is resin.

3. The interposer according to claim 1, wherein: The intermediate layer (1) further comprises a plurality of first welding points (13); The first solder joint (13) is arranged on the first surface and is electrically connected to the conductive through hole (111), and the first solder joint (13) is configured to be electrically connected to the chip (3).

4. The interposer according to claim 1, wherein: The intermediate layer (1) further comprises a plurality of second welding points (14); The second solder joint (14) is arranged on a surface of the rewiring layer (12) away from the substrate (11), the second solder joint (14) is electrically connected to the rewiring layer (12), and the second solder joint (14) is configured to be electrically connected to the packaging substrate (4).

5. A three-dimensional packaging structure, characterized in that: Comprising a plurality of chips (3) and an interposer (1) as claimed in claims 1 to 4; The plurality of chips (3) include at least a first chip and a second chip; The first chip and the second chip are respectively mounted on the corresponding connection areas on the intermediary layer, and the first chip and the second chip are electrically connected to the rewiring layer (12) through the conductive through-holes (111) on the intermediary layer.

6. The three-dimensional packaging structure according to claim 5, characterized in that: The first chip is a storage chip, and the second chip is a processing chip.

7. The three-dimensional packaging structure according to claim 5, characterized in that: The three-dimensional packaging structure (001) also includes a packaging substrate (4); The intermediate layer (1) further comprises a plurality of second welding points (14); The second solder joint (14) is arranged on a surface of the rewiring layer (12) away from the substrate (11), the second solder joint (14) is electrically connected to the rewiring layer (12), and the second solder joint (14) is electrically connected to the packaging substrate (4).

8. The three-dimensional packaging structure according to claim 5, characterized in that: The three-dimensional packaging structure (001) further comprises insulating glue, wherein the insulating glue is arranged between the substrate (11) and the chip (3), and the insulating glue wraps the solder joints electrically connected between the substrate (11) and the chip (3).

9. A method for manufacturing an intermediate layer, characterized in that: include: A substrate (11) is provided; wherein the substrate (11) has a first surface and a second surface opposite to each other; the substrate (11) has a plurality of through holes extending from the first surface to the second surface, each of the through holes being filled with a conductive material to form a conductive through hole (111); a rewiring layer (12) is arranged on the second surface, the rewiring layer (12) is flexible, and the rewiring layer (12) is electrically connected to the conductive through hole (111); The substrate (11) is patterned to form a groove (2); wherein the groove (2) runs from the first surface to the second surface, and the groove (2) divides the substrate (11) into a plurality of connection areas separated by the grooves, and one of the connection areas is configured to connect a chip (3), and the chip (3) is electrically connected to the conductive through hole (111) in the corresponding connection area.

10. A method for manufacturing a three-dimensional packaging structure, characterized in that: include: The intermediary layer (1) is prepared by adopting the method for manufacturing the intermediary layer (1) according to claim 9; Mounting at least two chips (3) to the corresponding connection areas, the at least two chips (3) comprising a first chip and a second chip, the first chip and the second chip being electrically connected to the rewiring layer (12) via the conductive through-hole (111); The interposer (1) with the chip (3) is mounted on a packaging substrate (4), and the packaging substrate (4) is electrically connected to the redistribution layer (12).

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