Optimal control method and device for staggered thyristor modular multilevel converter

Abstract

The invention relates to the technical field of flexible direct-current power transmission, and particularly provides an optimal control method and device for an interlaced thyristor modular multilevel converter, and the method comprises the steps: obtaining an upper / lower bridge arm insertion index of the interlaced thyristor modular multilevel converter; correcting the insertion index of the upper / lower bridge arm by using the feed-forward gain of the working state change of the staggered thyristor modular multilevel converter; based on the corrected upper / lower bridge arm insertion index, determining the number of upper / lower bridge arm input working sub-modules of the staggered thyristor modular multilevel converter; on the basis of the number of working sub-modules put into the upper / lower bridge arm of the interleaved thyristor modular multilevel converter, a capacitor voltage balance algorithm is adopted to generate switching signals for controlling the sub-modules in the upper / lower bridge arm of the interleaved thyristor modular multilevel converter. According to the scheme, by changing the working principle of the redundant module and reducing the capacitor voltage reference value, the average conduction duration of the switching device with serious loss is reduced, and then loss distribution optimization is achieved, and the total loss is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of flexible direct current power transmission, and in particular to an optimization control method and device for a staggered thyristor modular multi-level converter. Background Art

[0002] In the context of new power system construction, flexible DC transmission technology has become an increasingly important technical means to achieve large-scale new energy transmission and flexible interconnection of regional power grids. On the basis of achieving DC fault self-clearing, further improving the operating efficiency and economy of flexible DC transmission systems and reducing equipment costs and losses are one of the future development trends of flexible DC transmission.

[0003] Modular multilevel converters based on interleaved thyristors provide a new technical direction for achieving self-clearing of DC faults and reducing the proportion of full-bridge sub-modules. They have good engineering application prospects, but there is still a lack of effective measures to reduce device losses. Summary of the invention

[0004] In order to overcome the above defects, the present invention proposes an optimization control method and device for an interleaved thyristor modular multi-level converter.

[0005] In a first aspect, a method for optimizing control of an interleaved thyristor modular multilevel converter is provided, wherein the method for optimizing control of the interleaved thyristor modular multilevel converter comprises:

[0006] Get the upper / lower bridge arm insertion index of the interleaved thyristor modular multilevel converter;

[0007] The upper / lower bridge arm insertion index is corrected by using the feedforward gain of the working state change of the interleaved thyristor modular multi-level converter to obtain a corrected upper / lower bridge arm insertion index;

[0008] Determine the number of sub-modules of the upper / lower bridge arms of the interleaved thyristor modular multi-level converter put into operation based on the modified upper / lower bridge arm insertion index;

[0009] Based on the number of submodules put into operation in the upper / lower bridge arms of the interleaved thyristor modular multilevel converter, a capacitor voltage balance algorithm is used to generate switching signals for controlling the submodules in the upper / lower bridge arms of the interleaved thyristor modular multilevel converter.

[0010] Preferably, the upper / lower bridge arm insertion index of the interleaved thyristor modular multi-level converter is as follows:

[0011] n u,l =(U dc_ref / 2me j_ref -u comj_ref ) / Nu c_ref

[0012] In the above formula, n u,l Insert the index, U, for the upper / lower bridge arm of the interleaved thyristor modular multilevel converter dc_ref is the reference value of the DC output voltage of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter, e j_ref is the upper / lower differential mode voltage reference value of the interleaved thyristor modular multilevel converter, u comj_ref is the common mode voltage reference value of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter, N is the number of submodules in the bridge arm, u c_ref is the submodule capacitor voltage reference value.

[0013] Furthermore, the process of obtaining the upper / lower differential mode voltage reference value of the interleaved thyristor modular multi-level converter includes:

[0014] The active power reference value of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter and the reactive power reference value of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter or the reference value of the DC output voltage of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter are used as inputs of the outer loop power controller and the inner loop current controller to obtain the upper / lower differential mode voltage reference value of the interleaved thyristor modular multilevel converter output by the inner loop current controller.

[0015] Furthermore, the process of obtaining the common mode voltage reference value of the upper / lower bridge arm of the interleaved thyristor modular multi-level converter includes:

[0016] The upper / lower arm current and circulating current reference values ​​of the interleaved thyristor modular multilevel converter are used as inputs of the inner loop circulating current suppressor to obtain the upper / lower arm common mode voltage reference values ​​of the interleaved thyristor modular multilevel converter output by the inner loop circulating current suppressor.

[0017] Preferably, the upper / lower bridge arm insertion index of the interleaved thyristor modular multi-level converter is as follows:

[0018] n u,l =K0 mK1cos(ωt+θ1)-K2cos(2ωt+θ2)

[0019] In the above formula, n u,l is the upper / lower arm insertion index of the interleaved thyristor modular multilevel converter, K0, K1 and K2 are the DC component, fundamental frequency component and circulating current compensation voltage modulation index respectively, ω is the fundamental angular frequency, t is the time, θ1 is the initial phase of the fundamental frequency component, and θ2 is the initial phase of the double frequency component.

[0020] Furthermore, the DC component, fundamental frequency component and circulating current compensation voltage modulation index satisfy:

[0021]

[0022] Preferably, the modified upper / lower bridge arm insertion index is as follows:

[0023]

[0024] In the above formula, n u,l_new To correct the upper / lower bridge arm insert index, n u,l is the upper / lower bridge arm insertion index of the interleaved thyristor modular multilevel converter, K is the feedforward gain, K0, K1 and K2 are the DC component, fundamental frequency component and circulating current compensation voltage modulation index respectively, K h is the submodule health rate.

[0025] Furthermore, the submodule health rate is as follows:

[0026]

[0027] In the above formula, N f is the number of healthy submodules in the bridge arm, and N is the number of submodules in the bridge arm.

[0028] Furthermore, the number of sub-modules put into operation in the upper / lower bridge arms of the staggered thyristor modular multi-level converter is as follows:

[0029] N u,l_new =N·n u,l_new

[0030] In the above formula, N u,l_new is the number of submodules put into operation in the upper / lower bridge arms of the interleaved thyristor modular multi-level converter, and N is the number of submodules in the bridge arm.

[0031] In a second aspect, an optimization control device for an interleaved thyristor modular multilevel converter is provided, wherein the optimization control device for an interleaved thyristor modular multilevel converter comprises:

[0032] An acquisition module, used for acquiring an upper / lower bridge arm insertion index of an interleaved thyristor modular multi-level converter;

[0033] A correction module, used for correcting the upper / lower bridge arm insertion index by using the feedforward gain of the working state change of the interleaved thyristor modular multi-level converter to obtain a corrected upper / lower bridge arm insertion index;

[0034] A determination module, configured to determine the number of sub-modules of the upper / lower bridge arms of the interleaved thyristor modular multi-level converter put into operation based on the modified upper / lower bridge arm insertion index;

[0035] The control module is used to generate a switching signal for controlling the submodules in the upper / lower bridge arms of the interleaved thyristor modular multilevel converter by adopting a capacitor-voltage balance algorithm based on the number of submodules put into operation in the upper / lower bridge arms of the interleaved thyristor modular multilevel converter.

[0036] Preferably, the upper / lower bridge arm insertion index of the interleaved thyristor modular multi-level converter is as follows:

[0037] n u,l =(U dc_ref / 2me j_ref -u comj_ref ) / Nu c_ref

[0038] In the above formula, n u,l Insert the index, U, for the upper / lower bridge arm of the interleaved thyristor modular multilevel converter dc_ref is the reference value of the DC output voltage of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter, e j_ref is the upper / lower differential mode voltage reference value of the interleaved thyristor modular multilevel converter, u comj_ref is the common mode voltage reference value of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter, N is the number of submodules in the bridge arm, u c_ref is the submodule capacitor voltage reference value.

[0039] Furthermore, the process of obtaining the upper / lower differential mode voltage reference value of the interleaved thyristor modular multi-level converter includes:

[0040] The active power reference value of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter and the reactive power reference value of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter or the reference value of the DC output voltage of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter are used as inputs of the outer loop power controller and the inner loop current controller to obtain the upper / lower differential mode voltage reference value of the interleaved thyristor modular multilevel converter output by the inner loop current controller.

[0041] Furthermore, the process of obtaining the common mode voltage reference value of the upper / lower bridge arm of the interleaved thyristor modular multi-level converter includes:

[0042] The upper / lower arm current and circulating current reference values ​​of the interleaved thyristor modular multilevel converter are used as inputs of the inner loop circulating current suppressor to obtain the upper / lower arm common mode voltage reference values ​​of the interleaved thyristor modular multilevel converter output by the inner loop circulating current suppressor.

[0043] Preferably, the upper / lower bridge arm insertion index of the interleaved thyristor modular multi-level converter is as follows:

[0044] n u,l=K0 mK1cos(ωt+θ1)-K2cos(2ωt+θ2)

[0045] In the above formula, n u,l is the upper / lower arm insertion index of the interleaved thyristor modular multilevel converter, K0, K1 and K2 are the DC component, fundamental frequency component and circulating current compensation voltage modulation index respectively, ω is the fundamental angular frequency, t is the time, θ1 is the initial phase of the fundamental frequency component, and θ2 is the initial phase of the double frequency component.

[0046] Furthermore, the DC component, fundamental frequency component and circulating current compensation voltage modulation index satisfy:

[0047]

[0048] Preferably, the modified upper / lower bridge arm insertion index is as follows:

[0049]

[0050] In the above formula, n u,l_new To correct the upper / lower bridge arm insert index, n u,l is the upper / lower bridge arm insertion index of the interleaved thyristor modular multilevel converter, K is the feedforward gain, K0, K1 and K2 are the DC component, fundamental frequency component and circulating current compensation voltage modulation index respectively, K h is the submodule health rate.

[0051] Furthermore, the submodule health rate is as follows:

[0052]

[0053] In the above formula, N f is the number of healthy submodules in the bridge arm, and N is the number of submodules in the bridge arm.

[0054] Furthermore, the number of sub-modules put into operation in the upper / lower bridge arms of the staggered thyristor modular multi-level converter is as follows:

[0055] N u,l_new =N·n u,l_new

[0056] In the above formula, N u,l_new is the number of submodules put into operation in the upper / lower bridge arms of the interleaved thyristor modular multi-level converter, and N is the number of submodules in the bridge arm.

[0057] In a third aspect, a computer device is provided, comprising: one or more processors;

[0058] The processor is configured to execute one or more programs;

[0059] When the one or more programs are executed by the one or more processors, the optimization control method of the interleaved thyristor modular multi-level converter is implemented.

[0060] In a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed, the optimization control method of the interleaved thyristor modular multi-level converter is implemented.

[0061] The above one or more technical solutions of the present invention have at least one or more of the following beneficial effects:

[0062] The present invention provides an optimization control method and device for an interleaved thyristor modular multilevel converter, comprising: obtaining an upper / lower bridge arm insertion index of an interleaved thyristor modular multilevel converter; using a feedforward gain of a change in the working state of the interleaved thyristor modular multilevel converter to correct the upper / lower bridge arm insertion index to obtain a corrected upper / lower bridge arm insertion index; determining the number of submodules of the upper / lower bridge arms of the interleaved thyristor modular multilevel converter put into operation based on the corrected upper / lower bridge arm insertion index; based on the number of submodules of the upper / lower bridge arms of the interleaved thyristor modular multilevel converter put into operation, using a capacitor voltage balance algorithm to generate a switch signal for controlling the submodules in the upper / lower bridge arms of the interleaved thyristor modular multilevel converter. The technical solution provided by the present invention reduces the average conduction time of the switch device with serious loss by changing the working principle of the redundant module and reducing the capacitor voltage reference value, increases the on-state loss of the originally minor device, realizes the optimization of the loss distribution, and then reduces the overall loss of the converter under the inverter working condition, and the loss reduction can increase with the increase of the submodule redundancy. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 1 is a schematic flow chart of main steps of an optimization control method for an interleaved thyristor modular multi-level converter according to an embodiment of the present invention;

[0064] Figure 2 1 is a schematic diagram of the structure of an interleaved thyristor modular multi-level converter according to an embodiment of the present invention;

[0065] Figure 3 is a schematic diagram of optimization control of an interleaved thyristor modular multi-level converter according to an embodiment of the present invention;

[0066] Figure 4 is a comparison diagram of the upper bridge arm insertion index of phase a of the conventional method and the method of the present invention under a typical case of an embodiment of the present invention;

[0067] Figure 5 Schematic diagram of different working modes and bridge arm currents of the interleaved thyristor modular multi-level converter according to an embodiment of the present invention;

[0068] Figure 6 is a waveform diagram of the current flowing through T2 before and after optimization of an embodiment of the present invention;

[0069] Figure 7 3 is a loss comparison diagram of the power semiconductor device before and after optimization according to an embodiment of the present invention. DETAILED DESCRIPTION

[0070] The specific implementation modes of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0071] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0072] As disclosed in the background technology, in the context of new power system construction, flexible DC transmission technology has become an increasingly important technical means to achieve large-scale new energy transmission and flexible interconnection of regional power grids. On the basis of achieving DC fault self-clearing, further improving the operating efficiency and economy of the flexible DC transmission system and reducing equipment cost and loss are one of the future development trends of flexible DC transmission.

[0073] Modular multilevel converters based on interleaved thyristors provide a new technical direction for achieving self-clearing of DC faults and reducing the proportion of full-bridge sub-modules. They have good engineering application prospects, but there is still a lack of effective measures to reduce device losses.

[0074] In order to improve the above problems, the present invention provides an optimization control method and device for an interleaved thyristor modular multilevel converter, comprising: obtaining an upper / lower bridge arm insertion index of the interleaved thyristor modular multilevel converter; correcting the upper / lower bridge arm insertion index by using a feedforward gain of a working state change of the interleaved thyristor modular multilevel converter to obtain a corrected upper / lower bridge arm insertion index; determining the number of upper / lower bridge arm working submodules of the interleaved thyristor modular multilevel converter based on the corrected upper / lower bridge arm insertion index; and based on the number of upper / lower bridge arm working submodules of the interleaved thyristor modular multilevel converter, using a capacitor voltage balance algorithm to generate a switching signal for controlling a submodule in the upper / lower bridge arm of the interleaved thyristor modular multilevel converter. The technical solution provided by the present invention reduces the average conduction time of switching devices with serious losses by changing the working principle of the redundant module and lowering the capacitor voltage reference value, increases the conduction loss of the originally light devices, realizes loss distribution optimization, and further reduces the overall loss of the converter under inverter conditions. The loss reduction can increase with the increase of sub-module redundancy.

[0075] The above scheme is described in detail below.

[0076] Example 1

[0077] See attached Figure 1 , Figure 1 FIG. 1 is a flow chart showing the main steps of an optimization control method for a staggered thyristor modular multi-level converter according to an embodiment of the present invention. Figure 1 As shown, the optimization control method of the interleaved thyristor modular multi-level converter in the embodiment of the present invention mainly includes the following steps:

[0078] Step S101: obtaining an upper / lower bridge arm insertion index of an interleaved thyristor modular multi-level converter;

[0079] Step S102: correcting the upper / lower bridge arm insertion index by using the feedforward gain of the working state change of the interleaved thyristor modular multi-level converter to obtain a corrected upper / lower bridge arm insertion index;

[0080] Step S103: determining the number of sub-modules of the upper / lower bridge arms of the interleaved thyristor modular multi-level converter put into operation based on the modified upper / lower bridge arm insertion index;

[0081] Step S104: Based on the number of submodules in operation in the upper / lower bridge arms of the interleaved thyristor modular multilevel converter, a capacitor-voltage balance algorithm is used to generate switching signals for controlling the submodules in the upper / lower bridge arms of the interleaved thyristor modular multilevel converter.

[0082] In this embodiment, the upper / lower bridge arm insertion index of the interleaved thyristor modular multi-level converter is as follows:

[0083] n u,l =(U dc_ref / 2me j_ref -u comj_ref ) / Nu c_ref

[0084] In the above formula, n u,l Insert the index, U, for the upper / lower bridge arm of the interleaved thyristor modular multilevel converter dc_ref is the reference value of the DC output voltage of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter, e j_ref is the upper / lower differential mode voltage reference value of the interleaved thyristor modular multilevel converter, u comj_ref is the common mode voltage reference value of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter, N is the number of submodules in the bridge arm, u c_ref is the submodule capacitor voltage reference value.

[0085] In one embodiment, the process of obtaining the upper / lower differential mode voltage reference value of the interleaved thyristor modular multi-level converter includes:

[0086] The active power reference value of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter and the reactive power reference value of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter or the reference value of the DC output voltage of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter are used as inputs of the outer loop power controller and the inner loop current controller to obtain the upper / lower differential mode voltage reference value of the interleaved thyristor modular multilevel converter output by the inner loop current controller.

[0087] In one embodiment, the process of obtaining the common mode voltage reference value of the upper / lower bridge arm of the interleaved thyristor modular multi-level converter includes:

[0088] The upper / lower arm current and circulating current reference values ​​of the interleaved thyristor modular multilevel converter are used as inputs of the inner loop circulating current suppressor to obtain the upper / lower arm common mode voltage reference values ​​of the interleaved thyristor modular multilevel converter output by the inner loop circulating current suppressor.

[0089] In this embodiment, the upper / lower bridge arm insertion index of the interleaved thyristor modular multi-level converter is as follows:

[0090] n u,l =K0 mK1cos(ωt+θ1)-K2cos(2ωt+θ2)

[0091] In the above formula, n u,l is the upper / lower arm insertion index of the interleaved thyristor modular multilevel converter, K0, K1 and K2 are the DC component, fundamental frequency component and circulating current compensation voltage modulation index respectively, ω is the fundamental angular frequency, t is the time, θ1 is the initial phase of the fundamental frequency component, and θ2 is the initial phase of the double frequency component.

[0092] Generally, K0 is less than 0.5 to achieve a certain redundancy to handle submodule failures; K1 is not greater than K0 because the half-bridge submodule cannot output a negative level; K2 is generally a very small value compared to K1 and K0, so the DC component, base frequency component and circulating current compensation voltage modulation index meet the following requirements:

[0093]

[0094] In this embodiment, the modified upper / lower bridge arm insertion index is as follows:

[0095]

[0096] In the above formula, n u,l_new To correct the upper / lower bridge arm insert index, n u,lis the upper / lower bridge arm insertion index of the interleaved thyristor modular multilevel converter, K is the feedforward gain, K0, K1 and K2 are the DC component, fundamental frequency component and circulating current compensation voltage modulation index respectively, K h is the submodule health rate.

[0097] In one embodiment, the submodule health rate is as follows:

[0098]

[0099] In the above formula, N f is the number of healthy submodules in the bridge arm, and N is the number of submodules in the bridge arm.

[0100] In one embodiment, the number of sub-modules in operation of the upper / lower bridge arms of the interleaved thyristor modular multi-level converter is as follows:

[0101] N u,l_new =N·n u,l_new

[0102] In the above formula, N u,l_new is the number of submodules put into operation in the upper / lower bridge arms of the interleaved thyristor modular multi-level converter, and N is the number of submodules in the bridge arm.

[0103] In a specific embodiment, the interleaved thyristor modular multi-level converter is as follows: Figure 2 As shown in Figure 2, the optimization control principle of the interleaved thyristor modular multilevel converter is as follows: Figure 3 As shown, it includes traditional control links such as outer loop power control, inner loop current control, inner loop current suppression, submodule modulation (NLM) and capacitor voltage balancing. The method proposed in the present invention adds a feedforward gain coefficient to the traditional modulation link of the submodule, corrects the number of submodule inputs in real time according to the MMC operating status, changes the original redundant module working principle to reduce the capacitor voltage reference value, and then reduces the average conduction time of the IGBT at the bottom of the submodule, which can achieve loss distribution optimization without changing the original state of the system and reduce the total loss.

[0104] The method of the present invention is implemented by: firstly setting the given active power P ref , reactive power Q ref Or DC voltage U dc_ref Input to the outer loop power controller to obtain the d-axis current reference value i d_ref and q-axis current reference value i q_ref , and then the d-axis current reference value i d_ref and q-axis current reference value i q_ref After inputting into the inner loop current controller, the bridge arm differential mode voltage reference value e is obtained. j_ref ; The measured three-phase current i uj , lower arm three-phase current ilj and the circulating current reference value i c_ref After inputting to the inner loop current suppressor, the bridge arm common mode voltage reference value u is obtained. comj_ref ; Then in the submodule modulation link, the upper and lower bridge arm differential voltages, common mode voltages and DC voltage reference values ​​are combined to form the upper bridge arm voltage reference value u u_ref and the lower bridge arm voltage reference value u l_ref , divided by the total voltage Nu of the bridge arm capacitor c_ref Then we get the upper and lower bridge arm insertion index n under the traditional NLM u,l ; Further, n u,l Multiplying by the feedforward gain K which changes with the working state of the MMC, the modified bridge arm insertion index n is obtained. u,l_new ; Set n u,l_new Multiply by the total number of bridge arm submodules N to get the number of corrected submodules N put into operation in the upper and lower bridge arms u,l_new ; Finally, the switching signal of each sub-module is determined through the capacitor voltage balance algorithm.

[0105] In a specific embodiment, K h =100%, α=10%, m=0.9, K2=0.02, the comparison of insertion index under the traditional method (classical) and the modified method (modified) is as follows: Figure 4 As shown, under the method of the present invention, the insertion index is corrected in real time and can reach 1, which means that more redundant sub-modules are invested to share the voltage, thereby reducing the base value of the sub-module capacitor voltage.

[0106] Figure 5 Schematic diagram of different working modes and bridge arm current of staggered thyristor MMC submodule. T1-T4 are IGBTs in the submodule, the average conduction time of each device is T1-T4, and D1-D4 are diodes in the submodule. Figure 5 As shown in the figure, after the MMC power is selected, the bridge arm current cannot be changed. Therefore, the factors affecting the loss distribution of the sub-module devices are the average conduction time T1-T4 of each device, and the loss of the lower IGBT (T2) under inverter conditions is the dominant factor restricting the safe operation range of the MMC.

[0107] The average time T that a submodule is in the input state in a cycle on and the average duration of the resection state T off It is expressed as the following formula. When the main circuit parameters are selected, only the capacitor voltage reference value is a controllable variable. If the capacitor voltage reference value can be reduced, T1 and T4 can be reduced and T2 and T3 can be increased, thereby reducing the loss of D2 and T2 and realizing the optimization of loss distribution.

[0108]

[0109] In the above formula, is the capacitor voltage reference value, is the bridge arm voltage reference value, is the reference value of DC output voltage.

[0110] The bridge arm current flows from top to bottom as the positive direction. When the bridge arm current is positive, the current flows through T2 or D1; when the bridge arm current is negative, the current flows through T1 or D2. The relationship between the currents I of each device is obtained as follows, where the subscript avg represents the average value, rms represents the effective value, and the subscripts p and n represent the positive direction and negative direction respectively.

[0111]

[0112] The waveform of the current (i) flowing through the T2 tube before and after the optimization by the method of the present invention is as follows: Figure 6 As shown in the figure, if the submodule is in the on-state time, the current flowing through the lower switch T2 will decrease. It can be seen from the following formula that after optimization, the loss of the components T2 and D2, which originally had serious loss, can be reduced, and the loss of the components T1 and D1, which originally had slight loss, can be increased, thereby achieving loss distribution optimization.

[0113] The thyristor MMC submodule losses and internal power semiconductor losses of the rectifier station and inverter station before and after the loss optimization method is used are as follows: Figure 7 As shown, the outer ring of the annular diagram represents the proportion of each device loss in the submodule loss, and the inner ring represents the proportion of the conduction loss and the switching loss (reverse recovery loss) in the device loss. It can be seen that after adopting the method of the present invention, the loss of the devices T2 and D2, which originally had serious losses, is reduced, and the loss of the devices T1 and D1, which originally had slight losses, is increased, and the loss optimization distribution is effectively achieved; at the same time, the overall loss of the converter is reduced by 10% under the inverter working condition, and the loss reduction can be increased with the increase of the redundancy of the submodule.

[0114] Example 2

[0115] Based on the same inventive concept, the present invention further provides an optimization control device for an interleaved thyristor modular multilevel converter, wherein the optimization control device for an interleaved thyristor modular multilevel converter comprises:

[0116] An acquisition module, used for acquiring an upper / lower bridge arm insertion index of an interleaved thyristor modular multi-level converter;

[0117] A correction module, used for correcting the upper / lower bridge arm insertion index by using the feedforward gain of the working state change of the interleaved thyristor modular multi-level converter to obtain a corrected upper / lower bridge arm insertion index;

[0118] A determination module, configured to determine the number of sub-modules of the upper / lower bridge arms of the interleaved thyristor modular multi-level converter put into operation based on the modified upper / lower bridge arm insertion index;

[0119] The control module is used to generate a switching signal for controlling the submodules in the upper / lower bridge arms of the interleaved thyristor modular multilevel converter by adopting a capacitor-voltage balance algorithm based on the number of submodules put into operation in the upper / lower bridge arms of the interleaved thyristor modular multilevel converter.

[0120] Preferably, the upper / lower bridge arm insertion index of the interleaved thyristor modular multi-level converter is as follows:

[0121] n u,l =(U dc_ref / 2me j_ref -u comj_ref ) / Nu c_ref

[0122] In the above formula, n u,l Insert the index, U, for the upper / lower bridge arm of the interleaved thyristor modular multilevel converter dc_ref is the reference value of the DC output voltage of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter, e j_ref is the upper / lower differential mode voltage reference value of the interleaved thyristor modular multilevel converter, u comj_ref is the common mode voltage reference value of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter, N is the number of submodules in the bridge arm, u c_ref is the submodule capacitor voltage reference value.

[0123] Furthermore, the process of obtaining the upper / lower differential mode voltage reference value of the interleaved thyristor modular multi-level converter includes:

[0124] The active power reference value of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter and the reactive power reference value of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter or the reference value of the DC output voltage of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter are used as inputs of the outer loop power controller and the inner loop current controller to obtain the upper / lower differential mode voltage reference value of the interleaved thyristor modular multilevel converter output by the inner loop current controller.

[0125] Furthermore, the process of obtaining the common mode voltage reference value of the upper / lower bridge arm of the interleaved thyristor modular multi-level converter includes:

[0126] The upper / lower arm current and circulating current reference values ​​of the interleaved thyristor modular multilevel converter are used as inputs of the inner loop circulating current suppressor to obtain the upper / lower arm common mode voltage reference values ​​of the interleaved thyristor modular multilevel converter output by the inner loop circulating current suppressor.

[0127] Preferably, the upper / lower bridge arm insertion index of the interleaved thyristor modular multi-level converter is as follows:

[0128] n u,l =K0 mK1cos(ωt+θ1)-K2cos(2ωt+θ2)

[0129] In the above formula, n u,l is the upper / lower arm insertion index of the interleaved thyristor modular multilevel converter, K0, K1 and K2 are the DC component, fundamental frequency component and circulating current compensation voltage modulation index respectively, ω is the fundamental angular frequency, t is the time, θ1 is the initial phase of the fundamental frequency component, and θ2 is the initial phase of the double frequency component.

[0130] Furthermore, the DC component, fundamental frequency component and circulating current compensation voltage modulation index satisfy:

[0131]

[0132] Preferably, the modified upper / lower bridge arm insertion index is as follows:

[0133]

[0134] In the above formula, n u,l_new To correct the upper / lower bridge arm insert index, n u,l is the upper / lower bridge arm insertion index of the interleaved thyristor modular multilevel converter, K is the feedforward gain, K0, K1 and K2 are the DC component, fundamental frequency component and circulating current compensation voltage modulation index respectively, K h is the submodule health rate.

[0135] Furthermore, the submodule health rate is as follows:

[0136]

[0137] In the above formula, N f is the number of healthy submodules in the bridge arm, and N is the number of submodules in the bridge arm.

[0138] Furthermore, the number of sub-modules put into operation in the upper / lower bridge arms of the staggered thyristor modular multi-level converter is as follows:

[0139] N u,l_new =N·n u,l_new

[0140] In the above formula, N u,l_new is the number of submodules put into operation in the upper / lower bridge arms of the interleaved thyristor modular multi-level converter, and N is the number of submodules in the bridge arm.

[0141] Example 3

[0142] Based on the same inventive concept, the present invention also provides a computer device, which includes a processor and a memory, wherein the memory is used to store a computer program, wherein the computer program includes program instructions, and the processor is used to execute the program instructions stored in the computer storage medium. The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. It is the computing core and control core of the terminal, which is suitable for implementing one or more instructions, and is specifically suitable for loading and executing one or more instructions in the computer storage medium to implement the corresponding method flow or corresponding function, so as to implement the steps of the optimization control method of a staggered thyristor modular multi-level converter in the above embodiment.

[0143] Example 4

[0144] Based on the same inventive concept, the present invention also provides a storage medium, specifically a computer-readable storage medium (Memory), which is a memory device in a computer device for storing programs and data. It can be understood that the computer-readable storage medium here can include both built-in storage media in the computer device and, of course, extended storage media supported by the computer device. The computer-readable storage medium provides a storage space, which stores the operating system of the terminal. In addition, one or more instructions suitable for being loaded and executed by the processor are also stored in the storage space, and these instructions can be one or more computer programs (including program codes). It should be noted that the computer-readable storage medium here can be a high-speed RAM memory or a non-volatile memory, such as at least one disk memory. The processor can load and execute one or more instructions stored in the computer-readable storage medium to implement the steps of an optimization control method for a staggered thyristor modular multi-level converter in the above embodiment.

[0145] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0146] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0147] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0148] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0149] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. An optimization control method for a staggered thyristor modular multi-level converter, characterized in that: The method comprises: Get the upper / lower bridge arm insertion index of the interleaved thyristor modular multilevel converter; The upper / lower bridge arm insertion index is corrected by using the feedforward gain of the working state change of the interleaved thyristor modular multi-level converter to obtain a corrected upper / lower bridge arm insertion index; Determine the number of sub-modules of the upper / lower bridge arms of the interleaved thyristor modular multi-level converter put into operation based on the modified upper / lower bridge arm insertion index; Based on the number of submodules put into operation in the upper / lower bridge arms of the interleaved thyristor modular multilevel converter, a capacitor voltage balance algorithm is used to generate switching signals for controlling the submodules in the upper / lower bridge arms of the interleaved thyristor modular multilevel converter.

2. The method according to claim 1, characterized in that The upper / lower bridge arm insertion index of the interleaved thyristor modular multilevel converter is as follows: n u,l =(You dc_ref / 2me j_ref -you comj_ref ) / Now c_ref In the above formula, n u,l Insert the index, U, for the upper / lower bridge arm of the interleaved thyristor modular multilevel converter dc_ref is the reference value of the DC output voltage of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter, e j_ref is the upper / lower differential mode voltage reference value of the interleaved thyristor modular multilevel converter, u comj_ref is the common mode voltage reference value of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter, N is the number of submodules in the bridge arm, u c_ref is the submodule capacitor voltage reference value.

3. The method according to claim 2, characterized in that The process of obtaining the upper / lower differential mode voltage reference value of the interleaved thyristor modular multi-level converter includes: The active power reference value of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter and the reactive power reference value of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter or the reference value of the DC output voltage of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter are used as inputs of the outer loop power controller and the inner loop current controller to obtain the upper / lower differential mode voltage reference value of the interleaved thyristor modular multilevel converter output by the inner loop current controller.

4. The method according to claim 2, characterized in that The process of obtaining the common mode voltage reference value of the upper / lower bridge arm of the interleaved thyristor modular multi-level converter includes: The upper / lower arm current and circulating current reference values ​​of the interleaved thyristor modular multilevel converter are used as inputs of the inner loop circulating current suppressor to obtain the upper / lower arm common mode voltage reference values ​​of the interleaved thyristor modular multilevel converter output by the inner loop circulating current suppressor.

5. The method according to claim 1, characterized in that The upper / lower bridge arm insertion index of the interleaved thyristor modular multilevel converter is as follows: n u,l =K0 mK1cos(ωt+θ1)-K2cos(2ωt+θ2) In the above formula, n u,l is the upper / lower arm insertion index of the interleaved thyristor modular multilevel converter, K0, K1 and K2 are the DC component, fundamental frequency component and circulating current compensation voltage modulation index respectively, ω is the fundamental angular frequency, t is the time, θ1 is the initial phase of the fundamental frequency component, and θ2 is the initial phase of the double frequency component.

6. The method according to claim 5, characterized in that The DC component, fundamental frequency component and circulating current compensation voltage modulation index satisfy:

7. The method according to claim 1, characterized in that The modified upper / lower bridge arm insertion index is as follows: In the above formula, n u,l_new To correct the upper / lower bridge arm insert index, n u,l is the upper / lower bridge arm insertion index of the interleaved thyristor modular multilevel converter, K is the feedforward gain, K0, K1 and K2 are the DC component, fundamental frequency component and circulating current compensation voltage modulation index respectively, K h is the submodule health rate.

8. The method according to claim 7, characterized in that The submodule health rates are as follows: In the above formula, N f is the number of healthy submodules in the bridge arm, and N is the number of submodules in the bridge arm.

9. The method according to claim 7, characterized in that The number of sub-modules put into operation in the upper / lower bridge arms of the interleaved thyristor modular multi-level converter is as follows: N u,l_new =N·n u,l_new In the above formula, N u,l_new is the number of submodules put into operation in the upper / lower bridge arms of the interleaved thyristor modular multi-level converter, and N is the number of submodules in the bridge arm.

10. An optimization control device for a staggered thyristor modular multi-level converter, characterized in that: The device comprises: An acquisition module, used for acquiring an upper / lower bridge arm insertion index of an interleaved thyristor modular multi-level converter; A correction module, used for correcting the upper / lower bridge arm insertion index by using the feedforward gain of the working state change of the interleaved thyristor modular multi-level converter to obtain a corrected upper / lower bridge arm insertion index; A determination module, configured to determine the number of sub-modules of the upper / lower bridge arms of the interleaved thyristor modular multi-level converter put into operation based on the modified upper / lower bridge arm insertion index; The control module is used to generate a switching signal for controlling the submodules in the upper / lower bridge arms of the interleaved thyristor modular multilevel converter by adopting a capacitor-voltage balance algorithm based on the number of submodules put into operation in the upper / lower bridge arms of the interleaved thyristor modular multilevel converter.

11. The device according to claim 10, characterized in that The upper / lower bridge arm insertion index of the interleaved thyristor modular multilevel converter is as follows: n u,l =(You dc_ref / 2me j_ref -you comj_ref ) / Now c_ref In the above formula, n u,l Insert the index, U, for the upper / lower bridge arm of the interleaved thyristor modular multilevel converter dc_ref is the reference value of the DC output voltage of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter, e j_ref is the upper / lower differential mode voltage reference value of the interleaved thyristor modular multilevel converter, u comj_ref is the common mode voltage reference value of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter, N is the number of submodules in the bridge arm, u c_ref is the submodule capacitor voltage reference value.

12. The device according to claim 11, characterized in that The process of obtaining the upper / lower differential mode voltage reference value of the interleaved thyristor modular multi-level converter includes: The active power reference value of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter and the reactive power reference value of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter or the reference value of the DC output voltage of the upper / lower bridge arm of the interleaved thyristor modular multilevel converter are used as inputs of the outer loop power controller and the inner loop current controller to obtain the upper / lower differential mode voltage reference value of the interleaved thyristor modular multilevel converter output by the inner loop current controller.

13. The device according to claim 11, characterized in that The process of obtaining the common mode voltage reference value of the upper / lower bridge arm of the interleaved thyristor modular multi-level converter includes: The upper / lower arm current and circulating current reference values ​​of the interleaved thyristor modular multilevel converter are used as inputs of the inner loop circulating current suppressor to obtain the upper / lower arm common mode voltage reference values ​​of the interleaved thyristor modular multilevel converter output by the inner loop circulating current suppressor.

14. The device according to claim 10, characterized in that The upper / lower bridge arm insertion index of the interleaved thyristor modular multilevel converter is as follows: n u,l =K0 mK1cos(ωt+θ1)-K2cos(2ωt+θ2) In the above formula, n u,l is the upper / lower arm insertion index of the interleaved thyristor modular multilevel converter, K0, K1 and K2 are the DC component, fundamental frequency component and circulating current compensation voltage modulation index respectively, ω is the fundamental angular frequency, t is the time, θ1 is the initial phase of the fundamental frequency component, and θ2 is the initial phase of the double frequency component.

15. The device according to claim 14, characterized in that The DC component, fundamental frequency component and circulating current compensation voltage modulation index satisfy:

16. The device according to claim 10, characterized in that The modified upper / lower bridge arm insertion index is as follows: In the above formula, n u,l_new To correct the upper / lower bridge arm insert index, n u,l is the upper / lower bridge arm insertion index of the interleaved thyristor modular multilevel converter, K is the feedforward gain, K0, K1 and K2 are the DC component, fundamental frequency component and circulating current compensation voltage modulation index respectively, K h is the submodule health rate.

17. The device according to claim 16, characterized in that The submodule health rates are as follows: In the above formula, N f is the number of healthy submodules in the bridge arm, and N is the number of submodules in the bridge arm.

18. The device according to claim 16, characterized in that The number of sub-modules put into operation in the upper / lower bridge arms of the interleaved thyristor modular multi-level converter is as follows: N u,l_new =N·n u,l_new In the above formula, N u,l_new is the number of submodules put into operation in the upper / lower bridge arms of the interleaved thyristor modular multi-level converter, and N is the number of submodules in the bridge arm.

19. A computer device, characterized in that: include: one or more processors; The processor is configured to execute one or more programs; When the one or more programs are executed by the one or more processors, the optimization control method of the interleaved thyristor modular multi-level converter according to any one of claims 1 to 9 is implemented.

20. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed, the optimization control method of the interleaved thyristor modular multi-level converter according to any one of claims 1 to 9 is implemented.

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