Anti-magnetic bias circuit, device and system

Abstract

The invention discloses an anti-magnetic-bias circuit, device and system, and relates to the technical field of electronics, the anti-magnetic-bias circuit compares and amplifies voltages at two ends of a transformer of a full-bridge switching converter through a signal amplification circuit to obtain a voltage amplification signal, then integrates the voltage amplification signal, filters out an alternating current component in the signal, and outputs the voltage amplification signal; and an integral signal obtained by the direct-current component is transmitted to a loop compensation circuit connected with a post-stage circuit, so that the post-stage circuit compares the obtained integral signal with an internal reference quantity to obtain corresponding loop compensation. The switching time of each switching tube in the full-bridge switching converter can be adaptively adjusted, so that the transformer adaptively realizes magnetic balance and voltage direct-current component dynamic balance at the two ends of the transformer, and the phenomenon that the full-bridge switching converter is damaged due to the magnetic bias phenomenon is avoided.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to an anti-magnetic bias circuit, device and system. Background Art

[0002] In a circuit using a full-bridge switching converter, due to the different voltage drops generated by the conduction of each switch tube or power tube inside the full-bridge switching converter and the different on-off switching speeds of each switch tube or power tube, the voltage waveform on the primary winding of the transformer of the full-bridge switching converter may have different positive and negative values, and there may be a DC component in the voltage across the transformer, which may cause the magnetic elements inside the full-bridge switching converter to enter a unidirectional saturation state, resulting in a magnetic bias phenomenon, and the total current of the loop rises sharply, which may damage the power devices in the circuit.

[0003] Generally, the DC component is blocked by adding a DC blocking capacitor to the resonant cavity to achieve the purpose of anti-bias magnetization. However, the DC blocking capacitor will increase the distortion of the transformer waveform, especially for low-frequency signals. It cannot effectively block DC and will also increase the overall space occupancy. Summary of the invention

[0004] The main purpose of the present application is to provide an anti-magnetic bias circuit, device and system, aiming to solve the technical problem of how to prevent the closed-loop regulation circuit of a full-bridge switching converter from having a magnetic bias phenomenon under low-frequency conditions.

[0005] To achieve the above-mentioned purpose, an embodiment of the present application provides an anti-bias magnetic circuit, the anti-bias magnetic circuit comprising: a signal amplification circuit and an integration circuit;

[0006] The output end of the signal amplifying circuit is connected to the input end of the integrating circuit, the output end of the integrating circuit is connected to the loop compensation circuit, the output end of the loop compensation circuit is connected to the driver of the full-bridge switching converter, and the first input end and the second input end of the signal amplifying circuit are respectively connected to the two ends on the same side of the transformer of the full-bridge switching converter;

[0007] The signal amplifying circuit is used to output corresponding voltage amplified signals to the integrating circuit when receiving voltage signals at two ends of the same side of the transformer;

[0008] The integration circuit is used to filter out the AC component of the voltage amplification signal and integrate the DC component to obtain an integrated signal corresponding to the DC component;

[0009] The integration circuit is further used to transmit the integration signal to the loop compensation circuit, so that the loop compensation circuit outputs a target PWM signal to drive the full-bridge switching converter according to the integration signal.

[0010] In one embodiment, the signal amplifying circuit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor and a first operational amplifier;

[0011] The positive input terminal of the first operational amplifier is respectively connected to the first end of the second resistor, the first end of the third resistor, the first end of the fourth resistor and the first end of the first capacitor; the reverse input terminal of the first operational amplifier is respectively connected to the first end of the first resistor, the first end of the fifth resistor and the first end of the second capacitor; the output terminal of the first operational amplifier is respectively connected to the second end of the fifth resistor, the second end of the second capacitor and the input terminal of the integration circuit; the second end of the fourth resistor is connected to the first power supply, the second end of the third resistor and the second end of the first capacitor are grounded; the second end of the first resistor is connected to the first end of the transformer; the second end of the second resistor is connected to the second end of the transformer.

[0012] In one embodiment, the resistance value of the first resistor is equal to the resistance value of the second resistor, the resistance value of the third resistor, the resistance value of the fourth resistor and the resistance value of the fifth resistor are equal, and the capacitance value of the first capacitor is equal to the capacitance value of the second capacitor.

[0013] In one embodiment, the integration circuit includes: a sixth resistor, a seventh resistor, an eighth resistor, a third capacitor, a fourth capacitor and a second operational amplifier;

[0014] The positive input terminal of the second operational amplifier is respectively connected to the first end of the seventh resistor, the first end of the eighth resistor and the first end of the third capacitor, the reverse input terminal of the second operational amplifier is respectively connected to the first end of the sixth resistor and the first end of the fourth capacitor, the output terminal of the second operational amplifier is respectively connected to the second end of the fourth capacitor and the loop compensation circuit; the second end of the sixth resistor is connected to the output terminal of the signal amplification circuit; the second end of the seventh resistor is connected to the first power supply; the second end of the eighth resistor and the second end of the third capacitor are grounded.

[0015] In one embodiment, the resistance value of the seventh resistor is equal to the resistance value of the eighth resistor.

[0016] In one embodiment, the anti-magnetic bias circuit further includes: a low-pass filter circuit;

[0017] The input end of the low-pass filter circuit is connected to the output end of the integration circuit, and the output end of the low-pass filter circuit is connected to the loop compensation circuit;

[0018] The low-pass filtering circuit is used to perform low-pass filtering on the received integrated signal and transmit the integrated signal after low-pass filtering to the loop compensation circuit.

[0019] In one embodiment, the low-pass filter circuit includes: a ninth resistor and a fifth capacitor;

[0020] The first end of the ninth resistor is connected to the output end of the integration circuit, and the second end of the ninth resistor is respectively connected to the first end of the fifth capacitor and the loop compensation circuit; the second end of the fifth capacitor is grounded.

[0021] In one embodiment, the loop compensation circuit includes: a first comparator, a second comparator, a third operational amplifier and a PI controller;

[0022] The inverting input terminal of the first comparator is connected to the output terminal of the integration circuit, the positive input terminal of the first comparator is connected to the second power supply, the output terminal of the first comparator is connected to the input terminal of the PI controller, the output terminal of the PI controller is connected to the positive input terminal of the second comparator, the inverting input terminal of the second comparator is used to receive a first reference voltage, the output terminal of the second comparator is connected to the positive input terminal of the third operational amplifier, the inverting input terminal of the third operational amplifier is used to receive a narrow-band signal with an amplitude of the second reference voltage, and the output terminal of the third operational amplifier is connected to the driver of the full-bridge switching converter;

[0023] The second power supply is used to output a second power supply voltage, and the second power supply voltage is equal to half of the first power supply voltage output by the first power supply; and the second reference voltage is equal to twice the first reference voltage.

[0024] In addition, to achieve the above-mentioned purpose, the present application also provides an anti-bias magnetic device, which adopts the anti-bias magnetic circuit described above.

[0025] In addition, to achieve the above-mentioned purpose, the present application also provides an anti-bias magnetic system, which adopts the anti-bias magnetic device as described above.

[0026] The embodiments of the present application provide an anti-magnetic bias circuit, device and system, wherein the anti-magnetic bias circuit includes: a signal amplifying circuit and an integrating circuit; the output end of the signal amplifying circuit is connected to the input end of the integrating circuit, the output end of the integrating circuit is connected to the loop compensation circuit, the output end of the loop compensation circuit is connected to the drive of the full-bridge switching converter, the first input end and the second input end of the signal amplifying circuit are respectively connected to the two ends on the same side of the transformer of the full-bridge switching converter; the signal amplifying circuit is used to output a corresponding voltage amplification signal to the integrating circuit when receiving the voltage signal at the two ends on the same side of the transformer; the integrating circuit is used to filter out the AC component of the voltage amplification signal and integrate the DC component to obtain an integrated signal corresponding to the DC component; the integrating circuit is also used to transmit the integrated signal to the loop compensation circuit, so that the loop compensation circuit outputs a target PWM signal to the drive of the full-bridge switching converter according to the integrated signal.

[0027] The voltages at both ends of the transformer of the full-bridge switching converter are compared and amplified by a signal amplification circuit to obtain a voltage amplification signal, and then the voltage amplification signal is integrated to filter out the AC component in the signal, and the integral signal obtained from the DC component is transmitted to a loop compensation circuit connected to the subsequent stage, so that the subsequent stage circuit can compare the obtained integral signal with an internal reference quantity to obtain corresponding loop compensation, so that the switching time of each switch tube in the full-bridge switching converter can be adaptively adjusted, so that the transformer can adaptively achieve magnetic balance and achieve dynamic balance of the DC component of the voltage at both ends of the transformer, avoiding the occurrence of magnetic bias and causing damage to the full-bridge switching converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0029] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0030] Figure 1 A structural connection diagram provided for the first embodiment of the anti-bias magnetic circuit of the present application;

[0031] Figure 2 A circuit diagram of an example of a full-bridge switching converter;

[0032] Figure 3 An exemplary working state timing diagram of a full-bridge switching converter;

[0033] Figure 4 A circuit connection diagram provided for the second embodiment of the anti-bias magnetic circuit of the present application;

[0034] Figure 5 This is a circuit connection diagram provided for the third embodiment of the anti-bias magnetic circuit of the present application.

[0035] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0036] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0037] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0038] The main solution of the present application is: a signal amplification circuit and an integration circuit are arranged between the loop compensation circuit connected to the output end of the full-bridge switching converter and the driver of the full-bridge switching converter, and the voltage signals at the two ends of the same side of the transformer of the full-bridge switching converter are compared and amplified by the signal amplification circuit to obtain a corresponding voltage amplification signal, and the AC component in the voltage amplification signal is filtered out by the integration circuit, and the remaining DC component is integrated, and the obtained integrated signal is transmitted to the loop compensation circuit, so that the loop compensation circuit generates a corresponding target PWM signal according to the integration signal related to the DC component to complete feedback adjustment of the drive of the full-bridge switching converter.

[0039] At present, in the circuit using the full-bridge switching converter, due to the different voltage drops generated by the conduction of each switch tube or power tube inside the full-bridge switching converter and the different on-off switching speeds of each switch tube or power tube, the voltage waveform on the primary winding of the transformer of the full-bridge switching converter may have different positive and negative values, and there is a DC component in the voltage at both ends of the transformer, which makes the magnetic components inside the full-bridge switching converter enter a unidirectional saturation state, resulting in a magnetic bias phenomenon, and the total current of the loop rises sharply, which may damage the power devices in the circuit. Generally, the method of adding a DC blocking capacitor to the resonant cavity is adopted to block the DC component, so as to achieve the purpose of anti-magnetic bias, but the DC blocking capacitor will increase the distortion of the transformer waveform, especially for low-frequency signals. It cannot effectively isolate the DC, and it will also increase the overall space occupancy rate. Therefore, how to prevent the closed-loop regulation loop of the full-bridge switching converter from having a magnetic bias phenomenon under low-frequency conditions is a problem that needs to be solved urgently.

[0040] The present application compares and amplifies the voltages at both ends of the transformer of the full-bridge switching converter through a signal amplification circuit to obtain a voltage amplification signal, then integrates the voltage amplification signal, filters out the AC component in the signal, and transmits the integrated signal obtained from the DC component to a loop compensation circuit connected to the subsequent stage, so that the subsequent stage circuit compares the obtained integrated signal with an internal reference value, thereby obtaining corresponding loop compensation, so that the switching time of each switch tube in the full-bridge switching converter can be adaptively adjusted, so that the transformer can adaptively achieve magnetic balance and achieve dynamic balance of the DC component of the voltage at both ends of the transformer, avoiding the occurrence of magnetic bias and causing damage to the full-bridge switching converter.

[0041] Based on this, the present application proposes a first embodiment of an anti-magnetic bias circuit, please refer to Figure 1 , the anti-magnetic bias circuit includes: a signal amplification circuit 10 and an integration circuit 20;

[0042] The output end of the signal amplifying circuit 10 is connected to the input end of the integrating circuit 20, the output end of the integrating circuit 20 is connected to the loop compensation circuit 30, the output end of the loop compensation circuit 30 is connected to the driver of the full-bridge switching converter 40, and the first input end and the second input end of the signal amplifying circuit 10 are respectively connected to the two ends on the same side of the transformer of the full-bridge switching converter 40;

[0043] The signal amplifying circuit 10 is used to output corresponding voltage amplified signals to the integrating circuit 20 when receiving voltage signals at two ends of the same side of the transformer;

[0044] The integration circuit 20 is used to filter out the AC component of the voltage amplification signal and integrate the DC component to obtain an integrated signal corresponding to the DC component;

[0045] The integration circuit 20 is further used to transmit the integration signal to the loop compensation circuit 30 , so that the loop compensation circuit 30 outputs a target PWM signal to drive the full-bridge switching converter 40 according to the integration signal.

[0046] It should be noted that the full-bridge switching converter 40 can be a power conversion device consisting of a full-bridge circuit structure composed of multiple switch tubes or power tubes, an inductor and a transformer. The on-off state of each switch tube or power tube in the full-bridge circuit can be switched by combining the transformer to convert direct current and alternating current. In actual situations, there may be differences in the conduction voltage drop of each switch tube or power tube in the full-bridge circuit, or there may be differences in the switching speed of the power device itself, which will cause the positive and negative values ​​of the voltage waveform on the primary winding of the transformer of the full-bridge switching converter 40 to be unequal (i.e., there is a DC component), so that the internal magnetic elements of the full-bridge switching converter 40 (such as the iron core of the transformer) enter a unidirectional saturation state, the magnetic permeability drops sharply (i.e., the bias magnetic phenomenon), the equivalent inductance of the primary side of the transformer decreases sharply, and the total current of the loop rises sharply, which may damage the power device in the circuit.

[0047] Usually, a detection circuit can be set between the output end of the full-bridge switch converter 40 and its driver, and through a closed-loop feedback mechanism, based on the two voltage signals corresponding to the two ends of the same side of the transformer, the on-off time of each switch tube in the full-bridge switch converter 40 is adjusted, so as to prevent the occurrence of magnetic bias, thereby protecting the full-bridge switch converter 40. However, since there is an AC component in each voltage signal at the two ends of the same side of the transformer, it is necessary to remove the AC component to effectively and correctly adjust the on-off time of each switch tube or power tube in the full-bridge switch converter 40 to achieve the effect of anti-magnetic bias. In a high-frequency working environment, a DC blocking capacitor can be used in the detection circuit to distinguish between the AC component and the DC component, so that the on-off time of each switch tube or power tube is adjusted only according to the DC component; but in a low-frequency working environment, due to the characteristics of the capacitor itself, the DC blocking capacitor cannot effectively separate the DC component and the AC component, and cannot effectively adjust the on-off time of each switch tube in the full-bridge switch converter 40, and it is also impossible to effectively prevent the occurrence of magnetic bias.

[0048] It is easy to understand that in this embodiment, the loop compensation circuit 30 refers to a circuit that can output a PWM signal to the driver of the full-bridge switching converter 40. It can output an integral signal related to the DC component according to the anti-magnetic bias circuit of the present application, generate a corresponding target PWM signal and send it to the driver of the full-bridge switching converter 40 (not marked in the figure), which can effectively adjust the on-off time of each switch tube or power tube inside the full-bridge switching converter 40, thereby effectively avoiding the occurrence of magnetic bias.

[0049] It should be noted that, in this embodiment, the full-bridge switching converter 40 may be specifically a dual active full-bridge converter (Dual Active Bridge, DAB), one side of which may be composed of four switching tubes and have two bridge arms. The midpoint of each bridge arm is used as an output end, and a low-frequency voltage signal may be transmitted. The bridge arms of the two bridges are connected by a transformer. Figure 2 as well as Figure 3 The dual-active full-bridge converter is composed of a first switch tube S1, a second switch tube S2 to an eighth switch tube S8 to form a first bridge structure and a second bridge structure respectively, and each switch tube is also reversely connected in parallel with a freewheeling diode D0 and a buffer capacitor C0; the first bus capacitor Cm1 is the bus capacitor of the first bridge structure, and the second bus capacitor Cm2 is the bus capacitor of the second bridge structure; the midpoints of the two bridge arms of the first bridge structure are a and b respectively, and the midpoints of the two bridge arms of the second bridge structure are c and d respectively, a is connected to the first end of the first side of the transformer T through an inductor L, b is connected to the second end of the first side of the transformer T, c is connected to the first end of the second side of the transformer T, and d is connected to the second end of the second side of the transformer T, wherein the first side of the transformer T is the primary side of the transformer T. In this example, the first input terminal and the second input terminal of the signal amplifying circuit 10 can be a and b respectively. If the voltage at point a is Va, the voltage at point b is Vb, Vab=Va-Vb, and Vba=Vb-Va, then when |Vab|=|Vba|, the DC component of the voltage amplified signal Vo1 output by the signal amplifying circuit 10 is equal to the DC bias voltage set inside it, so that the voltage value of the integrated signal Vo2 obtained after passing through the integrating circuit 20 is also equal to the DC bias voltage set in the signal amplifying circuit 10, and the compensation value output by the PI controller in the loop compensation circuit 30 is 0, then the first switch tube S1 and the fourth switch tube S4 are turned on and off at the same time, and the duty cycle is 50%, the second switch tube S2 and the third switch tube S3 are turned on and off at the same time, and The duty cycle is 50%, and no compensation is performed; when |Vab|>|Vba|, the DC component of the voltage amplified signal Vo1 output by the signal amplifier circuit 10 is greater than the DC bias voltage set inside it, and the voltage value of the integrated signal Vo2 obtained after passing through the integration circuit 20 is also greater than the DC bias voltage set inside it. The output value of the PI controller (not shown in the figure) in the loop compensation circuit 30 is greater than 0, that is, the deviation value from the theoretical value is greater than 0. At this time, the first switch tube S1 and the fourth switch tube S4 are turned on and off at the same time, and the duty cycle is less than 50%, and the second switch tube S2 and the third switch tube S3 are turned on and off at the same time, and the duty cycle is greater than 50%, which is prone to magnetic bias. The situation of |Vab|<|Vba| is the opposite of the above situation, and will not be repeated here. Through the above principle, a feedback adjustment mechanism can be reversely constructed to adaptively adjust the DC component balance at both ends of the primary side of the transformer T, thereby avoiding magnetic bias.

[0050] In a specific implementation, the signal amplification circuit 10 can compare and amplify the low-frequency voltage signals corresponding to the two ends of the same side of the transformer, thereby obtaining a voltage amplification signal, and transmit the voltage amplification signal to the integration circuit 20. The integration circuit 20 can filter out the AC component in the voltage amplification signal, and perform integration processing according to the DC component in the voltage amplification signal to obtain an integration signal related to the DC component. Subsequently, the integration circuit 20 transmits the integration signal to the loop compensation circuit 30, so that the loop compensation circuit 30 generates a target PWM signal according to the integration signal related to the DC component, and transmits the target PWM signal to the driver of the full-bridge switch converter 40 to drive the on-off time of each switch tube or power tube in the full-bridge switch converter 40, which is suitable for a variety of low-frequency bandwidths, thereby effectively avoiding the occurrence of anti-bias magnetization. In addition, since the circuit does not need to set a large DC isolation capacitor, the total volume of the full-bridge switch converter 40 is reduced, which is convenient for the design of other functions of the full-bridge switch converter 40.

[0051] An embodiment of the present application provides an anti-magnetic bias circuit, which includes: a signal amplifying circuit and an integrating circuit; the output end of the signal amplifying circuit is connected to the input end of the integrating circuit, the output end of the integrating circuit is connected to the loop compensation circuit, the output end of the loop compensation circuit is connected to the drive of the full-bridge switching converter, and the first input end and the second input end of the signal amplifying circuit are respectively connected to the two ends on the same side of the transformer of the full-bridge switching converter; the signal amplifying circuit is used to output a corresponding voltage amplification signal to the integrating circuit when receiving the voltage signal at the two ends on the same side of the transformer; the integrating circuit is used to filter out the AC component of the voltage amplification signal and integrate the DC component to obtain an integrated signal corresponding to the DC component; the integrating circuit is also used to transmit the integrated signal to the loop compensation circuit, so that the loop compensation circuit outputs a target PWM signal to the drive of the full-bridge switching converter according to the integrated signal. The voltages at both ends of the transformer of the full-bridge switching converter are compared and amplified by a signal amplification circuit to obtain a voltage amplification signal, and then the voltage amplification signal is integrated to filter out the AC component in the signal, and the integral signal obtained from the DC component is transmitted to a loop compensation circuit connected to the subsequent stage, so that the subsequent stage circuit can compare the obtained integral signal with an internal reference quantity to obtain corresponding loop compensation, so that the switching time of each switch tube in the full-bridge switching converter can be adaptively adjusted, so that the transformer can adaptively achieve magnetic balance and achieve dynamic balance of the DC component of the voltage at both ends of the transformer, avoiding the occurrence of magnetic bias and causing damage to the full-bridge switching converter.

[0052] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the above-mentioned embodiment 1 can refer to the above introduction, and will not be repeated later. Figure 4 , the signal amplifying circuit 10 comprises: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, a second capacitor C2 and a first operational amplifier A1;

[0053] The positive input terminal of the first operational amplifier A1 is respectively connected to the first end of the second resistor R2, the first end of the third resistor R3, the first end of the fourth resistor R4 and the first end of the first capacitor C1; the reverse input terminal of the first operational amplifier A1 is respectively connected to the first end of the first resistor R1, the first end of the fifth resistor R5 and the first end of the second capacitor C2; the output terminal of the first operational amplifier A1 is respectively connected to the second end of the fifth resistor R5, the second end of the second capacitor C2 and the input terminal of the integration circuit 20; the second end of the fourth resistor R4 is connected to the first power supply VCC1, the second end of the third resistor R3 and the second end of the first capacitor C1 are grounded; the second end of the first resistor R1 is connected to the first end of the transformer; the second end of the second resistor R2 is connected to the second end of the transformer.

[0054] It should be noted that the full-bridge switching converter 40 may have two bridge structures, and each bridge arm between the two bridge structures is connected through a transformer. In this embodiment, the positive input end of the first operational amplifier A1 can be connected to the second end of the transformer through the second resistor R2, or understood as being connected to the midpoint of the second bridge arm of the full-bridge switching converter 40, and the reverse input end of the first operational amplifier A1 can be connected to the first end of the transformer through the first resistor R1, or understood as being connected to the midpoint of the first bridge arm of the full-bridge switching converter 40, wherein the first end and the second end of the transformer are on the same side of the transformer. Therefore, the first operational amplifier A1 can compare and amplify the voltage signals at both ends of the same side of the transformer, or the voltage signals output by each of the two bridge arms of the single-side bridge of the full-bridge switching converter 40. Among them, the third resistor R3 and the fourth resistor R4 are connected in series between the first power supply VCC1 and the ground line to form a series bias circuit, which provides a bias voltage for the positive input terminal of the first operational amplifier A1. The magnitude of the bias voltage depends on the first power supply voltage output by the first power supply VCC1 and the resistance selection of the third resistor R3 and the fourth resistor R4. In this way, the voltage at the positive input terminal of the first operational amplifier A1 will be higher than the voltage at the reverse input terminal, so that the voltage at the output terminal of the first operational amplifier A1 is positive. The first capacitor C1 is used as a filter capacitor to filter the voltage signal input to the reverse input terminal of the first operational amplifier A1. The fifth resistor R5 is connected to the reverse input terminal and the output terminal of the first operational amplifier A1 and is connected in series with the first resistor R1. Therefore, the amplification gain of the first operational amplifier A1 can be adjusted by adjusting the resistance values ​​of the first resistor R1 and the fifth resistor R5; the second capacitor C2 is used as a frequency compensation capacitor and a filter capacitor, which is connected in parallel with the fifth resistor R5 to filter out high-frequency interference signals in the circuit, and can also adjust the response speed of the first operational amplifier A1 and suppress self-oscillation. Based on the structure of the above-mentioned signal amplifier circuit 10, if the voltage difference Vin between the two sets of input voltage signals is expressed as V in the frequency domain in (f) The voltage amplified signal Vo1 output by the first operational amplifier A1 is expressed in the frequency domain as V o1 (f), then the frequency domain response expression G1(f) of the signal amplifying circuit 10 is:

[0055]

[0056] Wherein, f is the frequency of the voltage signal, C2 is the capacitance of the second capacitor C2, R1 is the resistance of the first resistor R1, and R5 is the resistance of the fifth resistor R5.

[0057] Furthermore, in this embodiment, the resistance value of the first resistor R1 is equal to the resistance value of the second resistor R2, the resistance value of the third resistor R3, the resistance value of the fourth resistor R4 and the resistance value of the fifth resistor R5 are equal, and the capacitance value of the first capacitor C1 is equal to the capacitance value of the second capacitor C2.

[0058] It is easy to understand that in this embodiment, the equal resistance of the first resistor R1 and the second resistor R2 can improve the common mode rejection ratio of the first operational amplifier A1 and ensure the accuracy of the amplification gain design. The resistance of the third resistor R3 is equal to the resistance of the fourth resistor R4, so the bias voltage received by the reverse input terminal of the first operational amplifier A1 can be set to half of the first power supply voltage output by the first power supply VCC1. The resistance of the fifth resistor R5 is also equal to the resistance of the third resistor R3 and the fourth resistor R4 (bias resistor), so the input of the first operational amplifier A1 can be balanced and the working stability can be improved. Based on similar reasons, the capacitance of the first capacitor C1 is also equal to the capacitance of the second capacitor C2, so that the signal amplifier circuit 10 can work more stably.

[0059] Further, in this embodiment, the integration circuit 20 includes: a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a third capacitor C3, a fourth capacitor C4 and a second operational amplifier A2;

[0060] The positive input terminal of the second operational amplifier A2 is respectively connected to the first end of the seventh resistor R7, the first end of the eighth resistor R8 and the first end of the third capacitor C3, the reverse input terminal of the second operational amplifier A2 is respectively connected to the first end of the sixth resistor R6 and the first end of the fourth capacitor C4, the output terminal of the second operational amplifier A2 is respectively connected to the second end of the fourth capacitor C4 and the loop compensation circuit 30; the second end of the sixth resistor R6 is connected to the output end of the signal amplifying circuit 10; the second end of the seventh resistor R7 is connected to the first power supply VCC1; the second end of the eighth resistor R8 and the second end of the third capacitor C3 are grounded.

[0061] It is easy to understand that in this embodiment, the seventh resistor R7 and the eighth resistor R8 form a voltage-dividing structure, which is connected between the first power supply VCC1 and the ground line, and provides a reference voltage for the reverse input terminal of the second operational amplifier A2. The fourth capacitor C4 is used as an integrating capacitor, which can be accumulated according to the voltage of the DC component of the voltage amplification signal, and the accumulated amount of the AC component is offset as the charging and discharging of the integrating capacitor, thereby forming an integrated signal related only to the DC component. The third capacitor C3 is a decoupling capacitor, which is used to improve the frequency response in the circuit and reduce noise or high-frequency interference. Based on the structure of the above-mentioned integrating circuit 20, if the input voltage amplification signal Vo1 is represented as V in the frequency domaino1 (f), the integrated signal Vo2 output by the second operational amplifier A2 is expressed as V o2 (f), then the frequency domain response expression G2(f) of the integration circuit 20 is:

[0062]

[0063] Wherein, f is the frequency of the voltage amplified signal, C4 is the capacitance of the fourth capacitor C4, and R6 is the resistance of the sixth resistor R6.

[0064] Further, in this embodiment, the resistance value of the seventh resistor R7 is equal to the resistance value of the eighth resistor R8.

[0065] It is easy to understand that in this embodiment, in order to improve the working stability of the second operational amplifier A2 in the integration circuit 20, the resistance value of the seventh resistor R7 and the resistance value of the eighth resistor R8 are set to be the same resistance value.

[0066] In combination with the above embodiments, after converting the frequency domain into the time domain, the time domain expression V of the integration circuit 20 can be obtained: o2 (t):

[0067]

[0068] Among them, V cc is the first power supply voltage output by the first power supply VCC1, C4 is the capacitance of the fourth capacitor C4, R6 is the resistance of the sixth resistor R6, V o1 (t) is the time domain function of each voltage signal input to the signal amplifier circuit 10.

[0069] Based on the first embodiment and / or the second embodiment of the present application, in the third embodiment of the present application, the same or similar contents as those of the above-mentioned first and second embodiments can refer to the above introduction, and will not be repeated later. Figure 5 , the anti-magnetic bias circuit further includes: a low-pass filter circuit 50;

[0070] The input end of the low-pass filter circuit 50 is connected to the output end of the integration circuit 20, and the output end of the low-pass filter circuit 50 is connected to the loop compensation circuit 30;

[0071] The low-pass filter circuit 50 is used to perform low-pass filtering on the received integrated signal and transmit the integrated signal after low-pass filtering to the loop compensation circuit 30 .

[0072] It is easy to understand that in this embodiment, the integral signal output by the integral circuit 20 may contain high-frequency noise caused by the integration process. Therefore, a low-pass filter circuit 50 may be set between the integral circuit 20 and the loop compensation circuit 30 to perform low-pass filtering on the integral signal to ensure the accuracy of the integral signal received by the loop compensation circuit 30.

[0073] Further, in this embodiment, the low-pass filter circuit 50 includes: a ninth resistor R9 and a fifth capacitor C5;

[0074] A first end of the ninth resistor R9 is connected to the output end of the integration circuit 20 , a second end of the ninth resistor R9 is respectively connected to a first end of the fifth capacitor C5 and the loop compensation circuit 30 ; a second end of the fifth capacitor C5 is grounded.

[0075] It is easy to understand that in this embodiment, the ninth resistor R9 and the fifth capacitor C5 form a first-order low-pass filter structure, which can effectively filter out high-frequency interference signals in the integral signal and only transmit the low-frequency integral signal to the loop compensation circuit 30 to ensure that the loop compensation circuit 30 can generate the required target PWM signal according to the accurate integral signal.

[0076] Further, in this embodiment, the loop compensation circuit 30 includes: a first comparator UA1, a second comparator UA2, a third operational amplifier A3 and a PI controller 31;

[0077] The inverting input terminal of the first comparator UA1 is connected to the output terminal of the integration circuit 20, the positive input terminal of the first comparator UA1 is connected to the second power supply VCC2, the output terminal of the first comparator UA1 is connected to the input terminal of the PI controller 31, the output terminal of the PI controller 31 is connected to the positive input terminal of the second comparator UA2, the inverting input terminal of the second comparator UA2 is used to receive the first reference voltage Vref1, the output terminal of the second comparator UA2 is connected to the positive input terminal of the third operational amplifier A3, the inverting input terminal of the third operational amplifier A3 is used to receive a narrow-band signal with an amplitude of the second reference voltage Vref2, and the output terminal of the third operational amplifier A3 is connected to the driver of the full-bridge switching converter 40;

[0078] The second power supply VCC2 is used to output a second power supply voltage, which is equal to half of the first power supply voltage output by the first power supply; and the second reference voltage Vref2 is equal to twice of the first reference voltage Vref1.

[0079] It is easy to understand that in this embodiment, the loop compensation circuit 30 is mainly composed of a first comparator UA1, a second comparator UA2, a third operational amplifier A3 and a PI controller 31, and is mainly used to generate a target PWM signal for adjusting the on-off time of each switch tube or power tube in the full-bridge switch converter 40 according to the integral signal, and output it to the drive of the full-bridge switch converter 40 to achieve the corresponding driving effect. In this embodiment, the integral circuit 20 can output the integral signal to the subsequent circuit, which passes through the first comparator UA1, the PI controller 31, the second comparator UA2 and the third operational amplifier A3 in sequence. The first comparator UA1 can compare and amplify the integral signal based on the second power supply voltage output by the second power supply VCC2, and the PI controller 31 can compensate according to the output voltage of the first comparator UA1. After a series of operational amplifications through the second comparator UA2 and the third operational amplifier A3, the corresponding target PWM signal is finally generated. The positive input terminal of the first comparator UA1 is connected to the second power supply VCC2, that is, the second power supply voltage output by the second power supply VCC2 can be used as the reference voltage for integration. If the reference voltage received by the front-stage circuit (the positive input terminal of the signal amplifier circuit 10 and the positive input terminal of the integration circuit 20) is half of the first power supply voltage, the second power supply voltage should also be half of the first power supply voltage; the positive input terminal of the second comparator UA2 is used to receive the first reference voltage Vref1, and the first reference voltage Vref1 is used as the reference voltage of the second comparator UA2; the third operational amplifier A3 can be a comparison amplifier, and its reverse input terminal is used to receive a narrow-band signal with an amplitude of the second reference voltage Vref2. Among them, the second reference voltage Vref2 should be twice the first reference voltage Vref1, so that when the amplitude of the narrow-band signal is lower than the first reference voltage Vref1, a high level can be output, and when the amplitude of the narrow-band signal is higher than the first reference voltage Vref1, a low level can be output, so that the driving of the full-bridge switching converter 40 can adjust the duty cycle of the generated target PWM signal by changing the waveform of the narrow-band signal. As a preferred solution, the narrow-band signal may be a triangular wave signal.

[0080] In addition, to achieve the above-mentioned purpose, the embodiment of the present application also proposes an anti-bias magnetic device, and the anti-bias magnetic device adopts all the embodiments of the anti-bias magnetic circuit described above. Compared with the prior art, the beneficial effects of the anti-bias magnetic device provided in the embodiment of the present application are the same as the beneficial effects of the anti-bias magnetic circuit provided in the above embodiment, and other technical features of the anti-bias magnetic device are the same as the features disclosed in the above embodiment, which will not be repeated here.

[0081] In addition, to achieve the above-mentioned purpose, the embodiment of the present application also proposes an anti-bias magnetic system, and the anti-bias magnetic device adopts all the embodiments of the anti-bias magnetic device described above. Compared with the prior art, the beneficial effects of the anti-bias magnetic system provided by the embodiment of the present application are the same as the beneficial effects of the anti-bias magnetic device provided by the above-mentioned embodiment, and other technical features of the anti-bias magnetic system are the same as the features disclosed in the above-mentioned embodiment, which will not be repeated here.

[0082] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent processing scope of the present application.

Claims

1. An anti-magnetic bias circuit, characterized in that: The anti-magnetic bias circuit includes: a signal amplification circuit and an integration circuit; The output end of the signal amplifying circuit is connected to the input end of the integrating circuit, the output end of the integrating circuit is connected to the loop compensation circuit, the output end of the loop compensation circuit is connected to the driver of the full-bridge switching converter, and the first input end and the second input end of the signal amplifying circuit are respectively connected to the two ends on the same side of the transformer of the full-bridge switching converter; The signal amplifying circuit is used to output corresponding voltage amplified signals to the integrating circuit when receiving voltage signals at two ends of the same side of the transformer; The integration circuit is used to filter out the AC component of the voltage amplification signal and integrate the DC component to obtain an integrated signal corresponding to the DC component; The integration circuit is further used to transmit the integration signal to the loop compensation circuit, so that the loop compensation circuit outputs a target PWM signal to drive the full-bridge switching converter according to the integration signal.

2. The anti-bias magnetic circuit according to claim 1, characterized in that: The signal amplifying circuit comprises: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor and a first operational amplifier; The positive input terminal of the first operational amplifier is respectively connected to the first end of the second resistor, the first end of the third resistor, the first end of the fourth resistor and the first end of the first capacitor; the reverse input terminal of the first operational amplifier is respectively connected to the first end of the first resistor, the first end of the fifth resistor and the first end of the second capacitor; the output terminal of the first operational amplifier is respectively connected to the second end of the fifth resistor, the second end of the second capacitor and the input terminal of the integration circuit; the second end of the fourth resistor is connected to the first power supply, the second end of the third resistor and the second end of the first capacitor are grounded; the second end of the first resistor is connected to the first end of the transformer; the second end of the second resistor is connected to the second end of the transformer.

3. The anti-bias magnetic circuit according to claim 2, characterized in that: The resistance value of the first resistor is equal to the resistance value of the second resistor, the resistance values ​​of the third resistor, the fourth resistor and the fifth resistor are equal, and the capacitance value of the first capacitor is equal to the capacitance value of the second capacitor.

4. The anti-bias magnetic circuit according to claim 1, characterized in that: The integration circuit comprises: a sixth resistor, a seventh resistor, an eighth resistor, a third capacitor, a fourth capacitor and a second operational amplifier; The positive input terminal of the second operational amplifier is respectively connected to the first end of the seventh resistor, the first end of the eighth resistor and the first end of the third capacitor, the reverse input terminal of the second operational amplifier is respectively connected to the first end of the sixth resistor and the first end of the fourth capacitor, the output terminal of the second operational amplifier is respectively connected to the second end of the fourth capacitor and the loop compensation circuit; the second end of the sixth resistor is connected to the output terminal of the signal amplification circuit; the second end of the seventh resistor is connected to the first power supply; the second end of the eighth resistor and the second end of the third capacitor are grounded.

5. The anti-bias magnetic circuit according to claim 4, characterized in that: The resistance value of the seventh resistor is equal to the resistance value of the eighth resistor.

6. The anti-bias magnetic circuit according to claim 1, characterized in that: The anti-magnetic bias circuit also includes: a low-pass filter circuit; The input end of the low-pass filter circuit is connected to the output end of the integration circuit, and the output end of the low-pass filter circuit is connected to the loop compensation circuit; The low-pass filtering circuit is used to perform low-pass filtering on the received integrated signal and transmit the integrated signal after low-pass filtering to the loop compensation circuit.

7. The anti-bias magnetic circuit according to claim 6, characterized in that: The low-pass filter circuit comprises: a ninth resistor and a fifth capacitor; The first end of the ninth resistor is connected to the output end of the integration circuit, and the second end of the ninth resistor is respectively connected to the first end of the fifth capacitor and the loop compensation circuit; the second end of the fifth capacitor is grounded.

8. The anti-bias magnetic circuit according to claim 2, characterized in that: The loop compensation circuit includes: a first comparator, a second comparator, a third operational amplifier and a PI controller; The inverting input terminal of the first comparator is connected to the output terminal of the integration circuit, the positive input terminal of the first comparator is connected to the second power supply, the output terminal of the first comparator is connected to the input terminal of the PI controller, the output terminal of the PI controller is connected to the positive input terminal of the second comparator, the inverting input terminal of the second comparator is used to receive a first reference voltage, the output terminal of the second comparator is connected to the positive input terminal of the third operational amplifier, the inverting input terminal of the third operational amplifier is used to receive a narrow-band signal with an amplitude of the second reference voltage, and the output terminal of the third operational amplifier is connected to the driver of the full-bridge switching converter; The second power supply is used to output a second power supply voltage, and the second power supply voltage is equal to half of the first power supply voltage output by the first power supply; and the second reference voltage is equal to twice the first reference voltage.

9. An anti-magnetic bias device, characterized in that: The anti-bias magnetic device adopts the anti-bias magnetic circuit as described in any one of claims 1-8.

10. An anti-magnetic bias system, characterized in that: The anti-bias magnetic system adopts the anti-bias magnetic device as claimed in claim 9.

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