Clock pulse generation circuit and integrated circuit
By designing circuits that integrate clock gating and clock pulse generation functions in integrated circuits, the problem of increased circuit area overhead is solved, and a super-large-scale integrated circuit design with low power consumption and high performance is realized.
Patent Information
- Application Number
- CN202311008176.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-10
- Publication Date
- 2025-02-18
AI Technical Summary
In large-scale integrated circuit designs, a clock pulse generation unit and a clock gating unit are added to improve performance and reduce power consumption, resulting in an increase in circuit area overhead.
Design a clock pulse generation circuit in an integrated circuit, which integrates clock gate function and clock pulse generation function, generates enable signals synchronized with the clock signal through the latch, and controls the three-input AND gate output clock shutdown signal. or clock pulse signal.
The design can output a clock shutdown signal in low power mode, save pulse latch clock turnover power consumption, reduce overall power consumption of integrated circuits, and reduce circuit area overhead through integrated functions.
Smart Images
Figure CN119483550A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuits, and in particular to a clock pulse generating circuit and an integrated circuit. Background Art
[0002] In the field of large-scale integrated circuit design, PPA (Power, Performance, Area) are three important indicators. Among them, performance represents whether the circuit can complete the functional goal in less time, power consumption represents the energy consumption of the circuit to complete the functional goal, and area represents the size of the circuit. Higher performance, lower power consumption and smaller area are the goals of large-scale integrated circuit design.
[0003] In terms of improving performance, using a pulse latch has higher performance than using a flip-flop or a general latch. The pulse latch requires an input clock pulse, so a clock pulse generating unit needs to be added to the pulse latch, but this will increase the circuit area overhead.
[0004] In terms of reducing power consumption, clock gating can be used to shut down the clock of functional components that have no execution tasks, reducing the redundant internal register flips with the clock flips, thereby reducing power consumption. However, the need to increase the clock gating unit will also increase the circuit area overhead. Summary of the invention
[0005] In view of the above problems, embodiments of the present invention are proposed to provide a clock pulse generating circuit and integrated circuit that overcome the above problems or at least partially solve the above problems, which can save the integrated circuit area overhead and reduce the power consumption of the integrated circuit.
[0006] In a first aspect, an embodiment of the present invention discloses a clock pulse generating circuit, comprising: a first input terminal, a second input terminal, a latch, a three-input AND gate and an output terminal;
[0007] The first input terminal is used to receive a first control signal and transmit it to the latch;
[0008] The second input terminal is used to receive a second control signal and transmit it to the latch;
[0009] The latch is used to receive a clock signal and a reverse delay signal of the clock signal, and generate a synchronization enable signal synchronized with the clock signal according to the clock signal, the reverse delay signal of the clock signal, the first control signal and / or the second control signal, and input the synchronization enable signal to the three-input AND gate;
[0010] The three-input AND gate is used to receive the clock signal, the reverse delay signal of the clock signal and the synchronization enable signal, and control the output end to output a clock shutdown signal or a clock pulse signal according to the clock signal, the reverse delay signal of the clock signal and the synchronization enable signal.
[0011] Optionally, when the first control signal is valid and the second control signal is invalid, the output end outputs a clock pulse signal.
[0012] Optionally, when both the first control signal and the second control signal are invalid, the output end outputs a clock shutdown signal.
[0013] Optionally, the output end is further used to output a clock signal when the second control signal is valid.
[0014] Optionally, the latch includes a first inverter, a second inverter and a third inverter, and the first inverter and the second inverter are three-state inverters with gate control;
[0015] The first inverter is used to receive the output of the first input terminal and the second input terminal, sample when the clock signal is at a high level, and input the output to the third inverter after inversion; or, turn off when the clock signal is at a low level;
[0016] The third inverter is used to receive the output of the first inverter or the second inverter, and input the output to the second inverter and the three-input AND gate respectively after inversion;
[0017] The second inverter is used to receive the output of the third inverter and be turned off when the clock signal is at a high level; or, to sample when the clock signal is at a low level and input it into the third inverter after inversion.
[0018] Optionally, the clock pulse generating circuit further comprises an OR gate; the OR gate is used to receive the first control signal of the first input terminal and the second control signal of the second input terminal, and output to the latch;
[0019] The output end is a selector; the selector is used to receive the clock signal, the output of the three-input AND gate and the second control signal of the second input end, and select to output the clock signal or the output of the three-input AND gate according to the second control signal.
[0020] Optionally, the clock pulse generating circuit further includes a fourth inverter and a fifth inverter;
[0021] The fourth inverter is used to receive the clock signal, and after inversion, input the clock signal into the fifth inverter, the latch and the three-input AND gate respectively;
[0022] The fifth inverter is used to receive the output of the fourth inverter and input the output into the latch after inversion.
[0023] Optionally, the output ends are respectively connected to a clock input of at least one pulse latch.
[0024] In a second aspect, an embodiment of the present invention discloses an integrated circuit, comprising any one of the above-mentioned clock pulse generating circuits.
[0025] Optionally, the integrated circuit further includes at least one pulse latch, and the output ends of the clock pulse generating circuit are respectively connected to the clock input of the at least one pulse latch.
[0026] The clock pulse generating circuit and integrated circuit provided by the embodiments of the present invention have the following advantages:
[0027] The clock pulse generating circuit provided in the embodiment of the present invention can provide a clock pulse signal for a pulse latch in a high-performance integrated circuit. In addition, the clock pulse generating circuit in the embodiment of the present invention also integrates a clock gating function, and can output a clock shutdown signal in a low-power mode to save the power consumption of the pulse latch clock flip, thereby reducing the overall power consumption of the integrated circuit. Furthermore, the embodiment of the present invention integrates the clock gating function and the clock pulse generating function into one unit (the clock pulse generating circuit in the embodiment of the present invention), which can save a large circuit area overhead compared to the related art that requires two units, namely, a gated clock unit and a pulse generating unit, and thus can save chip area. Therefore, the clock pulse generating circuit in the embodiment of the present invention can be used in the design of high-performance and low-power ultra-large-scale integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 It is a block diagram schematic diagram of a clock pulse generating circuit of the present invention;
[0029] Figure 2 It is a unit schematic diagram of a clock pulse generating circuit of the present invention;
[0030] Figure 3 It is a structural schematic diagram of a clock pulse generating circuit of the present invention. DETAILED DESCRIPTION
[0031] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.
[0032] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.
[0033] Figure 1 A block diagram of a clock pulse generating circuit according to an embodiment of the present invention is shown, wherein the clock pulse generating circuit comprises a first input terminal 101, a second input terminal 102, a latch 103, a three-input AND gate 104 and an output terminal 105, wherein:
[0034] The first input terminal 101 is used to receive a first control signal and transmit it to the latch;
[0035] The second input terminal 102 is used to receive a second control signal and transmit it to the latch;
[0036] The latch 103 is used to receive a clock signal and a reverse delay signal of the clock signal, and generate a synchronization enable signal synchronized with the clock signal according to the clock signal, the reverse delay signal of the clock signal, the first control signal and / or the second control signal, and input the synchronization enable signal to the three-input AND gate;
[0037] The three-input AND gate 104 is used to receive the clock signal, the reverse delayed signal of the clock signal and the synchronization enable signal, and control the output end 105 to output a clock shutdown signal or a clock pulse signal according to the clock signal, the reverse delayed signal of the clock signal and the synchronization enable signal.
[0038] The embodiment of the present invention provides a clock pulse generating circuit, the input of the clock pulse generating circuit includes a first control signal, a second control signal and a clock signal, and the output of the clock pulse generating circuit includes a clock shutdown signal or a clock pulse signal. Through the embodiment of the present invention, the clock pulse generating function and the clock gating function can be integrated into one unit (i.e., the clock pulse generating circuit of the embodiment of the present invention), which can save a large circuit area overhead and reduce the overall power consumption of the circuit compared to using the two circuit units of the clock pulse generating unit and the clock gating unit separately.
[0039] Reference Figure 2 , shows a unit schematic diagram of a clock pulse generating circuit 200 according to an embodiment of the present invention, such as Figure 2 As shown, the clock pulse generating circuit 200 can receive a first control signal EN, a second control signal TE and a clock signal G, and the output of the clock pulse generating circuit 200 is CP. According to the first control signal EN and the second control signal TE, the output CP of the clock pulse generating circuit 200 can be controlled to be a clock shutdown signal or a clock pulse signal. The output CP of the clock pulse generating circuit 200 can be connected to the clock input of the pulse latch, so that the pulse latch can be controlled to enter a functional mode or a low power consumption mode. Furthermore, the embodiment of the present invention can also control the output CP of the clock pulse generating circuit 200 to be a normal clock signal G through the second control signal TE, thereby controlling the pulse latch to enter a scan test mode.
[0040] For example, the first control signal EN can control the clock enable in the functional mode, and the second control signal TE can control the clock enable in the scan test mode. When the clock is not turned off, only one of the first control signal EN and the second control signal TE is valid. When the clock is turned off, the first control signal EN and the second control signal TE are both invalid.
[0041] Optionally, when the first control signal is valid and the second control signal is invalid, the output end outputs a clock pulse signal.
[0042] like Figure 2 As shown, when the first control signal EN is valid (high level 1) and the second control signal TE is invalid (low level 0), the CP output by the clock pulse generating circuit 200 is a clock pulse signal, thereby providing a clock pulse signal for the pulse latch, so that the pulse latch is in a functional mode. The functional mode refers to a normal working mode.
[0043] Optionally, when both the first control signal and the second control signal are invalid, the output end outputs a clock shutdown signal.
[0044] like Figure 2 As shown, when the first control signal EN and the second control signal TE are both invalid, the CP output by the clock pulse generating circuit 200 is a clock shutdown signal, thereby shutting off the clock of the pulse latch and putting the pulse latch in a low power consumption mode, thereby saving the power consumption generated by the clock flip of the pulse latch.
[0045] Optionally, the output end may also be used to output a clock signal when the second control signal is valid.
[0046] like Figure 2 As shown, when the second control signal TE is valid, the CP output by the clock pulse generating circuit 200 is the clock signal G, so that the pulse latch is in the scan test mode.
[0047] Specifically, the clock pulse generating circuit may include a first input terminal 101 , a second input terminal 102 , a latch 103 , a three-input AND gate 104 , and an output terminal 105 .
[0048] The first input terminal 101 is used to receive a first control signal EN and transmit it to the latch 103. The second input terminal 102 is used to receive a second control signal TE and transmit it to the latch 103. The clock pulse generating circuit may further include a clock signal input terminal for receiving a clock signal. The latch 103 is used to receive a clock signal and a reverse delay signal of the clock signal, and generate a synchronization enable signal synchronized with the clock signal according to the clock signal, the reverse delay signal of the clock signal, the first control signal EN and / or the second control signal TE, and input the synchronization enable signal to the three-input AND gate 104.
[0049] In an embodiment of the present invention, the latch 103 can be used to generate an enable signal (referred to as a synchronous enable signal in the embodiment of the present invention) synchronized with the clock signal. The synchronous enable signal is input into the three-input AND gate 104. When the three-input AND gate 104 uses the synchronous enable signal to control the output terminal 105 to output a clock pulse signal, the output clock pulse signal can be synchronized with the clock signal.
[0050] The three-input AND gate 104 is used to receive the clock signal, the reverse delay signal of the clock signal and the synchronization enable signal output by the latch 103, and control the output end 105 to output a clock shutdown signal or a clock pulse signal according to the clock signal, the reverse delay signal of the clock signal and the synchronization enable signal.
[0051] In an optional embodiment of the present invention, the clock pulse generating circuit may further include an OR gate; the OR gate may be used to receive a first control signal from the first input terminal and a second control signal from the second input terminal, and output the signals to the latch;
[0052] The output end may be a selector; the selector may be configured to receive the clock signal, the output of the three-input AND gate, and a second control signal from the second input end, and select to output the clock signal or the output of the three-input AND gate according to the second control signal.
[0053] The embodiment of the present invention does not limit the specific structure of the first input terminal, the second input terminal, the latch and the output terminal. Exemplarily, the clock pulse generating circuit may also include an OR gate, the first input terminal and the second input terminal may be connected to the input of the OR gate, the first control signal and the second control signal are input to the OR gate, the output of the OR gate is connected to the input of the latch, and a synchronous enable signal synchronized with the clock signal is generated through the latch; the latch may be implemented by three inverters; the output terminal may be implemented by a multiplexer, and the second input terminal may also be connected to the input of the multiplexer to control the output of the multiplexer.
[0054] In an optional embodiment of the present invention, the latch may include a first inverter, a second inverter and a third inverter, and the first inverter and the second inverter are three-state inverters with gate control. Figure 3 , shows a schematic diagram of the structure of a clock pulse generating circuit according to an embodiment of the present invention. Figure 3 As shown, the clock pulse generating circuit includes a first input terminal, a second input terminal, a latch, a three-input AND gate and an output terminal, wherein the first input terminal and the second input terminal are implemented by an OR gate OR1, and the first control signal EN and the second control signal TE are input into the OR gate OR1. The latch is implemented by three inverters, specifically, the latch includes a first inverter T1, a second inverter T2 and a third inverter I1, the first inverter T1 and the second inverter T2 are three-state inverters with gate control; the third inverter I1 is a general general inverter. The output terminal of the clock pulse generating circuit is implemented by a selector MUX, and the selector MUX is a two-selection multiplexer.
[0055] Specifically, the first inverter is used to receive the output of the first input terminal and the second input terminal (i.e., the OR gate OR1); the first inverter samples when the clock signal is at a high level, and inputs the output to the third inverter after inversion; or, the first inverter is turned off when the clock signal is at a low level. The third inverter is used to receive the output of the first inverter or the second inverter, and inputs the output to the second inverter and the three-input AND gate respectively after inversion. When the first inverter is turned off, the third inverter receives the output of the second inverter; when the second inverter is turned off, the third inverter receives the output of the first inverter. The second inverter is used to receive the output of the third inverter; the second inverter is turned off when the clock signal is at a high level; or, the second inverter samples when the clock signal is at a low level, and inputs the output to the third inverter after inversion. The second inverter and the third inverter connected end to end form a mutual feedback coupling form.
[0056] like Figure 3 As shown, the first control signal EN and the second control signal TE are input to the OR gate OR1. The output of OR1 is input to the first inverter T1. The first inverter T1 samples when the clock signal is at a high level, and then inputs to the third inverter I1 after inversion. When the clock signal is at a low level, the first inverter T1 is turned off.
[0057] Among them, T1 is a three-state inverter with gate control. T1 receives the output of OR1, GI and GN. When G is high level 1, GN is low level 0, GI is high level 1, and T1 samples at this time, that is, T1 reverses the output of OR1 and then outputs it to the third inverter I1. When G is low level 0, GN is high level 1, GI is low level 0, and T1 is turned off at this time.
[0058] I1 is a general inverter, which inverts the output of T1 and outputs GL. GL is respectively input into the second inverter T2 and the three-input AND gate AND1.
[0059] T2 is a three-state inverter with gate control. T2 receives GN, GI and the output GL of I1. When G is high level 1, GN is low level 0, GI is high level 1, and T2 is turned off. When G is low level 0, GN is high level 1, GI is low level 0, and T2 samples at this time, that is, T2 inverts the output of I1 at this time, and then outputs it to the third inverter I1.
[0060] like Figure 3As shown, the output of the latch is the output GL of the third inverter I1, GL is a synchronization enable signal synchronized with the clock, and the three-input AND gate AND1 uses the synchronization enable signal synchronized with the clock to control the generation of the clock pulse signal selected by the selector MUX, thereby outputting a clock pulse signal synchronized with the clock.
[0061] Further, the selector MUX is used to receive the clock signal, the output of the three-input AND gate and the second control signal, and select to output the clock signal or the output of the three-input AND gate according to the second control signal. For example, when the second control signal TE is valid (TE is high level 1), the MUX selects to output the clock signal G; when the second control signal TE is invalid (TE is low level 0), the MUX selects to output the output of the three-input AND gate.
[0062] Furthermore, the clock pulse generating circuit may further include a clock delay unit, which is used to receive a clock signal and output a delayed signal of the clock signal. The pulse width of the clock pulse signal output by the clock pulse generating circuit of the embodiment of the present invention may be determined by the length of the clock delay generated by the clock delay unit.
[0063] Furthermore, the clock delay unit may include a fourth inverter (such as Figure 3 I2 in) and the fifth inverter (such as Figure 3 I3 in the figure); the fourth inverter I2 is used to receive the clock signal, delay and invert it to output a reverse delay signal GN, which is respectively input to the fifth inverter, the latch and the three-input AND gate; the fifth inverter I3 is used to receive the output of the fourth inverter, delay and invert it to output a reverse delay signal GI, which is input to the latch. GI is the delayed signal of the clock signal G.
[0064] like Figure 3 As shown, the input of the fourth inverter I2 is the clock signal G, which is delayed and inverted by I2 to obtain GN, which is respectively input into the fifth inverter I3, the first inverter T1 and the three-input AND gate AND1, and GN is delayed and inverted by I3 to obtain GI, which is respectively input into the first inverter T1 and the second inverter T2.
[0065] In low power mode, the first control signal EN and the second control signal TE are both invalid (both are low level 0), and the output of OR1 is low level 0; when the rising edge of clock G arrives, the first inverter T1 starts sampling, and the second inverter T2 is turned off; the output of OR1 is high level 1 after being inverted by T1, and after being inverted by the third inverter I1, the output GL of I1 is low level 0; at this time, one input (that is, GL) of the three-input AND gate AND1 is low level 0, so the output of the three-input AND gate AND1 is low level 0. Since TE is 0, the selector MUX selects the output of AND1 for output, and the output CP is low level 0 at this time, that is, the output CP is the clock shutdown signal. When the falling edge of clock G arrives, the first inverter T1 is turned off, and the second inverter T2 starts sampling. At this time, the output GL of I1 (GL is low level 0 at this time) is input to T2, and after being inverted by T2, it is input to I1, and after being inverted by I1, the output GL is low level 0. Therefore, in low power mode, the latch keeps outputting low level 0.
[0066] In the functional mode, the first control signal EN is valid (high level 1), the second control signal TE is invalid (low level 0), and the output of OR1 is high level 1; when the rising edge of the clock G arrives, the first inverter T1 starts sampling, and the second inverter T2 is turned off; the output of OR1 is low level 0 after being reversed by T1, and after being reversed by the third inverter I1, the output GL of I1 is high level 1; the input of the three-input AND gate AND1 includes the clock signal G, the reverse delay signal GN of the clock signal, and the output GL of I1; at this time, GL is high level 1, G is high level 1, and GN is low level 0. Due to the delay between G and GN, the input GL of the three-input AND gate AND1 is high level 1, and becomes low level 0 after delay and inversion. The output is high level first, and then the output becomes low level 0 with the input G, thereby realizing the output as a pulse, and the pulse width depends on the reverse delay of the input G and the input GN. When TE=0, the selector MUX selects the output of AND1 as a pulse.
[0067] In the scan test mode, the second control signal TE is valid (high level 1), and the selector MUX selects the output of AND1 as G, and the output is a normal clock signal.
[0068] In an optional embodiment of the present invention, the output terminals may be respectively connected to a clock input of at least one pulse latch.
[0069] The clock pulse generating circuit provided by the embodiment of the present invention can be applied to a high-performance integrated circuit, which may include a group of pulse latches, wherein the group of pulse latches includes at least one pulse latch. The clock pulse generating circuit of the embodiment of the present invention can provide a clock pulse signal for the group of pulse latches, and the number of group pulse latches included in the group of pulse latches is determined by the driving capability of the clock pulse generating circuit.
[0070] In summary, the embodiment of the present invention provides a clock pulse generating circuit that can provide a clock pulse signal for a pulse latch under high-performance applications. The clock pulse generating circuit of the embodiment of the present invention also integrates a clock gating function, and can output a clock shutdown signal in a low-power mode to save the power consumption of the pulse latch clock flip, thereby reducing the overall power consumption of the integrated circuit. The embodiment of the present invention integrates the clock gating function and the clock pulse generating function into one unit (the clock pulse generating circuit of the embodiment of the present invention), which only adds a small area cost compared to a single-function clock gating unit, but can simultaneously meet the needs of generating clock pulses and clock gating. Compared with the related art that requires two units, the gated clock unit and the pulse generating unit, a large circuit area overhead can be saved. In addition, the embodiment of the present invention can save circuit area overhead in the design of high-performance integrated circuits, and thus can save chip area. Therefore, the embodiment of the present invention can be used for high-performance and low-power ultra-large-scale integrated circuit design.
[0071] Furthermore, based on the embodiments of the present invention, a clock gating unit that can generate a clock pulse signal can be realized, and the clock gating function and the clock pulse generating function are integrated into one unit. The clock pulse generating circuit of the embodiment of the present invention can be easily inserted into the digital circuit design process. In the design process, it is only necessary to replace the original clock gating unit and trigger with the clock pulse generating circuit of the embodiment of the present invention, which can save chip area and reduce chip cost.
[0072] Furthermore, the embodiment of the present invention synchronizes the clock gating enable with the clock through a latch, which can make the timing analysis and convergence process easier, and can reduce the time required for chip design sign-off and tape-out and the failure rate.
[0073] An embodiment of the present invention further provides an integrated circuit, the integrated circuit comprising Figures 1 to 3 The clock pulse generating circuit shown in any one of the embodiments.
[0074] The integrated circuit may be a high-performance integrated circuit, which may include a group of pulse latches, wherein the group of pulse latches includes at least one pulse latch. The clock pulse generating circuit of the embodiment of the present invention may provide a clock pulse signal for the group of pulse latches, and the number of the group of pulse latches included in the group of pulse latches is determined by the driving capability of the clock pulse generating circuit.
[0075] The embodiment of the present invention integrates the clock gating function and the clock pulse generating function into one unit (the clock pulse generating circuit of the embodiment of the present invention), which only adds a small area cost compared with the clock gating unit with a single function, but can simultaneously meet the requirements of generating clock pulses and clock gating. Compared with the related art that requires two units, the gated clock unit and the pulse generating unit, a large circuit area cost can be saved. Therefore, the embodiment of the present invention can save circuit area cost in the design of high-performance integrated circuits, and further save chip area, and can be used for high-performance and low-power ultra-large-scale integrated circuit design.
[0076] The embodiment of the present invention further provides a chip, the chip comprising Figures 1 to 3 The clock pulse generating circuit shown in any one of the embodiments. The embodiment of the present invention integrates the clock gating function and the clock pulse generating function into one unit (the clock pulse generating circuit of the embodiment of the present invention), and the clock gating enables synchronization with the clock through a latch, so that the clock pulse generating circuit of the embodiment of the present invention can be conveniently inserted into the digital circuit design process. In the design process, it is only necessary to replace the original clock gating unit and trigger with the clock pulse generating circuit of the embodiment of the present invention, which can make the timing analysis and convergence process easier, save chip area, and reduce chip cost.
[0077] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.
[0078] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.
[0079] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0080] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0081] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0082] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.
[0083] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.
Claims
1. A clock pulse generating circuit, characterized in that: include: A first input terminal, a second input terminal, a latch, a three-input AND gate, and an output terminal; The first input terminal is used to receive a first control signal and transmit it to the latch; The second input terminal is used to receive a second control signal and transmit it to the latch; The latch is used to receive a clock signal and a reverse delay signal of the clock signal, and generate a synchronization enable signal synchronized with the clock signal according to the clock signal, the reverse delay signal of the clock signal, the first control signal and / or the second control signal, and input the synchronization enable signal to the three-input AND gate; The three-input AND gate is used to receive the clock signal, the reverse delay signal of the clock signal and the synchronization enable signal, and control the output end to output a clock shutdown signal or a clock pulse signal according to the clock signal, the reverse delay signal of the clock signal and the synchronization enable signal.
2. The method according to claim 1, characterized in that When the first control signal is valid and the second control signal is invalid, the output end outputs a clock pulse signal.
3. The method according to claim 1, characterized in that When both the first control signal and the second control signal are invalid, the output end outputs a clock shut-off signal.
4. The method according to claim 1, characterized in that: The output end is also used to output a clock signal when the second control signal is valid.
5. The method according to claim 1, characterized in that The latch comprises a first inverter, a second inverter and a third inverter, wherein the first inverter and the second inverter are three-state inverters with gate control; The first inverter is used to receive the output of the first input terminal and the second input terminal, sample when the clock signal is at a high level, and input the output to the third inverter after inversion; or, turn off when the clock signal is at a low level; The third inverter is used to receive the output of the first inverter or the second inverter, and input the output to the second inverter and the three-input AND gate respectively after inversion; The second inverter is used to receive the output of the third inverter and be turned off when the clock signal is at a high level; or, to sample when the clock signal is at a low level and input it into the third inverter after inversion.
6. The method according to claim 1, characterized in that The clock pulse generating circuit further comprises an OR gate; the OR gate is used to receive the first control signal of the first input terminal and the second control signal of the second input terminal, and output to the latch; The output end is a selector; The selector is used to receive the clock signal, the output of the three-input AND gate and the second control signal at the second input terminal, and select to output the clock signal or the output of the three-input AND gate according to the second control signal.
7. The method according to claim 1, characterized in that The clock pulse generating circuit further comprises a clock delay unit, and the clock delay unit comprises a fourth inverter and a fifth inverter; The fourth inverter is used to receive the clock signal, delay and invert it, and then input it into the fifth inverter, the latch and the three-input AND gate respectively; The fifth inverter is used to receive the output of the fourth inverter, delay and invert the output, and then input it into the latch.
8. The method according to claim 1, characterized in that The output terminals are respectively connected to a clock input of at least one pulse latch.
9. An integrated circuit, characterized in that: The method comprises a clock pulse generating circuit as claimed in any one of claims 1 to 8.
10. The integrated circuit according to claim 9, further comprising at least one pulse latch, wherein the output terminals of the clock pulse generating circuit are respectively connected to the clock input terminals of the at least one pulse latch.