Power-on reset circuit and electronic equipment

Abstract

The embodiment of the invention relates to the technical field of integrated circuits, provides a power-on reset circuit and electronic equipment, and can greatly avoid the problem of false triggering or non-triggering of a reset signal caused by process fluctuation and temperature change, thereby improving the reliability of the equipment. The power-on reset circuit comprises a band-gap voltage reference module and an operational amplifier. The band-gap voltage reference module is used for controlling the resistance value of each resistor unit in the first branch and the resistance value of each resistor unit in the second branch, so that the band-gap voltage reference module has a first balanced voltage when the voltage of the power supply is in a rising stage and has a second balanced voltage when the voltage of the power supply is in a falling stage; the first balanced voltage is greater than the second balanced voltage; the operational amplifier is used for amplifying the difference value between the voltage of the emitter of the first PNP type triode and the voltage of the signal input end of the third resistor unit.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a power-on reset circuit and an electronic device. Background Art

[0002] The power-on reset (POR) circuit is a vital component in analog integrated circuits. Its main function is to generate a reset signal when the power supply voltage rises to ensure that the system starts working from a known initial state. With the continuous evolution of semiconductor technology, especially the widespread application of CMOS (Complementary Metal Oxide Semiconductor) technology, the traditional POR circuit design is prone to reset signal uncertainty under different process, temperature (Temperature, T), voltage (Voltage, V) and process variation (Process Variation, P) conditions, resulting in unreliable system initialization. Summary of the invention

[0003] The embodiments of the present application provide a power-on reset circuit and an electronic device, which can significantly avoid the problem of false triggering or non-triggering of a reset signal due to process fluctuations and temperature changes, thereby improving the reliability of the device.

[0004] An embodiment of the present application provides a power-on reset circuit, including: a bandgap voltage reference module and an operational amplifier; The bandgap voltage reference module includes a first branch and a second branch; the first branch includes a first PNP-type triode, a first resistor unit and a first bias resistor unit, the first bias resistor unit is arranged in parallel between the emitter and the collector of the first PNP-type triode, the base and the collector of the first PNP-type triode are electrically connected to the ground terminal, and the first resistor unit is arranged between a power supply and the emitter of the first PNP-type triode; The second branch includes a second PNP type triode, a second resistance unit, a second bias resistance unit and a third resistance unit, the second resistance unit and the third resistance unit are arranged in series between the power supply and the emitter of the second PNP type triode, the signal input end of the third resistance unit is electrically connected to the second resistance unit, the signal output end of the third resistance unit is electrically connected to the emitter of the second PNP type triode, the base and collector of the second PNP type triode are electrically connected to the ground end, and the second bias resistance unit is arranged in parallel between the signal input end of the third resistance unit and the collector of the second PNP type triode; The negative phase input terminal of the operational amplifier is electrically connected to the emitter of the first PNP type transistor, and the positive phase input terminal of the operational amplifier is electrically connected to the signal input terminal of the third resistance unit; The bandgap voltage reference module is used to: control the resistance of each resistor unit in the first branch and the resistance of each resistor unit in the second branch, so that the bandgap voltage reference module has a first balance voltage when the voltage of the power supply is in an ascending stage, and has a second balance voltage when the voltage of the power supply is in a descending stage, and the first balance voltage is greater than the second balance voltage, wherein the first balance voltage is the power supply voltage corresponding to when the voltage of the power supply is in an ascending stage and the difference between the voltage of the emitter of the first PNP type transistor and the voltage of the signal input end of the third resistor unit is zero; the second balance voltage is the power supply voltage corresponding to when the voltage of the power supply is in a descending stage and the difference between the voltage of the emitter of the first PNP type transistor and the voltage of the signal input end of the third resistor unit is zero; The operational amplifier is used to amplify the difference between the voltage of the emitter of the first PNP transistor and the voltage of the signal input end of the third resistor unit.

[0005] According to some embodiments of the present application, the power-on reset circuit further includes: a trigger; the output end of the operational amplifier is electrically connected to the input end of the trigger; The trigger is used to: When the voltage of the power supply is in a rising stage, when the voltage signal received by the negative phase input terminal of the operational amplifier is greater than or equal to the voltage signal received by the positive phase input terminal of the operational amplifier, a high level signal is output; when the voltage signal received by the negative phase input terminal of the operational amplifier is less than the voltage signal received by the positive phase input terminal of the operational amplifier, a low level signal is output; When the voltage of the power supply is in a decreasing stage, when the voltage signal received at the negative input terminal of the operational amplifier is less than the voltage signal received at the positive input terminal of the operational amplifier, the low level signal is output; when the voltage signal received at the negative input terminal of the operational amplifier is greater than or equal to the voltage signal received at the positive input terminal of the operational amplifier, the high level signal is output.

[0006] According to some embodiments of the present application, the first bias resistor unit and the second bias resistor unit have the same structure; The first resistance unit is configured to have a first resistance value under the control of the high level signal; and is configured to have a second resistance value under the control of the low level signal; the first resistance value is greater than the second resistance value; The first bias resistor unit is configured to have a third resistance value under the control of the high level signal; and is configured to have a fourth resistance value under the control of the low level signal; and the third resistance value is smaller than the fourth resistance value.

[0007] According to some embodiments of the present application, the resistance value of the third resistance unit is fixed.

[0008] According to some embodiments of the present application, the resistance of the first biasing resistor unit is M times the resistance of the third resistor unit, where M is greater than or equal to 6.

[0009] According to some embodiments of the present application, the second resistance unit and the first resistance unit have the same structure; the emitter area of ​​the second PNP type transistor is N times the emitter area of ​​the first PNP type transistor, and N is greater than 1.

[0010] According to some embodiments of the present application, the resistance of the second resistance unit is N times the resistance of the first resistance unit, and N is greater than 1; the emitter area of ​​the second PNP transistor is the same as the emitter area of ​​the first PNP transistor.

[0011] According to some embodiments of the present application, the first resistance unit includes a first switch, and a first resistor and a second resistor connected in series, the first resistor and the first switch are arranged in parallel; the first resistor is arranged between the power supply and the second resistor; the first switch is used to maintain an off state under the control of the high level signal; and maintain an on state under the control of the low level signal; The first bias resistor unit includes a second switch, and a first bias resistor and a second bias resistor connected in series, the second bias resistor and the second switch are arranged in parallel; the second bias resistor is arranged between the first bias resistor and the ground terminal; the second switch is used to maintain a conducting state under the control of the high level signal; and maintain a disconnected state under the control of the low level signal; The second resistor unit includes a third switch, and a fourth resistor and a fifth resistor connected in series, wherein the fourth resistor and the third switch are arranged in parallel; the fourth resistor is arranged between the power supply and the fifth resistor; the third switch is used to maintain an off state under the control of the high level signal; and maintain an on state under the control of the low level signal; The second bias resistor unit includes a fourth switch, and a third bias resistor and a fourth bias resistor connected in series, wherein the fourth bias resistor and the fourth switch are arranged in parallel; the fourth bias resistor is arranged between the third bias resistor and the ground terminal; the fourth switch is used to maintain a conducting state under the control of the high level signal; and maintain a disconnected state under the control of the low level signal; The third resistor unit includes a third resistor.

[0012] According to some embodiments of the present application, the power-on reset circuit further includes an inverter; The trigger includes a first P-type transistor, a second P-type transistor, a third P-type transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor and a fifth N-type transistor; The source of the first P-type transistor is electrically connected to the power supply, the drain of the first P-type transistor, the source of the second P-type transistor, and the source of the third P-type transistor are electrically connected, the drain of the second P-type transistor, the drain of the first N-type transistor, the gate of the third P-type transistor, and the gate of the third N-type transistor are electrically connected, the drain of the third N-type transistor is electrically connected to the ground terminal, the source of the first N-type transistor, the drain of the second N-type transistor, and the drain of the third N-type transistor are electrically connected, the source of the third N-type transistor is electrically connected to the power supply, the source of the second N-type transistor, the drain and the gate of the fourth N-type transistor, and the drain of the fifth N-type transistor are electrically connected, the sources of the fourth N-type transistor and the fifth N-type transistor are electrically connected to the ground terminal, the gates of the first P-type transistor, the second P-type transistor, the first N-type transistor, and the second N-type transistor are all electrically connected to the output terminal of the operational amplifier, and the gate of the fifth N-type transistor is electrically connected to the output terminal of the inverter; The drain of the second P-type transistor is used as the output terminal of the trigger, the input terminal of the inverter is electrically connected to the drain of the second P-type transistor, and the inverter is used to invert the signal output by the trigger.

[0013] According to some embodiments of the present application, another aspect of the embodiments of the present application provides an electronic device, including: the above-mentioned power-on reset circuit.

[0014] The embodiment of the present application provides a power-on reset circuit and an electronic device. When the voltage vddx of the power supply is in the rising stage, the power-on reset circuit controls the resistance of each resistor unit in the first branch and the resistance of each resistor unit in the second branch, so that the power-on reset circuit has a first equilibrium voltage; when the voltage vddx of the power supply is in the falling stage, the power-on reset circuit controls the resistance of each resistor unit in the first branch and the resistance of each resistor unit in the second branch, so that the power-on reset circuit has a second equilibrium voltage, and the first equilibrium voltage is greater than the second equilibrium voltage. In this way, when the voltage vddx of the power supply is in the process of slowly rising or slowly falling, even if the power supply voltage fluctuates upward or downward due to process fluctuations and temperature changes, since the first equilibrium voltage in the rising stage is greater than the second equilibrium voltage in the falling stage, the power supply voltage will not touch the second equilibrium voltage when the equilibrium state fluctuates in the rising stage, or, when the equilibrium state fluctuates in the falling stage, it will not touch the first equilibrium voltage, so there will be no problem of false triggering or non-triggering of the reset signal. The power-on reset circuit provided in the embodiment of the present application can greatly avoid the problem of false triggering or non-triggering of the reset signal caused by process fluctuations and temperature changes, thereby improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present application or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 A schematic diagram of the structure of a power-on reset circuit provided in an embodiment of the present application; Figure 2 A schematic diagram of the structure of another power-on reset circuit provided in an embodiment of the present application; Figure 3 A schematic diagram of the signal output of a Schmitt trigger provided for the related technology; Figure 4 A schematic diagram of a signal output by a trigger provided in an embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0018] In the description of the embodiments of the present application, "at least one" means one or more, "multiple" means two or more, and "multiple times" means two or more, unless otherwise clearly and specifically defined.

[0019] In the description of the embodiments of the present application, technical terms such as "first" and "second" are only used to distinguish different objects and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features.

[0020] In the description of the embodiments of the present application, the character “ / ” generally indicates that the previously associated objects are in an “or” relationship.

[0021] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0022] In the description of the embodiments of the present application, when a certain component “includes” another component, unless otherwise stated, other components are not excluded and other components may be further included.

[0023] The traditional POR circuit based on MOS (Metal Oxide Semiconductor) tube is easily affected by process fluctuations and temperature changes, resulting in the problem of false triggering or non-triggering of the reset signal. In the power-on reset circuit of the related art, only one balance voltage is set, that is, the balance voltage is the same when the power supply voltage is in the rising stage and when the power supply voltage is in the falling stage. Then, in the process of the power supply voltage slowly rising or slowly falling, the trigger point of the circuit is easy to drift, resulting in an unstable reset signal. For example, when the power supply voltage is in the slowly rising stage, the power supply voltage rises to the voltage trigger point and enters the reset state; at this time, if noise occurs due to process fluctuations and temperature changes, the power supply voltage is very likely to fluctuate upward or downward due to noise, and the power supply voltage fluctuates up and down at the voltage trigger point, which makes the reset signal extremely unstable, and it is very easy to cause the reset signal to be falsely triggered or not triggered.

[0024] Based on this, the embodiment of the present application provides a power-on reset circuit, referring to Figure 1 and Figure 2 As shown, it includes: a bandgap voltage reference module 1 and an operational amplifier 2.

[0025] refer to Figure 1 and Figure 2 As shown, the bandgap voltage reference module 1 includes a first branch and a second branch; the first branch includes a first PNP transistor Q1, a first resistor unit 11 and a first bias resistor unit 12, the first bias resistor unit 12 is arranged in parallel between the emitter and the collector of the first PNP transistor Q1, the base and the collector of the first PNP transistor Q1 are electrically connected to the ground terminal, and the first resistor unit 11 is arranged between the power supply and the emitter of the first PNP transistor Q1.

[0026] refer to Figure 1 and Figure 2 As shown, the second branch includes a second PNP transistor Q2, a second resistor unit 13, a second bias resistor unit 14 and a third resistor unit 15. The second resistor unit 13 and the third resistor unit 15 are arranged in series between the power supply and the emitter of the second PNP transistor Q2. The signal input end of the third resistor unit 15 is electrically connected to the second resistor unit 13, the signal output end of the third resistor unit 15 is electrically connected to the emitter of the second PNP transistor Q2, the base and collector of the second PNP transistor Q2 are electrically connected to the ground end, and the second bias resistor unit 14 is arranged in parallel between the signal input end of the third resistor unit 15 and the collector of the second PNP transistor Q2.

[0027] refer to Figure 1 and Figure 2As shown, the negative phase input terminal of the operational amplifier 2 is electrically connected to the emitter of the first PNP transistor Q1 , and the positive phase input terminal of the operational amplifier 2 is electrically connected to the signal input terminal of the third resistor unit 15 .

[0028] refer to Figure 1 and Figure 2 As shown, the bandgap voltage reference module 1 is used to: by controlling the resistance of each resistor unit in the first branch and the resistance of each resistor unit in the second branch, the bandgap voltage reference module has a first equilibrium voltage when the voltage vddx of the power supply is in the rising stage, and has a second equilibrium voltage when the voltage vddx of the power supply is in the falling stage, and the first equilibrium voltage is greater than the second equilibrium voltage, wherein the first equilibrium voltage is the voltage of the emitter of the first PNP transistor Q1 when the voltage of the power supply is in the rising stage. V be1 and the voltage at the signal input terminal of the third resistor unit 15 V be2_amp the second equilibrium voltage is when the power supply voltage is in the falling stage, the emitter voltage of the first PNP transistor Q1 and the voltage of the signal input terminal of the third resistor unit 15 are zero when the difference is the corresponding power supply voltage.

[0029] refer to Figure 1 and Figure 2 As shown, the operational amplifier 2 is used to amplify the difference between the voltage of the emitter of the first PNP transistor Q1 and the voltage of the signal input terminal of the third resistor unit 15, and output the signal Vin_smt.

[0030] refer to Figure 1 and Figure 2 As shown, the ground terminal can provide a ground voltage vssx.

[0031] In the embodiment of the present application, the first PNP transistor and the second PNP transistor are bipolar junction transistors (BJT). Compared with NPN transistors, PNP transistors are more widely compatible with various CMOS processes and reduce design adjustments caused by different processes.

[0032] In the first branch of the embodiment of the present application, the specific structures of the first resistor unit and the first bias resistor unit are not limited; in the second branch of the embodiment of the present application, the specific structures of the second resistor unit, the second bias resistor unit and the third resistor unit are not limited.

[0033] In the embodiment of the present application, the resistance of each resistor unit in the first branch and the resistance of each resistor unit in the second branch will directly affect the size of the equilibrium voltage (i.e., the voltage trigger point). The embodiment of the present application does not limit the specific method for controlling the resistance of each resistor unit in the first branch and the resistance of each resistor unit in the second branch. For example, part of the structure of the resistor unit can be set as a variable resistor and the rest can be set as a resistor with a fixed resistance. By controlling the resistance of the variable resistor, the resistance of the resistor unit can be controlled; or, a switch can be set to control part of the structure of the resistor unit, thereby controlling the resistance of the resistor unit. Of course, other control methods can also be used, which will not be repeated here.

[0034] In the embodiment of the present application, controlling the resistance of each resistor unit in the first branch may be by separately controlling the first resistor unit and the first bias resistor unit in the first branch, that is, both the first resistor unit and the first bias resistor unit are controllable; or, only the first resistor unit may be controlled, and the resistance of the first bias resistor unit is fixed; or, only the first bias resistor unit may be controlled, and the resistance of the first resistor unit is fixed; this is not limited here.

[0035] In the embodiment of the present application, the resistance value of each resistor unit in the second branch is controlled by controlling the second resistor unit, the second bias resistor unit and the third resistor unit in the second branch respectively, that is, the second resistor unit, the second bias resistor unit and the third resistor unit are all controllable; or, only part of the second resistor unit, the second bias resistor unit and the third resistor unit can be controlled. For example, the second resistor unit and the second bias resistor unit in the second branch can be controlled respectively, and the resistance value of the third resistor unit is fixed; this is not limited here.

[0036] In the embodiment of the present application, the first balance voltage is greater than the second balance voltage. In order to further ensure the stability of the reset signal, the difference between the first balance voltage and the second balance voltage may be greater than or equal to a preset value, and the preset value may be determined according to the noise signal generated by process fluctuations and temperature changes. For example, the preset value may be 45mv, 50mv or 55mv, etc. The specific values ​​of the first balance voltage and the second balance voltage need to be determined according to the specific circuit structures of the first branch and the second branch, and are not limited here.

[0037] The power-on reset circuit provided by the embodiment of the present application has a hysteresis characteristic, that is, when the voltage vddx of the power supply is in the rising stage, by controlling the resistance of each resistor unit in the first branch and the resistance of each resistor unit in the second branch, the power-on reset circuit has a first equilibrium voltage; when the voltage vddx of the power supply is in the falling stage, by controlling the resistance of each resistor unit in the first branch and the resistance of each resistor unit in the second branch, the power-on reset circuit has a second equilibrium voltage, and the first equilibrium voltage is greater than the second equilibrium voltage. In this way, when the voltage vddx of the power supply is in the process of slowly rising or slowly falling, even if the power supply voltage fluctuates upward or downward due to process fluctuations and temperature changes, since the first equilibrium voltage in the rising stage is greater than the second equilibrium voltage in the falling stage, the power supply voltage will not touch the second equilibrium voltage when the equilibrium state fluctuates in the rising stage, or, when the equilibrium state fluctuates in the falling stage, it will not touch the first equilibrium voltage, so there will be no problem of false triggering or non-triggering of the reset signal. The power-on reset circuit provided by the embodiment of the present application can greatly avoid the problem of false triggering or non-triggering of the reset signal caused by process fluctuations and temperature changes, thereby improving the reliability of the device.

[0038] In one or more embodiments, in order to reduce the influence of noise on the output signal of the operational amplifier, reference Figure 2 As shown, the power-on reset circuit further includes: a trigger 3; the output end of the operational amplifier 2 is electrically connected to the input end of the trigger 3.

[0039] Trigger 3 is used to: When the voltage of the power supply is in the rising stage, when the voltage signal received by the negative phase input terminal of the operational amplifier 2 is greater than or equal to the voltage signal received by the positive phase input terminal of the operational amplifier 2, a high level signal is output, and at this time, the voltage of the power supply is less than or equal to the first equilibrium voltage; when the voltage signal received by the negative phase input terminal of the operational amplifier 2 is less than the voltage signal received by the positive phase input terminal of the operational amplifier 2, a low level signal is output, and at this time, the voltage of the power supply is greater than the first equilibrium voltage.

[0040] When the voltage of the power supply is in the decreasing stage, when the voltage signal received by the negative phase input terminal of the operational amplifier 2 is less than the voltage signal received by the positive phase input terminal of the operational amplifier 2, a low level signal is output, and at this time, the voltage of the power supply is greater than or equal to the second equilibrium voltage; when the voltage signal received by the negative phase input terminal of the operational amplifier 2 is greater than or equal to the voltage signal received by the positive phase input terminal of the operational amplifier 2, a high level signal is output, and at this time, the voltage of the power supply is less than the second equilibrium voltage.

[0041] The voltage of the high-level signal is greater than the voltage of the low-level signal. The definition of the high level and the low level is not specifically limited here. For example, a signal that fluctuates within the range of ±5% to ±10% of the power supply voltage is generally called a high-level signal, and a signal that fluctuates within the range of ±5% to ±10% of the insulation ground voltage is called a low-level signal. Of course, other methods can also be used to define high-level signals and low-level signals, which will not be repeated here.

[0042] The embodiments of the present application do not limit the specific structure of the trigger. By way of example, the trigger may be a Schmitt trigger or an improved Schmitt trigger.

[0043] A method for controlling the resistance of a first resistor unit and a first bias resistor unit is provided below.

[0044] The first resistance unit is configured to have a first resistance value under the control of a high-level signal; and is configured to have a second resistance value under the control of a low-level signal; the first resistance value is greater than the second resistance value; the first bias resistance unit is configured to have a third resistance value under the control of a high-level signal; and is configured to have a fourth resistance value under the control of a low-level signal; the third resistance value is less than the fourth resistance value.

[0045] In the embodiment of the present application, the signal output by the trigger is fed back to the first resistance unit, and when the signal is a high-level signal, the first resistance unit has a first resistance value; when the signal is a low-level signal, the first resistance unit has a second resistance value, wherein the first resistance value is greater than the second resistance value. Similarly, the signal output by the trigger is fed back to the first bias resistance unit, and when the signal is a high-level signal, the first bias resistance unit has a third resistance value; when the signal is a low-level signal, the first bias resistance unit has a fourth resistance value, wherein the third resistance value is less than the fourth resistance value.

[0046] In the embodiment of the present application, the difference range between the first resistance value and the second resistance value is not limited, and the difference range between the third resistance value and the fourth resistance value is not limited.

[0047] Based on the resistance control method of the first resistor unit and the first bias resistor unit, in order to reduce the design difficulty, the resistance of the third resistor unit is fixed; the second bias resistor unit has the same structure as the first bias resistor unit. At this time, the second bias resistor unit has the same resistance as the first bias resistor unit. Similarly, the second bias resistor unit is configured to have a third resistance under the control of a high-level signal; and is configured to have a fourth resistance under the control of a low-level signal; the third resistance is less than the fourth resistance.

[0048] In order to further reduce the design difficulty, the resistance of the first bias resistor unit is M times the resistance of the third resistor unit, where M is greater than or equal to 6, and for example, M can be 6, 7, 8, 9, 10, 11, 12 or 13. At this time, it can be considered that the resistance of the first bias resistor unit is much greater than the resistance of the third resistor unit.

[0049] It should be noted that the ratio of the resistance value of the second resistor unit to the resistance value of the first resistor unit is related to the ratio of the emitter area of ​​the second PNP transistor to the emitter area of ​​the first PNP transistor; by setting these two ratios, when the voltage of the power supply is the first equilibrium voltage or the second equilibrium voltage, the voltage of the emitter of the first PNP transistor is V be1 and the voltage at the signal input terminal of the third resistor unit V be2_amp The difference is zero, that is, the emitter voltage V of the first PNP transistor be1 and the voltage V at the signal input terminal of the third resistor unit be2_amp same.

[0050] In some embodiments, the second resistance unit and the first resistance unit have the same structure, and the ratio of the resistance value of the second resistance unit to the resistance value of the first resistance unit is 1:1; the emitter area of ​​the second PNP type transistor is N times the emitter area of ​​the first PNP type transistor, and N is greater than 1, then the ratio of the emitter area of ​​the second PNP type transistor to the emitter area of ​​the first PNP type transistor is N:1.

[0051] In some embodiments, the resistance of the second resistance unit is N times the resistance of the first resistance unit, and N is greater than 1, then the ratio of the resistance of the second resistance unit to the resistance of the first resistance unit is N:1; the emitter area of ​​the second PNP type transistor is the same as the emitter area of ​​the first PNP type transistor, then the ratio of the emitter area of ​​the second PNP type transistor to the emitter area of ​​the first PNP type transistor is 1:1.

[0052] A specific circuit structure of a first branch and a second branch is provided below.

[0053] refer to Figure 1 and Figure 2 As shown, the first resistance unit 11 includes a first switch Msw1, and a first resistor R12 and a second resistor R11 connected in series, and the first resistor R12 and the first switch Msw1 are arranged in parallel; the first resistor R12 is arranged between the power supply and the second resistor R11; the first switch Msw1 is used to maintain a disconnected state under the control of a high-level signal; and maintain a conductive state under the control of a low-level signal.

[0054] refer to Figure 1 and Figure 2 As shown, the first bias resistor unit 12 includes a second switch Msw2, and a first bias resistor Rsw1 and a second bias resistor Rsw2 connected in series, and the second bias resistor Rsw2 and the second switch Msw2 are arranged in parallel; the second bias resistor Rsw2 is arranged between the first bias resistor Rsw1 and the ground terminal vssx; the second switch Msw2 is used to maintain an on state under the control of a high-level signal; and maintain an off state under the control of a low-level signal.

[0055] refer to Figure 1 and Figure 2 As shown, the second resistance unit 13 includes a third switch Msw3, and a fourth resistor R22 and a fifth resistor R21 connected in series, and the fourth resistor R22 and the third switch Msw3 are arranged in parallel; the fourth resistor R22 is arranged between the power supply and the fifth resistor R21; the third switch Msw3 is used to maintain a disconnected state under the control of a high-level signal; and maintain a conductive state under the control of a low-level signal.

[0056] refer to Figure 1 and Figure 2 As shown, the second bias resistor unit 14 includes a fourth switch Msw4, and a third bias resistor Rsw3 and a fourth bias resistor Rsw4 connected in series, and the fourth bias resistor Rsw4 and the fourth switch Msw4 are arranged in parallel; the fourth bias resistor Msw4 is arranged between the third bias resistor and the ground terminal; the fourth switch Msw4 is used to maintain an on state under the control of a high-level signal; and maintain an off state under the control of a low-level signal.

[0057] refer to Figure 1 and Figure 2 As shown, the third resistor unit 15 includes a third resistor R3.

[0058] It should be noted that, in the above-mentioned first branch and the second branch, the resistance setting of each resistor unit can refer to any of the above-mentioned methods, the first switch Msw1 and the third switch Msw3 are both P-type transistors, and the second switch Msw2 and the fourth switch Msw4 are both N-type transistors. Two setting methods are specifically described below. In the first method, the first bias resistor unit and the second bias resistor unit have the same structure. At this time, the resistance value of the first bias resistor Rsw1 is the same as the resistance value of the third bias resistor Rsw3, and the resistance value of the second bias resistor Rsw2 is the same as the resistance value of the fourth bias resistor Rsw4; the first resistor unit and the second resistor unit have the same structure. At this time, the resistance value of the first resistor R12 is the same as the resistance value of the fourth resistor R22, and the resistance value of the second resistor R11 is the same as the resistance value of the fifth resistor R21; the emitter area of ​​the second PNP transistor Q2 is N times the emitter area of ​​the first PNP transistor Q1, and N is greater than 1.

[0059] The second type, the first bias resistor unit and the second bias resistor unit have the same structure. At this time, the resistance value of the first bias resistor Rsw1 is the same as the resistance value of the third bias resistor Rsw3, and the resistance value of the second bias resistor Rsw2 is the same as the resistance value of the fourth bias resistor Rsw4; the resistance value of the second resistor unit is N times the resistance value of the first resistor unit, and N is greater than 1. At this time, the resistance value of the fifth resistor R21 is N times the resistance value of the second resistor R11, and the resistance value of the fourth resistor R22 is N times the resistance value of the first resistor R12; the emitter area of ​​the second PNP transistor Q2 is the same as the emitter area of ​​the first PNP transistor Q1.

[0060] The following takes the first structure as an example to illustrate the derivation process of the first equilibrium voltage and the second equilibrium voltage.

[0061] refer to Figure 1 and Figure 2 As shown, when the power supply voltage reaches a balanced state, the following formula needs to be satisfied:

[0062]

[0063]

[0064]

[0065]

[0066]

[0067]

[0068] in, V be1 is the voltage of the emitter of the first PNP transistor Q1, V be2_amp is the voltage at the signal input terminal of the third resistor R3, V be2 is the voltage of the emitter of the second PNP transistor Q2, V T is the thermal voltage, the voltage at the signal input end of the third resistor R3, I c1 is the current flowing into the emitter of the first PNP transistor Q1, I c2 is the current flowing into the emitter of the second PNP transistor Q2, I 1 is the current passing through the first resistor R12, I 2 is the current passing through the fifth resistor R21, I sis the saturation current of the first PNP transistor Q1, R sw is the resistance value of the second bias resistor unit, R 3 is the resistance value of the third resistor R3, and N is the ratio of the emitter area of ​​the second PNP transistor Q2 to the emitter area of ​​the first PNP transistor Q1. V T The calculation formula of can be obtained according to relevant technologies and will not be described in detail here.

[0069] According to formula (5), formula (1) and formula (2), we can get:

[0070] Substituting formula (4) into formula (8), we can obtain:

[0071] According to formula (3) and formula (9), we can get:

[0072] Subtracting the two sides of formula (6) and formula (7) respectively, and then performing corresponding calculations, we can obtain:

[0073] The voltage of the power supply in a balanced state V tp for:

[0074]

[0075]

[0076]

[0077]

[0078]

[0079] when R sw >> R 3, formula (12) can be simplified to:

[0080]

[0081] Among them, the right side is the standard bandgap unit voltage V bg The calculation formula is

[0082] From formula (13), we can get that when the positive temperature coefficient term Can compensate V be2 When the negative temperature coefficient is , formula (13) can achieve temperature balance and has small fluctuations under different process angles. In addition, adjusting The size of the power-on reset circuit can be adjusted V tp The size of the balance voltage can be adjusted.

[0083] That is to say, each resistor unit in the first branch and the second branch is not only used to adjust the balance point of the power supply voltage, but also can be used as an adjustment element for the temperature compensation effect of the transistor to ensure that the circuit can still work accurately at different temperatures. The power-on reset circuit provided in the embodiment of the present application avoids the drift of the corresponding vddx flip voltage point caused by semiconductor process errors through precise resistance ratio design, thereby achieving process invariance; through the combination of PNP BJT and the resistor network, the drift of the corresponding vddx flip voltage point caused by different temperatures is avoided, thereby improving the stability of the system.

[0084] In the embodiment of the present application, when the voltage of the power supply is in the rising stage and the voltage of the power supply is less than or equal to the first equilibrium voltage (that is, the voltage of the power supply is in the equilibrium state or before reaching the equilibrium state), the trigger outputs a high level signal (POR=1). Under the control of the high level signal, the first switch Msw1 and the third switch Msw3 are disconnected, and the second switch Msw2 and the fourth switch Msw4 are turned on. R sw = R sw1= R sw3 , R 1= R 11 +R 12 , R 2= R 21 +R 22 , at this time, according to formula (13), the first equilibrium voltage can be calculated. When the voltage of the power supply is in the falling stage, and the voltage of the power supply is greater than or equal to the second equilibrium voltage (that is, the voltage of the power supply is in a balanced state or before reaching a balanced state), the trigger outputs a low-level signal (POR=0). Under the control of the low-level signal, the first switch Msw1 and the third switch Msw3 are turned on, and the second switch Msw2 and the fourth switch Msw4 are turned off.

[0085] For example, when N=8,V T ≈0.026v, R sw1 = R sw3 ≈795kohm, R sw2 = R sw4 ≈273kohm, R 11 ≈299kohm, R 12 ≈45kohm, R 21 ≈299kohm, R 22 ≈45kohm, R When 3≈27kohm, the first equilibrium voltage vtp_rise=1.6v and the second equilibrium voltage vtp_fall=1.45v can be calculated. Here, the symbol "≈" indicates an approximate relationship. In analog circuit and chip design, the resistance value of the resistor is acceptable as long as it is within a certain range of the design value.

[0086] It should be noted that R sw refers to the resistance value of the second bias resistor unit, the resistance value of the first bias resistor unit is the same as the resistance value of the second bias resistor unit, R sw1 refers to the resistance of the first bias resistor Rsw1, R sw3 refers to the resistance of the third bias resistor Rsw3, R sw2 refers to the resistance of the second bias resistor Rsw2, R sw4 refers to the resistance of the fourth bias resistor Rsw4, R 1 refers to the resistance value of the first resistance unit, R 11 refers to the resistance value of the second resistor R11, R 12 refers to the resistance value of the first resistor R12, R 2 refers to the resistance value of the second resistance unit, R 21 refers to the resistance value of the fifth resistor R21, R 22 Refers to the resistance of the fourth resistor R22.

[0087] It should be noted that the derivation process of the second structure is similar to the above, the difference is: Formula (5) is modified to , formula (7) is modified to , the rest of formulas (1) to (4) and (6) remain unchanged. Based on these seven formulas, we can also get formulas (10) and (11). The specific derivation process will not be repeated here.

[0088] To enhance scalability, refer to Figure 2 As shown, the power-on reset circuit also includes an inverter 4; the trigger 3 includes a first P-type transistor M1, a second P-type transistor M2, a third P-type transistor M3, a first N-type transistor M4, a second N-type transistor M5, a third N-type transistor M6, a fourth N-type transistor Mt and a fifth N-type transistor M7.

[0089] refer to Figure 2 As shown, the source of the first P-type transistor M1 is electrically connected to the power supply, the drain of the first P-type transistor M1, the source of the second P-type transistor M2, and the source of the third P-type transistor M3 are electrically connected, the drain of the second P-type transistor M2, the drain of the first N-type transistor M4, the gate of the third P-type transistor M3, and the gate of the third N-type transistor M6 are electrically connected, the drain of the third N-type transistor M6 is electrically connected to the ground terminal, the source of the first N-type transistor M4, the drain of the second N-type transistor M5, and the drain of the third N-type transistor M6 are electrically connected, The source of the third N-type transistor M6 is electrically connected to the power supply, the source of the second N-type transistor M5, the drain and gate of the fourth N-type transistor Mt, and the drain of the fifth N-type transistor M7 are electrically connected, the sources of the fourth N-type transistor Mt and the fifth N-type transistor M7 are electrically connected to the ground terminal, the gate of the first P-type transistor M1, the gate of the second P-type transistor M2, the gate of the first N-type transistor M4, and the gate of the second N-type transistor M5 are all electrically connected to the output terminal of the operational amplifier 2, and the gate of the fifth N-type transistor M7 is electrically connected to the output terminal of the inverter 4.

[0090] The drain of the second P-type transistor M2 is used as the output terminal of the trigger, the input terminal of the inverter 4 is electrically connected to the drain of the second P-type transistor M2 , and the inverter 4 is used to invert the signal output by the trigger 3 .

[0091] Figure 3 Schematic diagram of the waveform of the reset signal por and the inverted signal porb of the reset signal output by a conventional Schmitt trigger. Figure 4 The waveform diagram of the reset signal por and the inverted signal porb of the reset signal output by the Schmitt trigger provided by the present application is shown in FIG. 1 . The difference between the conventional Schmitt trigger and the Schmitt trigger provided by the embodiment of the present application is that the fourth N-type transistor Mt and the fifth N-type transistor M7 are not provided. Figure 3As shown, during the power-on process, the reset signal por and the inverted signal porb of the reset signal are prone to spurious signals (glitch) defined by the dashed box A, which may cause the power-on reset function to fail. In order to solve this problem, the present application improves the conventional Schmitt trigger by introducing a fourth N-type transistor Mt and a fifth N-type transistor M7. The fourth N-type transistor Mt is used to raise the flip level of the Schmitt trigger. Figure 4 As shown, the reset signal por can be prevented from being flipped prematurely when the power supply voltage vddx rises / falls and the voltage value is small, thereby preventing the reset signal por and the inverted signal porb of the reset signal from generating spurs.

[0092] based on Figure 2 The power-on reset circuit shown in the figure has branch 1 V be1 and branch 2 V be2_amp It can be used as a decision point for pulling the reset signal por low and the inverted signal porb of the reset signal high.

[0093] Specifically, during the rise or fall of vddx, when V be1 > V be2_amp , the voltage of the reset signal por is high level POR=1, and the voltage of the inverted signal porb of the reset signal is low level, PORB=0, indicating that the system is in reset state; when V be1 < V be2_amp , the voltage of the reset signal por is low level POR=0, and the voltage of the inverted signal porb of the reset signal is high level, PORB=1, indicating that the system can exit the reset state and enter the normal working mode.

[0094] refer to Figure 2 As shown in the figure, when the power supply voltage vddx rises / drops to a lower voltage, the operating state of the operational amplifier and the inverter is not fully established, which may lead to a high impedance state. Therefore, it can be set as follows Figure 2The first capacitor C1 and the second capacitor C2 are shown, wherein one end of the first capacitor C1 is connected between the operational amplifier 2 and the trigger 3, and the other end is grounded, and one end of the second capacitor C2 is connected between the inverter 4 and the trigger 3, and the other end is connected to the power supply. By setting the first capacitor C1 and the second capacitor C2, the voltage value of the corresponding node can be set during the rise / fall process of the power supply voltage vddx, so as to avoid the corresponding circuit node from being in a high impedance state during the rise / fall process of the power supply voltage vddx, thereby preventing the logic level error of the reset signal por / the inverted signal porb of the reset signal, and further preventing the function from failing.

[0095] The embodiment of the present application also provides an electronic device, comprising: any of the power-on reset circuits described above. The electronic device can significantly avoid the problem of false triggering or non-triggering of the reset signal due to process fluctuations and temperature changes, and has high reliability.

[0096] The type and application scenario of the electronic device are not limited, and the electronic device can be a component and product used in fields such as smart housing, transportation, smart home, consumer electronics, monitoring, industrial automation, cabin detection and health care. For example, the electronic device can be applied to consumer electronics fields such as 4G or 5G mobile phones, tablets, personal computers, etc.; or, it can also be applied to base stations, drones and other fields; or, it can also be applied to intelligent transportation equipment such as automobiles, bicycles, motorcycles, ships, subways or trains; or, it can also be applied to smart home equipment such as sweeping robots, televisions, air conditioners or smart lights; or, it can also be applied to automotive cabin detection, indoor personnel monitoring, intelligent medical equipment and other fields.

[0097] The division of various components above is only for clear description. When implemented, they can be combined into one component or some components can be split and decomposed into multiple components. As long as they include the same logical relationship, they are all within the protection scope of this application.

[0098] Those skilled in the art will appreciate that the above-mentioned embodiments are specific examples for implementing the present application, and in practical applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the present application. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application, and therefore the scope of protection of the present application shall be subject to the scope defined in the claims.

Claims

1. A power-on reset circuit, characterized in that: include: Bandgap voltage reference module and operational amplifier; The bandgap voltage reference module includes a first branch and a second branch; the first branch includes a first PNP-type triode, a first resistor unit and a first bias resistor unit, the first bias resistor unit is arranged in parallel between the emitter and the collector of the first PNP-type triode, the base and the collector of the first PNP-type triode are electrically connected to the ground terminal, and the first resistor unit is arranged between a power supply and the emitter of the first PNP-type triode; The second branch includes a second PNP type triode, a second resistance unit, a second bias resistance unit and a third resistance unit, the second resistance unit and the third resistance unit are arranged in series between the power supply and the emitter of the second PNP type triode, the signal input end of the third resistance unit is electrically connected to the second resistance unit, the signal output end of the third resistance unit is electrically connected to the emitter of the second PNP type triode, the base and collector of the second PNP type triode are electrically connected to the ground end, and the second bias resistance unit is arranged in parallel between the signal input end of the third resistance unit and the collector of the second PNP type triode; The negative phase input terminal of the operational amplifier is electrically connected to the emitter of the first PNP type transistor, and the positive phase input terminal of the operational amplifier is electrically connected to the signal input terminal of the third resistance unit; The bandgap voltage reference module is used to: control the resistance of each resistor unit in the first branch and the resistance of each resistor unit in the second branch, so that the bandgap voltage reference module has a first balance voltage when the voltage of the power supply is in an ascending stage, and has a second balance voltage when the voltage of the power supply is in a descending stage, and the first balance voltage is greater than the second balance voltage, wherein the first balance voltage is the power supply voltage corresponding to when the voltage of the power supply is in an ascending stage and the difference between the voltage of the emitter of the first PNP type transistor and the voltage of the signal input end of the third resistor unit is zero; the second balance voltage is the power supply voltage corresponding to when the voltage of the power supply is in a descending stage and the difference between the voltage of the emitter of the first PNP type transistor and the voltage of the signal input end of the third resistor unit is zero; The operational amplifier is used to amplify the difference between the voltage of the emitter of the first PNP transistor and the voltage of the signal input end of the third resistor unit.

2. The power-on reset circuit according to claim 1, characterized in that: The power-on reset circuit further includes: a trigger; the output end of the operational amplifier is electrically connected to the input end of the trigger; The trigger is used to: When the voltage of the power supply is in a rising stage, when the voltage signal received by the negative phase input terminal of the operational amplifier is greater than or equal to the voltage signal received by the positive phase input terminal of the operational amplifier, a high level signal is output; when the voltage signal received by the negative phase input terminal of the operational amplifier is less than the voltage signal received by the positive phase input terminal of the operational amplifier, a low level signal is output; When the voltage of the power supply is in a decreasing stage, when the voltage signal received at the negative input terminal of the operational amplifier is less than the voltage signal received at the positive input terminal of the operational amplifier, the low level signal is output; when the voltage signal received at the negative input terminal of the operational amplifier is greater than or equal to the voltage signal received at the positive input terminal of the operational amplifier, the high level signal is output.

3. The power-on reset circuit according to claim 2, characterized in that: The first bias resistor unit and the second bias resistor unit have the same structure; The first resistance unit is configured to have a first resistance value under the control of the high level signal; Under the control of the low level signal, it is configured to have a second resistance value; the first resistance value is greater than the second resistance value; The first bias resistor unit is configured to have a third resistance value under the control of the high level signal; and is configured to have a fourth resistance value under the control of the low level signal; and the third resistance value is smaller than the fourth resistance value.

4. The power-on reset circuit according to claim 3, characterized in that: The resistance value of the third resistance unit is fixed.

5. The power-on reset circuit according to claim 4, characterized in that: The resistance value of the first bias resistor unit is M times the resistance value of the third resistor unit, wherein M is greater than or equal to 6.

6. The power-on reset circuit according to claim 5, characterized in that: The second resistance unit has the same structure as the first resistance unit; the emitter area of ​​the second PNP type transistor is N times the emitter area of ​​the first PNP type transistor, and N is greater than 1.

7. The power-on reset circuit according to claim 5, characterized in that: The resistance value of the second resistance unit is N times the resistance value of the first resistance unit, and N is greater than 1; the emitter area of ​​the second PNP transistor is the same as the emitter area of ​​the first PNP transistor.

8. The power-on reset circuit according to any one of claims 1 to 7, characterized in that: The first resistor unit includes a first switch, and a first resistor and a second resistor connected in series, the first resistor and the first switch are arranged in parallel; the first resistor is arranged between the power supply and the second resistor; the first switch is used to maintain an off state under the control of the high level signal; and maintain an on state under the control of the low level signal; The first bias resistor unit includes a second switch, and a first bias resistor and a second bias resistor connected in series, the second bias resistor and the second switch are arranged in parallel; the second bias resistor is arranged between the first bias resistor and the ground terminal; the second switch is used to maintain a conducting state under the control of the high level signal; and maintain a disconnected state under the control of the low level signal; The second resistor unit includes a third switch, and a fourth resistor and a fifth resistor connected in series, wherein the fourth resistor and the third switch are arranged in parallel; the fourth resistor is arranged between the power supply and the fifth resistor; the third switch is used to maintain an off state under the control of the high level signal; and maintain an on state under the control of the low level signal; The second bias resistor unit includes a fourth switch, and a third bias resistor and a fourth bias resistor connected in series, wherein the fourth bias resistor and the fourth switch are arranged in parallel; the fourth bias resistor is arranged between the third bias resistor and the ground terminal; the fourth switch is used to maintain a conducting state under the control of the high level signal; and maintain a disconnected state under the control of the low level signal; The third resistor unit includes a third resistor.

9. The power-on reset circuit according to any one of claims 1 to 7, characterized in that: The power-on reset circuit also includes an inverter; The trigger includes a first P-type transistor, a second P-type transistor, a third P-type transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor and a fifth N-type transistor; The source of the first P-type transistor is electrically connected to the power supply, the drain of the first P-type transistor, the source of the second P-type transistor, and the source of the third P-type transistor are electrically connected, the drain of the second P-type transistor, the drain of the first N-type transistor, the gate of the third P-type transistor, and the gate of the third N-type transistor are electrically connected, the drain of the third N-type transistor is electrically connected to the ground terminal, the source of the first N-type transistor, the drain of the second N-type transistor, and the drain of the third N-type transistor are electrically connected, the source of the third N-type transistor is electrically connected to the power supply, the source of the second N-type transistor, the drain and the gate of the fourth N-type transistor, and the drain of the fifth N-type transistor are electrically connected, the sources of the fourth N-type transistor and the fifth N-type transistor are electrically connected to the ground terminal, the gates of the first P-type transistor, the second P-type transistor, the first N-type transistor, and the second N-type transistor are all electrically connected to the output terminal of the operational amplifier, and the gate of the fifth N-type transistor is electrically connected to the output terminal of the inverter; The drain of the second P-type transistor is used as the output terminal of the trigger, the input terminal of the inverter is electrically connected to the drain of the second P-type transistor, and the inverter is used to invert the signal output by the trigger.

10. An electronic device, characterized in that: include: A power-on reset circuit as claimed in any one of claims 1 to 9.

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