IGBT device and preparation method thereof

Abstract

According to the IGBT device and the preparation method thereof provided by the invention, the packaging layer is filled in the packaging window among the plurality of metal layers, and the emitter metal layer and the gate metal layer of the cellular region structure are exposed, so that the emitter layer and the trench gate in the cellular region structure can be electrically led out, the sealing performance of the device is improved, and the reliability of the device is improved. Meanwhile, a supporting effect can be provided for the device structure, the problems of hidden cracks, defects, water vapor, acid sticking, yellowing, fingerprints and the like of the front face of the device can be prevented in the substrate thinning technological process of the device, the substrate thinning technological process can be simplified, and the derived quality problems are reduced while the cost is saved. In the CP test needle inserting process, the packaging layer can prevent the CP test needle from being deviated and penetrating through the metal layer in the cellular area to cause device scrapping, and the thickness of the substrate can be reduced by using the supporting effect of the packaging layer on the device structure, so that the overall size of the device is reduced, and the market competitiveness is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit design and manufacturing, and in particular to an IGBT device and a preparation method thereof. Background Art

[0002] IGBT (Insulated Gate Bipolar Transistor) is a composite fully controlled voltage-driven power semiconductor device composed of BJT (Bipolar Junction Transistor) and MOSFET (Insulated Gate Field Effect Transistor). Therefore, it has the advantages of MOSFET's high input impedance, low drive circuit power, simple drive, fast switching speed and low switching loss, and also has the advantages of BJT's high current density, strong current handling capability and low on-saturation voltage.

[0003] At present, IGBT devices use two layers of passivation layers to cover the terminal area around the IGBT device, and the metal layer of the IGBT cell area is exposed. In the wafer back thin film process, due to the lack of protection on the front side, it is easy to have problems such as hidden cracks, defects, water vapor, sticky acid, yellowing or color difference. When the IGBT device is tested by wafer probe (CP, Chip Probing), the exposed metal layer of the thinned wafer is easily pierced, or the passivation layer is damaged due to the deviation of the test needle, resulting in low yield and high rework frequency. In addition, the thinned substrate wafer lacks support on the front side during the production process, which means that the substrate wafer cannot be too thin, reducing market competitiveness. Summary of the invention

[0004] In view of the shortcomings of the prior art described above, the object of the present invention is to provide an IGBT device and a method for preparing the same, so as to solve the problems in the prior art where the passivation layer covers the terminal area of ​​the field limiting ring IGBT device, and the metal layer in the IGBT cell area is exposed, resulting in problems such as hidden cracks, defects, water vapor, sticky acid, yellowing or color difference in the thin film process, and the metal layer is easily pierced during CP testing.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides an IGBT device, which comprises, from bottom to top, a collector metal layer, a collector layer, a substrate, and a cell region structure and a terminal region structure located on the substrate;

[0006] It also includes: multiple metal layers, multiple packaging windows and packaging layers; wherein the multiple metal layers include an emitter metal layer and a gate metal layer formed above the cell region structure to electrically lead out the cell region structure, and a terminal region metal layer formed above the terminal region structure to electrically lead out the terminal region structure; the multiple packaging windows extend downward from the upper surface of the metal layer to a preset depth in the metal layer, respectively; the packaging layer is filled in the packaging window and covers the cell region structure and the terminal region structure, and the packaging layer is flush with the top of the emitter metal layer and the gate metal layer.

[0007] Optionally, the number of the packaging windows located above the cellular region structure is 1 to 8, and the shape is a square with a side length ranging from 10 μm to 100 μm.

[0008] Optionally, the thickness of the thicker region of the metal layer in the height direction is 4 μm to 6 μm, and the thickness of the thinner region of the metal layer in the height direction is 0.2 μm to 1 μm.

[0009] Optionally, the material of the encapsulation layer includes an organic polymer material, and the organic polymer material includes one or a combination of polyimide and polysiloxane.

[0010] Optionally, the IGBT device further includes a passivation layer formed between the terminal region metal layer and the corresponding packaging layer, and the thickness of the passivation layer is less than 18 μm.

[0011] Optionally, the IGBT device further includes a buffer layer located between the collector layer and the substrate;

[0012] The cell region structure and the terminal region structure include, from bottom to top, a carrier storage layer, a well region, an emitter layer and an interlayer dielectric layer; and further include:

[0013] A field limiting ring, wherein the field limiting ring is formed between the substrate and the carrier storage layer in the terminal region structure;

[0014] A trench gate located in the cell region structure, the trench gate extending downward from the surface of the emitter layer to a preset depth in the substrate;

[0015] A plurality of electrical lead-out structures penetrating the interlayer dielectric layer, wherein the electrical lead-out structures electrically lead out the emitter layer, the trench gate and the terminal region structure;

[0016] At least one LOCOS oxidation isolation layer is located between the cell region structure and the terminal region structure, and between each structural unit in the terminal region structure.

[0017] The present invention also provides a method for preparing an IGBT device, the method comprising:

[0018] providing a substrate;

[0019] forming a cell region structure and a terminal region structure on the substrate;

[0020] A plurality of metal layers are formed on the obtained structure, wherein the metal layers include an emitter metal layer, a gate metal layer and a terminal region metal layer; the emitter metal layer and the gate metal layer are formed on the cell region structure to electrically lead out the cell region structure; the terminal region metal layer is formed on the terminal region structure to electrically lead out the terminal region structure;

[0021] Etching the metal layer to form a packaging window with a preset depth;

[0022] forming a packaging layer on the obtained structure, wherein the packaging layer at least fills the packaging window;

[0023] The encapsulation layer is thinned and planarized to expose the tops of the emitter metal layer and the gate metal layer.

[0024] Optionally, the method for forming the encapsulation window comprises the following steps:

[0025] forming a photoresist layer on the surface of the metal layer and patterning the photoresist layer;

[0026] Etching the metal layer to a preset depth based on the patterned photoresist layer to form the packaging window;

[0027] The patterned photoresist layer is removed.

[0028] Optionally, after forming the encapsulation layer, the following steps are further included:

[0029] performing backside thinning on the substrate;

[0030] Performing ion implantation from the lower surface of the substrate inward to form a buffer layer and a collector layer;

[0031] A back-gold process is performed on the lower surface of the collector layer to form a collector metal layer.

[0032] Optionally, the method for forming the cellular region structure and the terminal region structure comprises the following steps:

[0033] forming at least one LOCOS oxidation isolation layer on the upper surface of the substrate, wherein the LOCOS oxidation isolation layer is formed between the cell region structure and the terminal region structure, and between each structural unit in the terminal region structure;

[0034] Performing ion implantation at a preset depth on the upper surface of the substrate in the terminal region structure to form a field limiting ring;

[0035] Performing ion implantation to a preset depth on the upper surface of the substrate and the field limiting ring around the LOCOS oxidation isolation layer to form a carrier storage layer;

[0036] A trench gate is formed by extending downward from the upper surface of the carrier storage layer to a preset depth in the substrate;

[0037] Performing ion implantation at a preset depth on the upper surface of the carrier storage layer to form a well region;

[0038] Performing ion implantation at a preset depth on the upper surface of the well region to form an emitter layer;

[0039] forming an interlayer dielectric layer on the upper surface of the obtained structure;

[0040] An electrical lead-out structure penetrating the interlayer dielectric layer is formed, wherein the electrical lead-out structure electrically leads out the emitter layer, the trench gate and the terminal region structure.

[0041] Optionally, the thickness of the thicker region of the metal layer in the height direction is 4 μm to 6 μm, and the thickness of the thinner region of the metal layer in the height direction is 0.2 μm to 1 μm.

[0042] Optionally, before forming the encapsulation layer, the method further includes forming a passivation layer on the terminal region metal layer, wherein the thickness of the passivation layer is less than 18 μm.

[0043] Optionally, before the packaging layer is thinned and planarized, its top is higher than the top of the metal layer by 0 μm to 200 μm.

[0044] As described above, the IGBT device and its preparation method of the present invention have the following beneficial effects: by filling the packaging layer in the packaging window between the multiple metal layers and exposing the emitter metal layer and the gate metal layer of the cell region structure, not only can the electrical lead-out of the emitter layer and the trench gate in the cell region structure of the IGBT device be realized, but the packaging layer filled in the packaging window can also increase the sealing of the IGBT device, shielding the external impurities, ion charge, water vapor and other damages to the internal structure of the device, and the packaging layer can provide support for the IGBT device structure, and in the substrate thinning process of the IGBT device, it can prevent the front side of the IGBT device from being cracked, defective, water vapor, sticky acid, yellowing and fingerprints, and other problems, while simplifying the process of substrate thinning, saving costs and reducing the derived quality problems. In the CP test needle piercing process, the packaging layer can prevent the CP test needle from piercing the cell region metal layer to cause the IGBT device to be scrapped, and the supporting effect of the packaging layer on the IGBT device structure can also be used to reduce the substrate thickness to be thinner, thereby reducing the overall size of the IGBT device and improving market competitiveness. In addition, compared with the prior art which uses two passivation layers to cover the terminal region structure surrounding the IGBT device, two passivation layer masks are saved, thereby further saving costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a schematic diagram showing the cross-sectional structure of the IGBT device of the present invention.

[0046] Figure 2 Shown is a schematic flow chart of a method for preparing an IGBT device of the present invention.

[0047] Figure 3 to Figure 9 It shows a schematic diagram of the structure presented in each step of preparing an IGBT device according to the present invention.

[0048] Component number description

[0049] 11 Collector metal layer

[0050] 12 Collector layer

[0051] 13 Buffer layer

[0052] 14 Substrate

[0053] 15 Carrier storage layer

[0054] 16 Well region

[0055] 17 Emitter layer

[0056] 18 Interlayer dielectric layer

[0057] 19 Metal Layer

[0058] 191 emitter metal layer

[0059] 192 Gate metal layer

[0060] 193 Terminal area metal layer

[0061] 20 Encapsulation layer

[0062] 21 Encapsulation Window

[0063] 22 Trench Gate

[0064] 221 Gate Oxide

[0065] 222 gate conductive layer

[0066] 23 LOCOS Oxidation Isolation Layer

[0067] 24 Electrical lead structure

[0068] 241 Interconnect Metal Layer

[0069] 242 Adhesion layer

[0070] 25 Field Limiting Ring

[0071] 26 Conductive contact holes

[0072] 27 Groove

[0073] Steps S1 to S6 DETAILED DESCRIPTION

[0074] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0075] See also Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0076] This embodiment provides an IGBT device, such as Figure 1 As shown, the IGBT device includes, from bottom to top, a collector metal layer 11, a collector layer 12, a substrate 14, and a cell region structure and a terminal region structure located on the substrate 14;

[0077] It also includes: a plurality of metal layers 19, a plurality of packaging windows 21 and a packaging layer 20; wherein the plurality of metal layers 19 include an emitter metal layer 191 and a gate metal layer 192 formed above the cell region structure to electrically lead out the cell region structure, and a terminal region metal layer 193 formed above the terminal region structure to electrically lead out the terminal region structure; the plurality of packaging windows 21 extend downward from the upper surface of the metal layer 19 to a preset depth in the metal layer 19 respectively; the packaging layer 20 is filled in the packaging windows 21, and covers the cell region structure and the terminal region structure, and the packaging layer 20 is flush with the top of the emitter metal layer 191 and the gate metal layer 192. It should be noted here that the upper surface of the metal layer 19 is away from the substrate 14.

[0078] The IGBT device of this embodiment can not only realize the electrical lead-out of the emitter layer and the trench gate in the cell area structure of the IGBT device by filling the packaging layer in the packaging window between multiple metal layers and exposing the emitter metal layer and the gate metal layer of the cell area structure, but the packaging layer filled in the packaging window can also increase the sealing of the IGBT device, shield the external impurities, ion charges, water vapor and other damages to the internal structure of the device, and the packaging layer can provide support for the IGBT device structure. In the substrate thinning process of the IGBT device, problems such as hidden cracks, defects, water vapor, sticky acid, yellowing and fingerprints on the front of the IGBT device can be prevented, and in the CP test needle piercing process, the packaging layer can reduce or even avoid the CP test needle from piercing off or penetrating the cell area metal layer, causing the IGBT device to be scrapped. In addition, the supporting effect of the packaging layer on the IGBT device structure can be used to reduce the substrate thickness to be thinner, thereby reducing the overall size of the IGBT device and improving market competitiveness.

[0079] As an example, Figure 1 As shown, the IGBT device further includes a buffer layer 13 located between the collector layer 12 and the substrate 14;

[0080] The cell region structure and the terminal region structure include, from bottom to top, a carrier storage layer 15, a well region 16, an emitter layer 17 and an interlayer dielectric layer 18; and further include:

[0081] A field limiting ring 25, wherein the field limiting ring 25 is formed between the substrate 14 and the carrier storage layer 15 in the terminal region structure;

[0082] A trench gate 22 located in the cell region structure, the trench gate 22 extending downward from the surface of the emitter layer 17 to a preset depth in the substrate 14; it should be noted that the surface of the emitter layer 17 here refers to a side away from the substrate 14;

[0083] A plurality of electrical lead-out structures 24 penetrating the interlayer dielectric layer 18, wherein the electrical lead-out structures 24 electrically lead out the emitter layer 17, the trench gate 22 and the terminal region structure;

[0084] At least one LOCOS (Local Oxidation Of Silicon) oxidation isolation layer 23, wherein the LOCOS oxidation isolation layer 23 is located between the cell region structure and the terminal region structure, and between each structural unit in the terminal region structure.

[0085] In this embodiment, the IGBT device is implemented based on an N-type doped semiconductor substrate, that is, the collector layer 12 is P-type doped, the substrate 14 is N-type doped, the carrier storage layer 15 is N-type doped, the well region 16 is P-type doped, the emitter region 17 is N-type doped, and the field limiting ring 25 is P-type doped. The P-type doped ions can be trivalent ions such as boron, aluminum, gallium and indium, and the N-type doped ions can be pentavalent ions such as nitrogen, phosphorus, arsenic and antimony. The semiconductor substrate material includes but is not limited to silicon, germanium, gallium arsenide, indium phosphide and silicon carbide. The doping ions and semiconductor material types can be selected according to actual needs and are not excessively restricted here.

[0086] In order to perform CP testing on the IGBT device later, it is necessary to electrically lead out the emitter layer 17 and the trench gate 22. The emitter metal layer 191 and the gate metal layer 192 are formed above the cell region structure to electrically lead out the cell region structure, wherein the emitter metal layer 191 is electrically connected to the emitter layer 17, and the gate metal layer 192 is electrically connected to the trench gate 22. The encapsulation layer 20 is flush with the top of the emitter metal layer 191 and the gate metal layer 192. The exposed emitter metal layer 191 and the gate metal layer 192 are convenient for subsequent CP testing. During the CP test needle piercing process, the encapsulation layer 20 can reduce or even avoid the CP test needle from piercing off or penetrating the emitter metal layer 191 and the gate metal layer 192, and the encapsulation layer 20 can be polished a second time later to reduce or even avoid the impact on the appearance of the IGBT device.

[0087] As an example, the number of the packaging windows 21 located above the cellular area structure is 1 to 8, and the shape is a square with a side length ranging from 10μm to 100μm. The shape and number of the packaging windows 21 located above the cellular area structure can be set according to the packaging wire bonding process requirements, and no excessive restrictions are made here.

[0088] The metal layer 19 forms a thinner area and a thicker area in the height direction, the thinner area is used to electrically connect the cell area structure and the terminal area structure, and the thicker area can facilitate subsequent CP testing. The thickness of the thicker area and the thinner area can be set according to actual needs. As an example, the thicker area of ​​the metal layer 19 in the height direction is 4μm~6μm, and the thinner area of ​​the metal layer in the height direction is 0.2μm~1μm.

[0089] As an example, the metal layer 19 can be an aluminum-copper alloy layer, the collector metal layer 11 can be at least one of a copper layer, a gold layer, a nickel layer and other material layers, and there can also be an adhesion layer between the collector metal layer 11 and the collector layer 12, for example, a titanium layer and / or a titanium nitride layer, to enhance the adhesion between the collector metal layer 11 and the collector layer 12.

[0090] As an example, the material of the encapsulation layer 20 includes an organic polymer material, and the organic polymer material includes one or a combination of polyimide and polysiloxane. The material of the encapsulation layer 20 is not overly limited herein.

[0091] As an example, the IGBT device also includes a passivation layer (not shown) formed between the terminal area metal layer 193 and the corresponding packaging layer 20. Preferably, the thickness of the passivation layer can be set to be less than 18 μm. The material of the passivation layer includes one or a combination of polyimide, polysiloxane and silicone rubber. The passivation layer is used to pre-fill the packaging window 21 located above the terminal area metal layer 193 before forming the corresponding packaging layer 20, and is used to shield external impurities, ionic charges, etc. from contaminating the terminal area structure. If the material of the packaging layer 20 has a similar function, the passivation layer can be cancelled. There is no excessive restriction on whether the IGBT device has a passivation layer and the material of the passivation layer.

[0092] The electrical lead-out structure 24 electrically leads out the emitter layer 17, the trench gate 22 and the terminal region structure. For example, Figure 1 As shown, the electrical lead-out structure 24 includes:

[0093] A plurality of conductive contact holes 26 penetrating the interlayer dielectric layer 18 and extending to a preset depth in the emitter layer 17, wherein the conductive contact holes 26 are connected to the emitter layer 17, the trench gate 22 and the terminal region structure;

[0094] An adhesion layer 242 and an interconnection metal layer 241 are sequentially formed on the surface of the conductive contact hole 26 and fill the conductive contact hole 26 .

[0095] As an example, the adhesion layer 242 can be made of a titanium layer and / or a titanium nitride layer, and the interconnection metal layer 241 can be made of a tungsten layer, or the adhesion layer 242 can be made of a tantalum and / or a tantalum nitride layer, and the interconnection metal layer 241 can be made of a copper layer and / or a copper alloy layer, so as to enhance the electrical lead-out effect of the electrical lead-out structure 24, thereby reducing the switching loss of the IGBT device and improving the device performance.

[0096] This embodiment also provides a method for preparing an IGBT device, which is used to prepare the above-mentioned IGBT device, but is not limited thereto. Other suitable preparation methods are also possible. The above content can be quoted in its entirety here, and will not be described in detail below for the purpose of brevity. Figure 2 As shown, the preparation method comprises:

[0097] S1, providing a substrate;

[0098] S2, forming a cell region structure and a terminal region structure on the substrate;

[0099] S3, forming a plurality of metal layers on the obtained structure, wherein the metal layers include an emitter metal layer, a gate metal layer and a terminal region metal layer; the emitter metal layer and the gate metal layer are formed on the cell region structure to electrically lead out the cell region structure; the terminal region metal layer is formed on the terminal region structure to electrically lead out the terminal region structure;

[0100] S4, etching the metal layer to form a packaging window with a preset depth;

[0101] S5, forming a packaging layer on the obtained structure, wherein the packaging layer at least fills the packaging window;

[0102] S6, thinning and flattening the encapsulation layer to expose the top of the emitter metal layer and the gate metal layer.

[0103] The preparation method of the IGBT device of this embodiment, by filling the packaging layer in the packaging window between multiple metal layers and exposing the emitter metal layer and gate metal layer of the cell region structure, can not only realize the electrical extraction of the emitter layer and the trench gate in the cell region structure of the IGBT device, but also the packaging layer filled in the packaging window can increase the sealing of the IGBT device, shielding the external impurities, ion charge, water vapor and other damages to the internal structure of the device, and the packaging layer can provide support for the IGBT device structure, and can prevent the front side of the IGBT device from hidden cracks, defects, water vapor, sticky acid, yellowing and fingerprints in the substrate thinning process of the IGBT device, and simplify the substrate thinning process, saving costs while reducing the derived quality problems. In the CP test needle piercing process, the packaging layer can prevent the CP test needle from piercing the cell region metal layer and causing the IGBT device to be scrapped, and the supporting effect of the packaging layer on the IGBT device structure can be used to reduce the substrate thickness to be thinner, thereby reducing the overall size of the IGBT device and improving market competitiveness. In addition, compared with the prior art which uses two passivation layers to cover the terminal region structure surrounding the IGBT device, two passivation layer masks are saved, thereby further saving costs.

[0104] The method for preparing the IGBT device of this embodiment is described in detail below with reference to the specific drawings.

[0105] like Figure 2 and Figure 3 As shown, firstly, step S1 is performed to provide a substrate 14 ; and step S2 is performed to form a cell region structure and a terminal region structure on the substrate 14 .

[0106] As an example, the method for forming the cell region structure and the terminal region structure includes the following steps:

[0107] S21, forming at least one LOCOS oxidation isolation layer 23 on the upper surface of the substrate 14, wherein the LOCOS oxidation isolation layer 23 is formed between the cell region structure and the terminal region structure, and between each structural unit in the terminal region structure;

[0108] S22, performing ion implantation to a preset depth on the upper surface of the substrate 14 in the terminal region structure to form a field limiting ring 25;

[0109] S23, performing ion implantation to a preset depth on the upper surface of the substrate 14 and the field limiting ring 25 around the LOCOS oxidation isolation layer 23 to form a carrier storage layer 15;

[0110] S24, forming a trench gate 22 extending downward from the upper surface of the carrier storage layer 15 to a preset depth in the substrate 14;

[0111] S25, performing ion implantation to a preset depth on the upper surface of the carrier storage layer 15 to form a well region 16;

[0112] S26, performing ion implantation to a preset depth on the upper surface of the well region 16 to form an emitter layer 17;

[0113] S27, forming an interlayer dielectric layer 18 on the upper surface of the obtained structure;

[0114] S28 , forming an electrical lead-out structure 24 penetrating the interlayer dielectric layer 18 , wherein the electrical lead-out structure 24 electrically leads out the emitter layer 17 , the trench gate 22 , and the terminal region structure.

[0115] As a further example, Figure 3 As shown, the method for forming the trench gate 22 in step S24 includes:

[0116] S241, forming a mask layer on the upper surface of the obtained structure;

[0117] S242, defining a trench 27 region based on the mask layer, and etching the emitter layer 17, the well region 16, the carrier storage layer 15 and the substrate 14 to form the trench 27;

[0118] S243, removing the remaining mask layer;

[0119] S244, forming a gate oxide layer 221 on the bottom wall and the side wall of the trench 27, for example, the gate oxide layer 221 may be formed on the bottom wall and the side wall of the trench 27 by using a process including but not limited to a thermal oxidation process;

[0120] S245, forming a gate conductive layer 222 filling the trench 27 on the gate oxide layer 151, for example, the gate conductive layer 222 filling the trench 27 can be formed on the gate oxide layer 221 by a process including but not limited to chemical vapor deposition, the gate conductive layer 222 can be, for example, a polysilicon layer, the gate conductive layer 222 fills the remaining space of the trench 27, and the gate oxide layer 221 and the gate conductive layer 222 located in the trench 27 constitute the trench gate 22.

[0121] As another further example, Figure 3 As shown, the method for forming the electrical lead-out structure 24 in step S28 includes:

[0122] S281, forming a plurality of conductive contact holes 26 penetrating the interlayer dielectric layer 18 and extending to a preset depth in the emitter layer 17, wherein the plurality of conductive contact holes 26 are connected to the emitter layer 17, the trench gate 22 and the terminal region structure, and the conductive contact holes 26 may be formed by, but not limited to, etching processes;

[0123] S282, forming an adhesion layer 242 and an interconnection metal layer 241 on the surface of the conductive contact hole 26 in sequence by processes including but not limited to physical vapor deposition; the adhesion layer 242 may be a titanium layer and / or a titanium nitride layer, and the interconnection metal layer 241 may be a tungsten layer; or the adhesion layer 242 may be a tantalum and / or a tantalum nitride layer, and the interconnection metal layer 241 may be a copper layer and / or a copper alloy layer, so as to enhance the electrical lead-out effect of the electrical lead-out structure 24, thereby reducing the switching loss of the IGBT device and improving the device performance.

[0124] like Figure 2 and Figure 4 As shown, step S3 is then performed to form a plurality of metal layers 19 above the obtained structure, wherein the metal layers 19 include an emitter metal layer 191, a gate metal layer 192 and a terminal region metal layer 193; the emitter metal layer 191 and the gate metal layer 192 are formed above the cell region structure to electrically lead out the cell region structure; the terminal region metal layer 193 is formed above the terminal region structure to electrically lead out the terminal region structure.

[0125] Specifically, Figure 4 As shown, the emitter metal layer 191 electrically leads the emitter layer 17 through the electrical lead-out structure 24, and the gate metal layer 192 electrically leads the trench gate 22 through the electrical lead-out structure 24. As an example, the metal layer 19 may be formed by processes including but not limited to physical vapor deposition, and the metal layer 19 may be an aluminum-copper alloy layer. The height of the metal layer 19 is 4 μm to 6 μm, for example, 4 μm, 6 μm, etc., which may be set according to actual process conditions and is not excessively limited here.

[0126] like Figure 2 and Figure 7 As shown, step S4 is then performed to etch the metal layer 19 to form a packaging window 21 with a preset depth.

[0127] As an example, Figures 5 to 7 As shown, the method for forming the packaging window 21 includes the following steps:

[0128] like Figure 5 As shown, a photoresist layer 28 is formed on the surface of the metal layer 19 and patterned;

[0129] like Figure 6 As shown, the metal layer 19 is etched to a preset depth based on the patterned photoresist layer 28 to form the packaging window 21;

[0130] like Figure 7 As shown, the patterned photoresist layer 28 is removed.

[0131] As an example, the packaging window 21 located above the cellular area structure is a square with a side length between 10μm and 100μm, and the number of the packaging windows 21 is 1 to 8. The shape and number of the packaging windows 21 located above the cellular area structure can be set according to the packaging wire bonding process requirements, and no excessive restrictions are made here.

[0132] like Figure 2 and Figure 8 As shown, step S5 is then performed to form a packaging layer 20 on the obtained structure, and the packaging layer 20 at least fills the packaging window 21 .

[0133] The formed packaging layer 20 is used to provide support for the IGBT device during the subsequent thinning process of the substrate 14. As an example, based on the current mainstream packaging size of the IBGT device, the top of the formed packaging layer 20 is 0μm to 200μm higher than the top of the metal layer 19.

[0134] As an example, the method for forming the encapsulation layer 20 includes one of plastic encapsulation process, compression molding, transfer molding, liquid sealing molding, vacuum lamination molding and spin coating molding. Specifically, the encapsulation layer 20 can be formed by processes such as spreading materials, heating and melting, mold closing and cooling, so that the encapsulation window 21 can be filled and the cellular area structure and the terminal area structure can be covered.

[0135] As an example, before forming the packaging layer 20, a step of forming a passivation layer (not shown) on the terminal area metal layer 193 is also included. Preferably, the thickness of the passivation layer can be set to be less than 18μm. The material of the passivation layer includes one or a combination of polyimide, polysiloxane and silicone rubber. The passivation layer is used to pre-fill the packaging window 21 located above the terminal area metal layer 193 before forming the corresponding packaging layer 20, and is used to shield external impurities, ionic charges, etc. from polluting the terminal area structure. If the material of the packaging layer 20 has a similar function, the passivation layer can be cancelled. There is no excessive restriction on whether the IGBT device has a passivation layer and the material of the passivation layer.

[0136] As an example, the metal layer 19 and the collector metal layer 11 can be formed by processes including but not limited to physical vapor deposition. The metal layer 19 can be an aluminum-copper alloy layer, and the collector metal layer 11 can be at least one of a copper layer, a gold layer, a nickel layer and other material layers. There can also be an adhesion layer between the collector metal layer 11 and the collector layer 12, for example, a titanium layer and / or a titanium nitride layer, to enhance the adhesion between the collector metal layer 11 and the collector layer 12.

[0137] By filling the packaging layer 20 in the packaging window 21 between the metal layers, the sealing of the device is increased, and external impurities, ion charges, water vapor, etc. can be shielded from damaging the internal structure of the IGBT device. The packaging layer 20 can provide support for the IGBT device structure, and in the subsequent substrate thinning process, problems such as hidden cracks, defects, water vapor, sticky acid, yellowing and fingerprints on the front of the IGBT device can be prevented.

[0138] As an example, Figure 8 As shown, after forming the encapsulation layer 20, the following steps are also included:

[0139] Performing backside thinning on the substrate 14;

[0140] Ions are implanted from the bottom surface of the substrate 14 to form a buffer layer 13 and a collector layer 12;

[0141] A back-gold process is performed on the lower surface of the collector layer 12 to form a collector metal layer 11 .

[0142] It should be noted here that the lower surface of the substrate 14 and the lower surface of the collector layer 12 both refer to the side away from the metal layer 19 .

[0143] like Figure 2 and Fig. 9 As shown, step S6 is then performed to thin and planarize the encapsulation layer 20 to expose the top of the emitter metal layer 191 and the gate metal layer 192 .

[0144] As an example, the method of thinning and planarizing the encapsulation layer 20 includes grinding, chemical mechanical polishing and wet etching, which are not overly limited here.

[0145] As an example, the packaging layer 20 may be thinned and flattened by grinding, chemical etching, mechanical polishing or chemical mechanical polishing. Preferably, in this embodiment, a chemical mechanical polishing process is used to thin and flatten the packaging layer 20. The chemical mechanical polishing process combines the effects of mechanical grinding and chemical etching to form a smooth and flat surface on the packaging layer 20.

[0146] After thinning and flattening the packaging layer 20, the metal layer 19 forms a thinner area and a thicker area in the height direction, the thinner area is used to electrically connect the cell area structure and the terminal area structure, and the thicker area is convenient for subsequent CP testing. The thickness of the thicker area and the thinner area can be set according to actual needs. As an example, the thicker area of ​​the metal layer 19 in the height direction is 4μm~6μm, and the thinner area of ​​the metal layer in the height direction is 0.2μm~1μm.

[0147] In summary, the IGBT device and its preparation method of the present invention, by filling the encapsulation layer in the encapsulation window between multiple metal layers and exposing the emitter metal layer and the gate metal layer of the cell region structure, can not only realize the electrical extraction of the emitter layer and the trench gate in the cell region structure of the IGBT device, but also the encapsulation layer filled in the encapsulation window can increase the sealing of the IGBT device, shielding the external impurities, ion charge, water vapor and other damages to the internal structure of the device, and the encapsulation layer can provide support for the IGBT device structure, and can prevent the problems of hidden cracks, defects, water vapor, sticky acid, yellowing and fingerprints on the front of the IGBT device in the substrate thinning process of the IGBT device, and simplify the process of substrate thinning, saving costs while reducing the derived quality problems. In the CP test needle piercing process, the encapsulation layer can prevent the CP test needle from piercing the cell region metal layer to cause the IGBT device to be scrapped, and the supporting effect of the encapsulation layer on the IGBT device structure can be used to reduce the substrate thickness to be thinner, thereby reducing the overall size of the IGBT device and improving market competitiveness. In addition, compared with the prior art structure of using two passivation layers to cover the terminal area surrounding the IGBT device, two passivation layer masks are saved, further saving costs. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0148] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An IGBT device, characterized in that: The IGBT device comprises, from bottom to top, a collector metal layer, a collector layer, a substrate, and a cell region structure and a terminal region structure located on the substrate; It also includes: multiple metal layers, multiple packaging windows and packaging layers; wherein the multiple metal layers include an emitter metal layer and a gate metal layer formed above the cell region structure to electrically lead out the cell region structure, and a terminal region metal layer formed above the terminal region structure to electrically lead out the terminal region structure; the multiple packaging windows extend downward from the upper surface of the metal layer to a preset depth in the metal layer, respectively; the packaging layer is filled in the packaging window and covers the cell region structure and the terminal region structure, and the packaging layer is flush with the top of the emitter metal layer and the gate metal layer.

2. The IGBT device according to claim 1, characterized in that: The number of the packaging windows located above the cellular region structure is 1 to 8, and the shape is a square with a side length ranging from 10 μm to 100 μm.

3. The IGBT device according to claim 1, characterized in that: The thicker area of ​​the metal layer in the height direction is 4 μm to 6 μm, and the thinner area of ​​the metal layer in the height direction is 0.2 μm to 1 μm.

4. The IGBT device according to claim 1, characterized in that: The material of the encapsulation layer includes an organic polymer material, and the organic polymer material includes one or a combination of polyimide and polysiloxane.

5. The IGBT device according to claim 1, characterized in that: The IGBT device further includes a passivation layer formed between the terminal region metal layer and the corresponding packaging layer, and the thickness of the passivation layer is less than 18 μm.

6. The IGBT device according to claim 1, characterized in that: The IGBT device further includes a buffer layer located between the collector layer and the substrate; The cell region structure and the terminal region structure include, from bottom to top, a carrier storage layer, a well region, an emitter layer and an interlayer dielectric layer; and further include: A field limiting ring, wherein the field limiting ring is formed between the substrate and the carrier storage layer in the terminal region structure; A trench gate located in the cell region structure, the trench gate extending downward from the surface of the emitter layer to a preset depth in the substrate; A plurality of electrical lead-out structures penetrating the interlayer dielectric layer, wherein the electrical lead-out structures electrically lead out the emitter layer, the trench gate and the terminal region structure; At least one LOCOS oxidation isolation layer is located between the cell region structure and the terminal region structure, and between each structural unit in the terminal region structure.

7. A method for preparing an IGBT device, characterized in that: The preparation method comprises: providing a substrate; forming a cell region structure and a terminal region structure on the substrate; A plurality of metal layers are formed on the obtained structure, wherein the metal layers include an emitter metal layer, a gate metal layer and a terminal region metal layer; the emitter metal layer and the gate metal layer are formed on the cell region structure to electrically lead out the cell region structure; the terminal region metal layer is formed on the terminal region structure to electrically lead out the terminal region structure; Etching the metal layer to form a packaging window with a preset depth; forming a packaging layer on the obtained structure, wherein the packaging layer at least fills the packaging window; The encapsulation layer is thinned and planarized to expose the tops of the emitter metal layer and the gate metal layer.

8. The method for preparing an IGBT device according to claim 7, characterized in that: The method for forming the encapsulation window comprises the following steps: forming a photoresist layer on the surface of the metal layer and patterning the photoresist layer; Etching the metal layer to a preset depth based on the patterned photoresist layer to form the packaging window; The patterned photoresist layer is removed.

9. The method for preparing an IGBT device according to claim 7, characterized in that: After forming the encapsulation layer, the following steps are also included: performing backside thinning on the substrate; Performing ion implantation from the lower surface of the substrate inward to form a buffer layer and a collector layer; A back-gold process is performed on the lower surface of the collector layer to form a collector metal layer.

10. The method for preparing an IGBT device according to claim 7, characterized in that: The method for forming the cell region structure and the terminal region structure comprises the following steps: forming at least one LOCOS oxidation isolation layer on the upper surface of the substrate, wherein the LOCOS oxidation isolation layer is formed between the cell region structure and the terminal region structure, and between each structural unit in the terminal region structure; Performing ion implantation to a preset depth on the upper surface of the substrate in the terminal region structure to form a field limiting ring; Performing ion implantation to a preset depth on the upper surface of the substrate and the field limiting ring around the LOCOS oxidation isolation layer to form a carrier storage layer; A trench gate is formed by extending downward from the upper surface of the carrier storage layer to a preset depth in the substrate; Performing ion implantation at a preset depth on the upper surface of the carrier storage layer to form a well region; Performing ion implantation at a preset depth on the upper surface of the well region to form an emitter layer; forming an interlayer dielectric layer on the upper surface of the obtained structure; An electrical lead-out structure penetrating the interlayer dielectric layer is formed, wherein the electrical lead-out structure electrically leads out the emitter layer, the trench gate and the terminal region structure.

11. The method for preparing an IGBT device according to claim 7, characterized in that: The thicker area of ​​the metal layer in the height direction is 4 μm to 6 μm, and the thinner area of ​​the metal layer in the height direction is 0.2 μm to 1 μm.

12. The method for preparing an IGBT device according to claim 7, characterized in that: Before forming the encapsulation layer, the method further includes forming a passivation layer on the metal layer in the terminal region, wherein the thickness of the passivation layer is less than 18 μm.

13. The method for preparing an IGBT device according to claim 7, characterized in that: Before the packaging layer is thinned and planarized, the top of the packaging layer is higher than the top of the metal layer by 0 μm to 200 μm.

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