Semiconductor device with periodically changing trench gate and manufacturing method thereof
By adopting a periodically changing trench gate structure in semiconductor devices, and using alternate settings of the first region with a larger depth and the second region with a smaller depth, the problem of on-resistance limiting device performance improvement is solved, and the on-resistance limiting device performance is realized. Low resistance, high voltage operating range and long service life effects.
Patent Information
- Application Number
- CN202411718788.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-27
- Publication Date
- 2025-02-18
AI Technical Summary
The on-resistance of MOSFET devices prepared based on SiC materials limits its performance improvement, and the prior art protects the gate dielectric layer by reducing the trench gate density, but this limits the device's resistance reduction and the voltage tolerance range.
The trench gate is adopted with a periodically changing trench gate, wherein the trench gate includes a first region with a larger depth and a second region with a smaller depth. By alternately providing the first region and the second region, the trench gate is improved. The distribution of the bottom electric field reduces the intensity of the aggregated electric field, thereby protecting the gate dielectric layer from breakdown.
While increasing the trench gate density, the resistance at the bottom of the trench gate is reduced, the voltage working range of the device is expanded, and the service life is extended.
Smart Images
Figure CN119486194A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductors, and more specifically, to a semiconductor device with a periodically changing trench gate and a manufacturing method thereof. Background Art
[0002] With the continuous development of the semiconductor industry, more and more semiconductor materials have been discovered. Among them, SiC materials have advantages in physical properties such as large bandgap, high breakdown electric field, fast electron mobility, and high thermal conductivity. These characteristics make silicon carbide very suitable for high temperature, high pressure, high frequency and radiation-resistant environments. Compared with traditional devices based on Si materials, devices based on SiC materials have higher operating voltage, lower loss and higher power density. Among them, the on-resistance of MOSFET based on SiC is the main factor limiting its further performance improvement. Nowadays, the lateral channel is usually converted into a longitudinal channel to reduce the on-resistance. However, this method will increase the maximum electric field at the oxide layer inside the device, making it easy to break down. Summary of the invention
[0003] In view of this, the present application provides a semiconductor device with a periodically changing trench gate and a manufacturing method thereof, the scheme is as follows:
[0004] In a first aspect, the present application provides a semiconductor device having a periodically changing trench gate, comprising:
[0005] a substrate having opposing first and second surfaces;
[0006] A plurality of trench gates are arranged in the first surface, the trench gates are arranged in sequence and spaced apart in the first direction, and a source region is provided in the first surface between adjacent trench gates;
[0007] A source electrode located on the first surface, the source electrode is electrically connected to the source region and insulated from the trench gate;
[0008] Among them, in the second direction, the trench gate includes a first region and a second region alternately arranged in sequence, the depth of the first region is greater than the depth of the second region; the first direction and the second direction are both parallel to the first surface, and the two are perpendicular; the second direction is the extension direction of the trench gate.
[0009] Preferably, in the above semiconductor device, in the first region, a side of the trench gate facing the second surface has an ion implantation region, and the ion implantation region has no overlapping region with the substrate of the second region;
[0010] The doping type of the ion implantation region is opposite to the doping type of the substrate.
[0011] Preferably, in the above semiconductor device, in the second direction, the depth of the trench gate located in the first region gradually decreases from the middle to both sides; to match the trench gate located in the first region, the injection depth of the ion injection region gradually decreases from the middle to both sides.
[0012] Preferably, in the above semiconductor device, for two trench gates adjacent to each other in the first direction, a first region of one trench gate is arranged opposite to a second region of the other trench gate.
[0013] Preferably, in the above semiconductor device, the trench gate comprises:
[0014] a first groove extending along a second direction;
[0015] a gate dielectric layer covering a surface of the first trench;
[0016] The gate semiconductor material fills the first trench having the gate dielectric layer.
[0017] Preferably, in the above semiconductor device, the depth of the source region is less than the minimum depth of the trench gate.
[0018] Preferably, in the above semiconductor device, in the direction from the second surface to the first surface, the source region includes a first source region and a second source region which are arranged in sequence;
[0019] The doping type of the first source region is opposite to the doping type of the second source region, and the doping type of the second source region is the same as the doping type of the substrate.
[0020] Preferably, in the above semiconductor device, the first surface is covered with an insulating layer, and the insulating layer has an opening exposing the second source region;
[0021] The source electrode is located on the surface of the insulating layer, is electrically in contact with the second source region through the opening, and is isolated from the trench gate through the insulating layer.
[0022] Preferably, in the above semiconductor device, in the second direction, the first source region and the second source region both extend from one end along the target region to the other end of the target region;
[0023] A portion of the substrate between two adjacent trench gates is the target area.
[0024] Preferably, in the above semiconductor device, the first surface has a plurality of second trenches extending along the first direction; the trench gates separate the second trenches;
[0025] The first source region and the second source region are formed in the surface of the second trench based on an ion implantation process.
[0026] Preferably, in the above semiconductor device, a region of the second source region corresponding to the opening has an ohmic contact region, and a doping type of the ohmic contact region is opposite to a doping type of other parts of the second source region.
[0027] The second aspect of the second application provides a method for preparing the semiconductor device introduced above, comprising:
[0028] Providing a substrate having a first surface and a second surface opposite to each other;
[0029] A plurality of trench gates are formed in the first surface, the trench gates are sequentially spaced in a first direction, and a source region is provided in the first surface between adjacent trench gates;
[0030] A source electrode is formed on the first surface, the source electrode is electrically connected to the source region and is insulated from the trench gate;
[0031] Among them, in the second direction, the trench gate includes a first region and a second region alternately arranged in sequence, the depth of the first region is greater than the depth of the second region; the first direction and the second direction are both parallel to the first surface, and the two are perpendicular; the second direction is the extension direction of the trench gate.
[0032] Preferably, in the above-mentioned method for manufacturing a semiconductor device, the method for forming a trench gate comprises:
[0033] forming a first trench in the first surface;
[0034] forming a gate dielectric layer on a surface of the first trench;
[0035] A gate semiconductor material is filled in the first trench having the gate dielectric layer.
[0036] Preferably, in the above method for manufacturing a semiconductor device, before forming the gate dielectric layer, the method further comprises:
[0037] At a position corresponding to the first region, based on the first trench, ion implantation is performed on the substrate to form an ion implantation region;
[0038] The ion implantation region is located on the side of the trench gate facing the second surface, and the ion implantation region has no overlapping area with the substrate of the second region; the doping type of the ion implantation region is opposite to the doping type of the substrate.
[0039] Preferably, in the above method for manufacturing a semiconductor device, the method for forming a source region includes:
[0040] Performing ion implantation on the first surface to sequentially form a first source region in the first surface;
[0041] Ion implantation is performed on the first source region to form a second source region in the first source region; wherein an implantation depth of the second source region is less than an implantation depth of the first source region.
[0042] Preferably, in the method for manufacturing the semiconductor device, the method for forming the source electrode includes:
[0043] forming an insulating layer covering the first surface;
[0044] forming an opening in the insulating layer to expose the second source region;
[0045] A source electrode is formed on the insulating layer. The source electrode is electrically in contact with the second source region through the opening and is isolated from the trench gate through the insulating layer.
[0046] Preferably, in the above method for manufacturing a semiconductor device, before forming the insulating layer, the method further comprises:
[0047] Ion implantation is performed in the area corresponding to the opening of the second source region, so that the doping type of the area corresponding to the opening of the second source region is opposite to that of other parts of the second source region; wherein the part of the second source region implanted with ions serves as an ohmic contact area.
[0048] Based on the above introduction, the present application provides a semiconductor device with a periodically changing trench gate and a method for manufacturing the same. In the semiconductor device, the trench gate includes a first region with a larger depth and a second region with a smaller depth. The distribution of the electric field at the bottom of the trench gate is improved by alternating the first region and the second region. Under the condition of the same trench gate density, the intensity of the concentrated electric field at the bottom of the trench gate can be reduced, thereby solving the problem that the gate dielectric layer at the bottom of the trench is easily broken down. The semiconductor device prepared based on this trench gate structure can have a lower resistance while increasing the gate trench density, and has a larger voltage tolerance range and a longer service life. BRIEF DESCRIPTION OF THE DRAWINGS
[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.
[0050] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.
[0051] Figure 1A schematic diagram of the structure of a semiconductor device;
[0052] Figure 2 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application;
[0053] Figure 3 for Figure 2 The schematic diagram of the structure of the semiconductor device shown is provided with surface isolation and a metal layer;
[0054] Figure 4 for Figure 3 A schematic cross-sectional view of the semiconductor device at Q1 shown in FIG.
[0055] Figure 5 for Figure 3 A schematic cross-sectional view of the semiconductor device shown in FIG.
[0056] Figure 6 for Figure 3 A schematic cross-sectional view of the semiconductor device shown in FIG.
[0057] Figure 7 for Figure 3 A schematic cross-sectional view of the semiconductor device at Q4 shown in FIG.
[0058] Figure 8 A schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application;
[0059] Fig. 9 for Figure 8 The schematic diagram of the structure of the semiconductor device shown is provided with surface isolation and a metal layer;
[0060] Fig.10 for Fig. 9 A schematic cross-sectional view of the semiconductor device shown in FIG. 1 at M1;
[0061] Fig.11 for Fig. 9 A schematic cross-sectional view of the semiconductor device shown in FIG.
[0062] Fig.12 for Fig. 9 A schematic cross-sectional view of the semiconductor device shown in FIG. 1 at M3;
[0063] Fig.13 for Fig. 9 A schematic cross-sectional view of the semiconductor device shown in FIG. 5 at M5;
[0064] Figure 14-Figure 19 A process flow chart of a semiconductor device manufacturing method provided in an embodiment of the present application;
[0065] Figure 20-Figure 29A process flow chart for forming a first trench provided in an embodiment of the present application;
[0066] Figure 30-Figure 33 A process flow chart for forming an ion implantation region provided in an embodiment of the present application;
[0067] Figure 34-Figure 38 Another process flow chart for forming a first groove is provided in an embodiment of the present application. DETAILED DESCRIPTION
[0068] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.
[0069] Conventional trench gate structures such as Figure 1 As shown, the semiconductor structure includes: a substrate 30 having a first surface and a second surface relative to each other; a plurality of trench gates 31 located on the second surface of the substrate; a source region 32 located between two adjacent trench gates 31; a source electrode 34 covering the second surface, the source electrode 34 being electrically connected to the source region 32; and an isolation dielectric layer 33 between the source electrode 34 and the trench gate 31, the isolation dielectric layer 33 being used to isolate the source electrode 34 from the trench gate 31.
[0070] The substrate 30 includes a base 301 and an epitaxial layer 302 located on the base 301, the side of the base 301 facing away from the epitaxial layer 302 is a first surface, and the side of the epitaxial layer 302 facing away from the base 301 is a second surface. The trench gate 31 includes a trench 311 located in the epitaxial layer 302; a gate semiconductor material 313 filling the trench 311; and a gate dielectric layer 312, generally an oxide layer, between the gate semiconductor material 313 and the trench 311. The source region 32 includes a first source region 321 and a second source region 322, wherein the second source region 322 is electrically connected to the source 34.
[0071] For semiconductor devices of this structure, when SiC material is used as the substrate, the tolerance of the device in high temperature, high pressure, high frequency and radiation environment can be improved. However, the maximum electric field near the gate dielectric layer 312 is increased by about 10 times, making the gate dielectric layer at the bottom of the trench a relatively weak position and easily broken down.
[0072] In order to solve the above problems, in the prior art, in the first solution, trench sources are set on both sides of the trench gate, and the electric field near the gate dielectric layer is reduced by the trench sources, but the number of gate trenches will be reduced; in the second solution, part of the bottom of the trench gate is set in the well region, and the electric field near the gate dielectric layer is reduced by the well region, thereby protecting the gate dielectric layer at the bottom of the trench gate. Similarly, this solution will cause half of the structure of any trench gate to be covered by the well region, thereby reducing the number of effective gate trenches. Both of the above solutions protect the gate dielectric layer by reducing the effective gate trench density, which will limit the subsequent increase in the gate trench density. In the third solution, the gate dielectric layer is protected by forming an ion implantation region in the epitaxial layer at the bottom of the trench. However, the formed ion implantation region will produce a JFET effect, which increases the resistance of the trench gate and makes it difficult to reduce the total resistance. In the prior art, the protective layer oxide layer, increasing the gate trench density and reducing the resistance are difficult to achieve at the same time.
[0073] In order to solve the above problems, the present application provides a semiconductor device with a periodically changing trench gate and a manufacturing method thereof, the semiconductor device comprising: a substrate having a first surface and a second surface relative to each other; a plurality of trench gates arranged in the first surface, the trench gates being arranged in sequence and spaced apart in a first direction, and a source region being provided in the first surface between adjacent trench gates; a source electrode being located on the first surface, the source electrode being electrically connected to the source region and being insulated from the trench gates; wherein, in the second direction, the trench gate comprises a first region and a second region alternately arranged in sequence, and the depth of the first region is greater than the depth of the second region; the first direction and the second direction are both parallel to the first surface, and the two are perpendicular to each other; the second direction is the extension direction of the trench gate.
[0074] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.
[0075] refer to Figure 2-Figure 7 , Figure 2 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application is shown in FIG. Figure 3 for Figure 2 The schematic diagram of the structure of the semiconductor device shown is provided with surface isolation and a metal layer; Figure 4 for Figure 3 A schematic cross-sectional view of the semiconductor device at Q1 shown in FIG. Figure 5 for Figure 3 A schematic cross-sectional view of the semiconductor device shown in FIG. Figure 6 for Figure 3 A schematic cross-sectional view of the semiconductor device shown in FIG. Figure 7 for Figure 3 A schematic cross-sectional view of the semiconductor device shown in FIG. Figure 2-Figure 7The semiconductor device shown includes: a substrate 10 having a first surface and a second surface opposite to each other; a plurality of trench gates 11 arranged in the first surface, the trench gates 11 are arranged in sequence and spaced apart in a first direction X, and a source region 12 is provided in the first surface between adjacent trench gates 11; a source electrode 16 located on the first surface, the source electrode 16 is electrically connected to the source region 12 and is insulated from the trench gates 11; wherein, in a second direction Z, the trench gate 11 includes a first region 11a and a second region 11b alternately arranged in sequence, the depth of the first region 11a is greater than the depth of the second region 11b, thereby forming a trench gate 11 having a periodically changing trench gate, and the depth of the trench gate 11 periodically changes alternately in the second direction Z; the first direction X and the second direction Z are both parallel to the first surface, and the two are perpendicular; the second direction Z is the extension direction of the trench gate 11.
[0076] In the present application, SiC material is used as an example of the substrate 10 to introduce the semiconductor device. It should be noted that the technical solution provided in the present application can select other materials as the substrate 10 according to the situation, and the present application does not limit this.
[0077] The substrate 10 includes: a base 101 and an epitaxial layer 102 located on the surface of the base 101. The side surface of the epitaxial layer 102 facing away from the base 101 is the second surface, and the side surface of the base 101 facing away from the epitaxial layer 102 is the first surface. A drain is also provided on the first surface. The drain and the source 12 and the trench gate 11 form a MOSFET structure, wherein the trench gate 11 includes a first region with a larger depth and a second region with a smaller depth. The distribution of the electric field at the bottom of the trench gate 11 is improved by alternating the first region and the second region. Under the condition of the same trench gate 11 density, the intensity of the concentrated electric field at the bottom of the trench gate 11 can be reduced, thereby solving the problem that the gate dielectric layer at the bottom of the trench is easily broken down. The semiconductor device prepared based on this trench gate structure can have a lower resistance while increasing the gate trench density, and its voltage operating range is larger and its service life is longer.
[0078] The first direction X is the direction indicated by the X-axis of the coordinate axis in the figure, the second direction Z is the direction indicated by the Z-axis of the coordinate axis in the figure, and the direction indicated by the Y-axis is the direction from the first surface to the second surface.
[0079] Figure 4 In the cross section shown, the trench gates 11 on both sides are located at the deepest position of the first region 11a, while the middle trench gate 11 is located at the shallowest position of the second region 11b. It can be seen that the epitaxial layer 102 at the bottom of the trench gates 11 on both sides has a high P+ implantation, while the epitaxial layer 102 of the middle trench gate 11 does not have this structure. Figure 5The depths of the three trench gates 11 in the cross section are the same, and the three trench gates 11 are all located in the first region 11a. Figure 6 The middle trench gate 11 of the cross section is located at the deepest position of the first region 11a, and the trench gates 11 on both sides are located at the shallowest position of the second region 11b. The ion implantation region 14 doped in the bottom surface of the trench gate 11 varies according to the depth of the trench gate 11. Figure 7 The cross section shown shows the depth of the same trench gate 11 and the variation of the ion implantation region in the Z direction.
[0080] In the semiconductor device described above, in the first region 11a, the side of the trench gate 11 facing the second surface has an ion implantation region 14, and the ion implantation region 14 has no overlapping area with the substrate 10 of the second region 11b; wherein the doping type of the ion implantation region 14 is opposite to the doping type of the substrate 10.
[0081] By performing ion implantation on the side of the first region 11a of the trench gate 11 facing the second surface, an ion implantation region 14 is formed, and the ion implantation region 14 can suppress the leakage current of the trench gate 11 and protect the gate dielectric layer 112 at the bottom of the trench gate 11 from being broken down by the electric field. Since the trench gate 11 includes a deeper first region 11a and a shallower second region 11b, the electric field distribution at the bottom of the trench gate 11 can be changed, and the electric field strength at the bottom of the first region 11a can be made greater than that of the second region 11b. Therefore, the ion implantation region 14 only needs to be formed on the side of the first region 11a facing the second surface, so as to protect the gate dielectric layer 112 at the bottom of the trench gate 11 from being broken down, and at the same time, the area of the ion implantation region 14 is reduced, and the JFET effect is reduced, thereby reducing the overall on-resistance of the trench gate 11.
[0082] In the semiconductor devices described above, Figure 7 As shown, in the same trench gate 11, in the second direction Z, the depth of the trench gate 11 located in the first region 11a gradually decreases from the middle to the sides; it is adapted to the trench gate 11 located in the first region 11a, that is, the injection depth of the ion injection region 14 gradually decreases from the middle to the sides. When the trench gate 11 is located below the position where the depth of the first region 11a is the largest, the injection depth of the ion injection region 14 is the largest, and the depth of the trench gate 11 gradually decreases from the middle to the sides of the first region 11a, the injection depth of the ion injection region 14 below the first region 11a gradually decreases. The depth of the trench gate 11 located in the second region 11b gradually increases from the middle to the sides. Since the ion injection region 14 has no overlapping area with the substrate 10 of the second region 11b, there is no ion injection region 14 below the second region 11b.
[0083] Due to the structure of the trench gate 11, the electric field distribution at the bottom of the trench gate 11 will change, so that the electric field at the bottom of the first region 11a is larger, and the electric field at the bottom of the second region 11b is smaller, wherein the depth of the trench gate 11 in the first region 11a decreases from the middle to both sides, and the electric field distribution at the bottom of the first region 11a also decreases from the middle to both sides. Therefore, an ion implantation region 14 with a gradually changing depth can be set to provide a more accurate protection effect.
[0084] In the semiconductor device described above, for two adjacent trench gates 11 in the first direction X, the first region 11 a of one trench gate 11 is disposed opposite to the second region 11 b of the other trench gate 11 .
[0085] In the embodiment of the present application, the first region 11a and the second region 11b of two adjacent trench gates 11 are arranged relative to each other, so that the electric field at the bottom of the trench gate 11 is difficult to gather, disrupting the electric field distribution in the first direction X, thereby enabling the semiconductor device to withstand a higher density of trench gates 11.
[0086] The embodiment of the present application provides a device structure in which, in two adjacent trench gates 11, a first region 11a of one trench gate 11 and a second region 11b of another trench gate 11 are arranged relative to each other in a first direction X. Among them, for two adjacent trench gates 11 in the first direction X, the first region 11a of one trench gate 11 and the second region 11b of the other trench gate 11 can be set to a corresponding misalignment amplitude according to actual needs.
[0087] In other embodiments, for two adjacent trench gates 11 in the first direction, the first regions 11 a of the two trench gates 11 may be disposed opposite to each other in the first direction X, and the second regions 11 b may be disposed opposite to each other in the first direction X, thereby simplifying the process. This application does not limit this.
[0088] The trench gate 11 includes: a first trench 111 extending along the second direction; a gate dielectric layer 112 covering the surface of the first trench 111 ; and a gate semiconductor material 113 filling the first trench 111 having the gate dielectric layer 112 .
[0089] The gate dielectric layer 112 can isolate the gate semiconductor material 113 from the substrate 10 to prevent the two from contacting and causing a short circuit. The upper surface of the filled gate semiconductor material 113 is flush with the first surface of the substrate 10. The ion implantation region 14 described above is formed by implanting ions into the substrate 10 based on the first trench 111.
[0090] In the semiconductor device described above, the depth of the source region 12 is less than the minimum depth of the trench gate 11. The depth of the source region 12 within the first surface may be uniform.
[0091] In the semiconductor device introduced above, in the direction from the second surface to the first surface, the source region 12 includes a first source region 121 and a second source region 122 arranged in sequence; wherein the doping type of the first source region 121 is opposite to the doping type of the second source region 122, and the doping type of the second source region 122 is the same as the doping type of the substrate 10.
[0092] Among them, the second source region 122 and the substrate 10 are both N-type ion doped, the first source region 121 is P-type ion doped, the base 101 and the second source region 122 in the substrate 10 are N+ ion doped, the epitaxial layer 102 is N- ion doped, the first source region 121 is P- ion doped, and the ion implantation region 14 mentioned above is P-type doped, and P+ ion doping or P- ion doping can be set based on needs.
[0093] Combination Figure 3-Figure 7 As shown, the first surface of the semiconductor device is covered with an insulating layer 15, and the insulating layer 15 has an opening exposing the second source region 122; wherein the source electrode 16 is located on the surface of the insulating layer 15, electrically contacts the second source region 122 through the opening, and is isolated from the trench gate 11 through the insulating layer 15.
[0094] By providing the insulating layer 15, the trench gate 11 is isolated from the source 16. At the same time, the opening on the insulating layer 15 allows the source 16 to contact the second source region 122. By providing the insulating layer 15, the area of the source 16 can be consistent with the area of the first surface, thereby increasing the area of the source 16 and improving the performance of the semiconductor device.
[0095] In the semiconductor device introduced above, in the second direction, the first source region 121 and the second source region 122 both extend from one end along the target area to the other end of the target area; a portion of the substrate 10 between two adjacent trench gates 11 is the target area, specifically, the epitaxial layer 102 between two adjacent trench gates 11 in the first direction X is the target area, and the source region 12 is located on the surface of the target area facing away from the substrate 101.
[0096] The first source region 121 and the second source region 122 are arranged in the area between two adjacent trench gates 11, thereby improving the space utilization of the first surface. After the density of the trench gates 11 is increased, sufficient area of the source region 12 can be ensured.
[0097] The present application also provides another semiconductor device structure, referring to Figure 8-Figure 13 , Figure 8 A schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application; Fig. 9 for Figure 8The schematic diagram of the structure of the semiconductor device shown is provided with surface isolation and a metal layer; Fig.10 for Fig. 9 A schematic cross-sectional view of the semiconductor device shown in FIG. 1 at M1; Fig.11 for Fig. 9 A schematic cross-sectional view of the semiconductor device shown in FIG. Fig.12 for Fig. 9 A schematic cross-sectional view of the semiconductor device shown in FIG. 1 at M3; Fig.13 for Fig. 9 A schematic cross-sectional view of the semiconductor device shown in FIG. 5 at M5; wherein, Fig. 9 The cross-sectional view of the semiconductor device at M4 shown in FIG. Figure 3 The cross-sectional schematic diagram of the semiconductor device at Q4 shown in FIG. 1 is similar to that shown in FIG. Figure 7 For the convenience of illustration, Figure 8-Figure 13 In the illustrated embodiment, only one trench gate 11 is shown.
[0098] Different from the planar source region solution adopted in the above embodiment, Figure 7-Figure 13 The trench source region structure is used in the figure. In this semiconductor device, a first surface has multiple second trenches extending along the first direction; the trench gate 11 separates the second trenches; the first source region 121 and the second source region 122 are formed in the second trench surface based on the ion implantation process.
[0099] like Figure 8 As shown, the formed second trench is relatively perpendicular to the first trench 111, and a first source region 121 and a second source region 122 of the source region 12 are formed based on the second trench. The extension direction of the source region 12 is the first direction X, and the extension direction of the trench gate 11 is the second direction Z. The extension direction of the source region 12 is relatively perpendicular to the extension direction of the trench gate 11. Therefore, the current flow direction at the bottom of the trench gate 11 and the bottom of the source region 12 is converted into a three-dimensional structure, which reduces the intensity of the electric field at the bottom of the first region, improves the maximum trench gate 11 density of the semiconductor device prepared based on this structure, and improves the performance of the semiconductor device formed based on this structure.
[0100] A metal electrode layer is also disposed on the insulating layer 15, and an opening is provided on the insulating layer 15 to expose the ohmic contact region 13, and the metal electrode layer is connected to the second source region 122 through the ohmic contact region 13, thereby realizing the connection between the source region 12 and the external circuit.
[0101] in, Figure 10-12 Cross-sectional views of the trench gate 11 at the deepest position of the first region 11a, the position between the deepest position and the shallowest position of the first region 11a, and the shallowest position are respectively given. Fig.13The dotted line in the cross-sectional view is the layout structure of the trench gate and the ion implantation region at the bottom of the trench gate.
[0102] An insulating layer 15 is provided to cover and protect the trench gate 11 and the source region 12, and the opening on the insulating layer 15 can expose a portion of the second source region 122, so that the source region 12 located on the insulating layer 15 is electrically contacted with the second source region 122 through the opening, thereby realizing the connection between the second source region 122 and the outside.
[0103] In the semiconductor device described above, the region of the second source region 122 corresponding to the opening has an ohmic contact region 13 , and the doping type of the ohmic contact region 13 is opposite to the doping type of other parts of the second source region 122 .
[0104] The ohmic contact region 13 is doped with P+ ions, while the other positions of the second source region 122 are doped with N+ ions. By performing ion doping on the opening position of the second source region 122 to form the ohmic contact region 13, the reliability and stability of the connection between the second source region 122 and the source 16 can be improved.
[0105] The present application also provides a method for preparing any of the semiconductor devices described above, referring to Figure 14-Figure 19 as well as Figure 2-Figure 3 As shown, Figure 14-Figure 19 A flow chart of a method for manufacturing a semiconductor device provided in the present application, the manufacturing method comprising:
[0106] Step S11, as Fig.14 As shown, a substrate 10 is provided, having a first surface and a second surface opposite to each other.
[0107] Step S12, as Figure 15-17 As shown, a plurality of trench gates 11 are formed in the first surface, and the trench gates 11 are arranged in sequence and spaced apart in the first direction; wherein, in the second direction, the trench gates 11 include first regions and second regions which are arranged alternately in sequence, and the depth of the first region is greater than the depth of the second region; the first direction and the second direction are both parallel to the first surface, and the two are perpendicular; the second direction is the extension direction of the trench gates 11.
[0108] Step S13, as Figure 18-Figure 19 and Figure 3 As shown, a source electrode 16 is formed on the first surface. The source electrode 16 is electrically connected to the source region 12 and is insulated from the trench gate 11 .
[0109] In step S12 of the above manufacturing method, the method of forming the trench gate 11 includes:
[0110] Step S21, as Fig.15As shown, a first trench 111 is formed in the first surface. Before forming the first trench 111, an ion implantation layer is first formed in the first surface, and then the first trench 111 is formed by etching. The remaining ion implantation layer between the first trenches 111 serves as the source region 12.
[0111] Step S22, as Fig.16 As shown, a gate dielectric layer 112 is formed on the surface of the first trench 111 .
[0112] Step S23, as Fig.17 As shown, a gate semiconductor material 113 is filled in the first trench 111 having the gate dielectric layer 112 .
[0113] refer to Figure 20-Figure 29 , Figure 20-Figure 29 A process flow chart for forming a first trench 111 is provided in an embodiment of the present application.
[0114] In step S21 of the above manufacturing method, the method of forming the first trench 111 includes:
[0115] Step S211, as Figure 20-21 As shown, the substrate is etched to form a pre-processing groove 17 .
[0116] Step S212, as Figure 22-Figure 23 As shown, a sacrificial structure 18 is filled in the pre-processing trench 17 .
[0117] Step S213, as Figure 24-25 As shown, a sacrificial layer 19 is formed on the first surface, and the sacrificial layer 19 extends along the second direction. Fig.24 yes Fig.25 The top view shown corresponds to a side view of the device.
[0118] Step S214, as Figure 26-Figure 29 As shown, the substrate 10 is etched to form a first groove 111 extending along the second direction. Figure 26-Figure 27 and Figure 28-Figure 29 The two stages of etching the substrate 10 are shown. First, the substrate 10 is etched as a whole to form Figure 26-Figure 27 The structure shown in FIG. 1 is then formed by adjusting the etching parameters so that the etching rate of the sacrificial structure 18 is lower than the etching rate of the substrate 10, and finally forming the structure shown in FIG. Fig.28 Fig.29 The structure shown in FIG. Fig.26 yes Fig. 27 The top view shown corresponds to a side view of the device; Fig.28 yes Fig.29 The top view shown corresponds to a side view of the device.
[0119] Based on the above operation steps, the first groove 111 formed is a structure with alternating depths. At the same time, due to the existence of the sacrificial structure 18, the structure of any first area formed by etching is the same, and the structure of the second area is the same, thereby ensuring the consistency of the trench gate 11 formed based on the first groove 111 at various positions, thereby improving the performance of semiconductor devices formed based on this structure.
[0120] In the manufacturing method described above, before forming the gate dielectric layer 112 in step S22, the method further includes:
[0121] At the position corresponding to the first region, ion implantation is performed on the substrate 10 based on the first trench 111 to form an ion implantation region 14, wherein the ion implantation region 14 is located on the side of the trench gate 11 facing the second surface, and the ion implantation region 14 has no overlapping region with the substrate 10 of the second region; the doping type of the ion implantation region 14 is opposite to the doping type of the substrate 10. There is no ion implantation region 14 at the position corresponding to the second region.
[0122] Among them, in the Z-axis direction, the trench gate 31 is divided into a first area and a second area, and the ion implantation area 14 only exists at the bottom of the first area, and the implantation depth from the center of the first area to the edge of the first area gradually becomes shallower. The preparation time of the ion implantation area 14 can be achieved by alternately implanting in the process of forming the first trench, or by deposition and reverse etching after the trench etching is completed. In the embodiment of the present application, the formation of the ion implantation area 14 in the process of forming the first trench 111 is taken as an example for introduction, and the present application does not limit the time for forming the ion implantation.
[0123] refer to Figure 30-Figure 33 , Figure 30-Figure 33 A process flow chart of forming an ion implantation region 14 is provided in an embodiment of the present application. Forming the ion implantation region 14 includes:
[0124] First, refer to Figure 30-Figure 31 Based on the formed grooves, ion implantation is performed on the substrate 10 to form a thicker ion implantation region 14. Fig.30 yes Fig.31 The top view shown corresponds to a side view of the device.
[0125] Then, refer to Figure 32-Figure 33 , adjusting the etching parameters so that the etching speed of the ion implantation region 14 is lower than the etching speed of the sacrificial structure 18, forming the first trench 111, and retaining part of the ion implantation region 14 on the side of the first trench 111 facing the second surface. Fig.32 yes Fig.33 The top view shown corresponds to a side view of the device.
[0126] The ion implantation region 14 is formed by the above-described method. It is necessary to form a thicker ion implantation region 14, and then change the etching selectivity so that the etching speed of the ion implantation region 14 is lower than the etching speed of the sacrificial structure 18, so that after the etching of the sacrificial structure 18 is completed, the ion implantation region 14 can still remain, and finally form the following Fig.34 The structure shown.
[0127] In the above step S13, the method of forming the source 16 includes:
[0128] Step S31, as Fig.18 As shown, an insulating layer 15 is formed to cover the first surface.
[0129] Step S32, as Fig.19 As shown, an opening is formed in the insulating layer 15 to expose the second source region 122 .
[0130] Step S33, as Figure 3 As shown, a source electrode 16 is formed on the insulating layer 15 . The source electrode 16 is in electrical contact with the second source region 122 through the opening and is isolated from the trench gate 11 by the insulating layer 15 .
[0131] In the manufacturing method described above, before forming the insulating layer 15 in step S31, the method further includes:
[0132] like Figure 2 As shown, ion implantation is performed in the area corresponding to the opening of the second source region 122 , so that the doping type of the area corresponding to the opening of the second source region 122 is opposite to that of other parts of the second source region 122 ; wherein the part of the second source region 122 implanted with ions serves as the ohmic contact area 13 .
[0133] An ohmic contact region 13 is provided to improve the stability of the electrical connection between the second source region 122 and the source electrode 16, reduce the contact resistance, and reduce the heat generation of the device.
[0134] In the embodiment of the present application, another method for forming the first groove 111 is provided. Figure 34-Figure 38 As shown, Figure 34-Figure 38 Another process flow chart for forming the first trench 111 is provided in an embodiment of the present application. The method for forming the first trench 111 includes:
[0135] Step S41, as Fig.34 As shown, a plurality of second grooves 20 extending along the first direction are formed based on the first surface.
[0136] Step S42, as Fig.35 As shown, the second trench is filled with a mask material to form a sacrificial structure 18 .
[0137] Step S43, as Fig.36As shown, the substrate 10 is processed to form a sacrificial layer 19 .
[0138] Step S44, as Figure 37-Figure 38 As shown, based on the sacrificial structure 18 and the sacrificial layer 19 , the substrate 10 is etched to form a first trench 111 , and the formed first trench 111 separates the second trench 20 .
[0139] The second groove 20 can be formed simultaneously with the pre-processed groove, or the first groove 20 can be formed first, and then the substrate 10 is etched to form the second groove 20, which is not limited in this application. When the second groove 20 is formed simultaneously with the pre-processed groove, the process steps can be reduced, thereby reducing the process cost.
[0140] In this specification, each embodiment is described in a progressive, parallel, or progressive and parallel manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the device part description.
[0141] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same reference numerals throughout the embodiments of the specification identify the same structure. In addition, for the sake of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It is also understood that when an element such as a layer, film, region, or substrate is referred to as "on" another element, the element may be directly on the other element or there may be an intermediate element. In addition, "on" refers to positioning an element on or below another element, but does not essentially refer to positioning on the upper side of another element according to the direction of gravity.
[0142] The terms "upper", "lower", "top", "bottom", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.
[0143] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.
[0144] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A semiconductor device having a periodically changing trench gate, characterized in that: include: a substrate having opposing first and second surfaces; A plurality of trench gates are arranged in the first surface, the trench gates are arranged in sequence and spaced apart in a first direction, and a source region is provided in the first surface between adjacent trench gates; A source electrode located on the first surface, the source electrode being electrically connected to the source region and insulated from the trench gate; Among them, in the second direction, the trench gate includes a first region and a second region alternately arranged in sequence, the depth of the first region is greater than the depth of the second region; the first direction and the second direction are both parallel to the first surface, and the two are perpendicular; the second direction is the extension direction of the trench gate.
2. The semiconductor device according to claim 1, wherein: In the first region, the trench gate has an ion implantation region on a side facing the second surface, and the ion implantation region has no overlapping region with the substrate of the second region; Wherein, the doping type of the ion implantation region is opposite to the doping type of the substrate.
3. The semiconductor device according to claim 2, characterized in that In the second direction, the depth of the trench gate located in the first region gradually decreases from the middle to both sides; to match the trench gate located in the first region, the implantation depth of the ion implantation region gradually decreases from the middle to both sides.
4. The semiconductor device according to claim 1, wherein: For the two trench gates adjacent to each other in the first direction, the first region of one trench gate is arranged opposite to the second region of the other trench gate.
5. The semiconductor device according to claim 1, wherein: The trench gate comprises: a first groove extending along the second direction; a gate dielectric layer covering a surface of the first trench; A gate semiconductor material fills the first trench having the gate dielectric layer.
6. The semiconductor device according to claim 1, wherein: The depth of the source region is less than the minimum depth of the trench gate.
7. The semiconductor device according to claim 6, characterized in that In the direction from the second surface to the first surface, the source region includes a first source region and a second source region arranged in sequence; The doping type of the first source region is opposite to the doping type of the second source region, and the doping type of the second source region is the same as the doping type of the substrate.
8. The semiconductor device according to claim 7, characterized in that The first surface is covered with an insulating layer, and the insulating layer has an opening exposing the second source region; The source electrode is located on the surface of the insulating layer, is in electrical contact with the second source region through the opening, and is isolated from the trench gate by the insulating layer.
9. The semiconductor device according to claim 8, characterized in that In the second direction, the first source region and the second source region both extend from one end of the target region to the other end of the target region; A portion of the substrate between two adjacent trench gates is the target area.
10. The semiconductor device according to claim 8, characterized in that: The first surface has a plurality of second grooves extending along the first direction; The trench gate separates the second trench; The first source region and the second source region are formed in a surface of the second trench based on an ion implantation process.
11. The semiconductor device according to any one of claims 8 to 10, characterized in that: The second source region has an ohmic contact region in a region corresponding to the opening, and the doping type of the ohmic contact region is opposite to the doping type of other parts of the second source region.
12. A method for manufacturing a semiconductor device according to any one of claims 1 to 11, characterized in that: include: Providing a substrate having a first surface and a second surface opposite to each other; A plurality of trench gates are formed in the first surface, the trench gates are sequentially spaced apart in a first direction, and a source region is provided in the first surface between adjacent trench gates; forming a source electrode on the first surface, wherein the source electrode is electrically connected to the source region and insulated from the trench gate; Among them, in the second direction, the trench gate includes a first region and a second region alternately arranged in sequence, the depth of the first region is greater than the depth of the second region; the first direction and the second direction are both parallel to the first surface, and the two are perpendicular; the second direction is the extension direction of the trench gate.
13. The manufacturing method according to claim 12, characterized in that: The method of forming the trench gate includes: forming a first groove in the first surface; forming a gate dielectric layer on a surface of the first trench; A gate semiconductor material is filled in the first trench having the gate dielectric layer.
14. The manufacturing method according to claim 13, characterized in that: Before forming the gate dielectric layer, the method further includes: At a position corresponding to the first region, based on the first groove, ion implantation is performed on the substrate to form an ion implantation region; The ion implantation region is located on the side of the trench gate facing the second surface, and the ion implantation region has no overlapping area with the substrate of the second region; and the doping type of the ion implantation region is opposite to the doping type of the substrate.
15. The manufacturing method according to claim 12, characterized in that: The method of forming the source region comprises: Performing ion implantation on the first surface to sequentially form a first source region in the first surface; Ion implantation is performed on the first source region to form a second source region in the first source region; wherein an implantation depth of the second source region is less than an implantation depth of the first source region.
16. The manufacturing method according to claim 15, characterized in that: The method of forming the source electrode comprises: forming an insulating layer covering the first surface; forming an opening in the insulating layer to expose the second source region; The source electrode is formed on the insulating layer. The source electrode is electrically in contact with the second source region through the opening and is isolated from the trench gate by the insulating layer.
17. The manufacturing method according to claim 16, characterized in that: Before forming the insulating layer, the method further comprises: Ion implantation is performed in the area of the second source region corresponding to the opening, so that the doping type of the area of the second source region corresponding to the opening is opposite to that of other parts of the second source region; wherein the part of the second source region implanted with ions serves as an ohmic contact area.