Semiconductor device terminal structure and preparation method thereof

Abstract

The invention discloses a semiconductor device terminal structure and a preparation method thereof, the semiconductor device terminal structure comprises a wide bandgap N-type doped substrate, an N-type doped drift region, a P-type doped buried layer and an N-type doped current diffusion layer, a main junction region is formed at one end, close to an anode, of the terminal structure, a cutting channel is formed at one end, far away from the anode, of the terminal structure, and a terminal region is formed in the middle of the terminal structure; the upper portion of the terminal area is etched into a groove terminal comprising a main groove and an auxiliary groove, the main groove spans the P-type doped main junction area and goes deep into the N-type doped current diffusion layer, the auxiliary groove is etched in the bottom face of the main groove, and the auxiliary groove comprises a middle groove and a side groove. The middle groove penetrates through the P-type doped buried layer, the bottom of the middle groove is located in the N-type doped drift region, the side grooves are located in the direction from the main junction region to the terminal region, the distance between the side grooves in the direction from the cutting channel region to the terminal region is gradually reduced, and / or the size is gradually increased; the P-type doped buried layer with gradually reduced equivalent doping concentration can be reduced, and the problem of electric field concentration near a main junction region and a cutting channel can be relieved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a semiconductor device terminal structure and a preparation method thereof. Background Art

[0002] Traditional silicon devices are limited by their own material properties, and further performance improvement is expected to rely on higher performance semiconductor materials. The third and fourth generation wide bandgap semiconductor materials represented by SiC and Ga2O3 have emerged. Wide bandgap semiconductor materials have more advantages than Si in physical properties such as bandgap width, breakdown field strength, and electron saturation drift velocity.

[0003] In the blocking state, the device mainly bears voltage through the depletion region formed by the PN junction under reverse bias. According to Poisson's equation, the peak value of the electric field strength in the depletion region is located near the PN junction. When the peak value of the electric field strength reaches the critical breakdown electric field strength of the semiconductor material, the device will be broken down.

[0004] In the actual preparation process, cylindrical junctions and spherical junctions are formed at the edges and corners of the PN junction. Under the effect of curvature, the electric field near the cylindrical junction and spherical junction is more concentrated, and the electric field strength is much greater than the electric field strength of the parallel plane junction in the middle area. The edges and corners will break down before the parallel plane junction, resulting in the breakdown voltage of the device being much lower than the ideal case. Fig.21 shown.

[0005] In order to alleviate the problem of premature breakdown of the edges and corners of the PN junction (main junction of the device) due to the curvature effect, resulting in reduced device blocking ability, the industry often adds a junction terminal structure around the PN junction (main junction). The introduced junction terminal structure can disperse the electric field originally concentrated at the edge of the main junction, thereby reducing the electric field strength at the edge of the main junction and making the device breakdown voltage closer to the ideal value of a parallel plane junction.

[0006] Commonly used junction termination structures include field plates, table tops, junction termination extensions, and field limiting rings, such as Fig. 22As shown. The principle of the field plate (FP) structure is to expand the depletion layer on the junction terminal surface by applying an external voltage on the field plate, thereby alleviating the electric field concentration phenomenon at the edge of the PN junction. The principle of the mesa (MESA) structure is to widen the depletion region width at the PN junction by etching the bevel, thereby reducing the electric field concentration phenomenon. The junction termination extension (JTE) structure expands the depletion region of the P+ main junction through its own depletion, thereby reducing the electric field concentration phenomenon at the main junction. The existence of the field limiting ring (FLR) structure is equivalent to adding a voltage divider to the edge of the main junction of a planar power device. By reasonably optimizing the amount, ring width, doping concentration and ring spacing of the FLR, the width of the main junction depletion region can be effectively widened, and the electric field concentration phenomenon of the main junction and the ring can be reduced, thereby increasing the breakdown voltage.

[0007] However, the existing junction termination technology still has some problems. Taking SiC material as an example, the main technical defects are as follows: Technical defect 1: Although the junction termination technology is relatively mature for Si materials, due to the extremely low diffusion coefficient of impurities in SiC materials, the doping of SiC materials is often done through high-temperature ion implantation to form a shallow PN junction, which results in a smaller radius of curvature of the PN junction of SiC power devices, easier concentration of the electric field, and further reduction of the device's blocking capability and the protection capability of the junction termination. In addition, with the development of device structure design capabilities, NPN epitaxial layers have emerged, but due to the limitation of injection capabilities, the existing terminals cannot well protect the main junction of NPN epitaxial layer devices.

[0008] Technical defect 2: In a high-voltage, high-temperature, and high-humidity environment, charge accumulation, moisture corrosion, ion migration, and other phenomena will occur at the terminal, and the electrode on the front of the device and the cutting path may be short-circuited. At this time, the cutting path and the back electrode, and the main junction and the back electrode need to withstand the blocking voltage of the device. The traditional terminal structure only protects the main junction, but ignores the protection of the cutting path area, resulting in increased leakage current in the cutting path area or premature breakdown in the cutting path area, and the breakdown voltage of the device is lower than the ideal value.

[0009] Technical defect 3: On the outside of the junction terminal and at the edge of the device, that is, the cutting path area of ​​the device. When the device is in the blocking state, the potential of the cutting path area is equal to the bus voltage, while the potential of the electrode in the middle of the front of the device is 0V, which means that there is a huge potential difference between the electrode and the cutting path, and air breakdown may occur between the front electrode and the cutting path, causing the device to burn out.

[0010] Technical defect 4: Existing power devices usually include a substrate, a drift layer is arranged on the substrate, a metal layer is evaporated on the drift layer, and then a passivation layer is formed on the metal layer. A steep step may be formed at the edge of the main junction or the cutting path. If the metal layer and the passivation layer cover the step position, during the reliability test, due to the mismatch of the expansion coefficients of the metal, the passivation layer and the semiconductor material, the passivation layer is likely to crack at the step position of the metal layer, resulting in reduced long-term reliability of the power device in a high temperature and high humidity environment. Summary of the invention

[0011] In view of the problem that the existing junction terminal structure is unable to well protect the main junction of the power device due to the limitations of the material thermal diffusion coefficient, ion implantation depth and the like, especially the problem that air breakdown occurs between the surface electrode and the cutting path of the NPN power device and the existing terminal structure cannot protect the cutting path area, which ultimately leads to a serious reduction in the breakdown characteristics of the device, the present invention provides a new junction terminal structure and a preparation method thereof.

[0012] The technical solution of the present invention to solve the above technical problems is as follows: A semiconductor device terminal structure, the terminal structure comprising a wide bandgap N-type doped substrate, an N-type doped drift region, a P-type doped buried layer, and an N-type doped current diffusion layer connected in sequence from bottom to top; The side of the N-type doped current diffusion layer away from the P-type doped buried layer is connected to the P-type doped main junction region and the anode in sequence from bottom to top, and the side of the N-type doped substrate away from the P-type doped buried layer is connected to the cathode, the end of the terminal structure close to the anode forms the main junction region, the end away from the anode is the cutting path, and the middle is the terminal region; Etching the upper portion of the terminal region into a trench terminal including a main trench and a sub-trench, wherein the main trench crosses the P-type doped main junction region and penetrates into the N-type doped current diffusion layer, and etching a sub-trench at the bottom of the main trench, wherein the sub-trench includes a middle trench that etched through the P-type doped buried layer and at least one side trench on both sides that did not etch through the P-type doped buried layer; The middle trench passes through the P-type doped buried layer, and the bottom is located in the N-type doped drift region. The spacing between the side trenches on both sides gradually decreases and / or the volume gradually increases in the direction from the main junction region to the terminal region and from the cutting road region to the terminal region, so that the equivalent doping concentration of the P-type doped buried layer in the direction from the main junction region to the terminal region and from the cutting road region to the terminal region shows a trend of gradually decreasing; The gradual increase in volume includes a gradual increase in the width of the side grooves, and / or a gradual increase in the depth of the side grooves, and / or a gradual increase in the thickness of the side grooves.

[0013] Based on the above technical solution, the present invention can also be improved as follows.

[0014] Furthermore, in the above-mentioned semiconductor device terminal structure, the inner side walls of the sub-trench and the main trench are connected to the first insulating dielectric layer, the space in the sub-trench and the main trench below the highest point is filled with the second insulating dielectric layer, the third insulating dielectric layer is connected above the second insulating dielectric layer, one end of the third insulating dielectric layer is connected to the anode, and the other end covers the N-type doped current diffusion layer, and the fourth insulating dielectric layer is connected above the third insulating dielectric layer.

[0015] Furthermore, the above-mentioned semiconductor device terminal structure, The first insulating dielectric layer is silicon dioxide; and / or The second insulating medium layer is PI glue; and / or The third insulating dielectric layer is silicon nitride; and / or The fourth insulating medium layer is silicon dioxide.

[0016] Furthermore, in the above-mentioned semiconductor device terminal structure, the material of the wide bandgap N-type doped substrate is SiC, GaN, Ga2O3, C or AlN.

[0017] Furthermore, in the above-mentioned semiconductor device terminal structure, the doping types of the main junction region, the terminal region, and the cutting path region are changed from N-type to P-type, and from P-type to N-type.

[0018] Furthermore, in the above-mentioned semiconductor device terminal structure, the doping element of the N-type doped drift region is nitrogen; the doping element of the P-type doped buried layer is aluminum or boron; the doping element of the N-type doped current diffusion layer is nitrogen; and the doping element of the P-type doped main junction region is aluminum or boron.

[0019] Furthermore, in the above-mentioned semiconductor device terminal structure, the side trenches on both sides are replaced with a step structure with a larger step width closer to the middle trench; or The side trenches on both sides are replaced by N-type doped charge compensation regions of the same size with decreasing spacing from the main junction region to the terminal region and from the cutting road region to the terminal region, and the doping element of the N-type doped charge compensation region is nitrogen; or The depth of the P-type doped main junction region increases to completely replace the N-type doped current diffusion layer and penetrate into the P-type doped buried layer; or Connecting a P-type doped main junction region between the N-type doped current diffusion layer and the third insulating dielectric layer in the scribe line region; or The terminal structures on the left and right sides of the middle groove are different; or The middle trench and the side trench are replaced by an inverted trapezoidal structure inclined toward the N-type doped drift region, so that both sides are inclined surfaces, the inclined surfaces extend into the N-type doped drift region, and the bottom surface of the inverted trapezoidal structure is located in the N-type doped drift region.

[0020] Furthermore, in the above-mentioned semiconductor device terminal structure, the doping element of the N-type doped charge compensation region is nitrogen.

[0021] A method for preparing a semiconductor device terminal structure as described in any one of the above, comprising the following steps: Growing an N-type doped drift region on a wide bandgap N-type doped substrate; Forming a P-type doped buried layer by ion implantation, epitaxy or growing a P-type oxide; forming an N-type doped current diffusion layer by epitaxy; Forming a P-type doped main junction region by ion implantation, epitaxy or growing a P-type oxide; forming trench terminations by dry etching and / or wet etching; forming a first insulating dielectric layer by deposition or thermal oxidation; The second insulating dielectric layer is formed by deposition or coating, exposure and development.

[0022] The above-mentioned method for preparing a semiconductor device terminal structure further includes the following steps: Etching of the first insulating dielectric layer, deposition and etching of anode metal; A third insulating dielectric layer and a fourth insulating dielectric layer are deposited, the third insulating dielectric layer and the fourth insulating dielectric layer are etched, and a cathode metal is deposited.

[0023] Compared with the prior art, the technical solution of the present invention has the following beneficial technical effects: 1. The structure is formed by etching a middle trench and a plurality of side trenches in a P-type doped main junction region, an N-type doped current diffusion layer and a P-type doped buried layer; the deepest part of the middle trench needs to exceed the P-type doped buried layer, that is, at least one trench needs to etch through the P-type doped buried layer; the trench terminal can be formed by gradually reducing the spacing between the side trenches in the direction from the main junction region to the terminal region and from the cutting road region to the terminal region, and / or gradually increasing the volume, or gradually increasing the doping concentration of the N-type doped charge compensation region that replaces the side trench, or by other forms to gradually reduce the equivalent acceptor impurity atomic mass of the P-type doped buried layer in the direction from the main junction region to the terminal region and from the cutting road region to the terminal region. The gradual increase in volume includes gradually increasing the width of the side trench, and / or gradually increasing the depth of the side trench, and / or gradually increasing the thickness of the side trench.

[0024] This structure has a P-type doped buried layer formed in the middle trench near the anode (main junction region) and at least one side trench on the left side of the terminal, with the equivalent doping concentration gradually decreasing in the direction away from the main junction region. This can reduce the curvature effect of the main junction region, alleviate the problem of electric field concentration near the main junction, and avoid the problem of premature breakdown of the main junction of the power device.

[0025] 2. In this structure, a P-type doped buried layer whose equivalent doping concentration gradually decreases in the direction away from the cutting path area is formed by the middle groove and at least one side groove near the cutting path area on the right side of the terminal area, or by an N-type doped charge compensation area that replaces the side groove and has a gradually increasing doping concentration. This can reduce the curvature effect of the electric field in the cutting path area, alleviate the problem of electric field concentration near the cutting path, and prevent the cutting path area from breaking down prematurely after the cutting path surface is short-circuited with the anode metal (the front electrode of the device).

[0026] 3. In the blocking state of the device, the P-type doped buried layer can play a role in isolating the cathode (the electrode on the back of the device) potential and leakage current.

[0027] 4. Set up multiple layers of insulating media above the grooves, including the second insulating dielectric layer. The function of this dielectric layer is to fill the grooves, reduce the height difference of the device surface, prevent the metal layer or passivation layer from cracking at the step position, and ensure the long-term reliability of the device in high temperature and high humidity environments. The material used for this dielectric layer needs to have good hole-filling ability, such as PI glue or other organic matter.

[0028] 5. The trench that crosses the P-type doped main junction region, the N-type doped current diffusion layer, and the P-type doped buried layer and extends deep into the N-type doped drift region can play the role of a (field) stop ring. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic structural diagram of a semiconductor terminal structure provided in Embodiment 1 of the present invention; Figure 2 The step of growing an N-type doped drift region on a substrate in the preparation method of embodiment 1 of the present invention; Figure 3 The preparation method of Embodiment 1 of the present invention forms a P-type doped buried layer by ion implantation, epitaxy, growing a P-type oxide, etc.; Figure 4 Forming an N-type doped current diffusion layer by epitaxy in the preparation method of Example 1 of the present invention; Figure 5 The preparation method of Embodiment 1 of the present invention forms a P-type doped main junction region by ion implantation, epitaxy, growing a P-type oxide, etc.; Figure 6 Forming a plurality of trench terminals by dry etching and / or wet etching in the preparation method of embodiment 1 of the present invention; Figure 7 The first insulating dielectric layer is formed by deposition or thermal oxidation in the preparation method of embodiment 1 of the present invention; Figure 8 The second insulating dielectric layer is formed by deposition or coating, exposure and development in the preparation method of embodiment 1 of the present invention; Fig. 9 Etching the first insulating dielectric layer, depositing and etching the anode metal in the preparation method of Example 1 of the present invention; Fig.10 A simulated structure doping concentration distribution diagram of a semiconductor terminal structure on the left side of the structure terminal close to the main junction region of the semiconductor terminal structure according to the first embodiment of the present invention; Fig.11 A structural terminal breakdown characteristic curve diagram of a semiconductor terminal structure according to Embodiment 1 of the present invention; Fig.12 for Fig.10 Potential distribution diagram on AA' tangent line; Fig.13 for Fig.10 The electric field intensity distribution diagram on the AA' tangent line; Fig.14 A schematic structural diagram of a semiconductor terminal structure provided in Embodiment 2 of the present invention; Fig.15 A schematic structural diagram of a semiconductor terminal structure provided in Embodiment 3 of the present invention; Fig.16 A schematic structural diagram of a semiconductor terminal structure provided in Embodiment 4 of the present invention; Fig.17 A schematic structural diagram of a semiconductor terminal structure provided in Embodiment 5 of the present invention; Fig.18 A schematic structural diagram of a semiconductor terminal structure provided in Embodiment 6 of the present invention; Fig.19 A schematic structural diagram of a semiconductor terminal structure provided in Embodiment 7 of the present invention; Fig. 20 A schematic structural diagram of a semiconductor terminal structure provided in Embodiment 8 of the present invention; Fig.21 It is a schematic diagram of the structure in which the curvature effect of the PN junction edge leads to electric field concentration in the background technology of the present invention; Fig. 22 Schematic diagram of the common terminal structure of the background technology of the present invention, (a) field plate; (b) table; (c) junction terminal extension; (d) field limiting ring.

[0030] In the accompanying drawings, the components represented by the reference numerals are listed as follows: 1. Main junction region, 2. Terminal region, 3. Cutting road, 4. N-type doped substrate, 5. N-type doped drift region, 6. P-type doped buried layer, 7. N-type doped current diffusion layer, 8. P-type doped main junction region, 9. Anode, 10. Cathode, 11. First insulating dielectric layer, 12. Second insulating dielectric layer, 13. Third insulating dielectric layer, 14. Fourth insulating dielectric layer, 15. Sub-trench, 151. Middle trench, 152. Side trench, 16. Step, 17. N-type doped charge compensation region, 18. Inclined surface, 19. P-type doped substrate, 20. P-type doped drift region, 21. N-type doped buried layer, 22. P-type doped current diffusion layer, 23. N-type doped main junction region. DETAILED DESCRIPTION

[0031] In order to facilitate understanding of the present application, the present application will be described more comprehensively below. The present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0033] It will be appreciated that spatial relationship terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It will be appreciated that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0034] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. The "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0035] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0036] Taking the terminal structure of a semiconductor device made of SiC material as a substrate as an example, the existing junction terminal structure is limited by the thermal diffusion coefficient of the semiconductor material, the ion implantation depth, etc., and cannot well protect the main junction of the power device, especially the main junction of the NPN epitaxial wafer structure (technical defect 1); the short circuit may occur between the surface electrode and the cutting path 3 of the power device, and the existing terminal structure cannot protect the cutting path 3 area, which ultimately leads to a serious reduction in the breakdown characteristics of the device (technical defect 2); the air breakdown is prone to occur in the cutting path 3 area (technical defect 3); when the power device is subjected to reliability testing, due to the mismatch in the expansion coefficients of the metal, the passivation layer and the semiconductor material, the passivation layer is easily cracked at the step position of the metal layer, resulting in a reduction in the long-term reliability of the power device in a high temperature and high humidity environment (technical defect 4), the present invention provides a new junction terminal structure and a preparation method thereof.

[0037] A semiconductor device terminal structure, the terminal structure comprising a wide bandgap N-type doped substrate 4, an N-type doped drift region 5, a P-type doped buried layer 6, and an N-type doped current diffusion layer 7 connected in sequence from bottom to top; The side of the N-type doped current diffusion layer 7 away from the P-type doped buried layer 6 is connected to the P-type doped main junction region 81 and the anode 9 in sequence from bottom to top, and the side of the N-type doped substrate 4 away from the P-type doped buried layer 6 is connected to the cathode 10. The end of the terminal structure close to the anode 9 forms a main junction region 1, the end away from the anode 9 is a cutting path 3, and the middle is a terminal region 2; The upper portion of the terminal region 2 is etched into a trench terminal including a main trench and a sub-trench 15, wherein the main trench crosses the P-type doped main junction region 81 and penetrates into the N-type doped current diffusion layer 7, and a sub-trench 15 is etched at the bottom of the main trench, wherein the sub-trench 15 includes a middle trench 151 that penetrates the P-type doped buried layer 6 and at least one side trench 152 on both sides that do not penetrate the P-type doped buried layer 6; The middle trench 151 passes through the P-type doped buried layer 6, and the bottom is located in the N-type doped drift region 5. The side trenches 152 on both sides gradually decrease in spacing and / or increase in volume in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting road 3 region to the terminal region 2, so that the equivalent doping concentration of the P-type doped buried layer 6 in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting road 3 region to the terminal region 2 presents a trend of gradually decreasing; The gradual increase in volume includes a gradual increase in the width of the side groove 152 , and / or a gradual increase in the depth of the side groove 152 , and / or a gradual increase in the thickness of the side groove 152 .

[0038] The structure is formed by etching multiple grooves in the P-type doped main junction region 8, the N-type doped current diffusion layer 7 and the P-type doped buried layer 6; the deepest part of the grooves needs to exceed the P-type doped buried layer 6, that is, at least one groove needs to etch through the P-type doped buried layer 6; the multiple grooves can be formed by gradually reducing the spacing between the grooves in the direction from the main junction region 1 to the terminal region 2 and from the cutting road 3 region to the terminal region 2, and / or gradually increasing the volume, or gradually increasing the doping concentration of the N-type doped charge compensation region that replaces the side grooves, or by other forms to gradually reduce the equivalent acceptor impurity atomic mass of the P-type doped buried layer 6 in the direction from the main junction region 1 to the terminal region 2 and from the cutting road 3 region to the terminal region 2. The gradual increase in volume includes a gradual increase in the width of the side grooves, and / or a gradual increase in the depth of the side grooves, and / or a gradual increase in the thickness of the side grooves.

[0039] like Figure 1 As shown, at least one side trench 152 and a middle trench 151 are formed on the left side of the trench near the anode 9 (main junction region 1), or an N-type doped charge compensation region that replaces the side trench and whose doping concentration gradually increases, and a P-type doped buried layer 6 whose equivalent doping concentration gradually decreases in the direction away from the main junction region 1 can reduce the curvature effect of the main junction region 1, alleviate the problem of electric field concentration near the main junction, and avoid the problem of premature breakdown of the main junction of the power device, so as to solve the technical defect 1 in the background technology.

[0040] The P-type doped buried layer 6 with an equivalent doping concentration gradually decreasing in the direction away from the cutting path 3 area is formed by at least one side groove 152 and the middle groove 151 on the right side of the groove near the cutting path 3 area, or by an N-type doped charge compensation area that replaces the side groove and has a gradually increasing doping concentration. It can reduce the curvature effect of the electric field in the cutting path 3 area, alleviate the problem of electric field concentration near the cutting path 3, and prevent the cutting path 3 area from breaking down prematurely after the surface of the cutting path 3 is short-circuited with the anode 9 metal (the front electrode of the device), so as to solve the technical defect 2 in the background technology.

[0041] In the blocking state of the device, the P-type doped buried layer 6 can block the cathode 10 (device back electrode) potential and leakage current, so as to solve technical defects 2 and 3 in the background technology.

[0042] In addition, a multi-layer insulating medium is arranged above the groove, including a first insulating medium layer 11, the main function of which is to isolate metal ions from affecting the electric field distribution in the semiconductor body, and the commonly used material of this layer of medium is silicon dioxide. A second insulating medium layer 12, the function of which is to fill the groove, reduce the height difference of the device surface, prevent the metal layer or the passivation layer from cracking at the step 16, and ensure the long-term reliability of the device under high temperature and high humidity environment, so as to solve the technical defect 4 in the background technology, and the material used for this layer of medium needs to have good hole filling ability, such as PI glue or other organic matter; a third insulating medium layer 13, the main function of which is to isolate water vapor, and the commonly used materials are silicon nitride; a fourth insulating medium layer 14, the main function of which is to isolate the external electric field, and the commonly used materials of this layer of medium are silicon dioxide.

[0043] Example 1 A semiconductor device terminal structure, the terminal structure comprising a wide bandgap N-type doped substrate 4, an N-type doped drift region 5, a P-type doped buried layer 6, and an N-type doped current diffusion layer 7 connected in sequence from bottom to top; The side of the N-type doped current diffusion layer 7 away from the P-type doped buried layer 6 is connected to the P-type doped main junction region 81 and the anode 9 in sequence from bottom to top, and the side of the N-type doped substrate 4 away from the P-type doped buried layer 6 is connected to the cathode 10. The end of the terminal structure close to the anode 9 forms a main junction region 1, the end away from the anode 9 is a cutting path 3, and the middle is a terminal region 2; The upper portion of the terminal region 2 is etched into a trench terminal including a main trench and a sub-trench 15, wherein the main trench crosses the P-type doped main junction region 81 and penetrates into the N-type doped current diffusion layer 7, and a sub-trench 15 is etched at the bottom of the main trench, wherein the sub-trench 15 includes a middle trench 151 that penetrates the P-type doped buried layer 6 and at least one side trench 152 on both sides that do not penetrate the P-type doped buried layer 6; The middle trench 151 passes through the P-type doped buried layer 6, and the bottom is located in the N-type doped drift region 5. The spacing between the side trenches 152 on both sides gradually decreases in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting road 3 region to the terminal region 2, and / or the volume gradually increases, or the doping concentration of the N-type doped charge compensation region replacing the side trench gradually increases, so that the equivalent doping concentration of the P-type doped buried layer 6 in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting road 3 region to the terminal region 2 presents a trend of gradually decreasing; The gradual increase in volume includes a gradual increase in the width of the side groove 152 , and / or a gradual increase in the depth of the side groove 152 , and / or a gradual increase in the thickness of the side groove 152 .

[0044] The number of the side grooves 152 on both sides is not less than one, and can be one, two, three, six, etc. The number of the side grooves 152 on both sides can be the same or different, such as more on the left side and less on the right side, or less on the left side and more on the right side, or the same number on the left side and the right side. The middle groove 151 passes through the P-type doped buried layer 6, and the bottom is located in the N-type doped drift region 5. The spacing between the side grooves 152 on both sides gradually decreases in the direction from the main junction region 1 to the terminal region 2 and from the cutting road 3 region to the terminal region 2, and / or the volume gradually increases, or the doping concentration of the N-type doped charge compensation region replacing the side groove gradually increases, so that the area consumed by etching the P-type doped buried layer 6 in the direction from the main junction region 1 to the terminal region 2 and from the cutting road 3 region to the terminal region 2 shows an increasing trend.

[0045] The cathode 10 is connected to a side of the N-type doped substrate 4 away from the P-type doped buried layer 6 , and the anode 9 is connected to a side of the P-type doped main junction region 8 away from the P-type doped buried layer 6 .

[0046] The sidewalls of the secondary groove 15 and the main groove are connected to the first insulating dielectric layer 11. The main function of this dielectric layer is to isolate metal ions from affecting the electric field distribution in the semiconductor body. The commonly used material for this dielectric layer is silicon dioxide. The space in the secondary groove 15 and the main groove below the highest point is filled with a second insulating dielectric layer 12. The function of this dielectric layer is to fill the groove, reduce the height difference of the device surface, prevent the metal layer or the passivation layer from cracking at the step 16, and ensure the long-term reliability of the device under high temperature and high humidity environments, so as to solve the technical defect 4 in the background technology. This dielectric layer is PI glue. The third insulating dielectric layer 13 is connected above the second insulating dielectric layer 12. One end of the third insulating dielectric layer 13 is connected to the anode, and the other end is covered with an N-type doped current diffusion layer. The main function of this layer is to isolate water vapor. The commonly used materials are silicon nitride. The fourth insulating dielectric layer is connected above the third insulating dielectric layer. The main function of this dielectric layer is to isolate the external electric field. The commonly used materials for this dielectric layer are silicon dioxide.

[0047] The material of the wide bandgap N-type doped substrate 4 is SiC.

[0048] The specific production process is as follows: 1) Grow an N-type doped drift region 5 on a wide bandgap semiconductor material (SiC / GaN / Ga2O3 / C / AlN, etc.) substrate, such as Figure 2 As shown; 2) Forming a P-type doped buried layer 6 by ion implantation, epitaxy, growing a P-type oxide, etc. Figure 3 As shown; 3) Forming an N-type doped current diffusion layer 7 by epitaxy, such as Figure 4 As shown; 4) Form a P-type doped main junction region 8 by ion implantation, epitaxy, growth of P-type oxide, etc. Figure 5 As shown; 5) Forming the terminal of the auxiliary trench 15 by dry etching and (or) wet etching, such as Figure 6 As shown; 6) Forming a first insulating dielectric layer 11 by deposition or thermal oxidation, such as Figure 7 As shown; 7) Forming a second insulating dielectric layer 12 by deposition or coating, exposure and development, such as Figure 8 As shown; 8) The first insulating dielectric layer 11 is etched, and the anode 9 is metal deposited and etched, such as Fig. 9 As shown; 9) depositing a third insulating dielectric layer 13 and a fourth insulating dielectric layer 14, etching the third insulating dielectric layer 13 and the fourth insulating dielectric layer 14, and depositing a back metal (cathode metal), and finally forming Figure 1 A semiconductor terminal structure is shown.

[0049] In view of technical defect 1: the present structure etches a middle trench and at least one side trench in the P-type doped main junction region 8, the N-type doped current diffusion layer 7 and the P-type doped buried layer 6; the deepest part of the middle trench needs to exceed the P-type doped buried layer 6, and the middle trench needs to etch through the P-type doped buried layer 6; the main trench and the sub-trench 15 can be achieved by gradually reducing the spacing between the side trenches in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting path 3 region to the terminal region 2, and / or gradually increasing the volume, or gradually increasing the doping concentration of the N-type doped charge compensation region that replaces the side trench, or by other forms to gradually reduce the equivalent acceptor impurity atomic mass of the P-type doped buried layer 6 in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting path 3 region to the terminal region 2.

[0050] This structure is formed by at least one groove on the left side of the terminal near the anode 9 (main junction area 1), or an N-type doped charge compensation area with a gradually increasing doping concentration instead of a side groove, and a P-type doped buried layer 6 with an equivalent doping concentration gradually decreasing in the direction away from the main junction area 1. It can reduce the curvature effect of the main junction area 1, alleviate the problem of electric field concentration near the main junction, and avoid the problem of premature breakdown of the main junction of the power device, so as to solve the technical defect 1.

[0051] In order to more intuitively demonstrate the effect of this structure, the protection effect of the left side structure of the patent terminal on the main junction is demonstrated by simulation software, such as Figure 10~Figure 13 shown.

[0052] It can be seen from the breakdown characteristic curve that the terminal structure of this patent achieves a withstand voltage of more than 1500V on 11um SiC epitaxy, and the main trench, at least one side trench 152 and the middle trench 151 play a role in dispersing the potential and electric field strength distribution, avoiding the problem of premature breakdown caused by excessive concentration of the electric field at the edge of the main junction.

[0053] Regarding technical defect 2: In this structure, the middle groove formed by at least one side groove near the cutting path 3 area on the right side of the terminal area 2, or an N-type doped charge compensation area that replaces the side groove and has a gradually increasing doping concentration, and the P-type doped buried layer 6 with an equivalent doping concentration that gradually decreases in the direction away from the cutting path 3 area can reduce the curvature effect of the cutting path 3 area, alleviate the problem of electric field concentration near the cutting path 3, and prevent the cutting path 3 area from breaking down prematurely after the surface of the cutting path 3 is short-circuited with the anode 9 metal (the front electrode of the device), so as to solve technical defect 2.

[0054] Regarding technical defect 3: in the blocking state of the device, the P-type doped buried layer 6 can play a role in isolating the cathode 10 (the back electrode of the device) potential and leakage current.

[0055] Regarding technical defect 4: a multi-layer insulating medium is arranged above the trench terminal, wherein the second insulating medium layer 12 is used to fill the trench, reduce the height difference of the device surface, prevent the metal layer or the passivation layer from cracking at the step 16, and ensure the long-term reliability of the device in a high temperature and high humidity environment. The material used for this layer of medium needs to have good hole-filling ability, such as PI glue or other organic matter.

[0056] Example 2 Example 2 is substantially the same as Example 1, except that Fig.14 As shown, unlike the groove structure on both sides of the middle groove 151 in Example 1, Example 2 replaces the side grooves 152 on both sides of Example 1 with a step structure that becomes wider as it approaches the middle step 16, thereby achieving an effect of gradually reducing the equivalent acceptor impurity atomic mass of the P-type doped buried layer 6 in the direction from the main junction area 1 to the terminal area 2 and in the direction from the cutting path 3 area to the terminal area 2, ultimately reducing the curvature effect of the main junction area 1, alleviating the problem of electric field concentration near the main junction, and avoiding the problem of premature breakdown of the main junction of the power device.

[0057] Example 3 Example 3 is substantially the same as Example 1, except that Fig.15 As shown, unlike the solution of etching the side trenches 152 in Embodiment 1, Embodiment 3 replaces the side trenches 152 on both sides of Embodiment 1 with N-type doped charge compensation regions 17 with the same width but with a smaller spacing closer to the middle trench 151, and the doping element of the N-type doped charge compensation region 17 is nitrogen; Embodiment 3 achieves the effect of gradually reducing the equivalent acceptor impurity atomic mass of the P-type doped buried layer 6 in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting path 3 region to the terminal region 2 by means of injecting N-type doped impurities, thereby ultimately reducing the curvature effect of the main junction region 1, alleviating the problem of electric field concentration near the main junction, and avoiding the problem of premature breakdown of the main junction of the power device.

[0058] Example 4 Example 4 is substantially the same as Example 1, except that Fig.16 As shown, unlike the first embodiment in which the N-type doped current diffusion layer 7 is below the P-type doped main junction region 8, the depth of the P-type doped main junction region 8 of the fourth embodiment is increased until it completely replaces the N-type doped current diffusion layer 7 and penetrates deep into the P-type doped buried layer, so that the P-type doped main junction region 8 and the P-type doped buried layer 6 are connected.

[0059] Example 5 Example 5 is substantially the same as Example 1, except that Fig.17 As shown, unlike the first embodiment in which the third insulating dielectric layer 13 is located above the N-type doped current diffusion layer 7 , the fifth embodiment adds a P-type doped main junction region 8 between the N-type doped current diffusion layer 7 and the third insulating dielectric layer 13 .

[0060] By providing a P-type doped main junction region 8 in the cutting street 3 region, the risk of breakdown in the cutting street 3 region is further reduced.

[0061] Example 6 Example 6 is substantially the same as Example 1, except that Fig.18 As shown, unlike Example 1, where the side grooves 152 on both sides have the same width but are deeper as they are closer to the middle groove 151 , Example 6 has the same depth of the side grooves 152 on both sides but is wider as it is closer to the middle groove 151 .

[0062] By gradually increasing the width of the side trench in the direction from the main junction area 1 to the terminal area 2 and in the direction from the cutting path 3 area to the terminal area 2, the area of ​​the P-type doped buried layer 6 in the direction from the main junction area 1 to the terminal area 2 and in the direction from the cutting path 3 area to the terminal area 2 shows a decreasing trend (that is, the equivalent acceptor impurity atomic mass gradually decreases in this direction).

[0063] Example 7 Example 7 is substantially the same as Example 1, except that Fig.19 As shown, unlike the groove structure on both sides of the middle groove 151 in Example 1, Example 7 replaces the middle groove 151 and the side groove 152 with an inverted trapezoidal structure inclined toward the N-type doped drift region 5, so that the two sides are inclined surfaces 18, the inclined surfaces extend into the N-type doped drift region, and the bottom surface of the inverted trapezoidal structure is located in the N-type doped drift region 5.

[0064] By adopting a gradually decreasing slope in the direction from the main junction area 1 to the terminal area 2 and in the direction from the cutting path 3 area to the terminal area 2, the equivalent acceptor impurity atomic mass of the P-type doped buried layer 6 in the direction from the main junction area 1 to the terminal area 2 and in the direction from the cutting path 3 area to the terminal area 2 is gradually reduced.

[0065] Example 8 Example 8 is substantially the same as Example 1, except that Fig. 20 As shown, the semiconductor material in Example 1 is subjected to opposite type of doping, such as changing N-type doping to P-type doping, and P-type doping to N-type doping. The same is applicable and is within the scope of protection of this patent application. Specifically, the wide bandgap N-type doped substrate 4 is changed to a wide bandgap P-type doped substrate 19, the N-type doped drift region 5 is changed to a P-type doped drift region 20, the P-type doped buried layer 6 is changed to an N-type doped buried layer 21, the N-type doped current diffusion layer 7 is changed to a P-type doped current diffusion layer 22, and the P-type doped main junction region 8 is changed to an N-type doped main junction region 231.

[0066] Example 9 Embodiment 9 is basically the same as Embodiment 1, except that the terminal structures on the left and right sides of the middle trench 151 are different, that is, the terminal protection structure for the main junction region 1 and the terminal protection structure for the cutting street 3 can be freely combined.

[0067] Example 10 The semiconductor material used in the present invention takes SiC as an example, and the semiconductor material in the present invention can also be replaced by other semiconductor materials, such as Si, GaN, Ga2O3, AlN, diamond (C), etc.

[0068] The present invention has the following advantages: 1. The structure is formed by etching a middle trench and a plurality of side trenches in a P-type doped main junction region, an N-type doped current diffusion layer and a P-type doped buried layer; the deepest part of the middle trench needs to exceed the P-type doped buried layer, that is, at least one trench needs to etch through the P-type doped buried layer; the trench terminal can be formed by gradually reducing the spacing between the side trenches in the direction from the main junction region to the terminal region and from the cutting road region to the terminal region, and / or gradually increasing the volume, or gradually increasing the doping concentration of the N-type doped charge compensation region that replaces the side trench, or by other forms to gradually reduce the equivalent acceptor impurity atomic mass of the P-type doped buried layer in the direction from the main junction region to the terminal region and from the cutting road region to the terminal region. The gradual increase in volume includes gradually increasing the width of the side trench, and / or gradually increasing the depth of the side trench, and / or gradually increasing the thickness of the side trench.

[0069] This structure has a P-type doped buried layer formed in the middle trench near the anode (main junction region) and at least one side trench on the left side of the terminal, with the equivalent doping concentration gradually decreasing in the direction away from the main junction region. This can reduce the curvature effect of the main junction region, alleviate the problem of electric field concentration near the main junction, and avoid the problem of premature breakdown of the main junction of the power device.

[0070] 2. In this structure, a P-type doped buried layer whose equivalent doping concentration gradually decreases in the direction away from the cutting path area is formed by the middle groove and at least one side groove near the cutting path area on the right side of the terminal area, or by an N-type doped charge compensation area that replaces the side groove and has a gradually increasing doping concentration. This can reduce the curvature effect of the electric field in the cutting path area, alleviate the problem of electric field concentration near the cutting path, and prevent the cutting path area from breaking down prematurely after the cutting path surface is short-circuited with the anode metal (the front electrode of the device).

[0071] 3. In the blocking state of the device, the P-type doped buried layer can play a role in isolating the cathode (the electrode on the back of the device) potential and leakage current.

[0072] 4. Set up multiple layers of insulating media above the grooves, including the second insulating dielectric layer. The function of this dielectric layer is to fill the grooves, reduce the height difference of the device surface, prevent the metal layer or passivation layer from cracking at the step position, and ensure the long-term reliability of the device in high temperature and high humidity environments. The material used for this dielectric layer needs to have good hole-filling ability, such as PI glue or other organic matter.

[0073] 5. The trench that crosses the P-type doped main junction region, the N-type doped current diffusion layer, and the P-type doped buried layer and extends deep into the N-type doped drift region can play the role of a (field) stop ring.

[0074] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device terminal structure, characterized in that: The terminal structure includes a wide bandgap N-type doped substrate, an N-type doped drift region, a P-type doped buried layer, and an N-type doped current diffusion layer connected in sequence from bottom to top; The side of the N-type doped current diffusion layer away from the P-type doped buried layer is connected to the P-type doped main junction region and the anode in sequence from bottom to top, and the side of the N-type doped substrate away from the P-type doped buried layer is connected to the cathode, the end of the terminal structure close to the anode forms the main junction region, the end away from the anode is the cutting path, and the middle is the terminal region; Etching the upper portion of the terminal region into a trench terminal including a main trench and a sub-trench, wherein the main trench crosses the P-type doped main junction region and penetrates into the N-type doped current diffusion layer, and etching a sub-trench at the bottom of the main trench, wherein the sub-trench includes a middle trench that etched through the P-type doped buried layer and at least one side trench on both sides that did not etch through the P-type doped buried layer; The middle trench passes through the P-type doped buried layer, and the bottom is located in the N-type doped drift region. The spacing between the side trenches on both sides gradually decreases and / or the volume gradually increases in the direction from the main junction region to the terminal region and from the cutting road region to the terminal region, so that the equivalent doping concentration of the P-type doped buried layer in the direction from the main junction region to the terminal region and from the cutting road region to the terminal region shows a trend of gradually decreasing; The gradual increase in volume includes a gradual increase in the width of the side grooves, and / or a gradual increase in the depth of the side grooves, and / or a gradual increase in the thickness of the side grooves.

2. A semiconductor device terminal structure according to claim 1, characterized in that: The inner side walls of the auxiliary trench and the main trench are connected to the first insulating dielectric layer, the space in the auxiliary trench and the main trench below the highest point is filled with the second insulating dielectric layer, the third insulating dielectric layer is connected above the second insulating dielectric layer, one end of the third insulating dielectric layer is connected to the anode, and the other end covers the N-type doped current diffusion layer, and the fourth insulating dielectric layer is connected above the third insulating dielectric layer.

3. A semiconductor device terminal structure according to claim 2, characterized in that: The first insulating dielectric layer is silicon dioxide; and / or The second insulating medium layer is PI glue; and / or The third insulating dielectric layer is silicon nitride; and / or The fourth insulating medium layer is silicon dioxide.

4. A semiconductor device terminal structure according to claim 1, characterized in that: The material of the wide bandgap N-type doped substrate is SiC, GaN, Ga2O3, C or AlN.

5. A semiconductor device terminal structure according to claim 1, characterized in that: The doping types of the main junction region, the terminal region, and the cutting path region are changed from N-type to P-type, and changed from P-type to N-type.

6. A semiconductor device terminal structure according to claim 1, characterized in that: The doping element of the N-type doped drift region is nitrogen; the doping element of the P-type doped buried layer is aluminum or boron; the doping element of the N-type doped current diffusion layer is nitrogen; and the doping element of the P-type doped main junction region is aluminum or boron.

7. A semiconductor device terminal structure according to claim 1, characterized in that: The side grooves on both sides are replaced with a step structure with a larger step width as it approaches the middle groove; or The side trenches on both sides are replaced by N-type doped charge compensation regions of the same size with decreasing spacing from the main junction region to the terminal region and from the cutting road region to the terminal region, and the doping element of the N-type doped charge compensation region is nitrogen; or The depth of the P-type doped main junction region increases to completely replace the N-type doped current diffusion layer and penetrate into the P-type doped buried layer; or Connecting a P-type doped main junction region between the N-type doped current diffusion layer and the third insulating dielectric layer in the cutting street region; or The terminal structures on the left and right sides of the middle groove are different; or The middle trench and the side trench are replaced by an inverted trapezoidal structure inclined toward the N-type doped drift region, so that both sides are inclined surfaces, the inclined surfaces extend into the N-type doped drift region, and the bottom surface of the inverted trapezoidal structure is located in the N-type doped drift region.

8. A method for preparing a semiconductor device terminal structure according to any one of claims 1 to 7, characterized in that: The following steps are involved: Growing an N-type doped drift region on a wide bandgap N-type doped substrate; Forming a P-type doped buried layer by ion implantation, epitaxy or growing a P-type oxide; forming an N-type doped current diffusion layer by epitaxy; Forming a P-type doped main junction region by ion implantation, epitaxy or growing a P-type oxide; forming trench terminations by dry etching and / or wet etching; forming a first insulating dielectric layer by deposition or thermal oxidation; The second insulating dielectric layer is formed by deposition or coating, exposure and development.

9. The method for preparing a semiconductor device terminal structure according to claim 8, characterized in that: The following steps are also included: Etching of the first insulating dielectric layer, deposition and etching of anode metal; A third insulating dielectric layer and a fourth insulating dielectric layer are deposited, the third insulating dielectric layer and the fourth insulating dielectric layer are etched, and a cathode metal is deposited.

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