Etching method

Abstract

The invention discloses an etching method applied to a manufacturing process of a metal gate device, and the method comprises the steps: providing a substrate, enabling a region used for forming a semiconductor device on the substrate to comprise a first region and a second region which are adjacent to each other, enabling the first region to be used for forming an N-type MOS device, enabling a P-type MOS device to be formed on the substrate in the second region, the P-type MOS device comprises a metal gate and work function layers located on the peripheral side and the bottom of the metal gate, a polycrystalline silicon pseudo gate is formed on the substrate in the first region, an oxide mask layer is formed on the substrate, and the oxide mask layer covers the first region and the second region; a BARC layer and a light resistor are formed on the oxide layer in sequence, the BARC layer and the light resistor in a target area are removed through exposure and development in sequence, and the target area comprises the first area and does not comprise the second area; etching is carried out, the pseudo gate is removed, a groove is formed in the first region, and the groove is used for forming a work function layer and a metal gate of the N-type MOS device; and carrying out cleaning treatment.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices and integrated circuits, and in particular to an etching method used in the manufacturing process of metal gate devices. Background Art

[0002] In the semiconductor integrated circuit manufacturing industry, compared with polysilicon gate (poly gate), metal gate (MG) has a lower resistivity, which can improve carrier mobility and threshold voltage (V T )'s regulatory capabilities have been widely used.

[0003] In the related art, a wafer integrated with a P (positive) type metal-oxide-semiconductor field-effect transistor (MOSFET, hereinafter referred to as "MOS") device and an N (negative) type MOS device can be formed into a P-type MOS device and an N-type MOS device in sequence through a separate manufacturing (N / P split) process for independent regulation, thereby improving the performance of the device. Figures 1 to 4 , which shows a schematic diagram of etching the polysilicon pseudo gate of an N-type MOS device in a separate manufacturing process, and the manufacturing process is as follows:

[0004] refer to Figure 1 , which shows a cross-sectional schematic diagram of covering the substrate with photoresist and exposing the area where the N-type MOS device is located, for example, Figure 1 As shown, the first region 101 on the substrate 110 is used to form an N-type MOS device, and a P-type MOS device is formed in the second region 102. The P-type MOS device includes a metal gate 141 and a work function layer located on the side and bottom of the metal gate 141 (which includes a tantalum nitride (TaN) layer 121, a titanium nitride (TiN) layer 122, a tantalum nitride layer 123 and a titanium nitride layer 124 from the inside to the outside), a polysilicon pseudo gate 132 is formed in the first region 101, and a sidewall (which includes an etch stop layer 151 and an oxide layer 152 covered by the etch stop layer 151) is formed on the side of the first region 101 and the second region 102. A nitride layer 161 and an oxide layer 162 are formed on the P-type MOS device and the polysilicon pseudo gate 142, and a bottom anti-reflective (bottom anti-reflective) layer is formed on the oxide layer 162 in sequence. After exposure and development in sequence, the BARC layer 163 and the photoresist 301 in the target area are removed.

[0005] refer to Figure 2, which shows a cross-sectional schematic diagram of the oxide layer 162 of the target area after etching; Figure 3 , which shows a cross-sectional schematic diagram of removing the photoresist 301 and the BARC layer 163; refer to Figure 4 , which shows a cross-sectional schematic diagram of the polysilicon pseudo gate 142 of the second region 102 after etching. Figures 2 to 4 As shown, due to the etching process of the pseudo gate 142, an etching corner ( Figure 4 In the process of cleaning after etching, the cleaning solution will enter the P-type MOS device through the weak point of the chamfered position to corrode its metal gate 141, causing defects, thereby reducing the reliability and yield of the product. Summary of the invention

[0006] The present application provides an etching method applied to the manufacturing process of a metal gate device, which can solve the problem that the pseudo gate etching method of an N-type MOS device provided in the related art easily causes surface defects of the metal gate of a P-type MOS device. The method comprises:

[0007] A substrate is provided, wherein a region on the substrate for forming a semiconductor device comprises a first region and a second region adjacent to each other, the first region is used to form an N-type MOS device, a P-type MOS device is formed on the substrate of the second region, the P-type MOS device comprises a metal gate and a work function layer located around and at the bottom of the metal gate, a polysilicon dummy gate is formed on the substrate of the first region, an oxide mask layer is formed on the substrate, the oxide mask layer covers the first region and the second region, and the thickness of the oxide mask layer is greater than 60 angstroms;

[0008] forming a BARC layer and a photoresist on the oxide layer in sequence, and removing the BARC layer and the photoresist in a target area by exposure and development in sequence, wherein the target area includes the first area and does not include the second area;

[0009] Performing etching to remove the dummy gate and forming a trench in the first region, wherein the trench is used to form a work function layer and a metal gate of an N-type MOS device;

[0010] Carry out cleaning treatment.

[0011] In some embodiments, the agent used in the cleaning process includes ammonia.

[0012] In some embodiments, the metal gate includes metal aluminum.

[0013] In some embodiments, the etching comprises:

[0014] Performing a first etching to remove the oxide mask layer in the target area;

[0015] Removing the remaining BARC layer and photoresist;

[0016] A second etching is performed to remove the polysilicon dummy gate.

[0017] In some embodiments, the work function layer includes, from inside to outside, a tantalum nitride layer, a titanium nitride layer, a tantalum nitride layer, and a titanium nitride layer.

[0018] In some embodiments, sidewall spacers are formed on the substrate around the first region and the second region.

[0019] In some embodiments, the sidewall spacer includes an etch stop layer and an oxide layer covered by the etch stop layer.

[0020] In some embodiments, the etch stop layer includes a nitride layer.

[0021] The technical solution of this application has at least the following advantages:

[0022] In the process of manufacturing metal gate devices, after forming a P-type MOS device, a thicker (thickness greater than 60 angstroms) oxide mask layer is formed on the substrate, and then the oxide mask layer and the polysilicon pseudo gate of the N-type MOS region are etched and removed in sequence through a photolithography process, thereby solving the problem in the related art that when a nitride layer and an oxide layer are formed as a mask layer, chamfers are easily formed at the boundary between the P-type MOS region and the N-type MOS region, and then the nitride layer at the boundary is corroded, causing ammonia water in the cleaning process to cause metal gate defects, thereby improving the reliability and yield of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figures 1 to 4 It is a schematic diagram of etching the polysilicon pseudo gate of an N-type MOS device in a separate manufacturing process;

[0025] Figure 5 It is a flow chart of an etching method applied to a manufacturing process of a metal gate device provided by an exemplary embodiment of the present application;

[0026] Figures 6 to 9 It is a schematic diagram of an etching process of a polysilicon dummy gate applied to a manufacturing process of a metal gate device provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0027] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0028] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0029] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0030] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0031] refer to Figure 5 , which shows a flow chart of an etching method applied to a manufacturing process of a metal gate device provided by an exemplary embodiment of the present application, such as Figure 5 As shown, the method includes:

[0032] Step S1, providing a substrate, wherein an area on the substrate for forming a semiconductor device includes a first area and a second area adjacent to each other, the first area is used to form an N-type MOS device, a P-type MOS device is formed on the substrate of the second area, the P-type MOS device includes a metal gate and a work function layer located around and at the bottom of the metal gate, a polysilicon dummy gate is formed on the substrate of the first area, an oxide mask layer is formed on the substrate, the oxide mask layer covers the first area and the second area, and the thickness of the oxide mask layer is greater than 60 angstroms.

[0033] Step S2, forming a BARC layer and a photoresist on the oxide layer in sequence, and removing the BARC layer and the photoresist in the target area by exposure and development in sequence, wherein the target area includes the first area and does not include the second area.

[0034] refer to Figure 6 , which shows a cross-sectional schematic diagram after exposure and development. Figure 6 As shown, the area on the substrate 210 for forming a semiconductor device includes an adjacent first area 201 and a second area 202, the first area 201 is used to form an N-type MOS device, a P-type MOS device is formed on the substrate 210 of the second area 202, the P-type MOS device includes a metal gate 241 and a work function layer located around and at the bottom of the metal gate 241, a polysilicon dummy gate 232 is formed on the substrate 210 of the first area 201, an oxide mask layer 261 (for example, it may include a silicon dioxide (SiO2) layer) is formed on the substrate 210, and the oxide mask layer 261 covers the first area 201 and the second area 202.

[0035] The metal gate 232 includes metal aluminum, the work function layer includes a tantalum nitride layer 221, a titanium nitride layer 222, a tantalum nitride layer 223 and a titanium nitride layer 224 from the inside to the outside, and the oxide mask layer 261 is greater than 60 angstroms. A sidewall is formed on the substrate around the first region 201 and the second region 202. The sidewall includes an etch stop layer 251 and an oxide layer 252 covered thereon. The etch stop layer 251 includes a nitride layer (e.g., a silicon nitride (Si3N4) layer). A BARC layer 262 and a photoresist 302 may be coated on the oxide mask layer 261 in sequence, and the BARC layer 262 and the photoresist 302 in the target region may be removed in sequence by exposure and development.

[0036] Step S3, performing etching to remove the dummy gate and forming a trench in the first region, wherein the trench is used to form a work function layer and a metal gate of the N-type MOS device.

[0037] Exemplarily, step S3 includes but is not limited to: performing a first etching to remove the oxide mask layer 261 in the target area; removing the remaining BARC layer 262 and the photoresist 302 ; and performing a second etching to remove the polysilicon dummy gate 232 .

[0038] refer to Figure 7 , which shows a cross-sectional schematic diagram after the first etching, such as Figure 7 As shown, after the first etching, the oxide mask layer 261 of the target area is removed; Figure 8 , which shows a cross-sectional schematic diagram after removing the remaining BARC layer 262 and the photoresist 302; Fig. 9 , which shows a cross-sectional schematic diagram after the second etching, such as Fig. 9 As shown, by forming a thicker (thickness greater than 60 angstroms) oxide mask layer 261 to replace the hard mask layer of the nitride layer and the oxide layer, the risk of the mask layer of the nitride layer being easily corroded to form chamfers and thus produce weak areas is avoided.

[0039] Step S4, performing cleaning process.

[0040] Exemplarily, the chemical used in the cleaning process includes ammonia.

[0041] In summary, in the embodiments of the present application, during the manufacturing process of the metal gate device, after the P-type MOS device is formed, a thicker (thickness greater than 60 angstroms) oxide mask layer is formed on the substrate, and then the oxide mask layer and the polysilicon pseudo-gate of the N-type MOS region are sequentially etched and removed through a photolithography process, thereby solving the problem in the related art that the formation of a nitride layer and an oxide layer as a mask layer easily forms chamfers at the boundaries of the P-type MOS region and the N-type MOS region, and then corrodes the nitride layer at the boundary, causing ammonia water in the cleaning process to cause metal gate defects, thereby improving the reliability and yield of the device.

[0042] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. An etching method, characterized in that: The method is applied to a manufacturing process of a metal gate device, and the method comprises: A substrate is provided, wherein a region on the substrate for forming a semiconductor device comprises a first region and a second region adjacent to each other, the first region is used to form an N-type MOS device, a P-type MOS device is formed on the substrate of the second region, the P-type MOS device comprises a metal gate and a work function layer located around and at the bottom of the metal gate, a polysilicon dummy gate is formed on the substrate of the first region, an oxide mask layer is formed on the substrate, the oxide mask layer covers the first region and the second region, and the thickness of the oxide mask layer is greater than 60 angstroms; forming a BARC layer and a photoresist on the oxide layer in sequence, and removing the BARC layer and the photoresist in a target area by exposure and development in sequence, wherein the target area includes the first area and does not include the second area; Performing etching to remove the dummy gate and forming a trench in the first region, wherein the trench is used to form a work function layer and a metal gate of an N-type MOS device; Carry out cleaning treatment.

2. The method according to claim 1, characterized in that Chemicals used in the cleaning process include ammonia water.

3. The method according to claim 2, characterized in that The metal gate includes metal aluminum.

4. The method according to any one of claims 1 to 3, characterized in that: The etching comprises: Performing a first etching to remove the oxide mask layer in the target area; Removing the remaining BARC layer and photoresist; A second etching is performed to remove the polysilicon dummy gate.

5. The method according to claim 4, characterized in that The work function layer includes, from the inside to the outside, a tantalum nitride layer, a titanium nitride layer, a tantalum nitride layer and a titanium nitride layer.

6. The method according to claim 5, characterized in that Sidewall spacers are formed on the substrate around the first region and the second region.

7. The method according to claim 6, characterized in that The sidewall spacer includes an etch stop layer and an oxide layer covered by the etch stop layer.

8. The method according to claim 7, characterized in that The etch stop layer includes a nitride layer.

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