Back contact solar cell and preparation method thereof, photovoltaic module and photovoltaic system

Abstract

The embodiment of the invention provides a back contact solar cell, a preparation method thereof, a photovoltaic module and a photovoltaic system. The method comprises the steps that (1) a tunneling layer, an intrinsic amorphous silicon layer and a buffer layer are sequentially deposited on the surface of one side of a substrate, the buffer layer comprises at least one of SiNx and SiOy, the buffer layer is provided with a first preset area, a second preset area and an insulation area, the first preset area and the second preset area are distributed in a finger shape, and the insulation area is arranged between the first preset area and the second preset area; the insulating region is arranged between the first predetermined region and the second predetermined region; and (2) penetrating through the first predetermined region or the second predetermined region of the buffer layer by adopting an ion implantation mode so as to carry out doping treatment on the intrinsic amorphous silicon layer, and carrying out annealing treatment on a product obtained by the doping treatment so as to obtain the doped region. Therefore, the manufacturing yield and the photoelectric property of the back contact solar cell can be greatly improved, and the process circuit can be stabilized.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a back-contact solar cell and a preparation method thereof, a photovoltaic module, and a photovoltaic system. Background Art

[0002] At present, the preparation process of back-contact solar cells is basically: alkali polishing, deposition of the first tunnel oxide layer and the first polysilicon layer on the back, boron diffusion (boron doping to form a mask borosilicate glass-BSG layer), first grooving and cleaning, deposition of the second tunnel oxide layer and the second polysilicon layer on the back, phosphorus doping (forming a mask phosphorus silicon glass-PSG layer), second grooving, cleaning and simultaneous double-sided texturing, and deposition of AlO on the back. x SiN is deposited on the back and front sides of the x Anti-reflection film, screen printing, sintering and test sorting.

[0003] However, the polysilicon doping layer formed by thermal diffusion cannot accurately control the doping concentration, doping depth and doping uniformity; secondly, the BSG and PSG formed by thermal diffusion act as masks to become the process window for wet adjustment, but the uneven thickness and overall thinness of BSG and PSG limit the adjustment window of the wet method. In addition, the current process route easily causes the interconnection of the back doping area, causing the battery to short-circuit and affect the photoelectric conversion efficiency of the solar cell.

[0004] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of patent protection of this application. Summary of the invention

[0005] The embodiments of the present application provide a back-contact solar cell and a method for preparing the same, a photovoltaic module, and a photovoltaic system to solve or alleviate at least one of the above problems.

[0006] In a first aspect of an embodiment of the present application, a method for preparing a back-contact solar cell is provided, the method comprising: (1) depositing a tunneling layer, an intrinsic amorphous silicon layer and a buffer layer in sequence on a surface of one side of a substrate, the buffer layer comprising SiN x 、SiO y At least one of the above, the buffer layer has a first predetermined area, a second predetermined area and an insulating area, the first predetermined area and the second predetermined area are distributed in a finger shape, and the insulating area is between the first predetermined area and the second predetermined area; (2) ion implantation is performed through the first predetermined area or the second predetermined area to perform a doping treatment on the intrinsic amorphous silicon layer, and a product obtained by the doping treatment is annealed to obtain the doped area.

[0007] The method of the embodiment of the present application is simple to operate. The doped region is obtained by depositing a buffer layer, then using ion implantation to penetrate the buffer layer and annealing oxidation. The ion implantation is carried out through the buffer layer, so that the doping concentration, doping depth, doping width, and doping uniformity can be accurately controlled, and the doped regions will not be connected; the buffer layer can also be provided to greatly reduce the lattice damage to the intrinsic amorphous silicon layer and / or the polycrystalline silicon layer during ion implantation. At the same time, the method of the embodiment of the present application can also avoid the generation of borosilicate glass layers and phosphorus silicon glass layers in the process of forming the doped region, thereby simplifying the process of forming the doped region, thereby greatly improving the manufacturing yield and stable process line of the back-contact solar cell, and obtaining a back-contact solar cell with a higher photoelectric conversion efficiency.

[0008] According to an embodiment of the present application, step (2) is implemented in the following manner: the intrinsic amorphous silicon layer is subjected to boron doping treatment by ion implantation through the first predetermined area, and the product obtained by the boron doping treatment is annealed to obtain a boron-doped polycrystalline silicon layer; the polycrystalline silicon layer is subjected to phosphorus doping treatment by ion implantation through the second predetermined area of ​​the product obtained by the annealing treatment, and the product obtained by the phosphorus doping treatment is annealed to obtain a phosphorus-doped polycrystalline silicon layer.

[0009] According to an embodiment of the present application, step (2) is implemented in the following manner: ion implantation is performed through the first predetermined area to perform boron doping treatment on the intrinsic amorphous silicon layer, and then ion implantation is performed through the second predetermined area to perform phosphorus doping treatment on the intrinsic amorphous silicon layer; and products obtained by the boron doping treatment and the phosphorus doping treatment are annealed to obtain a boron-doped polysilicon layer and a phosphorus-doped polysilicon layer.

[0010] According to an embodiment of the present application, the ion implantation energy is 5-60kev.

[0011] According to an embodiment of the present application, the ion implantation dose is 1×e 15 ~6×e 15 cm -2 .

[0012] According to an embodiment of the present application, the annealing temperature is 700-1000°C.

[0013] According to the embodiments of the present application, the time is 10 to 60 minutes.

[0014] According to an embodiment of the present application, the method further includes: performing a removal process on the polysilicon layer in the insulating region to form a gap between the doped regions; performing a buffer layer removal process on the product obtained after the removal process. Thus, the polysilicon layer and the buffer layer are removed from the non-first predetermined region and the second predetermined region to form a gap between the doped regions. In this way, the doped regions are discontinuous and will not cause leakage or short circuit of the back contact solar cell. The method can also avoid the generation of borosilicate glass layer and phosphosilicate glass layer, simplifying the process of forming the back contact solar cell. According to an embodiment of the present application, the method of removing the buffer layer includes etching the buffer layer.

[0015] According to an embodiment of the present application, the method of removing the polysilicon layer in the insulating region includes laser ablation.

[0016] The second aspect of the embodiment of the present application provides a back-contact solar cell prepared by the method of the first aspect. The doping region of the solar cell is obtained by depositing a buffer layer, then using ion implantation to penetrate the buffer layer and annealing oxidation to obtain the doping region, so that the doping region has a uniform doping depth and doping concentration, and the doping regions are not connected, and the lattice damage to the intrinsic amorphous silicon layer during ion implantation can be greatly reduced, so that the back-contact solar cell has better photoelectric performance.

[0017] In a third aspect of the embodiments of the present application, a photovoltaic module is provided, wherein the photovoltaic module comprises a plurality of solar cells connected in series and / or in parallel; wherein at least one solar cell is a solar cell according to the second aspect of the present invention. A plurality of solar cells in series form a cell string, and adjacent heterojunction solar cells can be connected together by series welding.

[0018] In a fourth aspect of the embodiment of the present application, a photovoltaic system is provided, comprising the photovoltaic assembly of the third aspect of the present application. The photovoltaic system also has the advantages of the above photovoltaic assembly, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments according to the present application and should not be regarded as limiting the scope of the present application.

[0020] Figure 1 It is a schematic diagram of the structure of a back-contact solar cell according to some embodiments of the present application.

[0021] Description of reference numerals: 1: N-type substrate; 2: tunneling oxide layer; 3: boron-doped polysilicon layer; 4: phosphorus-doped polysilicon layer; 5: passivation layer; 6: anti-reflection layer; 7: electrode. DETAILED DESCRIPTION

[0022] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings. In the accompanying drawings, for clarity, the sizes of layers and regions and their relative sizes may be exaggerated. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limitations on the present application. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0023] It should be understood that when a layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another layer, it may be directly on, adjacent to, connected to, or coupled to the other layer, or there may be intervening layers. It should be understood that although the terms first, second, third, etc. may be used to describe various regions, layers, and / or portions, these regions, layers, and / or portions should not be limited by these terms. These terms are merely used to distinguish one region, layer, or portion from another region, layer, or portion. Therefore, without departing from the teachings of the present application, the first region, layer, or portion discussed below may be represented as the second region, layer, or portion. When the second region, layer, or portion is discussed, it does not mean that the first region, layer, or portion necessarily exists in the present application.

[0024] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0025] In the present application, when it comes to a numerical interval (i.e., a numerical range), unless otherwise specified, the distribution of the optional numerical values ​​in the numerical interval is considered to be continuous, and includes the two numerical endpoints (i.e., the minimum and maximum values) of the numerical interval, and each numerical value between the two numerical endpoints. Unless otherwise specified, when the numerical interval only refers to an integer in the numerical interval, it includes the two endpoint integers of the numerical range, and each integer between the two endpoints, which is equivalent to directly listing each integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be merged. In other words, unless otherwise specified, the numerical ranges disclosed in the present application should be understood to include any and all sub-ranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, a percentage, a ratio, etc. "Numerical interval" allows for broadly including quantitative intervals such as percentage intervals, ratio intervals, and ratio intervals.

[0026] In a first aspect of an embodiment of the present application, a method for preparing a back-contact solar cell is provided, the method comprising: (1) depositing a tunneling layer, an intrinsic amorphous silicon layer and a buffer layer in sequence on a surface of one side of a substrate, the buffer layer comprising SiN x 、SiO y At least one of the above, the buffer layer has a first predetermined area, a second predetermined area and an insulating area, the first predetermined area and the second predetermined area are distributed in a finger shape, and the insulating area is between the first predetermined area and the second predetermined area; (2) ion implantation is performed through the first predetermined area or the second predetermined area to perform doping treatment on the intrinsic amorphous silicon layer, and the doping treatment product is annealed to obtain the doping area.

[0027] The method of the embodiment of the present application is simple to operate. The buffer layer is deposited, and then the doped area is obtained by ion implantation through the buffer layer and annealing oxidation. The ion implantation is carried out through the buffer layer, so that the doping concentration, doping depth, doping width, and doping uniformity can be accurately controlled, and the doped areas will not be connected; it can also greatly reduce the lattice damage to the intrinsic amorphous silicon layer and / or polycrystalline silicon layer during ion implantation. At the same time, the method of the embodiment of the present application can also avoid the generation of borosilicate glass layer and phosphorus silicon glass layer in the process of forming the doped area, thereby simplifying the process of forming the doped area, thereby greatly improving the manufacturing yield and stable process line of the back-contact solar cell, and obtaining a back-contact solar cell with higher photoelectric conversion efficiency.

[0028] The ion implantation method can precisely control the depth and concentration distribution of ions in the material, thereby achieving the regulation and customization of material properties, that is, the doping concentration, doping depth, doping width and doping uniformity of the precise doping area. At the same time, the setting of the buffer layer avoids the lattice distortion and damage to the crystalline silicon of the intrinsic amorphous silicon layer caused by the direct injection of doping ions into the doping layer. That is, through the setting of ion implantation and the buffer layer, the intrinsic amorphous silicon is doped to form a doping area, and the doping concentration, doping depth, doping width and doping uniformity are precisely controlled, and the doping areas will not be connected. It can also greatly reduce the lattice damage to the intrinsic amorphous silicon layer during ion implantation, thereby simplifying the process route and improving the manufacturing yield while improving the efficiency of forming the doping area.

[0029] It is understandable that, in the ion implantation method, not all ions will pass through the first region and the second region, and some doping atoms may remain in the buffer layer, and these doping atoms will be transferred to the doping region during the annealing process.

[0030] According to an embodiment of the present application, in step (1), a tunneling layer, an intrinsic amorphous silicon layer and a buffer layer are sequentially deposited on a surface of one side of the substrate, wherein the buffer layer comprises SiN x 、SiO y At least one of the above, the buffer layer has a first predetermined area, a second predetermined area and an insulating area, the first predetermined area and the second predetermined area are distributed in a finger shape, and the insulating area is between the first predetermined area and the second predetermined area.

[0031] It can be understood that, since the tunneling layer, the intrinsic amorphous silicon layer and the buffer layer are sequentially deposited on the surface of the substrate, when the buffer layer has a first predetermined area, a second predetermined area and an insulating area, the first predetermined area and the second predetermined area are distributed in a finger shape, and there is an insulating area between the first predetermined area and the second predetermined area, the corresponding intrinsic amorphous silicon layer also has a first predetermined area, a second predetermined area and an insulating area at corresponding positions. For example, in the thickness direction of the buffer layer, the first predetermined area and the second predetermined area of ​​the intrinsic amorphous silicon layer and the first predetermined area and the second predetermined area of ​​the buffer layer overlap in projection.

[0032] In some embodiments, in step (1), the substrate comprises an N-type silicon wafer.

[0033] In some embodiments, in step (1), before depositing the tunneling layer on one side surface of the substrate, the step further includes polishing the substrate.

[0034] In some other embodiments, in step (1), the substrate is a polished N-type silicon wafer.

[0035] In some embodiments, in step (1), a tunneling layer, an intrinsic amorphous silicon layer and a buffer layer are sequentially deposited on a polished N-type silicon wafer using plasma enhanced deposition (PEVCD).

[0036] In some embodiments, in step (1), the thickness of the tunneling layer is 1-2 nm, such as 1 nm, 1.2 nm, 1.6 nm, 2 nm, etc. Thus, while improving the passivation effect and increasing carrier recombination, the effective tunneling of electrons is not hindered as much as possible.

[0037] In some embodiments, in step (1), the thickness of the intrinsic amorphous silicon layer is 60-150 nm, such as 60 nm, 70 nm, 80 nm, 90 nm, 120 nm, 130 nm, 150 nm, etc., thereby improving the carrier transport characteristics.

[0038] In some embodiments, in step (1), the thickness of the buffer layer is 5-50 nm, for example, 5 nm, 10 nm, 15 nm, 20 nm, 30 nm, 40 nm, 50 nm, etc. Thus, when ion implantation is performed to form the doped layer, the damage to the amorphous silicon layer is reduced. Generally, the material of the buffer layer needs to not introduce external impurities during ion implantation and be easy to remove later.

[0039] Optionally, the buffer layer comprises SiN x 、SiO y At least one of .

[0040] In the present embodiment, the chemical formula (AlO x 、SiN y ) in which the values ​​of x and / or y may be positive integers or may be positive decimals. Since a chemical formula represents a relative atomic ratio rather than a strict chemical structure, the chemical formula may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds. As used in this application, the term "non-stoichiometric compound" means and includes a compound having a certain element composition that cannot be represented by a ratio of well-defined natural numbers and violates the law of definite proportions.

[0041] Furthermore, the buffer layer is silicon dioxide.

[0042] According to an embodiment of the present application, in step (2), ion implantation is performed through the first predetermined area or the second predetermined area of ​​the buffer layer to perform doping treatment on the intrinsic amorphous silicon layer, and the doping treatment product is annealed to obtain the doping region.

[0043] In some embodiments, step (2) is implemented in the following manner: ion implantation is used to perform boron doping on the intrinsic amorphous silicon layer through the first predetermined region, and the product obtained by the boron doping treatment is annealed to obtain a boron doped polysilicon layer; ion implantation is used to perform phosphorus doping on the polysilicon layer through the second predetermined region of the product obtained by the annealing treatment, and the product obtained by the phosphorus doping treatment is annealed to obtain a phosphorus doped polysilicon layer. In this implementation, the intrinsic amorphous silicon layer is doped with boron and annealed through the first predetermined region to obtain a boron doped polysilicon layer. At this time, the intrinsic amorphous silicon layer is annealed to form a polysilicon layer, and then ion implantation is used to perform phosphorus doping on the polysilicon layer and annealed through the second predetermined region of the product obtained by the annealing treatment to obtain a phosphorus doped polysilicon layer. This method allows both phosphorus doping and boron doping to achieve their respective best passivation effects.

[0044] Generally, in step (2), the annealing treatment is performed in a nitrogen atmosphere to activate the doped atoms and the damaged lattice. In addition, some doped atoms will remain in the silicon dioxide layer, and during the annealing process, these atoms will move to the amorphous silicon layer or the polycrystalline silicon layer to further promote the formation of the doped region.

[0045] In some embodiments, in step (2), the temperature of the annealing treatment is 700-1000°C, for example, 700°C, 800°C, 900°C, 1000°C, etc.

[0046] Furthermore, the temperature of annealing the product obtained by the boron doping treatment is 800-1000° C., such as 800° C., 900° C., 1000° C., etc. The annealing temperature is controlled to obtain a boron doped region with a good passivation effect, and to avoid too low a doping amount due to too low a temperature as much as possible.

[0047] Furthermore, the temperature of annealing the product obtained by the phosphorus doping treatment is 700-900° C., for example, 700° C., 800° C., 900° C., etc. The annealing temperature is controlled to obtain a phosphorus doped region with a good passivation effect, and to avoid too low a doping amount due to too low a temperature as much as possible.

[0048] In some embodiments, in step (2), the annealing time is 10 to 60 minutes, for example, 10, 20, 30, 40, 50, 60, etc. The annealing time is controlled to obtain a phosphorus-doped region with a better passivation effect.

[0049] According to an embodiment of the present application, ion implantation is a method of accurately introducing doping elements into a semiconductor, and the process is that ions pass through a buffer layer and hit an amorphous silicon layer or a polycrystalline silicon layer. These high-energy particles enter the crystal lattice and collide with some silicon atoms and lose energy, eventually stopping at a certain depth, allowing the ions to penetrate and embed.

[0050] In some embodiments, in step (2), the energy of the ion implantation is 5-60kev, such as 5kev, 10kev, 20kev, 33kev, 40kev, 48kev, 55kev, 60kev, etc. Therefore, in the process of forming the doped region, it is possible to avoid excessive doping penetration depth or even penetration into the substrate due to excessive energy.

[0051] In some embodiments, in step (2), the ion implantation dose is 1×e 15 ~6×e 15 cm -2 , for example 1×e 15 cm -2 , 2×e 15 cm -2 , 2.5×e 15 cm -2 , 3.5×e 15 cm -2 , 4×e 15 cm -2 , 5×e 15 cm -2 , 6×e 15 cm -2 Etc. Therefore, in the process of forming the doping region, it is best to avoid the doping from penetrating too deeply or even penetrating onto the substrate due to an overly high dose.

[0052] Furthermore, in step (2), when the intrinsic amorphous silicon layer is doped with boron by ion implantation through the first predetermined area, the energy of the ion implantation is 5-60keV, and the dose of the ion implantation is 1×e 15 ~4×e 15 cm -2 .

[0053] Furthermore, in step (2), when phosphorus doping is performed on the polysilicon layer through the second predetermined area by ion implantation, the energy of the ion implantation is 5-50kev, and the dose of the ion implantation is 2×e 15 ~6×e 15 cm -2 .

[0054] As an example, the energy of ion implantation during phosphorus doping is 5-50kev, and the energy of ion implantation during boron doping is 5-60kev, and the energy of ion implantation during phosphorus doping is less than the energy of ion implantation during boron doping. This is conducive to obtaining phosphorus doping regions and boron doping regions with different doping concentrations.

[0055] As an example, the ion implantation dose during phosphorus doping is 2×e15 ~6×e 15 cm -2 The dose of ion implantation during boron doping is 1×e 15 ~4×e 15 cm -2 , and the dose of ion implantation during phosphorus doping is greater than the dose of ion implantation during boron doping. This is conducive to obtaining phosphorus doping regions and boron doping regions with different doping concentrations.

[0056] In some other embodiments, step (2) is implemented in the following manner: ion implantation is performed through the first predetermined region to perform boron doping on the intrinsic amorphous silicon layer, and ion implantation is performed through the second predetermined region to perform phosphorus doping on the intrinsic amorphous silicon layer; the products obtained by the boron doping and phosphorus doping are annealed to obtain a boron doped polysilicon layer and a phosphorus doped polysilicon layer. This method allows the doping products to be annealed after the phosphorus doping and boron doping are completed, and only one annealing is required, which is simple and easy.

[0057] Furthermore, the energy of the ion implantation is 5-60kev; the ion implantation dose is 1×e 15 ~6×e 15 cm -2 .

[0058] Furthermore, the annealing treatment is performed in a nitrogen atmosphere, the annealing treatment temperature is 700-1000° C., and the annealing treatment time is 10-60 min.

[0059] In some embodiments, in step (3), the polysilicon layer in the insulating area is removed to form a gap between the doped areas. The polysilicon layer in the non-first predetermined area and the second predetermined area and the buffer layer are removed to form a gap between the doped areas. In this way, the doped areas are discontinuous, which will not cause leakage or short circuit of the back contact solar cell. The method can also avoid the generation of borosilicate glass layer and phosphorus silicon glass layer, simplify the process of forming the back contact solar cell, and thus greatly improve the manufacturing yield and stable process line of the back contact solar cell, and obtain a back contact solar cell with higher photoelectric conversion efficiency.

[0060] In some embodiments, in step (3), the method of removing the polysilicon layer in the insulating region includes laser ablation. Laser ablation has good positioning accuracy and processing accuracy, so that the undoped polysilicon layer can be accurately removed without causing defects and damage to the doped region.

[0061] Generally speaking, the laser ablation process has good positioning accuracy and processing accuracy, and will hardly cause defects and damage to the doped area. Even if there is slight damage, it can be eliminated by wet etching.

[0062] In some embodiments, in step (3), the damage is removed by chain pickling the substrate after laser ablation using HF with a concentration of 0.5-5wt%.

[0063] In some embodiments, the method for preparing a back-contact solar cell further includes, after removing the insulating region and before removing the buffer layer: (4) texturing the surface of the other side of the substrate.

[0064] In some embodiments, in step (5), the product obtained after the removal treatment is subjected to a buffer layer removal treatment.

[0065] Furthermore, the etching step is to perform chain pickling etching on the substrate after the winding etching using HF with a concentration of 0.5-10wt%.

[0066] In some embodiments, the method for preparing a back-contact solar cell further includes: (6) depositing a passivation layer on the surface of the textured substrate to form a solar cell.

[0067] Furthermore, a PEVCD device is used to deposit a passivation layer on the surface of the textured substrate.

[0068] Optionally, the thickness of the passivation layer is 4-5 nm.

[0069] In some embodiments, the method for preparing a back-contact solar cell further includes: (7) depositing an anti-reflection layer on both the front and back sides of the cell.

[0070] Furthermore, the thickness of the anti-reflection layer is 70-85 nm.

[0071] Furthermore, the thickness of the front anti-reflection layer is 70-80 nm, and the thickness of the back anti-reflection layer is 75-85 nm.

[0072] In some embodiments, the method for preparing a back-contact solar cell further includes: (8) forming an electrode by screen printing.

[0073] The second aspect of the embodiment of the present application provides a back-contact solar cell prepared by the method of the first aspect. The doping region of the solar cell is obtained by depositing a buffer layer, then using ion implantation to penetrate the buffer layer and annealing oxidation to obtain the doping region, so that the doping region has a uniform doping depth and doping concentration, and the doping regions are not connected, and the lattice damage to the intrinsic amorphous silicon layer during ion implantation can be greatly reduced, so that the back-contact solar cell has better photoelectric conversion efficiency.

[0074] In some embodiments, reference Figure 1 The back contact heterojunction cell includes: an N-type substrate 1; a tunneling oxide layer 2; a boron-doped polysilicon layer 3; a phosphorus-doped polysilicon layer 4; a passivation layer 5; an anti-reflection layer 6; and an electrode 7. The boron-doped polysilicon layer 3 and the phosphorus-doped polysilicon layer 4 are separated by an anti-reflection layer 6, and a tunneling oxide layer 2 is arranged between the boron-doped polysilicon layer 3 and the N-type substrate 1, and a tunneling oxide layer 2 is also arranged between the phosphorus-doped polysilicon layer 4 and the N-type substrate 1, and the electrode 7 is connected to the boron-doped polysilicon layer 3 and the phosphorus-doped polysilicon layer 4, respectively.

[0075] In a third aspect of the embodiments of the present application, a photovoltaic module is provided, wherein the photovoltaic module comprises a plurality of solar cells connected in series and / or in parallel; wherein at least one solar cell is a solar cell according to the second aspect of the present invention. A plurality of solar cells in series form a cell string, and adjacent heterojunction solar cells can be connected together by serial welding.

[0076] In a fourth aspect of the embodiment of the present application, a photovoltaic system is provided, comprising the photovoltaic assembly of the third aspect of the present application. The photovoltaic system also has the advantages of the above photovoltaic assembly, which will not be described in detail here.

[0077] The above-mentioned photovoltaic system has a wide range of applications, not only limited to photovoltaic power stations, such as ground power stations, rooftop power stations and water power stations, but also includes various equipment and devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars and solar buildings. Of course, it is understandable that the application scenarios of photovoltaic systems are not limited to this, that is to say, photovoltaic systems can be used in all fields that require solar energy to generate electricity. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array may be an array combination of multiple photovoltaic components. For example, multiple photovoltaic components can form multiple photovoltaic arrays. The photovoltaic array is connected to the junction box. The junction box can converge the current generated by the photovoltaic array. The converged current flows through the inverter and is converted into the alternating current required by the mains power grid, and then connected to the mains network to realize solar power supply.

[0078] Hereinafter, exemplary embodiments according to the present application will be described in more detail with reference to the accompanying drawings. It should be noted that these exemplary embodiments can be implemented in many different forms and should not be construed as being limited to the embodiments described herein.

[0079] Example 1 S1: Polishing is performed on an N bare silicon wafer, and a SiO2 tunneling layer, an intrinsic amorphous silicon layer and a SiO2 buffer layer are sequentially deposited on the back of the polished silicon wafer using PECVD, wherein: the tunneling layer is about 2nm thick, the intrinsic amorphous silicon layer is 120nm thick, and the SiO2 buffer layer is 30nm thick.

[0080] S2: By means of ion implantation, the first predetermined region of the silicon dioxide buffer layer of the cell obtained in step S1 is penetrated, the intrinsic amorphous silicon layer is doped with boron in the buffer layer, and then annealing and oxidation are used to activate the doped boron atoms and the damaged lattice, and a boron-doped polysilicon layer is obtained in the first predetermined region; the ion implantation energy is 30 keV, and the implantation dose is 3.0×e 15 cm -2 ; Annealing temperature 900℃, holding time 40min.

[0081] S3: By ion implantation, the polysilicon layer is doped with phosphorus through the second predetermined area of ​​the silicon dioxide buffer layer of the cell obtained in step S2, and then annealing and oxidation are used to activate the doped phosphorus atoms and the damaged lattice, and a phosphorus-doped polysilicon layer in a limited area is obtained at the same time; the implantation energy is 30 keV, and the implantation dose is 4.0×e 15 cm -2 ; Annealing temperature 800℃, holding time 40min.

[0082] S4: removing the polysilicon layer in the insulating area by laser ablation, and then performing chain pickling etching on the laser ablated substrate by using HF with a concentration of 1 wt % to remove laser damage and form intervals between the doped areas.

[0083] S5: After texturing the front side of the cell obtained in step S4, the texturized substrate is subjected to chain pickling and etching using HF with a concentration of 1wt% to remove the buffer layer, and a 4nm aluminum oxide passivation layer is plated on the front side using a PEVCD device.

[0084] S6: Silicon nitride anti-reflection layer is plated on the front and back sides of the cell obtained in step S5 by using PEVCD equipment. The thickness of the front anti-reflection layer is 75 nm, and the thickness of the back anti-reflection layer is 85 nm.

[0085] S7: Screen-printing a silver electrode on the back side of the cell obtained in step S6 to obtain a back-contact solar cell.

[0086] Example 2 A back-contact solar cell was prepared according to the method described in Example 1, except that the ion implantation energies in steps S2 and S3 were both 5 keV.

[0087] Example 3 A back-contact solar cell was prepared according to the method described in Example 1, except that the ion implantation energy in steps S2 and S3 was 60 keV.

[0088] Example 4 A back-contact solar cell was prepared according to the method described in Example 1, except that the ion implantation dose in step S2 was 1×e 15 cm -2 The ion implantation dose in step S3 is 2×e 15 cm -2 .

[0089] Example 5 A back contact solar cell was prepared according to the method described in Example 1, except that the ion implantation dose in step S2 was 4×e 15 cm -2 The ion implantation dose in step S3 is 6×e 15 cm -2 .

[0090] Example 6 A back-contact solar cell is prepared according to the method described in Example 1, except that the annealing temperature in step S2 is 800° C., and the annealing temperature in step S3 is 700° C.

[0091] Example 7 A back-contact solar cell is prepared according to the method described in Example 1, except that the annealing temperature in step S2 is 1000° C., and the annealing temperature in step S3 is 900° C.

[0092] Example 8 A back-contact solar cell is prepared according to the method described in Example 1, except that S2 and S3 are performed simultaneously, namely: the intrinsic amorphous silicon layer is doped with boron in the buffer layer through the first predetermined area of ​​the silicon dioxide buffer layer of the cell obtained in step S1 by ion implantation; the polycrystalline silicon layer is doped with phosphorus in the second predetermined area of ​​the silicon dioxide buffer layer of the cell obtained in step S1 by ion implantation; and the doped boron atoms, phosphorus atoms and damaged lattice are activated by annealing oxidation to obtain a phosphorus-doped polycrystalline silicon layer in a limited area; the implantation energy is 30 keV and the implantation dose is 4.0×e 15 cm -2 ; Annealing temperature 800℃, holding time 40min.

[0093] Comparative Example 1 A solar cell was prepared in the manner of Example 1, except that a silicon dioxide buffer layer was not deposited in step S1.

[0094] Test Example The heterojunction solar cell was subjected to the following performance tests, and the results are shown in Table 1.

[0095] Photoelectric conversion efficiency, short-circuit current, open-circuit voltage, and fill factor testing: The specific testing method is to place the battery under a light source of 100 mW / cm 2 The results are obtained by connecting the source meter using the four-wire method under AM 1.5G simulated sunlight at 25°C.

[0096] Table 1

[0097] By comparing Examples 1-8 with Comparative Example 1, it can be seen that the photoelectric conversion efficiency of the solar cell of the embodiment is relatively high, which is because the buffer layer is deposited, and then the doped region is obtained by ion implantation through the buffer layer and annealing oxidation. The ion implantation is carried out through the buffer layer, so that the doping concentration, doping depth, doping width, and doping uniformity can be accurately controlled, and the doping regions will not be connected; it can also greatly reduce the lattice damage to the intrinsic amorphous silicon layer or the polycrystalline silicon layer during ion implantation, so that the passivation effect of the tunneling layer and the doping region is better, thereby improving the photoelectric conversion efficiency of the solar cell.

[0098] By comparing Example 1 with Example 8, it can be seen that the performance of the battery obtained by first performing boron doping and annealing and then performing phosphorus doping and annealing is better than that of the battery obtained by simultaneously doping phosphorus and boron and then annealing. This is because the doping concentrations of phosphorus and boron are different, and performing the doping and annealing processes separately can optimize the passivation effect.

[0099] It should be noted that the "some embodiments", "other embodiments", "embodiments", etc. mentioned in this application refer to the specific features, structures or characteristics described in conjunction with the embodiment included in at least one embodiment generally described in this application. The same expression appearing in multiple places in the specification does not necessarily refer to the same embodiment. Furthermore, when a specific feature, structure or characteristic is described in conjunction with any embodiment, it is claimed that the realization of such feature, structure or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0100] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0101] It should also be noted that the above are only preferred embodiments of the present application, and the patent protection scope of the present application is not limited thereto. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for preparing a back contact solar cell, characterized in that: include: (1) A tunneling layer, an intrinsic amorphous silicon layer and a buffer layer are sequentially deposited on one surface of the substrate, wherein the buffer layer comprises SiN x 、SiO y At least one of the above, the buffer layer has a first predetermined area, a second predetermined area and an insulating area, the first predetermined area and the second predetermined area are distributed in a finger shape, and the insulating area is between the first predetermined area and the second predetermined area; (2) ion implantation is performed through the first predetermined region or the second predetermined region of the buffer layer to perform a doping treatment on the intrinsic amorphous silicon layer, and a product obtained by the doping treatment is annealed to obtain the doping region.

2. The method according to claim 1, characterized in that Step (2) is implemented in the following way: Performing a boron doping treatment on the intrinsic amorphous silicon layer through the first predetermined area by ion implantation, and performing an annealing treatment on a product obtained by the boron doping treatment to obtain a boron doped polycrystalline silicon layer; The second predetermined area of ​​the product obtained by the annealing treatment is penetrated by ion implantation to perform phosphorus doping treatment on the polysilicon layer, and the product obtained by the phosphorus doping treatment is annealed to obtain a phosphorus doped polysilicon layer.

3. The method according to claim 1, characterized in that Step (2) is implemented in the following way: ion implantation is performed through the first predetermined region to perform boron doping on the intrinsic amorphous silicon layer, and ion implantation is performed through the second predetermined region to perform phosphorus doping on the intrinsic amorphous silicon layer; The products obtained by the boron doping treatment and the phosphorus doping treatment are both subjected to annealing treatment to obtain a boron doped polysilicon layer and a phosphorus doped polysilicon layer.

4. The method according to any one of claims 1 to 3, characterized in that: The ion implantation satisfies at least one of the following conditions: The ion implantation energy is 5~60kev; The ion implantation dose is 1×e 15 ~6×e 15 cm -2 .

5. The method according to any one of claims 1 to 3, characterized in that: The annealing treatment satisfies at least one of the following conditions: Annealing temperature is 700~1000℃; The time is 10~60min.

6. The method according to claim 1, characterized in that The method further comprises: Removing the polysilicon layer in the insulating region to form a gap between the doped regions; The resultant obtained through the removal process is subjected to a buffer layer removal process.

7. The method according to claim 6, characterized in that The method of removing the buffer layer includes etching the buffer layer; And / or, the method of removing the polysilicon layer in the insulating region includes laser ablation.

8. A back contact solar cell, characterized in that: The method is prepared by any one of claims 1 to 7.

9. A photovoltaic module, characterized in that: The photovoltaic module comprises a plurality of solar cells connected in series and / or in parallel; wherein at least one solar cell is the back-contact solar cell as described in claim 8.

10. A photovoltaic system, characterized in that: The photovoltaic system comprises the photovoltaic assembly according to claim 10.

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