Light emitting diode chip and preparation method thereof

Abstract

The invention relates to a light emitting diode chip and a preparation method thereof. The light emitting diode chip comprises an epitaxial layer, a reflection barrier layer, a current diffusion layer, a first electrode and a second electrode. The epitaxial layer comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer which are stacked in sequence; the second semiconductor layer has a plurality of trenches therein. The reflective barrier layer fills the trench. The current diffusion layer covers the reflection barrier layer and is arranged on the surface, away from the light-emitting layer, of the second semiconductor layer. The first electrode is arranged on the side, away from the light-emitting layer, of the second semiconductor layer and makes contact with the current diffusion layer. The second electrode is arranged on one side of the first semiconductor layer close to the light-emitting layer. According to the light emitting diode chip, the embedded reflection barrier layer is adopted, so that the reliability of the chip is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a light emitting diode chip and a preparation method thereof. Background Art

[0002] In recent years, Micro-LED display technology has received widespread attention. Compared with liquid crystal display (LCD) technology and organic light emitting diode display (OLED) technology, Micro-LED display has the advantages of high luminous intensity, high resolution, high contrast, fast response speed, long life and low power consumption.

[0003] However, when preparing Micro-LEDs, due to the large etching angle of the mesa structure, it is easier to cause cracks in the reflective layer and the pad during evaporation, causing abnormal phenomena such as low thrust value, thereby reducing chip reliability.

[0004] Therefore, how to improve the reliability of Micro-LED is an urgent problem to be solved. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide a light-emitting diode chip and a method for preparing the same, aiming to solve the problem of how to improve the reliability of Micro-LED.

[0006] The embodiment of the present application provides a light-emitting diode chip, comprising: an epitaxial layer, a reflective blocking layer, a current diffusion layer, a first electrode and a second electrode. The epitaxial layer comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer stacked in sequence; the second semiconductor layer has a plurality of grooves. The reflective blocking layer fills the grooves. The current diffusion layer covers the reflective blocking layer and is arranged on the surface of the second semiconductor layer away from the light-emitting layer. The first electrode is arranged on the side of the second semiconductor layer away from the light-emitting layer and is in contact with the current diffusion layer. The second electrode is arranged on the side of the first semiconductor layer close to the light-emitting layer.

[0007] In the embodiment of the present application, a plurality of grooves are provided in the second semiconductor layer, and the grooves are filled with a reflection blocking layer, so that the reflection blocking layer is embedded in the second semiconductor layer. In this way, the reflection blocking layer is covered by the current diffusion layer and is in contact with the first electrode, so that the current of the first electrode is evenly distributed to the surface of the second semiconductor layer through the current diffusion layer, increasing the diffusion area of ​​the current, thereby increasing the luminous efficiency. At the same time, the current diffusion layer contacts the first electrode, indirectly reinforcing the first electrode, and avoiding the first electrode from completely falling off and affecting the chip appearance, chip voltage and current diffusion effect. In summary, the present application adopts an embedded reflection blocking layer to avoid cracks when forming a reflection layer on the second semiconductor layer due to the large etching angle of the mesa structure, thereby improving the reliability of the chip.

[0008] Optionally, the current diffusion layer has an electrode accommodating hole, and the electrode accommodating hole exposes a surface of the second semiconductor layer away from the light-emitting layer. The first electrode is disposed in the electrode accommodating hole.

[0009] Optionally, the light emitting diode chip further includes: an ohmic contact layer, which is disposed between the first electrode and the second semiconductor layer and contacts the current diffusion layer.

[0010] In the embodiment of the present application, the ohmic contact layer is disposed between the first electrode and the second semiconductor layer, and both the first electrode and the ohmic contact layer are in contact with the current diffusion layer. In this way, the current of the first electrode can only diffuse outward from the ohmic contact layer, and then diffuse the current to the edge of the table through the current diffusion layer, thereby avoiding the uneven light-emitting area caused by the current flow being affected by the contact area between the ohmic contact layer and the second semiconductor layer, thereby further increasing the light extraction efficiency.

[0011] Optionally, the surface of the ohmic contact layer away from the epitaxial layer is lower than the surface of the current diffusion layer away from the epitaxial layer. The surface of the first electrode away from the epitaxial layer is higher than the surface of the current diffusion layer away from the epitaxial layer. In this way, the current diffusion layer can fully diffuse the current to the edge, further increasing the light extraction efficiency.

[0012] Optionally, the surface of the reflection blocking layer facing away from the light emitting layer is higher than the surface of the second semiconductor layer facing away from the light emitting layer, or the surface of the reflection blocking layer facing away from the light emitting layer is flush with the surface of the second semiconductor layer facing away from the light emitting layer.

[0013] Optionally, the reflection blocking layer comprises a distributed Bragg reflection layer. The current spreading layer comprises a transparent conductive material layer.

[0014] Optionally, the shape of the groove includes a cylinder, a cone or a right prism.

[0015] Based on the same inventive concept, the present application also provides a method for preparing a light-emitting diode chip, which is used to prepare the light-emitting diode chips in some of the above embodiments. The preparation method also has the technical advantages of the above light-emitting diode chips, which will not be described in detail here. The preparation method comprises the following steps:

[0016] forming an epitaxial layer, wherein the epitaxial layer comprises a first semiconductor layer, a light emitting layer, and a second semiconductor layer which are sequentially stacked;

[0017] forming a first electrode on a side of the second semiconductor layer away from the light emitting layer;

[0018] forming a plurality of grooves in the second semiconductor layer around the first electrode;

[0019] filling the trench to form a reflection barrier layer;

[0020] forming a current diffusion layer on a surface of the second semiconductor layer that is away from the light emitting layer and not covered by the first electrode, wherein the current diffusion layer covers the reflection blocking layer and contacts the side wall of the first electrode;

[0021] A second electrode is formed on a surface of the first semiconductor layer close to the light emitting layer.

[0022] Optionally, before forming the epitaxial layer, the method further includes: forming an ohmic contact layer. The ohmic contact layer is located on a surface of the second semiconductor layer away from the light-emitting layer. Forming a first electrode on a side of the second semiconductor layer away from the light-emitting layer includes: forming the first electrode on a side of the ohmic contact layer away from the second semiconductor layer; and the orthographic projection of the ohmic contact layer on the second semiconductor layer coincides with the orthographic projection of the first electrode on the second semiconductor layer.

[0023] Optionally, forming a plurality of grooves in the second semiconductor layer around the first electrode, and filling the grooves to form a reflection blocking layer, comprises:

[0024] forming a first mask on the surface of the second semiconductor layer and the first electrode away from the light emitting layer; the first mask has a first mask pattern located on the periphery of the first electrode;

[0025] etching the second semiconductor layer based on the first mask pattern to form a plurality of trenches;

[0026] removing the first mask;

[0027] filling the trench to form a reflection blocking material layer;

[0028] forming a second mask on the surface of the reflection blocking material layer facing away from the light emitting layer; the second mask has a second mask pattern with an orthographic projection outside each groove;

[0029] etching the reflection blocking material layer based on the second mask pattern to form a reflection blocking layer;

[0030] The second mask is removed. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a cross-sectional schematic diagram of a light emitting diode chip;

[0032] Figure 2 A cross-sectional schematic diagram of a light emitting diode chip provided by an embodiment;

[0033] Figure 3 A cross-sectional schematic diagram of another light emitting diode chip provided by an embodiment;

[0034] Figure 4 A flowchart of a method for preparing a light emitting diode chip provided by an embodiment;

[0035] Figure 5 A flow chart of forming a plurality of grooves in a second semiconductor layer in a method for preparing a light emitting diode chip provided by an embodiment;

[0036] Figure 6 A flow chart of forming a reflection blocking layer in a method for preparing a light emitting diode chip provided by an embodiment;

[0037] Figure 7 A schematic cross-sectional view of a structure obtained after an ohmic contact layer is formed in a method for preparing a light emitting diode chip provided by an embodiment;

[0038] Figure 8 A schematic cross-sectional view of a structure obtained after forming a bonding layer in a method for preparing a light-emitting diode chip provided by an embodiment;

[0039] Fig. 9 A schematic cross-sectional view of a structure obtained in step S10 in a method for preparing a light emitting diode chip provided in an embodiment;

[0040] Fig.10 A schematic cross-sectional view of a structure obtained in step S20 in a method for preparing a light emitting diode chip provided in an embodiment;

[0041] Fig.11 A schematic cross-sectional view of a structure obtained in step S31 in a method for preparing a light emitting diode chip provided in an embodiment;

[0042] Fig.12 A schematic cross-sectional view of a structure obtained in step S32 in a method for preparing a light emitting diode chip provided in an embodiment;

[0043] Fig.13 A schematic cross-sectional view of a structure obtained in step S41 in a method for preparing a light emitting diode chip provided in an embodiment;

[0044] Fig.14 A schematic cross-sectional view of a structure obtained in step S42 in a method for preparing a light emitting diode chip provided in an embodiment;

[0045] Fig.15 A schematic cross-sectional view of a structure obtained in step S44 in a method for preparing a light emitting diode chip provided in an embodiment;

[0046] Fig.16 A schematic cross-sectional view of a structure obtained in step S50 in a method for preparing a light emitting diode chip provided in an embodiment;

[0047] Fig.17 A schematic cross-sectional view of a structure obtained after a third mask is formed in a method for preparing a light emitting diode chip provided by an embodiment;

[0048] Fig.18 A schematic cross-sectional view of a structure obtained after removing the third mask in a method for preparing a light emitting diode chip provided by an embodiment;

[0049] Fig.19 A schematic cross-sectional view of a structure obtained in step S60 in a method for preparing a light emitting diode chip provided in an embodiment;

[0050] Fig. 20 A schematic cross-sectional view of a structure obtained after etching an epitaxial layer based on a fifth mask in a method for preparing a light emitting diode chip provided by an embodiment;

[0051] Fig.21 A schematic cross-sectional view of a structure obtained after forming a passivation layer in a method for preparing a light-emitting diode chip provided by an embodiment;

[0052] Fig. 22 The present invention is a cross-sectional schematic diagram of a structure obtained after forming a first solder pad and a second solder pad in a method for preparing a light emitting diode chip provided by an embodiment.

[0053] Description of reference numerals:

[0054] 1-epitaxial layer; 11-first semiconductor layer; 12-light-emitting layer; 13-second semiconductor layer; 2-reflection blocking layer; 20-reflection blocking material layer; 3-current diffusion layer; 31-electrode accommodating hole; 41-first electrode; 42-second electrode; 5-ohmic contact layer; 6-passivation layer; 71-first pad; 72-second pad;

[0055] G-groove; S0-growth substrate; B-bonding layer; S-substrate; Y1-first mask; Y2-second mask; Y3-third mask; Y4-fourth mask; Y5-fifth mask; K-through hole. DETAILED DESCRIPTION

[0056] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0058] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., can be used here to describe the relationship between an element or feature shown in the figures and other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0059] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0060] As used herein, a "deposition" process includes, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0061] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0062] Micro-Light Emitting Diode (Micro-LED) display technology is a self-luminous display technology that integrates arrayed Micro-LED light-emitting devices on an active driving substrate to achieve individual control and lighting, thereby outputting display images.

[0063] In recent years, Micro-LED display technology has received widespread attention. Compared with liquid crystal display (LCD) technology and organic light emitting diode display (OLED) technology, Micro-LED display has the advantages of high luminous intensity, high resolution, high contrast, fast response speed, long life and low power consumption.

[0064] However, when preparing Micro-LEDs, due to the large etching angle of the mesa structure, it is easier to cause cracks in the reflective layer and the pad during evaporation, causing abnormal phenomena such as low thrust value, thereby reducing chip reliability.

[0065] Figure 1 A Micro-LED structure is provided, and a preparation method of the Micro-LED structure includes the following steps: vapor-depositing an ohmic contact layer 5 on a roughened epitaxial layer 1 and performing a planarization operation; bonding a substrate to the epitaxial layer 1 and then removing the substrate; vapor-depositing to form a second electrode 42; vapor-depositing to form a first electrode 41 and removing excess ohmic contact layer 5; etching a mesa structure to separate connected Micro-LEDs; vapor-depositing a reflective layer and a passivation layer 6; opening a hole to lead out the first electrode 41 and the second electrode 42, and vapor-depositing a first solder pad 71 and a second solder pad 72 connected to the first electrode 41 and the second electrode 42, respectively.

[0066] Based on the above-mentioned Micro-LED preparation method, the following abnormal phenomena are likely to occur: on the one hand, the etching angle of the mesa structure is large, which is more likely to cause cracks in the reflective layer and the pad during evaporation, thereby causing abnormal phenomena such as low thrust value, thereby reducing chip reliability; on the other hand, the removal of the ohmic contact layer requires control of the operation time, otherwise it is easy to cause the first electrode to fall off completely and affect the ohmic contact, thereby affecting the Micro-LED voltage. In addition, the current flow is determined by the contact area of ​​the ohmic contact layer, and the luminous area is uneven, thus affecting the luminous efficiency.

[0067] Based on this, the present application hopes to provide a solution that can solve the above-mentioned technical problems, the details of which will be described in the subsequent embodiments.

[0068] See also Figure 2 The embodiment of the present application provides a light-emitting diode chip, comprising: an epitaxial layer 1, a reflective barrier layer 2, a current diffusion layer 3, a first electrode 41 and a second electrode 42. The epitaxial layer 1 comprises a first semiconductor layer 11, a light-emitting layer 12 and a second semiconductor layer 13 which are stacked in sequence; the second semiconductor layer 13 has a plurality of grooves G. The reflective barrier layer 2 fills the grooves G. The current diffusion layer 3 covers the reflective barrier layer 2 and is arranged on the surface of the second semiconductor layer 13 away from the light-emitting layer 12. The first electrode 41 is arranged on the side of the second semiconductor layer 13 away from the light-emitting layer 12 and is in contact with the current diffusion layer 3. The second electrode 42 is arranged on the side of the first semiconductor layer 11 close to the light-emitting layer 12.

[0069] In the embodiment of the present application, a plurality of grooves G are provided in the second semiconductor layer 13, and the reflective blocking layer 2 is filled in the grooves G, so that the reflective blocking layer 2 is embedded in the second semiconductor layer 13. In this way, the reflective blocking layer 2 is covered by the current diffusion layer 3 and is in contact with the first electrode 41, so that the current of the first electrode 41 is evenly distributed to the surface of the second semiconductor layer 13 through the current diffusion layer 3, increasing the diffusion area of ​​the current, thereby increasing the luminous efficiency. At the same time, the current diffusion layer 3 contacts the first electrode 41, indirectly reinforcing the first electrode 41, and avoiding the first electrode 41 from completely falling off and affecting the chip appearance, chip voltage and current diffusion effect. In summary, the present application adopts an embedded reflective blocking layer 2, which avoids the generation of cracks when forming a reflective layer on the second semiconductor layer 13 due to the large etching angle of the mesa structure, thereby improving the reliability of the chip.

[0070] Optionally, the shape of the groove G includes a cylinder, a cone or a right prism. For example, the shape of the groove G can also be a ring.

[0071] In some examples, the first semiconductor layer 11 may include but is not limited to a P-type semiconductor layer, and the second semiconductor layer 13 may include but is not limited to an N-type semiconductor layer; for example, the first semiconductor layer 11 may include but is not limited to a P-type gallium nitride layer, and the second semiconductor layer 13 may include but is not limited to an N-type gallium nitride layer.

[0072] In some examples, the reflection blocking layer 2 includes a distributed Bragg reflector (DBR). The DBR layer is a periodic structure composed of two materials with different refractive indices stacked alternately. The material of the DBR layer may include but is not limited to any two of silicon oxide (SiOx), titanium oxide (TiOx), silicon nitride (SiNx), or aluminum oxide (AlOx).

[0073] In some examples, the current diffusion layer 3 is made of a transparent conductive material with high visible light transmittance and strong conductivity. The current diffusion layer 3 may include but is not limited to an indium tin oxide (ITO) layer, a zinc oxide (ZnO) layer, a cadmium tin oxide (CTO) layer, an indium oxide (InO) layer, an indium (In)-doped zinc oxide (ZnO) layer, an aluminum (Al)-doped zinc oxide (ZnO) layer, or a gallium (Ga)-doped zinc oxide (ZnO) layer, etc.

[0074] In some examples, the first electrode 41 and the second electrode 42 may include metal electrodes; for example, the first electrode 41 and the second electrode 42 may include but are not limited to aluminum electrodes, copper electrodes, nickel electrodes, gold electrodes, and the like.

[0075] In some examples, the current diffusion layer 3 has an electrode receiving hole 31 , and the electrode receiving hole 31 exposes the surface of the second semiconductor layer 13 facing away from the light emitting layer 12 . The first electrode 41 is disposed in the electrode receiving hole 31 .

[0076] For some examples, see Figure 2 The light emitting diode chip further includes an ohmic contact layer 5. The ohmic contact layer 5 is disposed between the first electrode 41 and the second semiconductor layer 13, and is in contact with the current diffusion layer 3. The ohmic contact layer 5 includes a gallium arsenide layer.

[0077] In the embodiment of the present application, the ohmic contact layer 5 is disposed between the first electrode 41 and the second semiconductor layer 13, and both the first electrode 41 and the ohmic contact layer 5 are in contact with the current diffusion layer 3. In this way, the current of the first electrode 41 can only diffuse outward from the ohmic contact layer 5, and then diffuse the current to the edge of the table through the current diffusion layer 3, thereby avoiding the uneven light-emitting area caused by the current flow being affected by the contact area between the ohmic contact layer 5 and the second semiconductor layer 13, thereby further increasing the light extraction efficiency.

[0078] For some examples, see Figure 3 The light emitting diode chip further includes: a passivation layer 6, a first pad 71 and a second pad 72. The passivation layer 6 is disposed on the surface of the epitaxial layer 1, the current diffusion layer 3, the first electrode 41 and the second electrode 42. The passivation layer 6 has pores exposing the first electrode 41 and the second electrode 42.

[0079] The first pad 71 is disposed on a side of the passivation layer 6 facing away from the epitaxial layer 1 and is connected to the first electrode 41 .

[0080] The second pad 72 is disposed on a side of the passivation layer 6 facing away from the epitaxial layer 1 and is connected to the second electrode 42 .

[0081] For example, the passivation layer 6 may include but is not limited to a light-reflecting insulating layer. For example, silicon oxide (SiO X ) layer, titanium oxide (TiO X ) layer, silicon nitride (SiN X ) layer or aluminum oxide (AlO X ) layer.

[0082] In some examples, the surface S1 of the ohmic contact layer 5 facing away from the epitaxial layer 1 is lower than the surface S2 of the current diffusion layer 3 facing away from the epitaxial layer 1. The surface S3 of the first electrode 41 facing away from the epitaxial layer 1 is higher than the surface S2 of the current diffusion layer 3 facing away from the epitaxial layer 1. In this way, the current diffusion layer 3 can fully diffuse the current to the edge, further increasing the light extraction efficiency.

[0083] In some examples, a surface S4 of the reflection blocking layer 2 facing away from the light emitting layer 12 is higher than a surface S5 of the second semiconductor layer 13 facing away from the light emitting layer 12 , or a surface of the reflection blocking layer 2 facing away from the light emitting layer 12 is flush with a surface S5 of the second semiconductor layer 13 facing away from the light emitting layer 12 .

[0084] Based on the same inventive concept, please refer to Figure 4 Some embodiments of the present disclosure provide a method for preparing a semiconductor structure, which is used to prepare the semiconductor structure in some of the above embodiments. The semiconductor preparation method provided by the embodiments of the present disclosure is used to prepare the semiconductor structure in some of the above embodiments. The technical advantages of the above semiconductor structure are also possessed by the preparation method, which will not be described in detail here. The preparation method comprises the following steps.

[0085] S10: forming an epitaxial layer, wherein the epitaxial layer includes a first semiconductor layer, a light emitting layer, and a second semiconductor layer stacked in sequence;

[0086] S20: forming a first electrode on a side of the second semiconductor layer away from the light emitting layer;

[0087] S30: forming a plurality of grooves in the second semiconductor layer around the first electrode;

[0088] S40: filling the groove to form a reflection blocking layer;

[0089] S50: forming a current diffusion layer on a surface of the second semiconductor layer away from the light emitting layer and not covered by the first electrode, wherein the current diffusion layer covers the reflection blocking layer and contacts the side wall of the first electrode;

[0090] S60: forming a second electrode on a surface of the first semiconductor layer close to the light emitting layer.

[0091] In some examples, before forming the epitaxial layer in step S10 , the preparation method further includes: S5 : forming an ohmic contact layer. The ohmic contact layer 5 is located on the surface of the second semiconductor layer 13 away from the light emitting layer 12 .

[0092] In some examples, step S20 forms a first electrode on a side of the second semiconductor layer away from the light-emitting layer, including: forming a first electrode on a side of the ohmic contact layer away from the second semiconductor layer; the orthographic projection of the ohmic contact layer on the second semiconductor layer coincides with the orthographic projection of the first electrode on the second semiconductor layer.

[0093] For some examples, see Figure 5 Step S30 of forming a plurality of grooves in the second semiconductor layer around the first electrode comprises:

[0094] S31: forming a first mask on the surface of the second semiconductor layer and the first electrode away from the light emitting layer; the first mask has a first mask pattern located on the periphery of the first electrode;

[0095] S32: etching the second semiconductor layer based on the first mask pattern to form a plurality of trenches;

[0096] S33: removing the first mask.

[0097] For some examples, see Figure 6 Step S40 of filling the groove to form a reflective barrier layer includes:

[0098] S41: filling the groove to form a reflection blocking material layer;

[0099] S42: forming a second mask on a surface of the reflection blocking material layer facing away from the light emitting layer; the second mask has a second mask pattern whose orthographic projection is located outside each groove;

[0100] S43: etching the reflection blocking material layer based on the second mask pattern to form a reflection blocking layer;

[0101] S44: removing the second mask.

[0102] In order to more clearly illustrate the method for preparing the light emitting diode chip provided in the above embodiment, Figure 7 to Figure 22The preparation method of the light emitting diode chip is described in detail.

[0103] In step S5, refer to Figure 7 , forming an ohmic contact layer 5. The ohmic contact layer 5 is located on the surface of the second semiconductor layer 13 away from the light emitting layer 12. The ohmic contact layer 5 is reinforced by secondary growth, evaporation, etc. to improve the adhesion strength to the metal electrode.

[0104] In step S10, forming the epitaxial layer 1 includes the following steps:

[0105] See also Figure 7 , a second semiconductor layer 13, a light-emitting layer 12 and a first semiconductor layer 11 are sequentially stacked on the surface of the ohmic contact layer 5 away from the growth substrate S0, and the first semiconductor layer 11 is roughened; thus, the roughened epitaxial layer 1 can improve the light emission angle of the light-emitting diode chip and the strength of the epitaxial layer 1;

[0106] By way of example, the growth substrate S0 may be, but is not limited to, a sapphire substrate, a silicon carbide substrate, a silicon substrate, or a gallium nitride substrate.

[0107] See also Figure 8 , forming a bonding layer B on the surface of the roughened first semiconductor layer 11 on the side away from the growth substrate S0; for example, the bonding layer B may include but is not limited to an oxide layer;

[0108] See also Fig. 9 , the epitaxial layer 1 and the ohmic contact layer 5 are bonded to the substrate S through the bonding layer B, and the growth base S0 is removed to facilitate subsequent electrode production.

[0109] By way of example, the substrate S may be, but is not limited to, a sapphire substrate, a silicon carbide substrate, a silicon substrate, or a gallium nitride substrate.

[0110] For example, after forming the bonding layer B, a grinding process may be used to ensure that the surface of the bonding layer B is flat, and then high temperature and high pressure are used for bonding. The grinding process includes but is not limited to chemical mechanical polishing (CMP).

[0111] In step S20, refer to Fig.10 A first electrode 41 is formed on the side of the ohmic contact layer 5 facing away from the second semiconductor layer 13. The orthographic projection of the ohmic contact layer 5 on the second semiconductor layer 13 coincides with the orthographic projection of the first electrode 41 on the second semiconductor layer 13.

[0112] For example, forming the first electrode 41 on the side of the ohmic contact layer 5 away from the second semiconductor layer 13 includes: forming a first electrode material layer (not shown) on the side of the ohmic contact layer 5 away from the second semiconductor layer 13; patterning the first electrode material layer to form the first electrode 41; removing excess ohmic contact layer 5 so that the orthographic projection of the ohmic contact layer 5 on the second semiconductor layer 13 coincides with the orthographic projection of the first electrode 41 on the second semiconductor layer 13. In this way, since the ohmic contact layer 5 affects the light extraction efficiency of the core particle, the excess ohmic contact layer 5 is removed to ensure the light extraction efficiency.

[0113] For example, the first electrode material layer may be formed by, but is not limited to, an evaporation method, such as an electron beam evaporation process.

[0114] In step S31, refer to Fig.11 A first mask Y1 is formed on the surface of the second semiconductor layer 13 and the first electrode 41 away from the light emitting layer 12 ; the first mask Y1 has a first mask pattern located on the peripheral side of the first electrode 41 .

[0115] In step S32, refer to Fig.12 , the second semiconductor layer 13 is etched based on the first mask pattern to form a plurality of trenches G.

[0116] For example, a dry etching process may be used to form a plurality of trenches G in the second semiconductor layer 13 .

[0117] In step S41, refer to Fig.13 , filling the groove G to form a reflection blocking material layer 20.

[0118] In step S42, refer to Fig.14 A second mask Y2 is formed on the surface of the reflective blocking material layer 20 away from the light emitting layer 12 ; the second mask Y2 has a second mask pattern whose orthographic projection is located outside each groove G.

[0119] In step S43, refer to Fig.15 , based on the second mask pattern, the reflective blocking material layer 20 is etched to form a reflective blocking layer 2 .

[0120] By way of example, the reflection blocking material layer 20 may be etched by a dry etching process to form the reflection blocking layer 2 .

[0121] Here, the first electrode 41 is wrapped by the reflection blocking material layer 20 and cannot conduct electricity. Therefore, the second mask Y2 is used to dry-etch the redundant reflection blocking material layer 20 to expose the first electrode 41 so as to form a pad later.

[0122] In step S50, refer to Fig.16A current diffusion layer 3 is formed on a surface of the second semiconductor layer 13 that is away from the light emitting layer 12 and not covered by the first electrode 41 . The current diffusion layer 3 covers the reflection blocking layer 2 and contacts the side wall of the first electrode 41 .

[0123] After step S50, the method for preparing the light emitting diode chip further includes:

[0124] See also Fig.17 , forming a third mask Y3 on the surface of the current diffusion layer 3 away from the second semiconductor layer 13 , wherein the third mask Y3 covers the first electrode 41 ;

[0125] See also Fig.18 , etching the current diffusion layer 3, the second semiconductor layer 13 and the light emitting layer 12 based on the third mask Y3 to expose the surface of the first semiconductor layer 11 away from the bonding layer B, and removing the third mask Y3;

[0126] In step S60, refer to Fig.19 , forming a second electrode 42 on the surface of the first semiconductor layer 11 close to the light-emitting layer 12 includes: forming a fourth mask Y4 on the surface of the epitaxial layer 1 away from the bonding layer B, the fourth mask Y4 covers the first electrode 41 and has a through hole K exposing the surface of the first semiconductor layer 11 close to the light-emitting layer 12; forming the second electrode 42 in the through hole K.

[0127] Here, the second electrode material layer may be formed by, but is not limited to, evaporation, such as low-temperature evaporation, to avoid oxidation of the surface of the first electrode 41 due to excessive temperature and thus affect the working current after the subsequent formation of the first pad.

[0128] By way of example, after forming the second electrode 42 , the method for preparing the light emitting diode chip further includes: removing the fourth mask Y4 .

[0129] For example, after removing the fourth mask Y4, the method for preparing the light emitting diode chip further includes:

[0130] See also Fig. 20 , forming a fifth mask Y5 on the surface of the epitaxial layer 1 away from the bonding layer B, the fifth mask Y5 covers the first electrode 41 and the second electrode 42, and exposes a portion of the current diffusion layer 3 and the surface of the first semiconductor layer 11 away from the substrate S; etching the epitaxial layer 1 based on the fifth mask Y5 to prevent the epitaxial layer 1 from sticking and causing electrode leakage;

[0131] See also Fig.21 , remove the fifth mask Y5, and form a passivation layer 6 on the surfaces of the epitaxial layer 1, the current diffusion layer 3, the first electrode 41 and the second electrode 42;

[0132] For example, it may include but is not limited to a reflective insulating layer. For example, silicon oxide (SiO X ) layer, titanium oxide (TiO X ) layer, silicon nitride (SiN X ) layer or aluminum oxide (AlO X In this way, it is possible to prevent the chip from leaking electricity due to thinning, cracking and other processes of the epitaxial layer 1, further improving the chip reliability.

[0133] See also Fig. 22 , the passivation layer 6 is etched to form a pore exposing the first electrode 41 and the second electrode 42, and a first pad 71 connected to the first electrode 41 and a second pad 72 connected to the second electrode 42 are respectively formed in the pore for use by the client.

[0134] For example, the first pad 71 and the second pad 72 may be formed by, but not limited to, an evaporation method, such as an electron beam evaporation process.

[0135] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A light emitting diode chip, characterized in that: include: The epitaxial layer comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are stacked in sequence; The second semiconductor layer has a plurality of grooves; a reflection blocking layer filling the groove; a current diffusion layer, covering the reflection blocking layer and disposed on a surface of the second semiconductor layer away from the light emitting layer; A first electrode is disposed on a side of the second semiconductor layer away from the light emitting layer and in contact with the current diffusion layer; The second electrode is arranged on a side of the first semiconductor layer close to the light emitting layer.

2. The light emitting diode chip according to claim 1, characterized in that: The current diffusion layer has an electrode accommodating hole, and the electrode accommodating hole exposes a surface of the second semiconductor layer away from the light emitting layer; The first electrode is disposed in the electrode accommodating hole.

3. The light emitting diode chip according to claim 1 or 2, characterized in that: Also includes: The ohmic contact layer is disposed between the first electrode and the second semiconductor layer and is in contact with the current diffusion layer.

4. The light emitting diode chip according to claim 3, characterized in that: The surface of the ohmic contact layer away from the epitaxial layer is lower than the surface of the current diffusion layer away from the epitaxial layer; the surface of the first electrode away from the epitaxial layer is higher than the surface of the current diffusion layer away from the epitaxial layer.

5. The light emitting diode chip according to claim 1, characterized in that: The surface of the reflection blocking layer facing away from the light emitting layer is higher than the surface of the second semiconductor layer facing away from the light emitting layer, or the surface of the reflection blocking layer facing away from the light emitting layer is flush with the surface of the second semiconductor layer facing away from the light emitting layer.

6. The light emitting diode chip according to claim 1, characterized in that: The reflection blocking layer includes a distributed Bragg reflection layer; and the current diffusion layer includes a transparent conductive material layer.

7. The light emitting diode chip according to claim 1, characterized in that: The groove has a shape of a cylinder, a cone or a right prism.

8. A method for preparing a light emitting diode chip, characterized in that: include: forming an epitaxial layer, wherein the epitaxial layer comprises a first semiconductor layer, a light emitting layer, and a second semiconductor layer which are sequentially stacked; forming a first electrode on a side of the second semiconductor layer away from the light emitting layer; forming a plurality of grooves in the second semiconductor layer around the first electrode; Filling the groove to form a reflection blocking layer; forming a current diffusion layer on a surface of the second semiconductor layer away from the light emitting layer and not covered by the first electrode, wherein the current diffusion layer covers the reflection blocking layer and contacts the side wall of the first electrode; A second electrode is formed on a surface of the first semiconductor layer close to the light emitting layer.

9. The method for preparing a light emitting diode chip according to claim 8, characterized in that: Before forming the epitaxial layer, the method further includes: forming an ohmic contact layer; the ohmic contact layer is located on the surface of the second semiconductor layer away from the light emitting layer; The forming of the first electrode on the side of the second semiconductor layer away from the light emitting layer comprises: forming the first electrode on the side of the ohmic contact layer away from the second semiconductor layer; the orthographic projection of the ohmic contact layer on the second semiconductor layer coincides with the orthographic projection of the first electrode on the second semiconductor layer.

10. The method for preparing a light emitting diode chip according to claim 8, characterized in that: The step of forming a plurality of grooves in the second semiconductor layer around the first electrode and filling the grooves to form a reflection blocking layer comprises: forming a first mask on the surface of the second semiconductor layer and the first electrode away from the light emitting layer; the first mask has a first mask pattern located on the periphery of the first electrode; etching the second semiconductor layer based on the first mask pattern to form a plurality of the grooves; removing the first mask; Filling the groove to form a reflection blocking material layer; forming a second mask on a surface of the reflection blocking material layer away from the light emitting layer; the second mask having a second mask pattern with an orthographic projection outside each of the grooves; etching the reflection blocking material layer based on the second mask pattern to form a reflection blocking layer; The second mask is removed.

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