Display device and method for setting the same

Abstract

A display device and a method for setting the same are provided, the display device including: a pixel electrode in a light emitting area; a pixel defining layer on the pixel electrode and defining a light emitting region; a light emitting layer and a common electrode on the pixel electrode; a bank on the pixel defining layer, the bank including a first bank layer defining a lower portion of a bank opening corresponding to the light emitting area, and a second bank layer defining an upper portion of the bank opening and a tip of the bank, the tip including an upper surface and a lower surface of the second bank layer; a lower inorganic encapsulation layer on the bank and including an inorganic pattern on the common electrode and facing and spaced apart from both the upper and lower surfaces of the tip; and an auxiliary pattern between a lower surface of the tip and the inorganic pattern.

Description

[0001] This application claims priority to and all benefits of Korean Patent Application No. 10-2023-0104408, filed on August 9, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0002] The present disclosure relates to a display device and a method of setting (or manufacturing) the display device. Background Art

[0003] With the development of the information society, the demand for display devices for displaying images has increased and diversified. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, or an organic light emitting display device. Among such flat panel display devices, a light emitting display device can display an image without a backlight unit that provides light to the display panel, because each of the pixels of the display panel includes a light emitting element that can emit light by itself.

[0004] The display device has been applied to a glasses type device to provide virtual reality and augmented reality. The display device is implemented in a very small size of two inches or less so as to be applied to the glasses type device. Summary of the invention

[0005] When a relatively small display device is applied to an electronic device, the display device has a high pixel integration so as to be implemented with a high resolution. For example, a display device applied to a glasses-like device may have a high pixel integration of 400 pixels per inch (PPI) or more. When a display device is implemented in a very small size but has a high pixel integration as described above, the plane area of ​​the emission region in which the light-emitting element is disposed is reduced. Therefore, it may be difficult to implement light-emitting elements separated from each other for each light-emitting region through a mask process.

[0006] Aspects of the present disclosure provide a display device in which light emitting elements separated from each other are respectively provided for each of a plurality of emission regions without a mask process.

[0007] Aspects of the present disclosure also provide a display device in which emission deviation that may occur for each pixel (or light emitting area) due to penetration of an etchant into a light emitting element in an etching process performed during a process for manufacturing the display device is reduced.

[0008] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0009] Details of other embodiments are described in the detailed description and shown in the accompanying drawings.

[0010] According to a disclosed embodiment, a display device includes: a first pixel electrode, which is arranged on a substrate; a pixel defining film, which is arranged on the substrate and exposes the first pixel electrode; a first light-emitting layer, which is arranged on the first pixel electrode; a first common electrode, which is arranged on the first light-emitting layer; a first embankment layer, which is arranged on the pixel defining film; a second embankment layer, which is arranged on the first embankment layer and has a side surface that protrudes much more than a side surface of the first embankment layer; a first inorganic layer, which is arranged on the first common electrode and the second embankment layer and is spaced apart from an upper surface of the second embankment layer; and a first auxiliary layer, which is arranged between a lower surface of the second embankment layer and the first inorganic layer.

[0011] The first auxiliary layer may be disposed on an upper surface of the first common electrode and side surfaces of the first bank layer.

[0012] A thickness of the first auxiliary layer on an upper surface of the first common electrode may be different from a thickness of the first auxiliary layer on a lower surface of the second bank layer.

[0013] The display device may further include: an organic encapsulation layer disposed between an upper surface of the second bank layer and the first inorganic layer.

[0014] The first inorganic layer may include: a first surface facing an upper surface of the second bank layer; and a second surface facing a side surface of the second bank layer.

[0015] A first auxiliary layer may also be disposed on the second surface of the first inorganic layer.

[0016] A first auxiliary layer may also be disposed on the first surface of the first inorganic layer.

[0017] A thickness of the first auxiliary layer on the first surface of the first inorganic layer may be greater than a thickness of the first auxiliary layer on a lower surface of the second bank layer.

[0018] The second bank layer in a region overlapping the first light emitting layer in a thickness direction of the substrate may be in contact with the organic encapsulation layer.

[0019] The first auxiliary layer may include a transparent conductive oxide (TCO).

[0020] One end and the other end of the first common electrode may overlap the second bank layer in a thickness direction of the substrate.

[0021] The display device may also include: a second pixel electrode, arranged on the substrate and separated from the first pixel electrode; a second light-emitting layer, arranged on the second pixel electrode and separated from the first light-emitting layer; a second common electrode, arranged on the second light-emitting layer and separated from the first common electrode; and a second inorganic layer, arranged on the second common electrode and the second embankment layer, and separated from the upper surfaces of the first inorganic layer and the second embankment layer.

[0022] According to a disclosed embodiment, a display device includes: a first pixel electrode, which is arranged on a substrate; a pixel defining film, which is arranged on the substrate and exposes the first pixel electrode; a first light-emitting layer, which is arranged on the first pixel electrode; a first common electrode, which is arranged on the first light-emitting layer; a first embankment layer, which is arranged on the pixel defining film; a second embankment layer, which is arranged on the first embankment layer and has a side surface that protrudes much more than the side surface of the first embankment layer; a first inorganic layer, including a main body arranged on the first common electrode and a wing portion arranged on the second embankment layer; a first auxiliary layer, which is arranged between the main body of the first inorganic layer and the first common electrode; and an organic encapsulation layer, which is arranged between the wing portion of the first inorganic layer and the second embankment layer.

[0023] A first auxiliary layer may also be disposed on a side surface of the first bank layer and a lower surface of the second bank layer.

[0024] The second bank layer in a region overlapping the wing portion of the first inorganic layer in a thickness direction of the substrate may be in contact with the organic encapsulation layer.

[0025] According to the disclosed embodiments, a method for manufacturing a display device includes: preparing a plurality of pixel electrodes, a pixel defining film, a first embankment layer, and a second embankment layer on a substrate, the plurality of pixel electrodes being spaced apart from each other, the pixel defining film exposing the pixel electrodes, the first embankment layer being disposed on the pixel defining film, and the second embankment layer protruding from a side surface of the first embankment layer; forming a first light-emitting layer on the first pixel electrode of the pixel electrode and a first light-emitting pattern layer on the second embankment layer; forming a first common electrode on the first light-emitting layer and a first electrode pattern layer on the first light-emitting pattern layer; forming a first auxiliary material layer on the upper surface of the first common electrode, the upper surface of the first electrode pattern layer, and the lower surface of the second embankment layer; forming a first inorganic material layer on the first auxiliary material layer; etching a portion of the first inorganic material layer; etching a portion of the first auxiliary material layer; and exposing the second embankment layer by etching the first light-emitting pattern layer and the first electrode pattern layer.

[0026] In the step of etching a portion of the first inorganic material layer, the portion of the first inorganic material layer may be removed by a dry etching process, and in the step of etching a portion of the first auxiliary material layer, the portion of the first auxiliary material layer may be removed by a wet etching process.

[0027] In the step of exposing the second bank layer by etching the first light emitting pattern layer and the first electrode pattern layer, the first light emitting pattern layer and the first electrode pattern layer between the second bank layer and the first inorganic material layer may be removed.

[0028] The step of forming a first light emitting layer on the first pixel electrode of the pixel electrode and the step of forming a first light emitting pattern layer on the second bank layer may include: disconnecting the material deposited on the substrate through the protruding side surface of the second bank layer to separate the material into the first light emitting layer and the first light emitting pattern layer.

[0029] The method for manufacturing a display device may also include: forming a second light-emitting layer on the second pixel electrode of the pixel electrode, and forming a second light-emitting pattern layer on the second embankment layer and the first inorganic material layer; forming a second common electrode on the second light-emitting layer, and forming a second electrode pattern layer on the second light-emitting pattern layer; forming a second auxiliary material layer on the upper surface of the second common electrode, the upper surface of the second electrode pattern layer, and the lower surface of the second embankment layer; forming a second inorganic material layer on the second auxiliary material layer; and etching a portion of the second inorganic material layer, wherein, in the step of forming the second light-emitting pattern layer on the second embankment layer and the first inorganic material layer, the material deposited on the second embankment layer can be disconnected by the first inorganic material layer to form a separated second light-emitting pattern layer on the second embankment layer and the first inorganic material layer.

[0030] With the display device according to the embodiment and the method for manufacturing the display device, an auxiliary layer may be included between the lower surface of the second bank layer and the lower inorganic encapsulation layer to prevent free radicals of the etchant from penetrating between the second bank layer and the lower inorganic encapsulation layer during the etching process. Damage to the light-emitting element caused by the etchant or moisture can be prevented, and thus the brightness difference between the light-emitting elements can be reduced.

[0031] The effects of the present disclosure are not limited to the above-mentioned effects, and various other effects are included in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 is a perspective view showing a display device according to an embodiment; Figure 2 It is viewed from the side Figure 1 A cross-sectional view of a display device; Figure 3 is an enlarged plan view showing the arrangement of a light emitting element, a lower inorganic encapsulation layer, and a second bank layer of a display device according to an embodiment; Figure 4 is a cross-sectional view showing a portion of a display device according to an embodiment; Figure 5 is a diagram showing the first emission region (specifically, Figure 4 An enlarged cross-sectional view of area A1); Figure 6 is an enlarged cross-sectional view of a display device according to an embodiment; Figure 7 is an enlarged cross-sectional view of a display device according to another embodiment; Figure 8 is an enlarged cross-sectional view of a display device according to yet another embodiment; Fig. 9 is an enlarged cross-sectional view showing the penetration of an etchant into a light emitting element when there is no auxiliary layer; Fig.10 is an enlarged cross-sectional view showing prevention of penetration of an etchant by an auxiliary layer; and Figures 11 to 23 are cross-sectional views illustrating processes in a method of providing a display device according to an embodiment. DETAILED DESCRIPTION

[0033] The invention will now be described more fully below with reference to the accompanying drawings in which embodiments of the invention are shown. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout the specification, the same reference numerals indicate the same components. In the disclosed figures and texts, the reference numerals indicating the elements in the singular form may also be used to refer to a plurality of singular elements.

[0034] It will also be understood that when a layer is referred to as being associated with another element (such as “on” another layer or substrate), the layer can be directly on the other layer or substrate, or intervening layers may also be present. Conversely, when a layer is referred to as being associated with another element (such as “directly on” another layer or substrate), there are no intervening layers.

[0035] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the invention, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0036] The terms used here are only used for the purpose of describing specific embodiments, and are not intended to be limiting. As used here, unless the context clearly indicates otherwise, "one", "one (kind / person)", "the (said)" and "at least one (kind / person)" do not represent the limitation of quantity, and are intended to include both singular and plural. Therefore, after mentioning "one" element in the claim, mentioning "said" element includes one element and multiple elements. For example, unless the context clearly indicates otherwise, "one element" has the same meaning as "at least one element". "At least one (kind / person)" should not be interpreted as being limited to "one" or "one (kind / person)". "Or" means "and / or". As used here, the term "and / or" includes any combination and all combinations of one or more of the related listed items. It will be further understood that when the term "includes" or "comprising" and / or its variations are used in this specification, it is explained that there are stated features, regions, wholes, steps, operations, elements and / or components, but it is not excluded that there are or add one or more other features, regions, wholes, steps, operations, elements, components and / or their groups.

[0037] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used here to describe the relationship of one element to another element as shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, the relative terms are intended to include different orientations of the device. For example, if the device in one of the figures is turned over, the element described as being on the "lower" side of the other element will then be oriented on the "upper" side of the other element. Therefore, the term "lower" can include both "lower" and "upper" orientations according to the specific orientation of the figure. Similarly, if the device in one of the figures is turned over, the element described as being "below" or "under" the other element will then be oriented "above" the other element. Therefore, the term "below..." or "under..." can include both "upper" and "lower" orientations.

[0038] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation of the particular value determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0039] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0040] Here, embodiments are described with reference to cross-sectional views as schematic diagrams of idealized embodiments. As such, variations in the shapes of the diagrams, such as those caused by manufacturing techniques and / or tolerances, are expected. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the regions as shown herein, but will include shape deviations, such as those caused by manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp corners shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, and are not intended to limit the scope of the claims presented.

[0041] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0042] Figure 1 is a perspective view showing a display device 10 according to the embodiment.

[0043] Reference Figure 1 The display device 10 according to the embodiment may be included in an electronic device to provide a screen (e.g., a display screen) for displaying an image on the electronic device. The electronic device may refer to all electronic devices that provide a display screen. For example, a television, a laptop computer, a monitor, a billboard, an Internet of Things (IoT) device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, smart glasses, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera, a video camera, etc. that provide a display screen may be included in the electronic device.

[0044] The shape of the display device 10 may be variously changed. For example, the display device 10 may have a planar shape similar to a rectangular shape having short sides extending in a first direction DR1 and long sides extending in a second direction DR2 intersecting the first direction DR1. In a plan view, a corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be rounded with a curvature, but is not limited thereto, and may also be a right angle. The shape of the display device 10 in a plan view (e.g., a planar shape) is not limited to a rectangular shape, but may be a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0045] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400 (see Figure 2 ).

[0046] The display panel 100 may include a main area MA and a sub area SBA.

[0047] The main area MA may include a display area DA including pixels displaying an image and a non-display area NDA adjacent to the display area DA. In an embodiment, in a plan view, the non-display area NDA may be disposed around the display area DA. The display area DA may emit light from a plurality of emission areas or a plurality of opening areas (e.g., a plurality of light-emitting areas including a plurality of light-emitting areas). For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining film (or a pixel defining layer) defining an emission area or an opening area, and a self-luminous element connected to the pixel circuit.

[0048] For example, the self-luminous element as the light emitting element may include at least one of an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0049] A plurality of pixels, a plurality of scan lines, a plurality of data lines, and a plurality of power lines may be provided in the display area DA. Each of the plurality of pixels may be defined as a minimum unit for emitting light, displaying an image, etc., and each of the above-mentioned self-luminous elements may be each of the pixels. A plurality of scan lines as signal lines may supply scan signals as electrical signals received from a scan driver to a plurality of pixels. A plurality of data lines as signal lines may supply data voltages as electrical signals received from a display driver 200 to a plurality of pixels. A plurality of power lines as signal lines may supply source voltages as electrical signals received from a display driver 200 to a plurality of pixels.

[0050] The non-display area NDA may be an area (e.g., a plane area) outside the display area DA, such as being closer to the outer edge of the display device 10 than the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a scan driver supplying a scan signal to a scan line and a fan-out line connecting the display driver 200 and the display area DA to each other.

[0051] The sub-region SBA may be a region extending from one side of the main region MA. The sub-region SBA may include a flexible material that can be bent, folded, and curled. For example, when the display device 10 is bent at the sub-region SBA, the sub-region SBA may overlap with the main region MA in the thickness direction (e.g., the third direction DR3). That is, the thickness of the display device 10 and its various components or layers may be defined along a third direction DR3 that intersects a plane defined by the first direction DR1 and the second direction DR2 that intersect each other. The sub-region SBA may include a display driver 200 and a pad (also referred to as a "pad", "solder pad") portion connected to the circuit board 300. In another embodiment, the sub-region SBA may be omitted, and the display driver 200 and the pad portion may be disposed in the non-display area NDA. In an embodiment, the sub-region SBA may be part of the non-display area NDA.

[0052] The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may supply data voltages to data lines. The display driver 200 may supply source voltages to power lines and supply scan control signals to scan drivers. The display driver 200 may be formed (or provided) as an integrated circuit (IC) and may be mounted on the display panel 100 in a chip on glass (COG) manner, a chip on plastic (COP) manner, or an ultrasonic bonding manner. As an example, the display driver 200 may be provided in a sub-region SBA and may be overlapped with the main region MA in a thickness direction (e.g., a third direction DR3) by bending the display device 10 at the sub-region SBA. As another example, the display driver 200 may be mounted on a circuit board 300.

[0053] The circuit board 300 may be attached to the display panel 100 at a pad portion of the display panel 100, such as by using an anisotropic conductive film (ACF). Leads of the circuit board 300 may be electrically connected to the display panel 100 at the pad portion of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0054] Figure 2 It is viewed from the side Figure 1 10 is a cross-sectional view of a display device 10. Specifically, Figure 2 Shows Figure 1 The side surface of the display device 10 in a state where the display device 10 is folded. The display device 10 and its various components or layers may be bendable, foldable, rollable, etc., such as to be deformed together with each other.

[0055] Reference Figure 2, the display panel 100 may include a substrate SUB, a thin film transistor layer TFTL as a circuit layer, a light emitting element layer EML, a thin film encapsulation layer TFEL as an encapsulation layer, and a color filter layer CFL.

[0056] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or curled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. In another embodiment, the substrate SUB may include a glass material or a metal material.

[0057] The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer TFTL may also include a scan line, a data line, a power line, a scan control line, a fan-out line connecting the display driver 200 and the data line to each other, and a lead connecting the display driver 200 and the pad portion to each other. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when a scan driver is formed on one side of the non-display area NDA of the display panel 100, the scan driver may include a thin film transistor.

[0058] The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistor, the scan line, the data line, and the power line of each pixel of the thin film transistor layer TFTL may be disposed in the display area DA. The scan control line and the fan-out line of the thin film transistor layer TFTL may be disposed in the non-display area NDA. The lead line of the thin film transistor layer TFTL may be disposed in the sub-area SBA.

[0059] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a plurality of light emitting elements each including a first electrode for emitting light, a second electrode, and a light emitting layer to emit light, and a pixel defining film defining a pixel or a light emitting region thereof. The plurality of light emitting elements of the light emitting element layer EML may be disposed in the display area DA. The light emitting element layer EML may be electrically connected to a circuit layer (e.g., a thin film transistor layer TFTL) to emit light, display an image using light, and the like.

[0060] In an embodiment, the light emitting layer may be an organic light emitting layer including an organic material. The light emitting layer may include a hole transport layer, an organic light emitting layer, and an electron transport layer. When the first electrode receives a voltage through the thin film transistor of the thin film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and may be combined with each other in the organic light emitting layer to emit light.

[0061] In another embodiment, the light emitting element may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0062] The thin film encapsulation layer TFEL may cover the upper surface and the side surface of the light emitting element layer EML and may protect the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one inorganic film and at least one organic film for encapsulating the light emitting element layer EML.

[0063] The color filter layer CFL may be disposed on the thin film encapsulation layer TFEL. The color filter layer CFL may include a plurality of color filters each corresponding to a plurality of emission regions. Each of the color filters may selectively transmit light of a specific wavelength therethrough and block or absorb light of other wavelengths. The color filter layer CFL may absorb some of the light (e.g., external light) introduced from outside the display device 10 to reduce reflected light caused by the external light. Therefore, the color filter layer CFL may prevent distortion of color due to reflection of external light.

[0064] Since the color filter layer CFL is directly disposed on the thin film encapsulation layer TFEL, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively small.

[0065] In some embodiments, the display device 10 may further include an optical device as a functional component thereof that provides functions to the display device 10. The optical device may emit or receive light in an infrared band, an ultraviolet band, and a visible light band. For example, the optical device may be an optical sensor that senses light incident on the display device 10, such as a proximity sensor, an illumination sensor, a camera sensor, a fingerprint sensor, or an image sensor.

[0066] Figure 3 is a plan view showing a part of the display device 10 according to the embodiment. Figure 3 is a plan view showing the arrangement of the light emitting elements ED1 , ED2 , and ED3 , the lower inorganic encapsulation layers TL1 , TL2 , and TL3 as a pattern of the lower inorganic layer, and the second bank layer BN2 in the display area DA of the display device 10 .

[0067] Reference Figure 3 The second bank layer BN2 may cover the display area DA, but expose a portion (eg, components, layers, etc.) of the display area DA outside the second bank layer BN2. Figure 3 The dotted area in the figure) may be formed in an exposed area not covered by the second bank layer BN2, and the light emitting elements ED1, ED2 and ED3 may be disposed in corresponding openings to be exposed outside the second bank layer BN2.

[0068] The lower inorganic encapsulation layers TL1, TL2, and TL3 may cover the boundary portions of the openings on the second bank layer BN2, and may cover the light emitting elements ED1, ED2, and ED3 within the openings. Portions of the lower inorganic encapsulation layers TL1, TL2, and TL3 covering the boundary portions of the openings on the second bank layer BN2 may be referred to as wing portions.

[0069] exist Figure 3 It has been shown that the exposed area not covered by the second bank layer BN2 has a circular shape in a plan view, but the exposed area not covered by the second bank layer BN2 may have a polygonal shape such as a triangular shape, a quadrilateral shape, or a hexagonal shape in a plan view. The shapes of the lower inorganic encapsulation layers TL1, TL2, and TL3 covering the exposed area and the peripheral portion of the exposed area may also be changed. Portions (wings) of the lower inorganic encapsulation layers TL1, TL2, and TL3 may be disposed at a level (or height) above the second bank layer BN2, and the light-emitting elements ED1, ED2, and ED3 may be disposed at a level below the second bank layer BN2.

[0070] A plurality of light emitting elements ED1, ED2 and ED3 may be arranged as PenTile along the display area DA. ® Type (for example, diamond PenTile ® For example, the first light emitting element ED1 and the third light emitting element ED3 may be arranged to be spaced apart from each other in the first direction DR1, and may be alternately arranged in the first direction DR1 and the second direction DR2. The second light emitting element ED2 may be spaced apart from other adjacent second light emitting elements ED2 in the first direction DR1 and the second direction DR2. The second light emitting element ED2 and the first light emitting element ED1 or the second light emitting element ED2 and the third light emitting element ED3 may be alternately arranged along any direction (such as along an inclined direction) on a plane formed by the first direction DR1 and the second direction DR2. The shape and arrangement of the exposed area not covered by the second bank layer BN2 and the plurality of light emitting elements ED1, ED2, and ED3 are not limited to Figure 3 The shapes and arrangements shown in FIG.

[0071] Figure 4 is a cross-sectional view showing a portion of the display device 10 according to the embodiment. Specifically, Figure 4 It is along Figure 3 A sectional view taken along line II', and showing the Figure 3 The organic encapsulation layer TFE2, the upper inorganic encapsulation layer TFE3, the color filters CF1, CF2 and CF3, the light blocking layer BM and the overcoat layer OC are shown in the plan view. Figure 4 The cross sections of the substrate SUB, the thin film transistor layer TFTL, the light emitting element layer EML, the thin film encapsulation layer TFEL, and the color filter layer CFL are shown.

[0072] The thin film transistor layer TFTL may include a first buffer layer BF1, a bottom metal layer BML, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2. One or more of the above insulating layers may be considered as an "insulating layer".

[0073] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic film capable of preventing air or moisture from penetrating. For example, the first buffer layer BF1 may include a plurality of inorganic films alternately stacked.

[0074] The bottom metal layer BML may be disposed on the first buffer layer BF1. For example, the bottom metal layer BML may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0075] The second buffer layer BF2 may cover the first buffer layer BF1 and the bottom metal layer BML. The second buffer layer BF2 may include an inorganic layer capable of preventing air or moisture from penetrating. For example, the second buffer layer BF2 may include a plurality of inorganic films alternately stacked.

[0076] The thin film transistor TFT may be disposed on the second buffer layer BF2 and may constitute a pixel circuit of each of the plurality of pixels. For example, the thin film transistor TFT may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0077] The semiconductor layer ACT may be disposed on the second buffer layer BF2. The semiconductor layer ACT may overlap the bottom metal layer BML and the gate electrode GE in the thickness direction (eg, the third direction DR3), and may be insulated from the gate electrode GE by the gate insulating layer GI. The material of the semiconductor layer ACT in a portion of the semiconductor layer ACT may become a conductor to form a source electrode SE and a drain electrode DE.

[0078] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor layer ACT in a thickness direction (eg, the third direction DR3) with the gate insulating layer GI interposed therebetween.

[0079] The gate insulating layer GI may be disposed on the semiconductor layer ACT. For example, the gate insulating layer GI may cover the semiconductor layer ACT and the second buffer layer BF2, and may insulate the semiconductor layer ACT and the gate electrode GE from each other. The gate insulating layer GI may include (or define) a contact hole through which the first connection electrode CNE1 passes. That is, the contact hole may be defined in the gate insulating layer GI. As used herein, the contact hole may completely penetrate the thickness of the corresponding layer, such as to open at both the upper surface of the corresponding layer and the lower surface opposite to the upper surface.

[0080] The first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer ILD1 may be connected to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0081] The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1 . The capacitor electrode CPE may overlap the gate electrode GE in a thickness direction (eg, the third direction DR3 ). The capacitor electrode CPE and the gate electrode GE may form a capacitor.

[0082] The second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer insulating layer ILD2 may be connected to the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0083] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT and the second connection electrode CNE2 to each other. The first connection electrode CNE1 may be inserted into a contact hole formed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0084] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may include a contact hole through which the second connection electrode CNE2 passes.

[0085] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 and the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED to each other. The second connection electrode CNE2 may be inserted into a contact hole formed in the first passivation layer PAS1 to contact the first connection electrode CNE1. The first connection electrode CNE1 contacting the second connection electrode CNE2 may form a connection electrode together with the second connection electrode CNE2.

[0086] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may include contact holes through which the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED pass.

[0087] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a light emitting element ED, a pixel defining layer PDL, a capping layer CAP, and a bank structure BNS. The light emitting element ED may include pixel electrodes AE1, AE2, and AE3, light emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3.

[0088] Figure 5 It is shown Figure 4 An enlarged view of the first emission area EA1 (specifically, area A1).

[0089] Apart from Figure 4 In addition, refer to Figure 5 , the display device 10 may include a plurality of emission areas EA1, EA2, and EA3 disposed in the display area DA. The emission areas EA1, EA2, and EA3 may include areas where light is emitted from the light emitting elements ED1, ED2, and ED3 and passes through the color filter layer CFL in the third direction DR3, and pixel electrodes AE1, AE2, and AE3, light emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3 are stacked in the light emitting elements ED1, ED2, and ED3, respectively. The emission areas EA1, EA2, and EA3 may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 that are spaced apart from each other and emit light of the same color or different colors.

[0090] In an embodiment, the areas or sizes of the first to third emission areas EA1, EA2, and EA3 may be the same as each other. For example, in the display device 10, the first to third emission areas EA1, EA2, and EA3 may have the same area (e.g., planar area) in a plan view. However, the present disclosure is not limited to this. In the display device 10, the areas or sizes of the first to third emission areas EA1, EA2, and EA3 may be different from each other. For example, the area of ​​the second emission area EA2 may be larger than the area of ​​the first emission area EA1 and the area of ​​the third emission area EA3, and the area of ​​the third emission area EA3 may be larger than the area of ​​the first emission area EA1. The intensity of light emitted from the emission areas EA1, EA2, and EA3 may be changed according to the areas of the emission areas EA1, EA2, and EA3, and the color sense of the picture displayed on the display device 10 may be controlled by adjusting the areas of the emission areas EA1, EA2, and EA3. Figure 4 In the embodiment of FIG. 5 , it has been illustrated that the areas of the emission areas EA1 , EA2 , and EA3 are the same as each other, but the present disclosure is not limited thereto.

[0091] In the display device 10, one first emission area EA1, one second emission area EA2, and one third emission area EA3 disposed adjacent to each other may form a pixel group. One pixel group may include emission areas EA1, EA2, and EA3 that emit light of different colors to express a white grayscale. However, the present disclosure is not limited thereto, and various modifications may be made to the combination of emission areas EA1, EA2, and EA3 constituting one pixel group according to the arrangement of the emission areas EA1, EA2, and EA3, the color of the light emitted by the emission areas EA1, EA2, and EA3, and the like.

[0092] A plurality of openings (eg, bank openings) formed in the bank structure BNS of the light emitting element layer EML may be defined along boundaries of the emission areas EA1, EA2, and EA3. The bank openings are defined by a material portion (eg, a solid portion) of the bank structure BNS.

[0093] The material portions of the first bank layer BN1 and the second bank layer BN2 of the bank structure BNS may have a planar shape surrounding the emission areas EA1, EA2, and EA3. The bank opening may include the first emission area EA1, the second emission area EA2, and the third emission area EA3. That is, the planar area of ​​the bank opening may include the planar areas of the emission areas EA1, EA2, and EA3, respectively. Each of the bank openings may have a lower thickness portion or a lower volume portion corresponding to the first bank layer BN1 and an upper thickness portion or an upper volume portion corresponding to the second bank layer BN2. The solid portions of the first bank layer BN1 and the second bank layer BN2 together may define a bank, and the bank together with the bank opening may define a bank layer (e.g., a bank structure BNS).

[0094] The display device 10 may include a plurality of light emitting elements ED1, ED2, and ED3 disposed in different emission areas EA1, EA2, and EA3. The light emitting elements ED1, ED2, and ED3 may include a first light emitting element ED1 disposed in a first emission area EA1, a second light emitting element ED2 disposed in a second emission area EA2, and a third light emitting element ED3 disposed in a third emission area EA3.

[0095] The light emitting elements ED1, ED2 and ED3 may include pixel electrodes AE1, AE2 and AE3, light emitting layers EL1, EL2 and EL3, and common electrodes CE1, CE2 and CE3, respectively, and the light emitting elements ED1, ED2 and ED3 disposed in different emission areas EA1, EA2 and EA3 may emit light of different colors, respectively, according to the materials of the light emitting layers EL1, EL2 and EL3. For example, the first light emitting element ED1 disposed in the first emission area EA1 may emit a first light (as red light) having a peak wavelength in the range of about 610 nanometers (nm) to about 650 nm, the second light emitting element ED2 disposed in the second emission area EA2 may emit a second light (as green light) having a peak wavelength in the range of about 510 nm to about 550 nm, and the third light emitting element ED3 disposed in the third emission area EA3 may emit a third light (as blue light) having a peak wavelength in the range of about 440 nm to about 480 nm.

[0096] The first to third emission regions EA1, EA2, and EA3 constituting one pixel may include light emitting elements ED1, ED2, and ED3 that emit light of different colors to represent a white grayscale. Optionally, the light emitting layers EL1, EL2, and EL3 may include two or more materials that emit light of different colors, so that one light emitting layer may emit mixed light. For example, the light emitting layers EL1, EL2, and EL3 may include both a red light emitting material and a green light emitting material to emit yellow light, or may include all of a red light emitting material, a green light emitting material, and a blue light emitting material to emit white light.

[0097] The pixel electrodes AE1, AE2, and AE3 may be disposed on the second passivation layer PAS2. The pixel electrodes AE1, AE2, and AE3 may be disposed in emission areas EA1, EA2, and EA3, respectively. The pixel electrodes AE1, AE2, and AE3 may include a first pixel electrode AE1 disposed in the first emission area EA1, a second pixel electrode AE2 disposed in the second emission area EA2, and a third pixel electrode AE3 disposed in the third emission area EA3. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be disposed to be spaced apart from each other on the second passivation layer PAS2.

[0098] The pixel electrodes AE1, AE2, and AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT through (or via) the first connection electrode CNE1 and the second connection electrode CNE2. The edges of the pixel electrodes AE1, AE2, and AE3 spaced apart from each other may be covered by the pixel defining film PDL so that the first to third pixel electrodes AE1, AE2, and AE3 may be insulated from each other.

[0099] The pixel electrodes AE1, AE2, and AE3 may include a transparent electrode material and / or a conductive metal material. The conductive metal material may be one or more of silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), lanthanum (La), titanium (Ti), and titanium nitride (TiN). The transparent electrode material may be one or more of indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). The pixel electrodes AE1, AE2, and AE3 may have a multilayer structure of a transparent electrode material and a conductive metal material.

[0100] The pixel defining film PDL may be disposed on the second passivation layer PAS2, the residual pattern RP, and the pixel electrodes AE1, AE2, and AE3. The pixel defining film PDL may be entirely disposed on the second passivation layer PAS2 by covering the side surfaces of the pixel electrodes AE1, AE2, and AE3 and the side surfaces of the residual pattern RP, except for the pixel openings corresponding to the light-emitting areas to partially expose portions of the upper surfaces of the pixel electrodes AE1, AE2, and AE3 outside the pixel defining film PDL. For example, at each pixel opening, the pixel defining film PDL may expose the first pixel electrode AE1 in the first emission area EA1, and the first light-emitting layer EL1 may be directly disposed on the exposed portion of the first pixel electrode AE1.

[0101] The pixel defining layer PDL may include an inorganic insulating material. The pixel defining layer PDL may include at least one of a silicon nitride layer, a silicon nitride oxide layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, a tantalum oxide layer, a hafnium oxide layer, a zinc oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0102] According to an embodiment, the pixel defining film PDL may be disposed on the pixel electrodes AE1, AE2, and AE3, but may be spaced apart from the upper surfaces of the pixel electrodes AE1, AE2, and AE3. In the pixel opening, for example, a portion of the pixel defining film PDL may not be in direct contact with the upper surfaces of the pixel electrodes AE1, AE2, and AE3, but may partially overlap with the upper surfaces of the pixel electrodes AE1, AE2, and AE3 in the thickness direction (e.g., the third direction DR3) of the substrate SUB, and a residual pattern RP may be disposed between the pixel defining film PDL and the pixel electrodes AE1, AE2, and AE3. However, at an area adjacent to the light emitting area, the side wall of the pixel defining film PDL may be in direct contact with the side surfaces of the pixel electrodes AE1, AE2, and AE3.

[0103] The side surface of the pixel definition film PDL defines a pixel opening, and the side surface of the bank structure BNS defines a bank opening. The opening may have a thickness portion (or volume portion) arranged along a thickness direction (e.g., a third direction DR3) and corresponding to various material layers (e.g., the pixel definition film PDL, the first bank layer BN1, the second bank layer BN2, etc.). Figure 5 and Figure 6 , for example, a side surface of the pixel defining film PDL at the upper thickness portion may protrude farther than a side surface of the second bank layer BN2 at the upper thickness portion of the bank structure BNS in a direction toward the emission areas EA1, EA2, and EA3.

[0104] The residual patterns RP may be disposed on edges of the pixel electrodes AE1, AE2, and AE3, respectively. Since the residual patterns RP are disposed between the pixel defining films PDL and the upper surfaces of the pixel electrodes AE1, AE2, and AE3, respectively, at regions adjacent to the light emitting regions along the pixel openings, the pixel defining films PDL may not be in direct contact with the upper surfaces of the pixel electrodes AE1, AE2, and AE3.

[0105] In an embodiment, the sacrificial layer SFL (see FIG. 1 ) disposed on the pixel electrodes AE1, AE2, and AE3 may be removed during a process for manufacturing (or providing) the display device 10. Fig.11 ) to form a residual pattern RP. The residual pattern RP may include a metal or oxide semiconductor material. Although the accompanying drawings only show the case where the side surface of the residual pattern RP closest to the emission areas EA1, EA2, and EA3 is aligned with the side surface of the pixel defining film PDL, the present disclosure is not limited thereto. The side surface of the residual pattern RP closest to each emission area EA1, EA2, and EA3 may protrude much more than the side surface of the pixel defining film PDL closest to the emission areas EA1, EA2, and EA3, or may be much more recessed than the side surface of the pixel defining film PDL.

[0106] The light-emitting layers EL1, EL2 and EL3 may be disposed on the pixel electrodes AE1, AE2 and AE3, respectively. The light-emitting layers EL1, EL2 and EL3 may be organic light-emitting layers made of (or including) an organic material, and may be formed on the pixel electrodes AE1, AE2 and AE3, respectively, by a deposition process. The light-emitting layers EL1, EL2 and EL3 may have a multilayer structure, and hole injection materials, hole transport materials, light-emitting materials, electron transport materials and / or electron injection materials may constitute the layers of the light-emitting layers EL1, EL2 and EL3, respectively. When the thin film transistor TFT applies a predetermined voltage to the pixel electrodes AE1, AE2 and AE3 of the light-emitting elements ED1, ED2 and ED3 and the common electrodes CE1, CE2 and CE3 of the light-emitting elements ED1, ED2 and ED3 receive a common voltage or a cathode voltage, holes and electrons may be injected and transported, respectively, and may be recombined with each other in the light-emitting layers EL1, EL2 and EL3 to emit light.

[0107] The light-emitting layers EL1, EL2, and EL3 may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3, each of which is disposed in different emission areas EA1, EA2, and EA3. The first light-emitting layer EL1 may be disposed on the first pixel electrode AE1 in the first emission area EA1, the second light-emitting layer EL2 may be disposed on the second pixel electrode AE2 in the second emission area EA2, and the third light-emitting layer EL3 may be disposed on the third pixel electrode AE3 in the third emission area EA3. The plurality of light-emitting layers EL1, EL2, and EL3 may emit light of different colors, respectively, or one light-emitting layer EL1, EL2, or EL3 may emit mixed light. In an embodiment, the first light-emitting layer EL1 may emit red light, the second light-emitting layer EL2 may emit green light, and the third light-emitting layer EL3 may emit blue light. In another embodiment, the first light-emitting layer EL1 may emit yellow light as a mixed light of red light and green light, and the second light-emitting layer EL2 may emit blue light. In yet another embodiment, the first light-emitting layer EL1 may emit white light, which is a mixed light of red light, green light, and blue light.

[0108] The light-emitting layers EL1, EL2, and EL3 may be disposed on the upper surface of the pixel-defining film PDL. In an embodiment, the light-emitting layers EL1, EL2, and EL3 may be disposed in a space or gap defined between the lower surface of the common electrodes CE1, CE2, and CE3 and the upper surface of the pixel-defining film PDL, respectively, and the lower surfaces of the common electrodes CE1, CE2, and CE3 and the upper surface of the pixel-defining film PDL face each other in an area adjacent to the corresponding emission area. In an embodiment, the light-emitting layers EL1, EL2, and EL3 may be in contact with each of the upper surfaces of the pixel electrodes AE1, AE2, and AE3, the pixel-defining film PDL, and the residual pattern RP, which respectively form a space or gap opened toward the corresponding emission area.

[0109] The common electrodes CE1, CE2, and CE3 may be disposed on the light emitting layers EL1, EL2, and EL3, respectively. The common electrodes CE1, CE2, and CE3 may include a transparent conductive material to emit light generated from the light emitting layers EL1, EL2, and EL3. The common electrodes CE1, CE2, and CE3 may receive a common voltage or a low potential voltage. When the pixel electrodes AE1, AE2, and AE3 receive a voltage corresponding to the data voltage and the common electrodes CE1, CE2, and CE3 receive a low potential voltage, a potential difference is formed between the pixel electrodes AE1, AE2, and AE3 and the common electrodes CE1, CE2, and CE3, so that the light emitting layers EL1, EL2, and EL3 may emit light.

[0110] The common electrodes CE1, CE2, and CE3 may include a first common electrode CE1, a second common electrode CE2, and a third common electrode CE3, each of which is disposed in different emission areas EA1, EA2, and EA3. The first common electrode CE1 may be disposed on the first light emitting layer EL1 in the first emission area EA1, the second common electrode CE2 may be disposed on the second light emitting layer EL2 in the second emission area EA2, and the third common electrode CE3 may be disposed on the third light emitting layer EL3 in the third emission area EA3. The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be spaced apart from each other.

[0111] The covering layers CAP1, CAP2, and CAP3 as patterns within the covering layer may be disposed on the common electrodes CE1, CE2, and CE3, respectively. The covering layers CAP1, CAP2, and CAP3 may include an organic insulating material or an inorganic insulating material and a covering pattern disposed on the light emitting elements ED1, ED2, and ED3. The covering layers CAP1, CAP2, and CAP3 may prevent the light emitting elements ED1, ED2, and ED3 from being damaged by external air. In an embodiment, each of the covering layers CAP1, CAP2, and CAP3 may include a conductive material such as α-NPD, NPB, TPD, m-MTDATA, Alq 3 , LiF and / or CuPc, or an inorganic material such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and / or silicon oxynitride.

[0112] The capping layers CAP1, CAP2, and CAP3 may include first, second, and third capping layers CAP1, CAP2, and CAP3, respectively disposed in different emission areas EA1, EA2, and EA3. The first to third capping layers CAP1, CAP2, and CAP3 may be spaced apart from each other in a direction along the thin film transistor layer TFTL.

[0113] The display device 10 may include a plurality of dam structures BNS or dams disposed on the pixel definition film PDL. The dam structure BNS may have a structure in which dam layers BN1 and BN2 including different materials are sequentially stacked, may define a plurality of openings of a plane area including emission areas EA1, EA2, and EA3, and may be disposed to overlap with a light blocking layer BM to be described later. The light emitting elements ED1, ED2, and ED3 of the display device 10 may be disposed to overlap with the openings of the dam structure BNS.

[0114] The bank structure BNS may include a first bank layer BN1 and a second bank layer BN2 sequentially stacked on the pixel defining layer PDL.

[0115] The first bank layer BN1 may be disposed on the pixel defining film PDL. The inner side surface of the lower portion of the first bank layer BN1 defining the bank opening may be recessed from the inner side surface of the pixel defining film PDL defining the corresponding emission area in a direction opposite to the direction toward the emission areas EA1, EA2, and EA3 (for example, in a direction away from the corresponding emission area). The inner side surface of the first bank layer BN1 may be recessed from the inner side surface of the upper portion of the second bank layer BN2 defining the bank opening to be described later in a direction opposite to the direction toward the emission areas EA1, EA2, and EA3. The upper portion of the bank opening at the second bank layer BN2 and the lower portion of the bank opening at the first bank layer BN1 may together define the bank opening.

[0116] According to an embodiment, the first bank layer BN1 may include a metal material. In an embodiment, the first bank layer BN1 may include aluminum (Al) or an alloy of aluminum (Al).

[0117] In an embodiment, the thickness of the first bank layer BN1 may be in the range of 4000 angstroms (Å) to about 7000 Å. When the thickness of the first bank layer BN1 is within the above range, the light emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 spaced apart from each other in a direction parallel to the display panel DP may be formed by a deposition process and an etching process instead of a mask process.

[0118] According to an embodiment, the common electrodes CE1, CE2 and CE3 may be in direct contact with the inner surface of the first bank layer BN1. The common electrodes CE1, CE2 and CE3 of different light emitting elements ED1, ED2 and ED3 may be in direct contact with the first bank layer BN1, respectively, and the first bank layer BN1 may include a metal material so that the common electrodes CE1, CE2 and CE3 may be electrically connected to each other through the first bank layer BN1.

[0119] The light-emitting layers EL1, EL2, and EL3 may be in direct contact with the inner surface of the first bank layer BN1. The light-emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 may contact the inner surface at the contact region. The contact region may be a plane region defined in a plane including the third direction DR3 and another direction (such as the first direction DR1 and / or the second direction DR2) intersecting the third direction DR3. The contact area between the common electrodes CE1, CE2, and CE3 and the inner surface of the first bank layer BN1 may be greater than the contact area between the light-emitting layers EL1, EL2, and EL3 and the inner surface of the first bank layer BN1. The common electrodes CE1, CE2, and CE3 may be arranged to have a contact area greater than that of the light-emitting layers EL1, EL2, and EL3 along the inner surface of the first bank layer BN1, or may be further extended in the thickness direction (e.g., the third direction DR3) from the arranged pixel electrodes AE1, AE2, and AE3 along the inner surface of the first bank layer BN1 to a height greater than that of the light-emitting layers EL1, EL2, and EL3. Since the common electrodes CE1, CE2, and CE3 of the different light emitting elements ED1, ED2, and ED3 are electrically connected to each other through the first bank layer BN1, it may be advantageous for the common electrodes CE1, CE2, and CE3 to contact the first bank layer BN1 with a larger plane area.

[0120] The second bank layer BN2 may be disposed on the first bank layer BN1. The second bank layer BN2 may include or define a tip TIP, which is a region protruding from the inner side surface of the first bank layer BN1 at each of the light emitting regions. A side surface (e.g., inner side surface) of the second bank layer BN2 may protrude from a side surface (e.g., inner side surface) of the first bank layer BN1 in a direction toward the emission regions EA1, EA2, and EA3.

[0121] The side surface of the second bank layer BN2 has a shape in which the side surface of the second bank layer BN2 protrudes further toward the emission areas EA1, EA2, and EA3 than the side surface of the first bank layer BN1. Therefore, the undercut structure of the first bank layer BN1 can be formed by the tip TIP of the second bank layer BN2 relative to the side surface of the first bank layer BN1.

[0122] In the display device 10 according to the embodiment, the embankment structure BNS includes a tip TIP protruding toward the emission areas EA1, EA2, and EA3, so that the light-emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 can be formed by a deposition process and an etching process instead of a mask process. In addition, different layers can be formed separately in different emission areas EA1, EA2, and EA3 even by a deposition process. For example, even if discrete patterns of the light-emitting layers EL1, EL2, and EL3 of the light-emitting elements ED1, ED2, and ED3 and discrete patterns of the common electrodes CE1, CE2, and CE3 are formed by a deposition process without using a mask, the deposited material layers can be disconnected by the tip TIP of the second embankment layer BN2 and the embankment structure BNS is placed between the deposited material layers, rather than being connected to each other at the area between the emission areas EA1, EA2, and EA3.

[0123] Different layers can be formed separately at patterns in different emission areas EA1, EA2, and EA3, such as by forming a material layer for forming a specific layer on the entire surface of the display device 10, and then etching and removing the portion of the material layer formed in the unnecessary area. In the display device 10 according to one or more embodiments of the invention, a discrete pattern of different light-emitting elements ED1, ED2, and ED3 can be formed for each of the emission areas EA1, EA2, and EA3 through a deposition process and an etching process without using a mask process, unnecessary components can be omitted from the display device 10, and the area of ​​the non-display area NDA can be minimized.

[0124] Since the first bank layer BN1 and the second bank layer BN2 include different materials, the side surface shape of the bank structure BNS in the cross section may be a structure formed due to the difference in etching rates between the materials forming the first bank layer BN1 and the second bank layer BN2 in the etching process. According to an embodiment, the second bank layer BN2 may include a material having an etching rate slower than that of the first bank layer BN1, and in the etching process, the first bank layer BN1 may be further etched compared to the second bank layer BN2, so that the lower surface of the tip TIP of the second bank layer BN2 forming the second bank layer BN2 may be exposed at the bank opening, and an undercut may be formed by the tip TIP of the second bank layer BN2 together with the first bank layer BN1.

[0125] The second bank layer BN2 may include a metal material different from the metal material of the first bank layer BN1. The metal material of the second bank layer BN2 may be any material that is removed together with the metal material of the first bank layer BN1 by dry etching but has an etching rate much slower than that of the first bank layer BN1 or is not etched relative to wet etching. In an embodiment, the first bank layer BN1 may include aluminum (Al) or an alloy of aluminum (Al), and the second bank layer BN2 may include titanium (Ti) or an alloy of titanium (Ti).

[0126] At the embankment opening of the embankment structure BNS, the tip TIP of the second embankment layer BN2 may overlap with the common electrodes CE1, CE2, and CE3 in the third direction DR3 perpendicular to the substrate SUB. In addition, the tip TIP of the second embankment layer BN2 may overlap with the light-emitting layers EL1, EL2, and EL3 in the third direction DR3 perpendicular to the substrate SUB. In addition, the tip TIP of the second embankment layer BN2 may overlap with the pixel definition film PDL in the third direction DR3 perpendicular to the substrate SUB. The common electrodes CE1, CE2, and CE3 may be formed below the lower surface of the tip TIP of the second embankment layer BN2. The first end of the common electrodes CE1, CE2, and CE3 and the second end opposite to the first end may overlap with the second embankment layer BN2 in the thickness direction of the substrate (e.g., the third direction DR3). The maximum vertical distance from the substrate SUB to each of the common electrodes CE1, CE2, and CE3 may be less than the maximum vertical distance from the substrate SUB to the second embankment layer BN2.

[0127] The thin film encapsulation layer TFEL may be disposed on the light emitting elements ED1, ED2, and ED3 and the embankment structure BNS, and may cover the plurality of light emitting elements ED1, ED2, and ED3 and the embankment structure BNS. The thin film encapsulation layer TFEL may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one organic film to protect the light emitting element layer EML from foreign matter such as dust.

[0128] In embodiments, the thin film encapsulation layer TFEL may include a lower inorganic encapsulation layer TFE1 (eg, a lower inorganic layer), an organic encapsulation layer TFE2 (eg, an organic layer), and an upper inorganic encapsulation layer TFE3 (eg, an upper inorganic layer) which are sequentially stacked.

[0129] Each of the lower inorganic encapsulation layer TFE1 and the upper inorganic encapsulation layer TFE3 may include one or more inorganic insulating materials, such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0130] The organic encapsulation layer TFE2 may include a polymer material. The polymer material may include acrylic resin, epoxy resin, polyimide, polyethylene, etc. For example, the organic encapsulation layer TFE2 may include an acrylic resin such as polymethyl methacrylate or polyacrylic acid. The organic encapsulation layer TFE2 may be formed by curing a monomer or applying a polymer.

[0131] The inorganic pattern of the lower inorganic encapsulation layer TFE1 may be disposed on the light emitting elements ED1, ED2, and ED3 and the embankment structure BNS. The lower encapsulation layer TFE1 may include a first inorganic layer TL1 (e.g., a first inorganic pattern), a second inorganic layer TL2 (e.g., a second inorganic pattern), and a third inorganic layer TL3 (e.g., a third inorganic pattern) disposed to correspond to different emission areas EA1, EA2, and EA3, respectively. The first inorganic layer TL1 as the first inorganic pattern, the second inorganic layer TL2 as the second inorganic pattern, and the third inorganic layer TL3 as the third inorganic pattern may include an inorganic insulating material and may cover the light emitting elements ED1, ED2, and ED3, respectively. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may prevent the light emitting elements ED1, ED2, and ED3 from being damaged by external air.

[0132] The lower inorganic encapsulation layer TFE1 may be formed (or disposed) by chemical vapor deposition (CVD) and may thus be formed along the steps of the layers on which they are deposited. For example, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may even form a thin film below the undercut defined by the tip TIP of the bank structure BNS. The lower inorganic encapsulation layers TL1, TL2, and TL3 may be disposed along the upper surface, side surface, and bottom surface of the second bank layer BN2, the side surface of the first bank layer BN1, and the upper surface of the common electrodes CE1, CE2, and CE3.

[0133] The first inorganic layer TL1 may not overlap with the second bank opening and the third bank opening, and may be provided only in the first bank opening and on the first light-emitting element ED1 and along the region of the bank structure BNS adjacent to the first bank opening and extending around the first bank opening. The second inorganic layer TL2 may not overlap with the first bank opening and the third bank opening, and may be provided only in the second bank opening and on the second light-emitting element ED2 and along the region of the bank structure BNS adjacent to the second bank opening and extending around the second bank opening. The third inorganic layer TL3 may not overlap with the first bank opening and the second bank opening, and may be provided only in the third bank opening and on the third light-emitting element ED3 and along the region of the bank structure BNS adjacent to the third opening and extending around the third opening.

[0134] The first inorganic layer TL1 may be formed after forming the first common electrode CE1, the second inorganic layer TL2 may be formed after forming the second common electrode CE2, and the third inorganic layer TL3 may be formed after forming the third common electrode CE3. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may be disposed to be spaced apart from each other in a direction along the bank structure BNS.

[0135] The lower inorganic encapsulation layers TL1, TL2, and TL3 may include body portions TL1_B, TL2_B, and TL3_B surrounded by the bank structure BNS, and wing portions TL1_W, TL2_W, and TL3_W protruding from the body portions TL1_B, TL2_B, and TL3_B and spaced apart from the upper surface of the second bank layer BN2, respectively (see, for example, FIG. Fig.23 ).

[0136] The body portions TL1_B, TL2_B and TL3_B of the lower inorganic encapsulation layers TL1, TL2 and TL3 may cover the lower surface of the second bank layer BN2, the side surface of the first bank layer BN1, the capping layers CAP1, CAP2 and CAP3, and the common electrodes CE1, CE2 and CE3, and may include a portion surrounded by the bank structure BNS.

[0137] The wing portions TL1_W, TL2_W, and TL3_W of the lower inorganic encapsulation layers TL1, TL2, and TL3 may include a portion overlapping the second bank layer BN2 above the second bank layer BN2 and a portion facing the side surface of the second bank layer BN2. The lower inorganic encapsulation layers TL1, TL2, and TL3 may respectively include or define first surfaces TL1_W_S1, TL2_W_S1, and TL3_W_S1 facing the upper surface of the second bank layer BN2 and second surfaces TL1_W_S2, TL2_W_S2, and TL3_W_S2 extending from the respective first surfaces and facing the side surface of the second bank layer BN2 (e.g., see Fig.23 ). The first surfaces TL1_W_S1, TL2_W_S1, and TL3_W_S1 of the lower inorganic encapsulation layers TL1, TL2, and TL3 may be lower surfaces defining the wing portions TL1_W, TL2_W, and TL3_W. The second surfaces TL1_W_S2, TL2_W_S2, and TL3_W_S2 of the lower inorganic encapsulation layers TL1, TL2, and TL3 may be connection surfaces connecting the first surfaces TL1_W_S1, TL2_W_S1, and TL3_W_S1 to the body portions TL1_B, TL2_B, and TL3_B, respectively.

[0138] The auxiliary layers AXL1, AXL2, and AXL3 may be disposed between the light emitting elements ED1, ED2, and ED3 and the lower inorganic encapsulation layers TL1, TL2, and TL3 and between the second bank layer BN2 and the lower inorganic encapsulation layers TL1, TL2, and TL3. The auxiliary layers AXL1, AXL2, and AXL3 may cover the outer surfaces of various layers exposed to the light emitting region (e.g., within the opening formed by the bank structure BNS). That is, the auxiliary layers AXL1, AXL2, and AXL3 may be disposed on the upper surfaces of the common electrodes CE1, CE2, and CE3 or the cover layers CAP1, CAP2, and CAP3, the side surfaces of the first bank layer BN1, and the lower surface of the second bank layer BN2 at the tip TIP. The coverage of the auxiliary layers AXL1, AXL2, and AXL3 may be greater than that of the light emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3.

[0139] The auxiliary layers AXL1, AXL2, and AXL3 may include first, second, and third auxiliary layers AXL1, AXL2, and AXL3 disposed in different emission areas EA1, EA2, and EA3, respectively. The first to third auxiliary layers AXL1, AXL2, and AXL3 may be spaced apart from each other.

[0140] The auxiliary layers AXL1, AXL2, and AXL3 may extend from the lower surface of the second bank layer BN2 at the tip TIP to be disposed along the wing portions of the lower inorganic encapsulation layers TL1, TL2, and TL3. The auxiliary layers AXL1, AXL2, and AXL3 may extend at least along the outer surfaces of the body portions TL1_B, TL2_B, and TL3_B to be disposed within the bank opening. In an embodiment, the auxiliary layers AXL1, AXL2, and AXL3 may extend out of the bank opening and along the outer surface of the lower inorganic pattern, as described below.

[0141] Figures 5 to 8 Auxiliary layers AXL1 , AXL2 and AXL3 according to embodiments are respectively shown. Figures 5 to 8 The auxiliary layers AXL1, AXL2, and AXL3 may have differences in surface areas of the auxiliary layers AXL1, AXL2, and AXL3 disposed on the first surfaces TL1_W_S1, TL2_W_S1, and TL3_W_S1 and the second surfaces TL1_W_S2, TL2_W_S2, and TL3_W_S2 of the lower inorganic encapsulation layers TL1, TL2, and TL3.

[0142] Figure 5 It is shown Figure 4 An enlarged view of the first emission area EA1 (specifically, area A1). Figure 5, the auxiliary layers AXL1, AXL2, and AXL3 may cover the entire first surfaces TL1_W_S1, TL2_W_S1, and TL3_W_S1 and the entire second surfaces TL1_W_S2, TL2_W_S2, and TL3_W_S2 of the lower inorganic encapsulation layers TL1, TL2, and TL3, respectively. Here, the outer edges (or outer surfaces) of the auxiliary layers AXL1, AXL2, and AXL3 may coincide with the outer edges (or outer surfaces) of the lower inorganic patterns in the lower inorganic layer (e.g., the lower inorganic encapsulation layer TFE1) (such as being coplanar with the outer edges (or outer surfaces) of the lower inorganic patterns in the lower inorganic layer (e.g., the lower inorganic encapsulation layer TFE1)).

[0143] Figure 6 is shown with Figure 4 The first emission area EA1 and the enlarged view of the area A1_1 corresponding to the area A1. Figure 6 , the auxiliary layers AXL1, AXL2, and AXL3 represented by the auxiliary layer AXL1_1 may cover the interior of the first surfaces TL1_W_S1, TL2_W_S1, and TL3_W_S1 of the lower inorganic encapsulation layers TL1, TL2, and TL3, respectively, and the entire second surfaces TL1_W_S2, TL2_W_S2, and TL3_W_S2. Here, the outer edges of the auxiliary layers AXL1, AXL2, and AXL3 may not overlap with the outer edges of the lower inorganic patterns in the lower inorganic layer (e.g., the lower inorganic encapsulation layer TFE1). Alternatively, the distal ends of the auxiliary layers AXL1, AXL2, and AXL3, which are respectively farthest from the light emitting regions, may be spaced apart from (or recessed from) the outer edges of the lower inorganic patterns. Lower surfaces of the lower inorganic patterns (eg, portions of the first surfaces TL1_W_S1 , TL2_W_S1 , and TL3_W_S1 ) may be exposed outside auxiliary patterns of the auxiliary layers (eg, auxiliary layers AXL1 , AXL2 , and AXL3 ) as exposed portions of the lower inorganic patterns.

[0144] Figure 7 is shown with Figure 4 The enlarged view of the first emission area EA1 and the area A1_2 corresponding to the area A1. Figure 7, the auxiliary layers AXL1, AXL2, and AXL3 represented by the auxiliary layer AXL1_2 may not cover the first surfaces TL1_W_S1, TL2_W_S1, and TL3_W_S1 of the lower inorganic encapsulation layers TL1, TL2, and TL3, respectively, and may cover all or part of the second surfaces TL1_W_S2, TL2_W_S2, and TL3_W_S2 of the lower inorganic encapsulation layers TL1, TL2, and TL3, respectively. Here, the entire first surfaces TL1_W_S1, TL2_W_S1, and TL3_W_S1 are exposed outside the auxiliary pattern of the auxiliary layers (e.g., the auxiliary layers AXL1, AXL2, and AXL3) to define the exposed portion of the lower inorganic pattern.

[0145] Figure 8 is shown with Figure 4 The first emission area EA1 and the enlarged view of the area A1_3 corresponding to the area A1. Figure 8 , the auxiliary layers AXL1, AXL2, and AXL3 represented by the auxiliary layer AXL1_3 may not be disposed on the first surfaces TL1_W_S1, TL2_W_S1, and TL3_W_S1 and the second surfaces TL1_W_S2, TL2_W_S2, and TL3_W_S2 of the lower inorganic encapsulation layers TL1, TL2, and TL3, respectively. The auxiliary layers AXL1, AXL2, and AXL3 may be disposed only on the lower surface of the second bank layer BN2 at the tip TIP and along the inorganic body (e.g., the body parts TL1_B, TL2_B, and TL3_B). In an embodiment, the auxiliary layers AXL1, AXL2, and AXL3 may optionally be disposed on the first surfaces TL1_W_S1, TL2_W_S1, and TL3_W_S1 and the second surfaces TL1_W_S2, TL2_W_S2, and TL3_W_S2 of the lower inorganic encapsulation layers TL1, TL2, and TL3, respectively.

[0146] The contact areas of the auxiliary layers AXL1 , AXL2 , and AXL3 with respect to the lower inorganic pattern may be adjusted by controlling the wet etching of the auxiliary layers AXL1 , AXL2 , and AXL3 .

[0147] In an embodiment of the display panel DP, a first light emitting layer EL1, a first common electrode CE1, a first auxiliary layer AXL1, a first cover layer CAP1, and a first inorganic layer TL1 are formed in the first emission area EA1 to define a first stacked structure (eg, Fig.18), a second light emitting layer EL2, a second common electrode CE2, a second auxiliary layer AXL2, and a second inorganic layer TL2 may be formed in the second emission area EA2. In this case, the respective material layers are deposited across the entire substrate SUB having the first stacked structure thereon, such as to arrange a second light emitting pattern layer ELP2, a second electrode pattern layer CEP2, a second auxiliary material layer AXLL2, a second covering pattern layer CPP2, and a second inorganic material layer TLL2 on the first inorganic layer TL1 covering the first emission area EA1 and the periphery of the first emission area EA1 (for example, Fig.19 ).

[0148] The second light-emitting pattern layer ELP2 may be made of the same material as the second light-emitting layer EL2, the second electrode pattern layer CEP2 may be made of the same material as the second common electrode CE2, the second cover layer CAP2 may be made of the same material as the second cover pattern layer CPP2, and the second auxiliary material layer AXLL2 may be made of the same material as the second auxiliary layer AXL2. That is, the second light-emitting pattern layer ELP2 and the second light-emitting layer EL2, the second electrode pattern layer CEP2 and the second common electrode CE2, the second cover layer CAP2 and the second cover pattern layer CPP2, and the second auxiliary material layer AXLL2 and the second auxiliary layer AXL2 may be respectively in the same layer with each other. Since in the same layer, the elements may be formed in the same process and / or include the same material with each other, the elements may be corresponding parts of the same material layer, and the elements may be located in the same layer by forming an interface with the same lower layer or upper layer, etc., without being limited thereto.

[0149] Fig. 9 is an enlarged cross-sectional view showing penetration of an etchant into the light emitting elements ED1 , ED2 , and ED3 when there are no auxiliary layers AXL1 , AXL2 , and AXL3 . Fig.10 is an enlarged cross-sectional view showing that penetration of an etchant is prevented by the auxiliary layers AXL1 , AXL2 , and AXL3 .

[0150] like Fig. 9 As shown in FIG, due to the undercut structure below the wing TL1_W of the first inorganic layer TL1, a gap is defined between the wing TL1_W of the first inorganic layer TL1 and the region of the second bank layer BN2 closest to the first emission region EA1. The entrance of the gap is defined at the outer edge (eg, boundary) of the first inorganic layer TL1.

[0151] like Fig. 9As shown in , when the material portions of the auxiliary layers AXL1, AXL2, and AXL3 are not respectively disposed between the lower surface of the second bank layer BN2 and the lower inorganic encapsulation layers TL1, TL2, and TL3, due to the undercut structure below the wing portion TL1_W of the first inorganic layer TL1, the second light emitting pattern layer ELP2, the second electrode pattern layer CEP2, and the second covering pattern layer CPP2 are disconnected from each other at the boundary of the first inorganic layer TL1 and have a gap formed therebetween. After the second inorganic material layer TLL2 is formed above the stacked structure of the lower layer, a portion of the second inorganic material layer TLL2 that is only disposed in and around the second emission region EA2 is retained as the second inorganic layer TL2, and the other portions of the second inorganic material layer TLL2 that are disposed in the remaining region are removed by an etching process.

[0152] In the etching process, radicals of the etchant used to remove the other portions of the second inorganic material layer TLL2 may penetrate into the gap and penetrate under the tip TIP. Fig. 9 , for example, free radicals that penetrate into the gap (see Fig. 9 The first inorganic layer TL1 is formed by a wing portion TL1_W and a second bank layer BN2, and then passes through or through the lower surface of the second bank layer BN2 to remove the edge portion of the first inorganic layer TL1 defining the first bank opening, and weaken the adhesion or encapsulation between the bank structure BNS and the first inorganic layer TL1 at the first bank opening. This may cause moisture penetration or damage to the first light-emitting element ED1, resulting in dark spots in the display device 10.

[0153] On the contrary, Fig.10 As shown in , when the auxiliary layers AXL1, AXL2 and AXL3 are respectively arranged between the lower surface of the second bank layer BN2 and the lower inorganic encapsulation layers TL1, TL2 and TL3, the penetration of free radicals of the etchant between the lower surface of the second bank layer BN2 and the first inorganic layer TL1 can be prevented. Here, the auxiliary pattern effectively covers the inner surface of the first bank layer BN1 and the lower surface of the tip TIP to prevent the etchant from contacting the bank structure BNS and the lower inorganic pattern. The first inorganic layer TL1 may not be exposed to the etchant, and damage to the first light-emitting element ED1 may be prevented. In addition, since the pattern portions of the auxiliary layers AXL1, AXL2 and AXL3 are retained in the final stacked structure, moisture can be prevented from penetrating from the outside air at least within the bank opening and along the surface exposed to the bank opening, and the brightness difference between the light-emitting elements ED1, ED2 and ED3 can be reduced.

[0154] In embodiments, the auxiliary layers AXL1 , AXL2 , and AXL3 may be in contact with a lower surface of the second bank layer BN2 and a side surface of the first bank layer BN1 .

[0155] The auxiliary layers AXL1, AXL2 and AXL3 may be formed by a sputtering process. The thicknesses of the auxiliary layers AXL1, AXL2 and AXL3 may be different from each other depending on the direction along which the materials of the auxiliary layers AXL1, AXL2 and AXL3 are provided. The thickness of the material layer may be defined at various locations of the surface of the underlying layer along which the material layer extends in a direction orthogonal to the surface of such underlying layer.

[0156] The first thickness d1 of the auxiliary layers AXL1, AXL2 and AXL3 relative to the upper surface of the cover layers CAP1, CAP2 and CAP3 and the second thickness d2 of the auxiliary layers AXL1, AXL2 and AXL3 relative to the lower surface of the second bank layer BN2 may be different from each other. The third thickness d3 of the auxiliary layers AXL1, AXL2 and AXL3 relative to the first surfaces TL1_W_S1, TL2_W_S1 and TL3_W_S1 of the lower inorganic encapsulation layers TL1, TL2 and TL3 and the second thickness d2 of the auxiliary layers AXL1, AXL2 and AXL3 relative to the lower surface of the second bank layer BN2 may be different from each other. A first thickness d1 of the auxiliary layers AXL1, AXL2 and AXL3 relative to the upper surfaces of the cover layers CAP1, CAP2 and CAP3 and a third thickness d3 of the auxiliary layers AXL1, AXL2 and AXL3 relative to the first surfaces TL1_W_S1, TL2_W_S1 and TL3_W_S1 of the lower inorganic encapsulation layers TL1, TL2 and TL3 may be the same as or similar to each other.

[0157] The second thickness d2 of the auxiliary layers AXL1, AXL2 and AXL3 relative to the lower surface of the second bank layer BN2 may be very small. The auxiliary layers AXL1, AXL2 and AXL3 on the lower surface of the second bank layer BN2 may have a form in which material particles constituting the auxiliary layers AXL1, AXL2 and AXL3 may be retained on the lower surface of the second bank layer BN2, and the density of these material particles may be very low. On the other hand, the first thickness d1 of the auxiliary layers AXL1, AXL2 and AXL3 relative to the upper surface of the cover layers CAP1, CAP2 and CAP3 or the third thickness d3 of the auxiliary layers AXL1, AXL2 and AXL3 relative to the first surfaces TL1_W_S1, TL2_W_S1 and TL3_W_S1 of the lower inorganic encapsulation layers TL1, TL2 and TL3 may be relatively greater than the second thickness d2 of the first auxiliary layer AXL1 relative to the lower surface of the second bank layer BN2.

[0158] The auxiliary layers AXL1, AXL2, and AXL3 may include a transparent conductive oxide (TCO). The material of the transparent conductive oxide (TCO) may be one or more of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc indium tin oxide (ZITO), indium gallium zinc oxide (IGZO), and zinc tin oxide (ZTO), and may be mixed with some metal or silicon. The transparent conductive oxide (TCO) included in the auxiliary layers AXL1, AXL2, and AXL3 may be amorphous.

[0159] The arrangements of the first to third auxiliary layers AXL1, AXL2, and AXL3 along the first surfaces TL1_W_S1, TL2_W_S1, and TL3_W_S1 of the lower inorganic encapsulation layers TL1, TL2, and TL3 and along the second surfaces TL1_W_S2, TL2_W_S2, and TL3_W_S2 of the lower inorganic encapsulation layers TL1, TL2, and TL3 may be the same as or different from each other. The first auxiliary layer AXL1, the second auxiliary layer AXL2, and the third auxiliary layer AXL3 may all have the following structure: Figure 6 Alternatively, the first auxiliary layer AXL1 may be formed as shown in FIG. Figure 6 As shown in FIG. 1 , the second auxiliary layer AXL2 can be Figure 7 As shown in FIG. 1 , the third auxiliary layer AXL3 can be Figure 8 The settings are shown in .

[0160] The organic encapsulation layer TFE2 may be disposed on the second bank layer BN2 and the lower inorganic encapsulation layers TL1, TL2, and TL3. A portion of the organic encapsulation layer TFE2 may be disposed within the gap between the upper surface of the second bank layer BN2 and the wing portions TL1_W, TL2_W, and TL3_W of the lower inorganic encapsulation layers TL1, TL2, and TL3. When the auxiliary layers AXL1, AXL2, and AXL3 are disposed on the first surfaces TL1_W_S1, TL2_W_S1, and TL3_W_S1 of the lower inorganic encapsulation layers TL1, TL2, and TL3, respectively, a portion of the organic encapsulation layer TFE2 may be disposed at the gap between the auxiliary layers AXL1, AXL2, and AXL3 and the upper surface of the second bank layer BN2.

[0161] The organic encapsulation layer TFE2 may be in contact with the second bank layer BN2. The second bank layer BN2 in the region overlapping with the light-emitting layers EL1, EL2, and EL3 in the thickness direction (e.g., the third direction DR3) of the substrate SUB may be in contact with the organic encapsulation layer TFE2 in the region adjacent to the light-emitting region. The second bank layer BN2 in the region overlapping with the wings TL1_W, TL2_W, and TL3_W of the lower inorganic encapsulation layers TL1, TL2, and TL3 in the thickness direction (e.g., the third direction DR3) of the substrate SUB may be in contact with the organic encapsulation layer TFE2 in the region adjacent to the light-emitting region.

[0162] Portions of the organic encapsulation layer TFE2 may be disposed between second surfaces TL1_W_S2, TL2_W_S2, and TL3_W_S2 of the lower inorganic encapsulation layers TL1, TL2, and TL3, respectively, and side surfaces of the second bank layer BN2. Side surfaces of the second bank layer BN2 may contact the organic encapsulation layer TFE2, the auxiliary layers AXL1, AXL2, and AXL3, and / or the lower inorganic encapsulation layers TL1, TL2, and TL3.

[0163] The upper inorganic encapsulation layer TFE3 may be disposed on the organic encapsulation layer TFE2. The upper inorganic encapsulation layer TFE3 may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0164] A light blocking layer BM including a light blocking pattern and an opening defined between the light blocking patterns may be disposed on the thin film encapsulation layer TFEL. The light blocking layer BM may include (or define) a plurality of holes OPT1, OPT2, and OPT3 disposed to overlap with the emission areas EA1, EA2, and EA3. For example, the first hole OPT1 may be disposed to overlap with the first emission area EA1. The second hole OPT2 may be disposed to overlap with the second emission area EA2, and the third hole OPT3 may be disposed to overlap with the third emission area EA3. The area or size of each of the holes OPT1, OPT2, and OPT3 may be greater than the area or size of each of the emission areas EA1, EA2, and EA3. The holes OPT1, OPT2, and OPT3 of the light blocking layer BM are formed to be larger than the emission areas EA1, EA2, and EA3. Therefore, the light emitted from the emission areas EA1, EA2, and EA3 may be viewed by a user from outside the display device 10, not only from the farthest front surface along the third direction DR3, but also from the side surface of the display device 10.

[0165] The solid portion of the light blocking layer BM may include a light absorbing material. For example, the light blocking layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but the present disclosure is not limited thereto. The light blocking layer BM may prevent color mixing caused by visible light passing through the first emission area to the third emission area EA1, EA2, and EA3 to improve the color gamut of the display device 10.

[0166] The display device 10 may include a plurality of color filters CF1, CF2, and CF3 disposed on the emission areas EA1, EA2, and EA3. The plurality of color filters CF1, CF2, and CF3 may be disposed to correspond to the emission areas EA1, EA2, and EA3, respectively. For example, the color filters CF1, CF2, and CF3 may be disposed on a light blocking layer BM including a plurality of holes OPT1, OPT2, and OPT3 disposed corresponding to the emission areas EA1, EA2, and EA3. The holes OPT1, OPT2, and OPT3 of the light blocking layer BM may be formed to overlap with the emission areas EA1, EA2, and EA3 or the embankment openings of the embankment structure BNS, and may form a light emitting area through which light emitted from the emission areas EA1, EA2, and EA3 is emitted. Each of the color filters CF1, CF2, and CF3 may have an area larger than each of the holes OPT1, OPT2, and OPT3 of the light blocking layer BM, and may completely cover the light emitting area formed at each of the holes OPT1, OPT2, and OPT3.

[0167] The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 that are arranged to correspond to different emission areas EA1, EA2, and EA3, respectively. The color filters CF1, CF2, and CF3 may include a colorant (such as a dye or a pigment) that absorbs light of a wavelength band other than light of a specific wavelength band, and may be arranged to correspond to the color of the light emitted from the emission areas EA1, EA2, and EA3. For example, the first color filter CF1 may be a red color filter that is arranged to overlap with the first emission area EA1 and allows only the first light as red light to be transmitted therethrough. The second color filter CF2 may be a green color filter that is arranged to overlap with the second emission area EA2 and allows only the second light as green light to be transmitted therethrough, and the third color filter CF3 may be a blue color filter that is arranged to overlap with the third emission area EA3 and allows only the third light as blue light to be transmitted therethrough.

[0168] A plurality of color filters CF1, CF2 and CF3 may be spaced apart from other adjacent color filters CF1, CF2 and CF3 along the light blocking layer BM. The color filters CF1, CF2 and CF3 may have an area larger than the holes OPT1, OPT2 and OPT3 of the light blocking layer BM, respectively, while covering the holes OPT1, OPT2 and OPT3 of the light blocking layer BM, respectively, but may have an area sufficient to be spaced apart from other color filters CF1, CF2 and CF3 along the light blocking layer BM. However, the present disclosure is not limited thereto. A plurality of color filters CF1, CF2 and CF3 may be arranged to partially overlap with other adjacent color filters CF1, CF2 and CF3. Different color filters CF1, CF2 and CF3 may overlap each other on a solid portion of the light blocking layer BM to be described later, which is an area not overlapped with the emission areas EA1, EA2 and EA3. In the display device 10, the color filters CF1, CF2, and CF3 are arranged to overlap each other, so that the intensity of the reflected light caused by the external light can be reduced. In addition, in the plan view, the color sense of the reflected light caused by the external light can be controlled by adjusting the arrangement, shape, area, etc. of the color filters CF1, CF2, and CF3.

[0169] An overcoat layer OC may be disposed on the color filters CF1, CF2, and CF3 to flatten the upper ends of the color filters CF1, CF2, and CF3. The overcoat layer OC may be a colorless light-transmitting layer having no color in the visible light band. For example, the overcoat layer OC may include a colorless light-transmitting organic material such as acrylic resin.

[0170] Hereinafter, a process for manufacturing or setting the display device 10 according to the embodiment will be described with reference to other drawings.

[0171] Figures 11 to 23 are detailed cross-sectional views sequentially illustrating a process for manufacturing (or providing) the display device 10 according to the embodiment.

[0172] exist Figures 11 to 23 , a process of forming a dam structure BNS and a light emitting element ED of a light emitting element layer EML of a display device 10 and a thin film encapsulation layer TFEL on the light emitting element layer EML is schematically shown. Hereinafter, a description of a process of forming each layer in a process for manufacturing the display device 10 will be omitted, and an order of forming each layer will be described.

[0173] Reference Fig.11 A plurality of pixel electrodes AE1, AE2 and AE3 spaced apart from each other, a sacrificial layer SFL as a sacrificial pattern of a sacrificial layer, a pixel defining material layer PDLL as an initial pixel defining layer, and a plurality of embankment material layers BNL1 and BNL2 as an initial embankment layer of an embankment structure BNS are formed or arranged on the second passivation layer PAS2 as an initial stacked structure.

[0174] although Fig.11 1. However, a thin film transistor layer TFTL may be disposed on the substrate SUB having the initial stack structure thereon, and the structure of the thin film transistor layer TFTL may be the same as that of the substrate SUB described above. Figure 4 The structures described are the same and their detailed description will be omitted.

[0175] Then, refer to Fig.12 , a photoresist (not shown) is formed on the second bank material layer BNL2, and a first etching process (first etching) of etching portions of the first bank material layer BNL1 and the second bank material layer BNL2 is performed using the photoresist as a mask. The initial hole HOL may be formed by the first etching process. The photoresist patterns may be disposed to be spaced apart from each other along the second bank material layer BNL2, and may be disposed to expose regions of the second bank material layer BNL2 that overlap with the plurality of pixel electrodes AE1, AE2, and AE3, respectively.

[0176] In an embodiment, anisotropic dry etching may be performed as a first etching process (first etching). An initial hole HOL may be formed in a region overlapping the plurality of pixel electrodes AE1, AE2, and AE3, and may correspond to a bank opening of the bank structure BNS. An exposed portion of the initial pixel defining layer may be exposed outside the initial bank layer at the initial hole HOL.

[0177] Next, refer to Fig.13 , an undercut structure of the first bank layer BN1 may be formed by a second etching process (second etching). The first bank material layer BNL1 may have an etching rate faster than an etching rate of the second bank material layer BNL2 due to its corresponding material. Here, the side surface of the first bank layer BN1 may be recessed from the side surface of the second bank layer BN2 to form an undercut structure at the opposite side of the light emitting region. The second bank layer BN2 protrudes farther than the side surface of the first bank layer BN1 in a direction toward the initial hole HOL to form a tip TIP having the side surface of the second bank layer BN2, and an undercut may be formed by the tip TIP relative to the side surface of the first bank layer BN1.

[0178] In an embodiment, the second etching process may be an isotropic wet etching process. In the second etching process, an alkali etchant may be used. The bank structure BNS including the first bank layer BN1 and the second bank layer BN2 may be obtained through the second etching process.

[0179] Then, if Fig.14As shown in , the exposed portion of the pixel defining material layer PDLL at the initial hole HOL may be removed by a third etching process (third etching), and the portion of the sacrificial layer SFL at the initial hole HOL may also be removed. The third etching process may include a dry etching step for removing the exposed portion of the pixel defining material layer PDLL and a wet etching step for removing a portion of the sacrificial layer SFL. Here, a pattern of a pixel defining film PDL and a residual pattern RP located below the pattern of the pixel defining film PDL may be formed to expose the region of the pixel electrodes AE1, AE2, and AE3 to the outside of the pixel defining film PDL. The pixel defining film PDL may define therein a pixel opening corresponding to a light emitting region (e.g., emission regions EA1, EA2, and EA3). Within the pixel opening, the residual pattern RP may be within the pixel opening to occupy its volume between the pixel electrodes AE1, AE2, and AE3 and the protruding portion of the pixel defining film PDL.

[0180] The sacrificial layer SFL may protect the pixel electrodes AE1, AE2, and AE3 from the influence of plasma in the dry etching step. The portion of the sacrificial layer SFL exposed by the initial hole HOL and the portions of the sacrificial layer SFL respectively between the first bank material layer BNL1 and the pixel electrodes AE1, AE2, and AE3 may be removed. However, the sacrificial layer SFL may not be completely removed and may be retained as a partial residual pattern RP between the protruding portion of the pixel defining film PDL and the pixel electrodes AE1, AE2, and AE3, respectively. The pixel electrodes AE1, AE2, and AE3 may be exposed to the outside of the pixel defining film PDL and the bank structure BNS by the third etching process.

[0181] pass Figures 11 to 14 By using a process, a plurality of pixel electrodes AE1, AE2 and AE3 spaced apart from each other, a pixel defining film PDL exposing the pixel electrodes AE1, AE2 and AE3, a first bank layer BN1 disposed on the pixel defining film PDL, and a second bank layer BN2 protruding further than an inner surface of the first bank layer BN1 can be prepared on a substrate SUB to define a base stacking structure.

[0182] Then, if Fig.15As shown in , on the substrate stacking structure, the first light-emitting element ED1 can be formed by sequentially stacking the first light-emitting layer EL1 and the first common electrode CE1 on the first pixel electrode AE1, and the first cover layer CAP1 can be formed on the first common electrode CE1. In this case, the material layers of the first light-emitting layer EL1, the first common electrode CE1, and the first cover layer CAP1 can be formed on the entire surface of the substrate SUB. Therefore, together with the first light-emitting layer EL1, the first common electrode CE1, and the first cover layer CAP1 formed on the first pixel electrode AE1, the first light-emitting pattern layer ELP1, the first electrode pattern layer CEP1, and the first cover pattern layer CPP1 can be formed on the second bank layer BN2.

[0183] Among the various material layers, the first light emitting layer EL1 and the first light emitting pattern layer ELP1 may be separated from each other by the tip TIP of the second bank layer BN2, the first common electrode CE1 and the first electrode pattern layer CEP1 may be separated from each other by the tip TIP of the second bank layer BN2, and the first cover layer CAP1 and the first cover pattern layer CPP1 may be separated from each other by the tip TIP of the second bank layer BN2. The first light emitting layer EL1 may be formed on the first pixel electrode AE1, and at the same time, the first light emitting pattern layer ELP1 may be formed on the second bank layer BN2. The first common electrode CE1 may be formed on the first light emitting layer EL1, and at the same time, the first electrode pattern layer CEP1 may be formed on the first light emitting pattern layer ELP1. The first cover layer CAP1 may be formed in the bank opening, and at the same time, the first cover pattern layer CPP1 may be formed on the first electrode pattern layer CEP1.

[0184] The first light emitting layer EL1 and the first common electrode CE1 may be formed by a thermal deposition process. The material is not smoothly deposited in the opening due to the tip TIP of the second bank layer BN2. However, the material of the first light emitting layer EL1 and the first common electrode CE1 is deposited in a direction inclined relative to the upper surface of the substrate SUB rather than in a direction perpendicular to the upper surface of the substrate SUB, and thus may be deposited even in a region below the tip TIP of the second bank layer BN2.

[0185] The deposition process for forming the common electrodes CE1, CE2, and CE3 may be performed in an inclined direction relatively close to the horizontal direction than the deposition process for forming the light emitting layers EL1, EL2, and EL3. Therefore, the common electrodes CE1, CE2, and CE3 may contact the side surface of the first bank layer BN1 exposed to the bank opening with a larger area than the light emitting layers EL1, EL2, and EL3. Alternatively, the common electrodes CE1, CE2, and CE3 may be deposited on the side surface of the first bank layer BN1 exposed to the bank opening until a position higher than the light emitting layers EL1, EL2, and EL3. Different common electrodes CE1, CE2, and CE3 may contact the first bank layer BN1 having high conductivity to be electrically connected to each other.

[0186] Subsequently, a first auxiliary material layer AXLL1 is formed to cover the first light emitting element ED1 and the first cover layer CAP1. The first auxiliary material layer AXLL1 may be formed to completely cover the outer surface of the first light emitting element ED1, the inner side surface of the first bank layer BN1, and the inner side surface of the second bank layer BN2, the first cover layer CAP1, the first light emitting pattern layer ELP1, the first electrode pattern layer CEP1, and the first cover pattern layer CPP1 without any disconnected portion (e.g., continuously). Specifically, the first auxiliary material layer AXLL1 is formed on the upper surface of the first common electrode CE1, the upper surface of the first cover layer CAP1, the side surface of the first bank layer BN1 exposed at the bank opening, the lower surface of the second bank layer BN2, and the side surface of the first electrode pattern layer CEP1 and the side surface and upper surface of the first cover pattern layer CPP1.

[0187] In an embodiment, the first auxiliary material layer AXLL1 may be formed by a sputtering process. When the first auxiliary material layer AXLL1 is formed by a sputtering process, the step coverage of the first auxiliary material layer AXLL1 is better than the step coverage of the material used to form the light emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3, so that the film of the first auxiliary material layer AXLL1 may be formed even on the lower surface of the second bank layer BN2.

[0188] Subsequently, a first inorganic material layer TLL1 is formed covering the first auxiliary material layer AXLL1. In an embodiment, the first inorganic material layer TLL1 may be formed by chemical vapor deposition (CVD). The first inorganic material layer TLL1 may be formed along the steps of the first auxiliary material layer AXLL1, i.e., to follow the contour of the first auxiliary material layer AXLL1 even within and outside the bank opening.

[0189] Next, refer to Fig.16, a fourth etching process (fourth etching) of exposing the first auxiliary material layer AXLL1 by removing a portion of the first inorganic material layer TLL1 is performed. A photoresist (not shown) as a mask is formed in a region overlapping with the first emission area EA1 and an edge region surrounding the first emission area EA1, and the first inorganic material layer TLL1 not covered by the mask is removed. Through the fourth etching process, the first inorganic layer TL1 remains as a first inorganic pattern in a region overlapping with the first emission area EA1 and an edge region surrounding the first emission area EA1, while the remaining portion of the first inorganic material layer TLL1 is removed. In an embodiment, the fourth etching process may be anisotropic dry etching.

[0190] Then, refer to Fig.17 , a fifth etching process (fifth etching) of removing the exposed portion of the first auxiliary material layer AXLL1 is performed. Through the fifth etching process, the first auxiliary layer AXL1 disposed between the first inorganic layer TL1 and the first capping pattern layer CPP1 and between the first inorganic layer TL1 and the first light emitting element ED1 may be formed into a first auxiliary pattern of the first auxiliary material layer AXLL1. In an embodiment, the fifth etching process may be wet etching. By controlling the wet etching process, the following may be adjusted: Figures 5 to 8 The area of ​​the first auxiliary layer AXL1 between the first inorganic layer TL1 and the first capping pattern layer CPP1 is shown in FIG.

[0191] Here, a stacked pattern layer including a first light emitting pattern layer ELP1, a first electrode pattern layer CEP1 and a first covering pattern layer CPP1 is disposed at each of the embankments of the embankment structure BNS, and a stacked pattern layer including a first light emitting layer EL1, a first common electrode CE1 and a first covering layer CAP1 is exposed outside the first inorganic pattern and the first auxiliary pattern at an emission area other than the first emission area EA1.

[0192] Next, refer to Fig.18, a sixth etching process (sixth etching) is performed to expose the second bank layer BN2 by removing the first covering pattern layer CPP1, the first electrode pattern layer CEP1 and the first light emitting pattern layer ELP1. In an embodiment, the sixth etching process may include an isotropic wet etching step. Not only the first covering pattern layer CPP1, the first electrode pattern layer CEP1 and the first light emitting pattern layer ELP1 disposed on the second bank layer BN2 may be removed, but also the first light emitting pattern layer ELP1, the first electrode pattern layer CEP1 and the first covering pattern layer CPP1 not covered by the first inorganic material layer TLL1 in the second emission area EA2 and the third emission area EA3 may be removed. That is, the above-mentioned stacked pattern layer exposed outside the first inorganic pattern and the first auxiliary pattern is removed. Therefore, the first light emitting pattern layer ELP1, the first electrode pattern layer CEP1 and the first covering pattern layer CPP1 disposed between the wing portion TL1_W of the first inorganic layer TL1 and the second bank layer BN2 may also be removed, and an undercut structure of the first inorganic layer TL1 may be formed. In addition, the first inorganic layer TL1 as the first inorganic pattern and the first auxiliary layer AXL1 as the first auxiliary pattern overlapping the first emission area EA1 may be obtained.

[0193] Reference Fig.18 , a gap is defined under the wing TL1_W at the overlapping region of the second bank layer BN2 and the first inorganic layer TL1, and extends under the tip TIP of the second bank layer BN2. However, the first auxiliary layer AXL1 extends from under the tip TIP and along the outer surface of the wing TL1_W to cover the gap opening and block exposure of the first inorganic layer TL1, the second bank layer BN2, and the first bank layer BN1.

[0194] Then, if Fig.19 As shown in, a second light-emitting layer EL2, a second common electrode CE2, and a second covering layer CAP2 can be deposited on the second pixel electrode AE2 to form a second light-emitting element ED2. The material layer for forming the second light-emitting layer EL2, the second common electrode CE2, and the second covering layer CAP2 can be provided on the entire substrate SUB having the first inorganic pattern and the first auxiliary pattern thereon. Here, the material layer is disconnected at each wing of the first inorganic pattern to set a pattern including the second light-emitting layer EL2, the second common electrode CE2, and the second covering layer CAP2 at the light-emitting area, and the second light-emitting pattern layer ELP2, the second electrode pattern layer CEP2, and the second covering pattern layer CPP2 on the embankment of the embankment structure BNS.

[0195] like Fig.19As shown in the figure, the second light emitting layer EL2, the second common electrode CE2 and the second covering layer CAP2 which are arranged to overlap with the second emission area EA2 and the edge surrounding the second emission area EA2 are disconnected from the second light emitting pattern layer ELP2, the second electrode pattern layer CEP2 and the second covering pattern layer CPP2 which are adjacent to the first inorganic layer TL1. At the boundary of the first inorganic layer TL1, the stack of the second light emitting pattern layer ELP2, the second electrode pattern layer CEP2 and the second covering pattern layer CPP2 is arranged to be adjacent to the entrance of the gap under the wing TL1_W. The stack may be adjacent to the distal end of the previously formed first auxiliary layer AXL1 to substantially block or minimize the entrance of the gap. Referring to Fig.19 , the gap may be defined by the first auxiliary layer AXL1, the second bank layer BN2, and the inner side surface of the stack.

[0196] Thereafter, a second auxiliary material layer AXLL2 and a second inorganic material layer TLL2 covering the second light emitting element ED2 and the second capping layer CAP2 may be formed on all disconnected patterns. Fig.19 As shown in FIG. 1 , a material is deposited on the entire surface of the substrate SUB having the first inorganic pattern, the first auxiliary pattern, and all disconnected patterns. The second auxiliary material layer AXLL2 extends along the stack of the second light emitting pattern layer ELP2, the second electrode pattern layer CEP2, and the second covering pattern layer CPP2 disposed at the entrance of the gap. Fig.19 The second auxiliary material layer AXLL2 is shown as being continuous or integral with the previously formed first auxiliary layer AXL1, but it will be understood that a virtual boundary may be defined therebetween.

[0197] Next, if Fig. 20 As shown in , the second inorganic layer TL2 overlapping the second emission area EA2 and the edge around the second emission area EA2 may be formed by removing a portion of the second inorganic material layer TLL2 except for a position overlapping the second emission area EA2 and the edge around the second emission area EA2. This process may be similar to Fig.16 The dry etching step of removing the first inorganic material layer TLL1 is similarly performed. Here, the second auxiliary material layer AXLL2 may remain as a continuous layer across the entire substrate SUB, even extending under the second inorganic layer TL2 as the second inorganic pattern.

[0198] Return to reference Fig. 9 Also refer to Fig.18 and Fig.19 , without previously forming a pattern of the first auxiliary layer AXL1 to substantially block or minimize the inlet of the gap, the radicals of the etchant may penetrate into the gap. Fig.10 Also refer to Fig.19 and Fig. 20, since at least the pattern of the previously formed first auxiliary layer AXL1 is disposed on the lower surface of the second bank layer BN2 and extends along the gap, the radicals of the etchant do not damage the first inorganic layer TL1.

[0199] Then, if Fig.21 As shown in , a portion of the second auxiliary material layer AXLL2 may be removed. Here, the second auxiliary layer AXL2 overlapping the second emission area EA2 and the edge surrounding the second emission area EA2 may be formed by removing a portion of the second auxiliary material layer AXLL2 except for a portion overlapping the second emission area EA2 and the edge surrounding the second emission area EA2. This process may be similar to Fig.17 conduct.

[0200] Here, a stacked pattern layer including a second light-emitting pattern layer ELP2, a second electrode pattern layer CEP2 and a second covering pattern layer CPP2 is arranged at each of the embankments of the embankment structure BNS, and a stacked pattern layer including a second light-emitting layer EL2, a second common electrode CE2 and a second covering layer CAP2 is exposed to the outside of the second inorganic pattern and the second auxiliary pattern at the emission area other than the second emission area EA2.

[0201] Next, if Fig. 22 As shown in , the second cover pattern layer CPP2, the second electrode pattern layer CEP2 and the second light emitting pattern layer ELP2 can be removed. That is, the above stacked pattern layers exposed outside the second inorganic pattern and the second auxiliary pattern are removed. This process can be similar to Fig.18 The second inorganic layer TL2 as the second inorganic pattern and the second auxiliary layer AXL2 as the second auxiliary pattern overlapping the second emission area EA2 may be obtained.

[0202] Thereafter, when similarly executing Figures 19 to 22 When the process shown in Fig.23 As shown in FIG. 1 , the third light emitting element ED3 and the third inorganic layer TL3 may be formed at the third emission area EA3 .

[0203] Subsequently, although not shown in the drawings, by Fig.23 The display device 10 is manufactured by forming an organic encapsulation layer TFE2 and an upper inorganic encapsulation layer TFE3 of a thin film encapsulation layer TFEL on a stacked structure, and disposing a light blocking layer BM, a color filter layer CFL, and an overcoat layer OC on the light emitting elements ED1, ED2, and ED3 and the embankment structure BNS. The structures of the thin film encapsulation layer TFEL, the light blocking layer BM, the color filter layer CFL, and the overcoat layer OC are the same as the above-mentioned structures, and thus a detailed description thereof will be omitted.

[0204] In an embodiment, the display device 10 includes: a pixel electrode in the light emitting area; a pixel defining film PDL on the pixel electrode and defining the light emitting area; a light emitting layer and a common electrode on the pixel electrode; a dam (e.g., a dam structure BNS) on the pixel defining film PDL, the dam including a first dam layer BN1 defining a lower portion of a dam opening corresponding to the light emitting area and a second dam layer defining an upper portion of the dam opening and a tip TIP of the dam, the tip TIP including an upper surface and a lower surface of the second dam layer BN2; a lower inorganic encapsulation layer (e.g., TL1 and TL2 together) on the dam and including an inorganic pattern (e.g., TL1) on the common electrode and facing and spaced apart from both an upper surface and a lower surface of the tip TIP; and an auxiliary pattern (e.g., AXL1) between the lower surface of the tip TIP and the inorganic pattern (e.g., TL1).

[0205] The auxiliary pattern may extend from the lower surface of the tip TIP along the side surface of the first bank layer BN1 and along the common electrode (refer to Figures 5 to 8 A thickness portion of the auxiliary pattern extending along the common electrode (eg, a first thickness d1) and a thickness portion of the auxiliary pattern extending along the lower surface of the second bank layer BN2 (eg, a second thickness d2) may be different from each other.

[0206] The auxiliary pattern may extend from the lower surface of the tip TIP and along the second surface of the inorganic pattern (eg, referring to Figure 7 The auxiliary pattern may also extend from the second surface of the inorganic pattern and along the first surface of the inorganic pattern (for example, referring to Figure 5 and Figure 6 ). A thickness portion (eg, a third thickness d3) of the auxiliary pattern extending along the first surface of the inorganic pattern may be greater than a thickness portion of the auxiliary pattern extending along the lower surface of the tip TIP.

[0207] The tip end TIP of the second bank layer BN2 may overlap the light emitting layer and may contact the organic encapsulation layer TFE2. The opposite end of the common electrode may be in the bank opening and overlap the tip end TIP.

[0208] In an embodiment: the pixel electrode and the light-emitting area may be set to multiple, the pixel electrode includes a first pixel electrode AE1 in the first emission area EA1 and a second pixel electrode AE2 spaced apart from the first pixel electrode AE1 and in the second emission area EA2; the light-emitting layer and the common electrode may be set to multiple, including a first light-emitting layer EL1 and a first common electrode CE1 on the first pixel electrode AE1, and a second light-emitting layer EL2 spaced apart from the first light-emitting layer EL1 and a second common electrode CE2 spaced apart from the first common electrode CE1, and the second light-emitting layer EL2 and the second common electrode CE2 are on the second pixel electrode AE2; the embankment opening may be set to multiple, including a first embankment opening corresponding to the first emission area EA1 and a second embankment opening corresponding to the second emission area EA2; the tip TIP may be set to multiple; the inorganic pattern may be set to multiple, including inorganic patterns (for example, TL1 and TL2) on the first common electrode CE1 and the second common electrode CE2, respectively; and the auxiliary pattern may be set to multiple, including auxiliary patterns (for example, AXL1 and AXL2) respectively between the lower surface of the tip TIP and the inorganic pattern.

[0209] The display device 10 includes: a lower inorganic layer TFE1 of a thin film encapsulation layer TFEL, on the embankment, the lower inorganic layer TFE1 includes an inorganic pattern, the inorganic pattern includes a main body on a common electrode and a wing extending from the main body, the inorganic pattern faces and is spaced apart from the upper and lower surfaces of the tip; an auxiliary pattern between the common electrode and the main body of the inorganic pattern; and an organic encapsulation layer of the encapsulation layer between the wing of the inorganic pattern and the tip TIP.

[0210] A method for setting a display device includes preparing a first stacked structure (eg, Fig.14 ), the first stacked structure includes: pixel electrodes, which are spaced apart from each other and are respectively in the light-emitting areas; a pixel defining layer, which is on the pixel electrode and defines the light-emitting area at which the pixel electrode is exposed to the outside of the pixel defining layer; a first embankment layer of the embankment, which is on the pixel defining layer, and the first embankment layer includes a side surface of a lower portion defining embankment openings corresponding to the light-emitting areas respectively; and a second embankment layer of the embankment, which is on the first embankment layer, and the second embankment layer includes a side surface of an upper portion defining the embankment openings, the side surface of the second embankment layer protrudes farther than the side surface of the first embankment layer to define a tip of the embankment, and the tip includes an upper surface of the second embankment layer and a lower surface of the second embankment layer respectively opposite to the upper surface.

[0211] The method further includes: providing a first light-emitting material layer on the first stacked structure, the first light-emitting material layer including a first light-emitting layer on the first pixel electrode of the pixel electrode and a first light-emitting pattern layer on the second bank layer; providing a first common electrode material layer on the first light-emitting material layer, the first common electrode material layer including a first common electrode on the first light-emitting layer and a first electrode pattern layer on the first light-emitting pattern layer (for example, Fig.15 ); a first auxiliary material layer is provided on the first common electrode material layer ( Fig.15 AXLL1 in the figure), the first auxiliary material layer extends from the first common electrode along the lower surface of the first tip of the dam adjacent to the first common electrode and along the first electrode pattern layer; and the first inorganic material layer ( Fig.15 in TLL1).

[0212] The method further includes: etching the first inorganic material layer to provide a first inorganic pattern of a lower inorganic encapsulation layer ( Fig.16 TL1 in the figure), the first inorganic pattern overlaps the first common electrode and overlaps the first tip of the bank, while exposing a portion of the first auxiliary material layer at a region other than the first inorganic pattern; etching the portion of the first auxiliary material layer to provide a first auxiliary pattern ( Fig.17 AXL1 in the middle); and exposing the second bank layer by etching the first light emitting pattern layer and the first electrode pattern layer ( Fig.18 BN2 in ).

[0213] Step of exposing the second bank layer ( Fig.18 ) The first light emitting pattern layer and the first electrode pattern layer respectively between the first inorganic pattern and the upper surface of the first tip may be removed to expose the upper surface of the first tip to the outside of the first auxiliary pattern.

[0214] The steps of disposing a first light emitting layer on the first pixel electrode and disposing a first light emitting pattern layer on the second bank layer include: disconnecting the first light emitting material layer by a first tip to separate the first light emitting material layer into the first light emitting layer and the first light emitting pattern layer (for example, Fig.15 ).

[0215] For a second stack structure including the first inorganic pattern and the first auxiliary pattern and the exposed second bank layer ( Fig.18 The method may further include: providing a second light-emitting material layer on the second stacked structure, the second light-emitting material layer including a second light-emitting layer on the second pixel electrode of the pixel electrode and a second light-emitting pattern layer ( Fig.19 ); a second common electrode material layer is disposed on the second light-emitting layer, the second common electrode material layer includes a second common electrode on the second light-emitting layer and a second electrode pattern layer on the second light-emitting pattern layer ( Fig.19 ); a second auxiliary material layer is provided on the second common electrode material layer ( Fig.19AXLL2 in the figure), the second auxiliary material layer extends from the second common electrode along the lower surface of the second tip of the second bank layer adjacent to the second common electrode and along the second electrode pattern layer; a second inorganic material layer ( Fig.19 and etching the second inorganic material layer to set a second inorganic pattern of the lower inorganic encapsulation layer ( Fig. 20 TL2 in the figure), the second inorganic pattern overlaps the second common electrode and overlaps the second tip of the second bank layer, while exposing a portion of the second auxiliary material layer at a region other than the second inorganic pattern ( Fig. 20 ). The step of providing a second light emitting layer on the second pixel electrode and the step of providing a second light emitting pattern layer on the second bank layer include: disconnecting the second light emitting material layer by a second tip to separate the second light emitting material layer into the second light emitting layer and the second light emitting pattern layer.

Claims

1. A display device, comprising: a pixel electrode, in the light emitting region; A pixel defining layer, which is on the pixel electrode and defines the light emitting area; A light-emitting layer and a common electrode, on the pixel electrode; a bank, on the pixel defining layer, the bank comprising: a first bank layer including a side surface, the side surface defining a lower portion of a bank opening corresponding to the light emitting region; and a second bank layer, on the first bank layer, the second bank layer including a side surface defining an upper portion of the bank opening, the side surface of the second bank layer protruding further than the side surface of the first bank layer to define a tip of the bank, and the tip including an upper surface of the second bank layer and a lower surface of the second bank layer opposite to the upper surface; a lower inorganic layer of an encapsulation layer on the bank, the lower inorganic layer comprising an inorganic pattern on the common electrode, the inorganic pattern facing and spaced apart from both the upper surface and the lower surface of the tip; and An auxiliary pattern is between the lower surface of the tip and the inorganic pattern.

2. The display device according to claim 1, wherein: The auxiliary pattern extends from the lower surface of the tip along the side surface of the first bank layer and along the common electrode.

3. The display device according to claim 2, wherein: A thickness portion of the auxiliary pattern extending along the common electrode and a thickness portion of the auxiliary pattern extending along the lower surface of the second bank layer are different from each other.

4. The display device according to claim 1, further comprising: The organic encapsulation layer of the encapsulation layer is between the upper surface of the tip and the inorganic pattern.

5. The display device according to claim 1, wherein: The inorganic pattern includes a first surface facing the upper surface of the tip and a second surface facing the side surface of the second bank layer.

6. The display device according to claim 5, wherein: The auxiliary pattern extends from the lower surface of the tip along the second surface of the inorganic pattern.

7. The display device according to claim 6, wherein: The auxiliary pattern further extends from the second surface of the inorganic pattern along the first surface of the inorganic pattern.

8. The display device according to claim 7, wherein: A thickness portion of the auxiliary pattern extending along the first surface of the inorganic pattern is greater than a thickness portion of the auxiliary pattern extending along the lower surface of the tip.

9. The display device according to claim 4, wherein: The tip of the second bank layer overlaps the light emitting layer and contacts the organic encapsulation layer.

10. The display device according to claim 1, wherein: The auxiliary pattern includes a transparent conductive oxide.

11. The display device according to claim 1, wherein: An opposite end of the common electrode is in the bank opening and overlaps the tip.

12. The display device according to claim 1, further comprising: The pixel electrodes and the light emitting regions are provided in plurality, the pixel electrodes comprising a first pixel electrode in a first light emitting region and a second pixel electrode spaced apart from the first pixel electrode and in a second light emitting region; The light-emitting layer and the common electrode are provided in plurality, including a first light-emitting layer and a first common electrode on the first pixel electrode, a second light-emitting layer spaced apart from the first light-emitting layer and a second common electrode spaced apart from the first common electrode, and the second light-emitting layer and the second common electrode are on the second pixel electrode; The bank openings are arranged in plurality, including a first bank opening corresponding to the first light emitting area and a second bank opening corresponding to the second light emitting area; The tip is provided in plurality; The inorganic pattern is provided in plurality, including inorganic patterns respectively on the first common electrode and the second common electrode; as well as The auxiliary patterns are provided in plural, including auxiliary patterns respectively between the lower surface of the tip and the inorganic pattern.

13. A display device, comprising: a pixel electrode, in the light emitting region; A pixel defining layer, which is on the pixel electrode and defines the light emitting area; A light-emitting layer and a common electrode, on the pixel electrode; a bank, on the pixel defining layer, the bank comprising: a first bank layer including a side surface, the side surface defining a lower portion of a bank opening corresponding to the light emitting region; and a second bank layer, on the first bank layer, the second bank layer including a side surface defining an upper portion of the bank opening, the side surface of the second bank layer protruding further than the side surface of the first bank layer to define a tip of the bank, and the tip including an upper surface of the second bank layer and a lower surface of the second bank layer opposite to the upper surface; a lower inorganic layer of an encapsulation layer, on the bank, the lower inorganic layer comprising an inorganic pattern, the inorganic pattern comprising: a body portion on the common electrode; and a wing portion extending from the body portion, the inorganic pattern facing and spaced apart from both the upper surface and the lower surface of the tip; an auxiliary pattern between the common electrode and the main body of the inorganic pattern; and The organic encapsulation layer of the encapsulation layer is between the wing portion and the tip of the inorganic pattern.

14. The display device according to claim 13, wherein: The auxiliary pattern extends from the common electrode along the lower surface of the tip and along the side surface of the first bank layer.

15. The display device according to claim 13, wherein: The upper surface of the wing portion of the tip facing the inorganic pattern is in contact with the organic encapsulation layer.

16. A method for setting a display device, the method comprising: A first stacked structure is prepared on a substrate, the first stacked structure comprising: pixel electrodes spaced apart from each other and respectively located in light emitting regions; a pixel defining layer on the pixel electrode and defining the light emitting region, the pixel electrode being exposed outside the pixel defining layer at the light emitting region; a first bank layer of a bank, on the pixel defining layer, the first bank layer comprising a side surface, the side surface defining lower portions of bank openings respectively corresponding to the light emitting regions; and a second bank layer of the bank, on the first bank layer, the second bank layer comprising a side surface defining an upper portion of the bank opening, the side surface of the second bank layer protruding further than the side surface of the first bank layer to define a tip of the bank, and the tip comprising an upper surface of the second bank layer and lower surfaces of the second bank layer respectively opposite to the upper surface; Disposing a first light emitting material layer on the first stacked structure, the first light emitting material layer comprising a first light emitting layer on the first pixel electrode of the pixel electrode and a first light emitting pattern layer on the second bank layer; Disposing a first common electrode material layer on the first light-emitting material layer, wherein the first common electrode material layer includes a first common electrode on the first light-emitting layer and a first electrode pattern layer on the first light-emitting pattern layer; disposing a first auxiliary material layer on the first common electrode material layer, the first auxiliary material layer extending from the first common electrode along a lower surface of a first tip of the bank adjacent to the first common electrode and along the first electrode pattern layer; Disposing a first inorganic material layer of a lower inorganic encapsulation layer along the entire first auxiliary material layer; etching the first inorganic material layer to provide a first inorganic pattern of the lower inorganic encapsulation layer, the first inorganic pattern overlapping the first common electrode and overlapping the first tip of the bank while exposing a portion of the first auxiliary material layer at a region other than the first inorganic pattern; etching the portion of the first auxiliary material layer to provide a first auxiliary pattern between the first inorganic pattern and the first tip of the bank; and The second bank layer is exposed by etching the first light emitting pattern layer and the first electrode pattern layer.

17. The method according to claim 16, wherein: The step of etching the first inorganic material layer comprises a dry etching process, and The step of etching the first auxiliary material layer includes a wet etching process.

18. The method according to claim 16, wherein: The step of exposing the second bank layer removes the first light emitting pattern layer and the first electrode pattern layer respectively between the first inorganic pattern and the upper surface of the first tip to expose the upper surface of the first tip outside the first auxiliary pattern.

19. The method according to claim 16, wherein: The step of disposing the first light emitting layer on the first pixel electrode and the first light emitting pattern layer on the second bank layer includes: disconnecting the first light emitting material layer by the first tip to separate the first light emitting material layer into the first light emitting layer and the first light emitting pattern layer.

20. The method according to claim 16, wherein: a second stacked structure including the first inorganic pattern and the first auxiliary pattern on the substrate and the exposed second bank layer, The method further comprises: Disposing a second light emitting material layer on the second stacked structure, the second light emitting material layer comprising: a second light emitting layer on the second pixel electrode of the pixel electrode; and a second light emitting pattern layer on the second bank layer and on the pixel electrodes of the pixel electrode except the second pixel electrode; Disposing a second common electrode material layer on the second light-emitting layer, wherein the second common electrode material layer includes a second common electrode on the second light-emitting layer and a second electrode pattern layer on the second light-emitting pattern layer; disposing a second auxiliary material layer on the second common electrode material layer, the second auxiliary material layer extending from the second common electrode along a lower surface of a second tip of the second bank layer adjacent to the second common electrode and along the second electrode pattern layer; disposing a second inorganic material layer along the entire second auxiliary material layer; and etching the second inorganic material layer to provide a second inorganic pattern of the lower inorganic encapsulation layer, the second inorganic pattern overlapping the second common electrode and overlapping the second tip of the second bank layer, while exposing a portion of the second auxiliary material layer at a region other than the second inorganic pattern, The step of disposing the second light emitting layer on the second pixel electrode and the second light emitting pattern layer on the second bank layer includes: disconnecting the second light emitting material layer through the second tip to separate the second light emitting material layer into the second light emitting layer and the second light emitting pattern layer.

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