Three-in-one multifunctional instrument and working method thereof

Abstract

The invention provides a three-in-one multifunctional instrument and a working method thereof. The three-in-one multifunctional instrument comprises an MCU chip, an SOC chip, a CAN chip, an AMP chip, a DSP chip, a CVBS chip, a TFT screen, a FLASH, a Bluetooth WIFI chip, a USB charging management chip, an MIC and a power module. The power supply module is respectively connected with the SOC chip, the DSP chip, the Bluetooth WIFI chip, the CVBS chip, the USB charging management chip, the MCU and the CAN chip and supplies power to the SOC chip, the DSP chip, the Bluetooth WIFI chip, the CVBS chip, the USB charging management chip, the MCU and The SOC chip is respectively connected with the MCU chip, the TFT screen, the FLASH, the Bluetooth WIFI chip, the MIC, the DSP chip, the USB charging management chip and the CVBS chip; the MCU chip is also respectively connected with the CAN chip, the DET module, the AMP chip and the TFT screen; wherein the CAN chip is used for receiving internal signals of an automobile, and the DET module is used for receiving external signals of the automobile; and the DSP chip is connected with the AMP chip. Part of core functions of the central control function are integrated into the automobile instrument, and the problems that the functions are dispersed, operation is complex, and cable management is difficult are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of instrument design, and in particular to a three-in-one multifunctional instrument and a working method thereof. Background Art

[0002] As the core of vehicle infotainment and control, the central control system integrates a series of core functions such as reversing image, radio, Bluetooth WIFI, USB charging, etc. These functions provide drivers with a rich driving experience and convenient control methods. The reversing image helps the driver to judge the distance and obstacles more safely when reversing; the radio provides broadcasting services, allowing the driver to enjoy music and information while driving; the Bluetooth WIFI function allows the vehicle to be seamlessly connected with mobile phones, tablets and other devices, realizing multiple functions such as answering calls, playing music, browsing the Internet, etc.; and USB charging ensures that the driver and passengers have sufficient power for their devices during long-distance driving.

[0003] However, although the current central control system is already quite advanced, it still has some shortcomings. First, these functions are often scattered throughout the center console, and the driver needs to frequently shift his or her sight during operation, which not only increases the complexity of operation, but also may bring safety hazards. Secondly, the management of multiple interfaces and cables has also become a challenge. They not only affect the neatness and aesthetics of the car, but may also cause malfunctions or damage due to the clutter. Therefore, how to more reasonably integrate these functions into the car instrument has become a technical direction worthy of in-depth research and exploration. Summary of the invention

[0004] The present invention aims to at least solve the technical problems existing in the prior art, and in particular innovatively proposes a three-in-one multifunctional instrument.

[0005] In order to achieve the above-mentioned object of the present invention, the present invention provides a three-in-one multifunctional instrument, including an MCU chip, a SOC chip, a CAN chip, an AMP chip, a DSP chip, a CVBS chip, a TFT screen, a FLASH, a Bluetooth WIFI chip, a USB charging management chip, a MIC and a power module;

[0006] The power module is respectively connected to the SOC chip U6, DSP chip (UR1), Bluetooth WIFI chip UB1, CVBS chip UI1, USB charging management chip (U13), MCUU12, and CAN chip U1 to provide power for them;

[0007] The SOC chip is connected to the MCU chip, TFT screen, FLASH, Bluetooth WIFI chip, MIC (microphone), DSP chip, USB charging management chip, and CVBS chip respectively;

[0008] The MCU chip is also connected to the CAN chip, DET module, AMP chip, and TFT screen respectively; the CAN chip is used to receive internal signals of the car, and the DET module is used to receive external signals of the car;

[0009] The DSP chip is connected to the AMP chip.

[0010] Furthermore, the power module includes a primary power module and a secondary power module; the primary power module includes a power chip U2 and a power chip U11. The primary power module converts the power supply +VBATT into the power supply +5VSW and the power supply +5VCAN; when the power supply +5VSW output by the power chip U2 meets the static low power consumption in the sleep state, there is no need to use the power chip U11, and the power supply +5VSW is connected through the resistor R3 to output the power supply +5VCAN. If it does not meet the requirements, the power chip U11 is used, and there is no resistor R3 at this time; the power chip U11 converts the power supply +VBATT into the power supply +5VCAN.

[0011] Furthermore, the primary power module includes a power chip U2 and a power chip U11:

[0012] The power chip U2 includes:

[0013] The self-boosting terminal BOOT of the power chip U2 is connected to the first end of the resistor R21, the second end of the resistor R21 is connected to the first end of the capacitor C17, the second end of the capacitor C17 is connected to the cathode of the diode D9, the first end of the resistor R22, the switch control terminal SW of U2, and the first end of the inductor L1; the cathode of the diode D9 is connected to the power ground; the second end of the resistor R22 is connected to the first end of the capacitor C19, and the second end of the capacitor C19 is connected to the power ground;

[0014] The second end of the inductor L1 is connected to the first end of the capacitor C20, the first end of the capacitor C21, the first end of the capacitor C22, the first end of the capacitor C23, and the first end of the resistor R23, and the second end of the inductor L1 outputs the power supply +5VSW; the second end of the capacitor C20, the second end of the capacitor C21, the second end of the capacitor C22, and the second end of the capacitor C23 are connected to the power ground;

[0015] The output voltage feedback terminal FB of the power chip U2, the second end of the resistor R23, and the first end of the resistor R24 ​​are connected, and the second end of the resistor R24 ​​is connected to the power ground;

[0016] The ground terminal GND of the power chip U2 is connected to the power ground;

[0017] The soft start terminal SS of the power chip U2 is connected to the first terminal of the capacitor C18, and the second terminal of the capacitor C18 is connected to the power ground;

[0018] The power input terminal VIN of the power chip U2 is connected to the first end of the capacitor C14, the first end of the capacitor C15, the first end of the capacitor C16, and the first end of the resistor R18; the second end of the capacitor C14, the second end of the capacitor C15, and the second end of the capacitor C16 are connected to the power ground; the second end of the resistor R18 is connected to the power supply +VBATT;

[0019] The enable terminal EN of the power chip U2 is connected to the first end of the resistor R19, the first end of the capacitor C13, and the first end of the resistor R16; the second end of the resistor R16 is connected to the enable terminal of the MCU chip, which is used to control the power chip. The second end of the capacitor C13 is connected to the power ground, and the second end of the resistor R19 is connected to the power ground;

[0020] The frequency control terminal RT / CLK of the power chip U2 is connected to the first end of the resistor R20, and the second end of the resistor R20 is connected to the power ground;

[0021] The power chip U11 includes:

[0022] The power input terminal VIN of the power chip U11 is connected to the cathode of the diode D5, the anode of the polarized capacitor C7, and the first end of the capacitor C8. The cathode of the polarized capacitor C7 and the second end of the capacitor C8 are respectively connected to the power ground; the anode of the diode D5 is connected to the power supply +VBATT;

[0023] The power output terminal OUT of the power chip U11 is connected to the first end of the capacitor C9, the first end of the capacitor C166, and the first end of the resistor R3. The power output terminal OUT of the power chip U11 outputs the power supply +5VCAN; the second end of the resistor R3 outputs the power supply +5VSW; the second end of the capacitor C9 and the second end of the capacitor C166 are connected to the power ground;

[0024] The ground terminal GND of the power chip U11 is connected to the power ground.

[0025] Among them, resistor R22, capacitor C19, and diode D9 are reserved components.

[0026] Further, the secondary power module includes one or any combination of power chip U3, power chip U4, and power chip U5;

[0027] The power chip U3 includes:

[0028] The power input terminal VIN of the power chip U3, the first end of the resistor R25, the first end of the resistor R101, the first end of the capacitor C24, and the first end of the capacitor C26 are connected to the power supply +5VSW; the second end of the capacitor C24 and the second end of the capacitor C26 are connected to the power ground; the second end of the resistor R25 is connected to the power indication terminal PG of the power chip U3; the second end of the resistor R101 is connected to the first end of the capacitor C37 and the enable terminal EN of the power chip U3; the second end of the capacitor C37 is connected to the power ground;

[0029] The ground terminal GND of the power chip U3 is connected to the power ground;

[0030] The switching output terminal SW of the power chip U3 is connected to the first end of the inductor L2, and the second end of the inductor L2 is connected to the power output terminal VOUT of the power chip U3, the first end of the resistor RO3, the first end of the capacitor C30, the first end of the capacitor C34, and the first end of the capacitor C35; the power output terminal VOUT of the power chip U3 outputs the power supply +3.3VSW (3.3V); the second end of the capacitor C34 and the second end of the capacitor C35 are connected to the power ground;

[0031] The feedback terminal FB of the power chip U3 is connected to the second end of the resistor RO3, the second end of the capacitor C30, and the first end of the resistor RO1; the second end of the resistor RO1 is connected to the power ground;

[0032] The soft start terminal SS of the power chip U3 is connected to the first terminal of the capacitor C28, and the second terminal of the capacitor C28 is connected to the power ground.

[0033] The power chip U5 includes:

[0034] The power input terminal VIN of the power chip U5, the first end of the resistor R27, the enable terminal EN of the power chip U5, the first end of the capacitor C36, and the first end of the capacitor C1 are connected to the power supply +5VSW; the second end of the capacitor C36 and the second end of the capacitor C1 are connected to the power ground; the second end of the resistor R27 is connected to the power indication terminal PG of the power chip U5;

[0035] The ground terminal GND of the power chip U5 is connected to the power ground;

[0036] The switching output terminal SW of the power chip U5 is connected to the first end of the inductor L4, and the second end of the inductor L4 is connected to the power output terminal VOUT of the power chip U5, the first end of the resistor RO6, the first end of the capacitor C39, the first end of the capacitor C32, and the first end of the capacitor C41; the power output terminal VOUT of the power chip U5 outputs a power supply of +1.8V; the second end of the capacitor C32 and the second end of the capacitor C41 are connected to the power ground;

[0037] The feedback terminal FB of the power chip U5 is connected to the second end of the resistor RO6, the second end of the capacitor C39, and the first end of the resistor RO5; the second end of the resistor RO5 is connected to the power ground;

[0038] The soft start terminal SS of the power chip U5 is connected to the first terminal of the capacitor C38, and the second terminal of the capacitor C38 is connected to the power ground.

[0039] The power chip U4 includes:

[0040] The power input terminal VIN of the power chip U4, the first end of the resistor R26, the enable terminal EN of the power chip U4, the first end of the capacitor C25, and the first end of the capacitor C27 are connected to the power supply +5VSW; the second end of the capacitor C25 and the second end of the capacitor C27 are connected to the power ground; the second end of the resistor R26 is connected to the power indication terminal PG of the power chip U4;

[0041] The ground terminal GND of the power chip U4 is connected to the power ground;

[0042] The switching output terminal SW of the power chip U4 is connected to the first end of the inductor L3, and the second end of the inductor L3 is connected to the power output terminal VOUT of the power chip U4, the first end of the resistor RO4, the first end of the capacitor C31, the first end of the capacitor C33, and the first end of the capacitor C40; the power output terminal VOUT of the power chip U4 outputs a power supply of +1.2V; the second end of the capacitor C33 and the second end of the capacitor C40 are connected to the power ground;

[0043] The feedback terminal FB of the power chip U4 is connected to the second end of the resistor RO4, the second end of the capacitor C31, and the first end of the resistor RO2; the second end of the resistor RO2 is connected to the power ground;

[0044] The soft start terminal SS of the power chip U4 is connected to the first terminal of the capacitor C29, and the second terminal of the capacitor C29 is connected to the power ground.

[0045] Furthermore, the circuit connection of the CAN chip includes:

[0046] The data transmitting terminal TXD of the CAN chip U1 is connected to the data receiving terminal of the MCU chip;

[0047] The ground terminal GND of the CAN chip U1 is connected to the power ground;

[0048] The power supply terminal VCC of the CAN chip U1, the first end of the resistor R280, the first end of the capacitor C144, and the first end of the capacitor C142 are connected to the power supply +5VCAN;

[0049] The data receiving terminal RXD of the CAN chip U1 is connected to the second end of the resistor R280 and the data sending terminal of the MCU chip;

[0050] The standby mode control input terminal STB of the CAN chip U1 is connected to the control signal terminal of the MCU chip;

[0051] The high-level signal terminal CANH of the CAN chip U1 is connected to the first end of the resistor R102, the first end of the resistor R104, and the first end of the inductor L5; the second end of the resistor R102 is connected to the first end of the resistor R297, the first end of the resistor R103, and the first end of the capacitor C79; the second end of the capacitor C79 is connected to the power ground;

[0052] The second end of the resistor R297 is connected to the first end of the resistor R296, the first end of the capacitor C145, and the power-frequency conversion voltage terminal VIO of the CAN chip U1; the second end of the resistor R296 is connected to the power supply +5VCAN; the second end of the capacitor C145 is connected to the power ground;

[0053] The second end of the resistor R103 is connected to the low-level signal terminal CANL of the CAN chip U1, the first end of the resistor R149, and the fourth end of the inductor L5; the second end of the resistor R149 and the third end of the inductor L5 output a low-level signal; the second end of the resistor R104 is connected to the second end of the inductor L5, and the second end of the inductor L5 outputs a high-level signal.

[0054] Furthermore, the circuit connection of the SOC chip includes:

[0055] The crystal oscillator output end of the SOC chip U6 is connected to the first end of the resistor RM502, the third end of the crystal oscillator Y1, and the first end of the capacitor C45; the second end of the resistor RM502 is connected to the crystal oscillator input end of the SOC chip U6, the first end of the crystal oscillator Y1, and the first end of the capacitor C44; the second end of the capacitor C44, the second end of the capacitor C45, and the fourth end of the crystal oscillator Y1 are connected to the power ground; the second end of the crystal oscillator Y1 is connected to the power ground;

[0056] The reset end of the SOC chip U6 is connected to the first end of the capacitor C43, the collector of the transistor Q7, and the first end of the resistor RB5, and the second end of the capacitor C43 and the emitter of the transistor Q7 are connected to the power ground; the second end of the resistor RB5 is connected to the power supply VDD33_IO, the base of the transistor Q7 is connected to the first end of the resistor R131, and the second end of the resistor R131 is connected to the reset control end of the MCU chip;

[0057] The SOC chip U6 is also connected to the FLAH: the data transmission end of the FLAH chip U7 is connected to the data transmission end of the SOC chip U6 through a resistor; the power input end of the FLAH chip U7, the first end of the resistor R132, and the first end of the capacitor C48 are connected to the power supply VDD33_IO; the second end of the capacitor C48 is connected to the power ground.

[0058] The SOC chip U6 is also connected to the MIC, such as Fig. 9 As shown: the MIC first input terminal of the SOC chip U6 is connected to the first end of the MIC interface J12, the MIC second input terminal of the SOC chip U6 is connected to the first end of the capacitor C77, the first end of the transient diode LTVS10, the first end of the resistor R35, and the third end of the MIC interface J12; the second end of the resistor R35, the first end of the capacitor C63, the first end of the capacitor C64, and the first end of the resistor R36 are connected to the power supply +3.3VSW; the second end of the capacitor C63 and the second end of the capacitor C64 are connected to the power ground; the second end of the resistor R36 is connected to the fifth end of the MIC interface J12, the first end of the transient diode LTVS11, the first end of the capacitor C78, ​​and the microphone protocol terminal of the SOC chip U6;

[0059] The fourth end of the MIC interface J12 is connected to the first end of the inductor LS325.

[0060] The sixth terminal of the MIC interface J12 is connected to the first terminal of the inductor LS1.

[0061] The second end of the MIC interface J12, the second end of the capacitor C77, the second end of the transient diode LTVS10, the second end of the inductor LS325, the second end of the inductor LS1, the second end of the transient diode LTVS11, and the second end of the capacitor C78 are connected to the power ground.

[0062] Furthermore, the internal power supply circuit of the SOC chip includes a first part internal power supply circuit of the SOC, a second part internal power supply circuit of the SOC and a third part internal power supply circuit of the SOC:

[0063] The internal power supply circuit of the first part of the SOC includes: a first end of the inductor L6 is connected to the power supply +1.2V; the second end of the inductor L6 outputs the power supply VDD1V2_CORE, and is connected to the first end of the capacitor C50, the first end of the capacitor C51, the first end of the capacitor C52, the first end of the capacitor C53, the first end of the capacitor C54, the first end of the capacitor C55, the first end of the capacitor C56, the first end of the capacitor C57, the first end of the capacitor C58, the first end of the capacitor C59, the first end of the capacitor C60, the first end of the capacitor C61, and the first end of the capacitor C62; the second end of the capacitor C50, the second end of the capacitor C51, the second end of the capacitor C52, the second end of the capacitor C53, the second end of the capacitor C54, the second end of the capacitor C55, the second end of the capacitor C56, the second end of the capacitor C57, the second end of the capacitor C58, the second end of the capacitor C59, the second end of the capacitor C60, the second end of the capacitor C61, and the second end of the capacitor C62 are connected to the power ground;

[0064] The internal power supply circuit of the second part of the SOC includes: the first end of the inductor L8 is connected to the power supply +1.8V; the second end of the inductor L8 outputs the power supply +1.8V_MCU, and is connected to the first end of the capacitor C80, the first end of the capacitor C81, the first end of the capacitor C82, the first end of the capacitor C83, and the first end of the capacitor C84; the second end of the capacitor C80, the second end of the capacitor C81, the second end of the capacitor C82, the second end of the capacitor C83, and the second end of the capacitor C84 are connected to the power ground;

[0065] The internal power supply circuit of the third part of the SOC includes: a first end of the inductor L7 is connected to the power supply +3.3VSW; the second end of the inductor L7 outputs the power supply VDD33_IO, and is connected to the first end of the capacitor C65, the first end of the capacitor C66, the first end of the capacitor C67, the first end of the capacitor C68, and the first end of the capacitor C69, and the second end of the capacitor C65, the second end of the capacitor C66, the second end of the capacitor C67, the second end of the capacitor C68, and the second end of the capacitor C69 are connected to the power ground; the second end of the inductor L7 is connected to the first end of the capacitor C70, the first end of the capacitor C71, the first end of the capacitor C72, the first end of the capacitor C73, the first end of the capacitor C74, and the first end of the capacitor C75, and the second end of the capacitor C70, the second end of the capacitor C71, the second end of the capacitor C72, the second end of the capacitor C73, the second end of the capacitor C74, and the second end of the capacitor C75 are connected to the power ground.

[0066] Furthermore, the internal power supply circuit of the third part of the SOC includes three sub-power supply circuits:

[0067] The first sub-power supply circuit includes: a power supply VDD33_IO is connected to a first end of a resistor R39, a second end of the resistor R39 outputs a power supply VDD3.3V_SAR and is connected to a first end of a capacitor C85 and a first end of a capacitor C86, and a second end of the capacitor C85 and a second end of the capacitor C86 are connected to a power ground;

[0068] The second sub-power supply circuit includes: a power supply VDD33_IO is connected to a first end of a resistor R40, a second end of the resistor R40 outputs a power supply VDD3V3A and is connected to a first end of a capacitor C87, a first end of a capacitor C88, and a first end of a capacitor C89, and a second end of the capacitor C87, a second end of the capacitor C88, and a second end of the capacitor C89 are connected to a power ground;

[0069] The third sub-power supply circuit includes: a power supply VDD33_IO is connected to a first end of a resistor R41, a second end of the resistor R41 outputs a power supply VCC_RTC and is connected to a first end of a capacitor CO5 and a first end of a capacitor C90, and a second end of the capacitor CO5 and a second end of the capacitor C90 are connected to a power ground.

[0070] The power supply +3.3VSW is converted into the power supply VDD33_IO; the third part of the internal power supply circuit also includes: converting the power supply VDD33_IO into the power supply VDD3.3V_SAR, the power supply VDD3V3A, and the power supply VCC_RTC respectively.

[0071] Furthermore, the circuit of the DSP chip includes:

[0072] The crystal oscillator input terminal XTALI of the DSP chip UR1 is connected to the first terminal of the capacitor CR7 and the third terminal of the crystal oscillator XR1.

[0073] The crystal oscillator output terminal XTALO of the DSP chip UR1 is connected to the first end of the resistor RR19, the second end of the resistor RR19 is connected to the first end of the capacitor CR6 and the first end of the crystal oscillator XR1, the second end of the capacitor CR6 and the second end of the capacitor CR7 are connected to the power ground; the second end and the fourth end of the crystal oscillator XR1 are both connected to the power ground;

[0074] A frequency screening circuit is required between the DSP chip and the FM socket to allow signals within a specific frequency range to pass through, while preventing other frequency signals from passing through. It is used to ensure that only useful signals are passed to subsequent processing units, thereby improving the overall performance and stability of the system. Specifically, it includes frequency modulation and amplitude modulation circuits: the frequency modulation input terminal FMI of the DSP chip UR1 is connected to the first end of the capacitor CR5, the first end of the inductor LR1, and the first end of the inductor LR2, and the second end of the inductor LR2 and the second end of the capacitor CR5 are respectively connected to the power ground; the second end of the inductor LR1 is connected to the first end of the capacitor CR4, and the second end of the capacitor CR4 is connected to the first end of the capacitor CR2 and the first end of the capacitor CR3; the second end of the capacitor CR3 is connected to the first end of the inductor LR6 and the first end of the capacitor CR38; the second end of the inductor LR6 and the second end of the capacitor CR38 are connected to the first end of the capacitor CR39, the first end of the transient diode LTVS18, and the input end of the bandpass filter circuit, and the output end of the bandpass filter circuit is connected to the first end of the capacitor CR41; the bandpass filter circuit includes: a resistor RR31, an inductor LR8, and a capacitor CR40 connected in parallel;

[0075] The second end of the capacitor CR39 is connected to the first end of the inductor LR7, and the second end of the inductor LR7 is connected to the power ground; the second end of the transient diode LTVS18 is connected to the power ground;

[0076] The second end of the capacitor CR41 is connected to the amplitude modulation input terminal AMI of the DSP chip UR1;

[0077] The second end of the capacitor CR2, the first end of the transient diode LTVS17, and the antenna socket are connected to the power supply TUNER_RF; the power supply TUNER_RF is provided by the power chip U8. The second end of the transient diode LTVS17 is connected to the power ground;

[0078] The channel selection terminal ABYP of the DSP chip UR1 is connected to the first end of the capacitor CR42, the first end of the capacitor CR43, the first end of the capacitor CR44, the first end of the capacitor CR45, the first end of the capacitor CR46 and the first end of the inductor LR9, and the second end of the inductor LR9 is connected to the power supply +3.3VSW;

[0079] The analog input positive terminal AIN0P of the DSP chip UR1 is connected to the first end of the capacitor CR47, and the second end of the capacitor CR47 is connected to the first end of the resistor RR35.

[0080] The analog input negative terminal AIN0N of the DSP chip UR1 is connected to the first end of the capacitor CR48, and the second end of the capacitor CR48 is connected to the first end of the capacitor CR50, the first end of the capacitor CR52, the first end of the capacitor CR54, the first end of the capacitor CR55, the first end of the capacitor CR56, the first end of the capacitor CR57, the first end of the capacitor CR58, and the first end of the capacitor CR60 and the power ground;

[0081] The analog input positive terminal AIN1P of the DSP chip UR1 is connected to the first end of the capacitor CR49, and the second end of the capacitor CR49 is connected to the first end of the resistor RR36;

[0082] The analog input negative terminal AIN1N of the DSP chip UR1 is connected to the second end of the capacitor CR50.

[0083] The analog input positive terminal AIN2P of the DSP chip UR1 is connected to the first end of the capacitor CR51, the second end of the capacitor CR51 is connected to the first end of the resistor RR32, the second end of the resistor RR32 is connected to the first end of the capacitor C140, and the second end of the capacitor C140 is connected to the signal transmission end of the AMP chip and the signal transmission end of the SOC chip respectively;

[0084] The analog input negative terminal AIN2N of the DSP chip UR1 is connected to the second terminal of the capacitor CR52;

[0085] The analog input positive terminal AIN3P of the DSP chip UR1 is connected to the first end of the capacitor CR53, the second end of the capacitor CR53 is connected to the first end of the resistor RR33, the second end of the resistor RR33 is connected to the first end of the capacitor C141, and the second end of the capacitor C141 is connected to the signal transmission end of the AMP chip and the signal transmission end of the SOC chip respectively;

[0086] The analog input negative terminal AIN3N of the DSP chip UR1 is connected to the second terminal of the capacitor CR54;

[0087] The analog input positive terminal AIN4P of the DSP chip UR1 is connected to the second terminal of the capacitor CR55;

[0088] The analog input negative terminal AIN4N of the DSP chip UR1 is connected to the second terminal of the capacitor CR56;

[0089] The analog input positive terminal AIN5P of the DSP chip UR1 is connected to the second terminal of the capacitor CR57;

[0090] The analog input negative terminal AIN5N of the DSP chip UR1 is connected to the second end of the capacitor CR58 and the first end of the resistor RR39;

[0091] The analog input positive terminal AIN6P of the DSP chip UR1 is connected to the second end of the resistor RR39 and the first end of the capacitor CR59, and the second end of the capacitor CR59 is connected to the first end of the resistor RR34;

[0092] The analog input negative terminal AIN6N of the DSP chip UR1 is connected to the second terminal of the capacitor CR60;

[0093] The second end of the resistor RR35, the second end of the resistor RR36, the second end of the resistor RR37, the second end of the resistor RR38, and the second end of the resistor RR34 are connected to the power ground;

[0094] The reset signal terminal RSTB of the DSP chip UR1 is connected to the first end of the resistor RR42 and the reset control terminal of the SOC chip;

[0095] The mode selection terminal SMODE of the DSP chip UR1 is connected to the first end of the resistor RR40 and the first end of the resistor RR43; the second end of the resistor RR40 is connected to the power ground;

[0096] The interrupt request terminal INTB of the DSP chip UR1 is connected to the first end of the resistor RR41 and the interrupt request data terminal of the SOC chip;

[0097] The second end of the resistor RR41, the second end of the resistor RR42, and the second end of the resistor RR43 are connected to the power supply DSP_VIO1_3V3 / 1V8;

[0098] The data output terminal MISO / A0 of the DSP chip UR1 is connected to the first end of the resistor RB33, and the second end of the resistor RB33 is connected to the first end of the resistor RB29 and the data receiving end of the SOC chip;

[0099] The data receiving terminal MOSI / SDA of the DSP chip UR1 is connected to the first end of the resistor RB32, and the second end of the resistor RB32 is connected to the first end of the resistor RB28 and the data output terminal of the SOC chip;

[0100] The clock terminal SCLK / SCL of the DSP chip UR1 is connected to the first end of the resistor RB31, and the second end of the resistor RB31 is connected to the first end of the resistor RB27 and the clock control terminal of the SOC chip.

[0101] The chip select signal receiving terminal SSB / A1 of the DSP chip UR1 is connected to the first end of the resistor R0.1B30, and the second end of the resistor RB30 is connected to the first end of the resistor RB26 and the chip select control terminal of the SOC chip.

[0102] The second end of the resistor RB26, the second end of the resistor RB27, the second end of the resistor RB28, and the second end of the resistor RB29 are connected to the power supply +3.3VSW;

[0103] The digital bypass terminal DBYP of the DSP chip UR1 is connected to the first end of capacitor CR18, the first end of capacitor CR20, the first end of capacitor CR22, the first end of capacitor CR24, the first end of capacitor CR26, the first end of capacitor CR28, the first end of capacitor CR19, the first end of capacitor CR21, the first end of capacitor CR23, the first end of capacitor CR25, the first end of capacitor CR27, and the first end of capacitor CR29; the first end of capacitor CR30, the first end of capacitor CR31, the first end of capacitor CR32, the first end of capacitor CR33, the first end of capacitor CR34, the first end of capacitor CR35, the first end of capacitor CR36, and the first end of capacitor CR37;

[0104] The second end of capacitor CR19, the second end of capacitor CR21, the second end of capacitor CR23, the second end of capacitor CR25, the second end of capacitor CR27, the second end of capacitor CR29, and the first end of inductor LR3 are connected to the power supply DSP_DVDD1V8_250MA; the second end of inductor LR3 is connected to the first end of capacitor CR29 and the power supply +1.8V; the second end of capacitor CR29 is connected to the power supply ground;

[0105] The second end of capacitor CR30, the second end of capacitor CR31, the second end of capacitor CR32, the second end of capacitor CR33, the second end of capacitor CR34, the second end of capacitor CR35, the second end of capacitor CR36, the second end of capacitor CR37, and the first end of inductor LR5 are connected to power supply DSP_VIO1_3V3 / 1V8; the second end of inductor LR5 is connected to power supply +3.3VSW;

[0106] The second power input terminal VIO2 of the DSP chip UR1 is connected to the second end of the capacitor CR18, the second end of the capacitor CR20, the second end of the capacitor CR22, the second end of the capacitor CR24, the second end of the capacitor CR26, the second end of the capacitor CR28, the first end of the inductor LR4 and DSP_VIO2_3V3 / 1V8, and the second end of the inductor LR4 is connected to the power supply +3.3VSW;

[0107] The data input terminal NC of the DSP chip UR1 is connected to the first end of the resistor RR29, the second end of the resistor RR29 is connected to the first end of the resistor RR50 and the data output terminal of the Bluetooth WIFI chip, and the second end of the resistor RR50 is connected to the digital audio output terminal of the SOC chip.

[0108] The digital input frame synchronization terminal DIFS2 of the DSP chip UR1 is connected to the first end of the resistor RR28, the second end of the resistor RR28 is connected to the first end of the resistor RR51 and the frame synchronization clock signal output terminal of the Bluetooth WIFI chip, and the second end of the resistor RR51 is connected to the clock signal output terminal of the SOC chip.

[0109] The digital input clock terminal DICLK2 of the DSP chip UR1 is connected to the first end of the resistor RR27, the second end of the resistor RR27 is connected to the first end of the resistor RR52 and the data clock signal output end of the Bluetooth WIFI chip, and the second end of the resistor RR52 is connected to the clock signal control end of the SOC chip;

[0110] The first analog audio output terminal of the DSP chip UR1 is connected to the first end of the resistor RR23, the second end of the resistor RR23 is connected to the first end of the capacitor CR17 and the first end of the capacitor CR8, and the second end of the capacitor CR17 is connected to the audio left channel input terminal of the AMP chip;

[0111] The first analog audio output terminal of the DSP chip UR1 is connected to the first end of the resistor RR22, the second end of the resistor RR22 is connected to the first end of the capacitor CR16 and the first end of the capacitor CR9, and the second end of the capacitor CR16 is connected to the audio right channel input terminal of the AMP chip;

[0112] The third analog audio output terminal of the DSP chip UR1 is connected to the first end of the resistor RR21, and the second end of the resistor RR21 is connected to the first end of the capacitor CR10;

[0113] The fourth analog audio output terminal of the DSP chip UR1 is connected to the first end of the resistor RR20, and the second end of the resistor RR20 is connected to the first end of the capacitor CR11;

[0114] A second end of the capacitor CR8 , a second end of the capacitor CR9 , a second end of the capacitor CR10 , and a second end of the capacitor CR11 are connected to a power ground.

[0115] Further, the power supply circuit of the DSP chip includes: the power input terminal IN of the power chip U8, the first end of the capacitor CD1, and the first end of the capacitor C91 are connected to the power supply +VBATT, and the second end of the capacitor CD1 and the second end of the capacitor C91 are connected to the power ground;

[0116] The first enable terminal EN1 of the power chip U8 is connected to the first end of the resistor RO9, and the second end of the resistor RO9 is connected to the FM enable control terminal of the MCU chip.

[0117] The first enable terminal EN2 of the power chip U8 is connected to the first end of the resistor RO18, and the second end of the resistor RO18 is connected to the camera enable control terminal of the MCU chip;

[0118] The power supply terminal VCC of the power supply chip U8 is connected to the first terminal of the capacitor CO8.

[0119] The first current sensing output terminal SENSE1 of the power chip U8 is connected to the first end of the resistor RO7 and the first end of the capacitor CO6, and the second end of the resistor RO7, the second end of the capacitor CO6 and the second end of the capacitor CO8 are connected to the power ground;

[0120] The first current sensing output terminal SENSE2 of the power chip U8 is connected to the first end of the resistor RO8 and the first end of the capacitor CO7; the second end of the resistor RO8 and the second end of the capacitor CO7 are connected to the power ground;

[0121] The enable control terminal SENSE_SEL of the power chip U8 is connected to the first end of the resistor RO10, and the second end of the resistor RO10 is connected to the power ground.

[0122] The current sensing enable terminal SENSE_EN of the power chip U8 is connected to the first end of the resistor RO11, and the second end of the resistor RO11 is connected to the power ground.

[0123] The first power output terminal OUT1 of the power chip U8 is connected to the first end of the inductor LD1 and the first end of the resistor RO13, and the second end of the inductor LD1 is connected to the first end of the capacitor CD2, the first end of the capacitor CD3, and the first end of the inductor LD2; the second end of the inductor LD2 outputs the power supply TUNER_RF; the second end of the capacitor CD2 and the second end of the capacitor CD3 are connected to the power ground;

[0124] The first feedback terminal FB1 of the power chip U8 is connected to the second end of the resistor RO13 and the first end of the resistor RO15. The second end of the resistor RO15, the first end of the resistor RO17, the first end of the resistor RO16 and the first end of the resistor RO14 are connected to the power ground.

[0125] The first power output terminal OUT2 of the power chip U8 outputs the power supply CAMPOW+8V, and is connected to the first end of the resistor RO12, the first end of the capacitor CD6, and the first end of the capacitor CD5; the second end of the capacitor CD6 and the second end of the capacitor CD5 are connected to the power ground;

[0126] The first feedback terminal FB2 of the power chip U8 is connected to the second end of the resistor RO12 and the second end of the resistor RO17;

[0127] The ground terminal GND of the power chip U8 is connected to the power ground;

[0128] The first current limiting terminal LIM1 of the power chip U8 is connected to the second terminal of the resistor RO16;

[0129] The second current limiting terminal LIM2 of the power chip U8 is connected to the second end of the resistor RO14.

[0130] The present invention also provides a working method of a three-in-one multifunctional instrument, including a working method of one or any combination of an imaging function, a Bluetooth WIFI function, a USB charging function, and a radio function;

[0131] Working method of the imaging function: when the CAN chip receives a signal from inside the vehicle, it transmits the signal to the MCU chip; or when the DET module receives a signal from outside the vehicle, it transmits the signal to the MCU chip; the MCU chip transmits the signal to the SOC chip via UART; the SOC chip controls the CVBS chip, and the CVBS chip decodes the current video signal of the vehicle to obtain video data, and transmits the data to the SOC chip; the SOC chip performs image processing and other operations on the video data, and then outputs the data to the TFT screen via LVDS;

[0132] How the Bluetooth WIFI function works:

[0133] (1) How the Bluetooth function works:

[0134] Implementation path 1: When the Bluetooth WIFI chip receives the data signal from the mobile terminal, it transmits the data signal to the SOC chip through UART for decoding and other related operations; then the decoded data is transmitted to the DSP chip through I2S for signal processing; the DSP chip transmits the digital signal processed data to the AMP chip;

[0135] Implementation path two: receiving voice data through MIC, transmitting the voice data to SOC chip through ADC for decoding and other related operations; then transmitting the processed voice data to Bluetooth WIFI chip through UART, and then transmitting the voice data to the mobile terminal through Bluetooth WIFI chip;

[0136] (2) How the WIFI function works:

[0137] When the Bluetooth WIFI chip receives the data signal from the mobile terminal, the Bluetooth WIFI chip transmits the data signal to the SOC chip through SDIO; after the SOC chip performs decoding and other related operations, the decoded data is output to the TFT screen through LVDS for display;

[0138] The working method of the USB charging function is: the USB socket is connected to the USB charging management chip, and the current is transmitted to the USB charging management chip through the USB cable. The chip first detects and identifies the input voltage and current specifications to ensure that they meet the charging requirements of the device; the USB charging management chip communicates with the SOC chip, and the SOC chip calculates the optimal charging current and voltage through an algorithm based on factors such as the current battery status, temperature and the charging mode set by the user, and feeds this information back to the USB charging management chip, which accurately controls the charging process to ensure stable output of current and voltage, while monitoring the battery charging status to prevent overcharging or over-discharging, thereby completing the charging task safely and efficiently.

[0139] The working method of the radio function: when an external radio frequency signal RF is received, it is processed by the DSP chip, and the processed signal is transmitted to the SOC chip through SPI, and FM frequency tuning and station selection are performed through the SOC chip; then the DSP chip outputs the AOUT signal to the AMP chip.

[0140] In summary, due to the adoption of the above technical solution, the present invention integrates some core functions of the central control function into the automobile instrument, solving the problems of scattered functions, complex operations, and difficult cable management. The specific beneficial effects are: First, this design improves the integration and intuitiveness of information, and the convenience of operation is significantly improved. The driver can complete the switching and setting of various functions with fewer operations, and obtain the required information more conveniently without switching between multiple screens; thereby improving driving safety and efficiency. Furthermore, this design also saves space in the car, reduces the number of cables and interfaces, and makes the interior layout more tidy and beautiful; it also saves costs to a certain extent. Finally, the integrated instrument system is easier to achieve compatibility and integration with other vehicle systems, providing more possibilities for future technological upgrades and expansions.

[0141] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0142] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0143] Figure 1 It is a schematic diagram of the connection of various components of the three-in-one multifunctional instrument of the present invention.

[0144] Figure 2 It is a circuit connection diagram of the primary power module of the present invention.

[0145] Figure 3 It is a circuit connection diagram of the secondary power supply module of the present invention.

[0146] Figure 4 It is a circuit connection diagram of the CAN chip of the present invention.

[0147] Figure 5 It is a circuit connection diagram of the MCU chip of the present invention.

[0148] Figure 6 It is a circuit connection diagram of the SOC chip of the present invention.

[0149] Figure 7 It is a schematic diagram of the internal power supply circuit connection of the SOC chip of the present invention.

[0150] Figure 8 It is a circuit connection diagram of FLASH of the present invention.

[0151] Fig. 9 It is a circuit connection diagram of the MIC of the present invention.

[0152] Fig.10 It is a circuit connection diagram of the DSP chip of the present invention.

[0153] Fig.11 It is a schematic diagram of the connection of the power supply circuit of the DSP chip of the present invention.

[0154] Fig.12 It is a circuit connection diagram of the AMP chip of the present invention.

[0155] Fig.13 It is a circuit connection diagram of the Bluetooth WIFI chip of the present invention.

[0156] Fig.14 It is a schematic diagram of the power supply circuit connection of the Bluetooth WIFI chip of the present invention.

[0157] Fig.15It is a circuit connection diagram of the CVBS chip of the present invention.

[0158] Fig.16 It is a circuit connection schematic diagram of the TFT screen of the present invention.

[0159] Fig.17 It is a schematic diagram of the connection of the power supply circuit of the TFT screen of the present invention.

[0160] Fig.18 It is a circuit connection diagram of the USB charging management chip of the present invention. DETAILED DESCRIPTION

[0161] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0162] The components of the three-in-one multifunctional instrument are connected as follows Figure 1 As shown, it includes an MCU chip, a SOC chip, a CAN chip, an AMP chip, a DSP chip, a CVBS chip, a TFT screen, a FLASH, a Bluetooth WIFI chip, a USB charging management chip, a MIC (microphone) and a power module, and the power module includes a primary power module and a secondary power module;

[0163] The power module is respectively connected to the SOC chip U6, DSP chip (UR1), Bluetooth WIFI chip UB1, CVBS chip UI1, USB charging management chip (U13), MCUU12, and CAN chip U1 to provide power for them;

[0164] The SOC chip is connected to the MCU chip, TFT screen, FLASH, Bluetooth WIFI chip, MIC, DSP chip, USB charging management chip, and CVBS chip respectively;

[0165] The MCU chip is also connected to the CAN chip, DET module, AMP chip, and TFT screen respectively; the CAN chip is used to receive internal signals of the car, and the DET module is used to receive external signals of the car;

[0166] In addition, the DSP chip is connected to the AMP chip.

[0167] The present invention designs the central control's image, FM radio, Bluetooth WIFI and USB charging functions into the instrument, and the specific implementation method is as follows:

[0168] 1. Implementation of the imaging function: When the CAN chip receives a signal from inside the vehicle, it transmits the signal to the MCU chip through CAN_TX / RX; or when the DET module receives a signal from outside the vehicle, it transmits the signal to the MCU chip through DET / ADC. The MCU chip transmits the signal to the SOC chip through UART; the SOC chip controls the CVBS chip, and the CVBS chip (video processing chip) decodes the current video signal of the vehicle and transmits the data to the SOC chip; the SOC chip performs image processing and other operations on the video data, and then outputs the data to the TFT screen through LVDS. The usage scenarios of the imaging function include: reversing imaging, 360-degree panoramic imaging, driver monitoring imaging, in-vehicle monitoring, etc.

[0169] 2. Implementation of Bluetooth WIFI function:

[0170] (1) Implementation of Bluetooth function:

[0171] Implementation path 1: When the Bluetooth WIFI chip receives the data signal from the mobile phone, it transmits the data signal to the SOC chip through UART for decoding and other related processing; then transmits the processed data to the DSP chip through I2S for signal processing; and transmits the digital signal processed data to the AMP chip (audio power amplifier chip, i.e., power amplifier). Usage scenarios include: the mobile phone is connected to the vehicle via Bluetooth, and the vehicle plays music or calls externally.

[0172] Implementation path 2: Receive voice data through MIC, transfer it to SOC chip through ADC for decoding and other related processing; then transfer the processed voice data to Bluetooth WIFI chip through UART, and then transfer the voice data to the mobile phone through Bluetooth WIFI chip. Usage scenarios include: the vehicle is connected to the mobile phone through Bluetooth, and voice calls are made through the MIC on the vehicle.

[0173] (2) Implementation of WIFI function:

[0174] When the Bluetooth WIFI chip receives the data signal from the mobile phone, it transmits it to the SOC chip through SDIO; after the SOC chip performs relevant processing, it outputs the data to the TFT screen through LVDS for display. The usage scenarios include: the mobile phone is connected to the vehicle via WIFI, and the vehicle navigation screen is projected.

[0175] 3. Realization of USB charging function: Connected to the USB charging management chip through the USB socket, and the USB charging management chip is connected to the SOC chip. In addition to the charging function, it can also realize functions such as transparent transmission and upgrade.

[0176] 4. Implementation of radio function:

[0177] When an external radio frequency signal RF is received, it is processed by the DSP chip and transmitted to the SOC chip via SPI, and FM frequency modulation and station selection are performed by the SOC chip; then the DSP chip outputs the AOUT signal to the AMP chip.

[0178] In addition, there is also an audio playback function through a USB flash drive. The USB flash drive is connected to the SOC chip, which decodes the audio signal and transmits the decoded audio to the DSP chip through I2S. The DSP chip restores it to an analog signal and transmits the analog signal to the AMP chip for audio playback.

[0179] The circuit of the power module is as follows Figure 2 , Figure 3 As shown. The primary power module includes power chip U2 and power chip U11. The primary power module converts the power supply +VBATT (12V) into power supply +5VSW (5V) and power supply +5VCAN (5V); when the power supply +5VSW output by the power chip U2 meets the static low power consumption in the sleep state, there is no need to use the power chip U11, and the power supply +5VSW is connected through the resistor R3 to output the power supply +5VCAN. If it does not meet the requirements, the power chip U11 is used, and there is no resistor R3 at this time; the power chip U11 converts the power supply +VBATT (12V) into power supply +5VCAN (5V).

[0180] The self-boosting terminal BOOT of the power chip U2 is connected to the first end of the resistor R21, the second end of the resistor R21 is connected to the first end of the capacitor C17, the second end of the capacitor C17 is connected to the cathode of the diode D9, the first end of the resistor R22, the switch control terminal SW of U2, and the first end of the inductor L1; the cathode of the diode D9 is connected to the power ground; the second end of the resistor R22 is connected to the first end of the capacitor C19, and the second end of the capacitor C19 is connected to the power ground;

[0181] The second end of the inductor L1 is connected to the first end of the capacitor C20, the first end of the capacitor C21, the first end of the capacitor C22, the first end of the capacitor C23, and the first end of the resistor R23, and the second end of the inductor L1 outputs the power supply +5VSW (5V); the second end of the capacitor C20, the second end of the capacitor C21, the second end of the capacitor C22, and the second end of the capacitor C23 are connected to the power ground; wherein the capacitor C23 is a polar capacitor.

[0182] The output voltage feedback terminal FB of the power chip U2, the second end of the resistor R23, and the first end of the resistor R24 ​​are connected, and the second end of the resistor R24 ​​is connected to the power ground;

[0183] The ground terminal GND of the power chip U2 is connected to the power ground;

[0184] The soft start terminal SS of the power chip U2 is connected to the first terminal of the capacitor C18, and the second terminal of the capacitor C18 is connected to the power ground;

[0185] The power input terminal VIN of the power chip U2 is connected to the first end of the capacitor C14, the first end of the capacitor C15, the first end of the capacitor C16, and the first end of the resistor R18; the second end of the capacitor C14, the second end of the capacitor C15, and the second end of the capacitor C16 are connected to the power ground; the second end of the resistor R18 is connected to the power supply +VBATT;

[0186] The enable terminal EN of the power chip U2 is connected to the first end of the resistor R19, the first end of the capacitor C13, and the first end of the resistor R16; the second end of the resistor R16 is connected to the enable terminal of the MCU chip, which is used to control the power chip U2. The second end of the capacitor C13 is connected to the power ground, and the second end of the resistor R19 is connected to the power ground;

[0187] The frequency control terminal RT / CLK of the power chip U2 is connected to a first end of the resistor R20 , and a second end of the resistor R20 is connected to a power ground.

[0188] The model of the power chip U2 is SCT2432STER.

[0189] The power input terminal VIN of the power chip U11 is connected to the cathode of the diode D5, the anode of the polarized capacitor C7, and the first end of the capacitor C8. The cathode of the polarized capacitor C7 and the second end of the capacitor C8 are respectively connected to the power ground; the anode of the diode D5 is connected to the power supply +VBATT;

[0190] The power output terminal OUT of the power chip U11 is connected to the first end of the capacitor C9, the first end of the capacitor C166, and the first end of the resistor R3. The power output terminal OUT of the power chip U11 outputs the power supply +5VCAN; the second end of the resistor R3 outputs the power supply +5VSW; the second end of the capacitor C9 and the second end of the capacitor C166 are connected to the power ground;

[0191] The ground terminal GND of the power chip U11 is connected to the power ground.

[0192] The model of power chip U11 is SCT71403F50Q

[0193] Then, the 5V power outputted by the primary power module is converted to 3.3V by the secondary power module through the power chip U3, to 1.8V by the power chip U5, and to 1.2V by the power chip U4;

[0194] The power input terminal VIN of the power chip U3, the first end of the resistor R25, the first end of the resistor R101, the first end of the capacitor C24, and the first end of the capacitor C26 are connected to the power supply +5VSW; the second end of the capacitor C24 and the second end of the capacitor C26 are connected to the power ground; the second end of the resistor R25 is connected to the power indication terminal PG of the power chip U3; the second end of the resistor R101 is connected to the first end of the capacitor C37 and the enable terminal EN of the power chip U3; the second end of the capacitor C37 is connected to the power ground;

[0195] The ground terminal GND of the power chip U3 is connected to the power ground;

[0196] The switching output terminal SW of the power chip U3 is connected to the first end of the inductor L2, and the second end of the inductor L2 is connected to the power output terminal VOUT of the power chip U3, the first end of the resistor RO3, the first end of the capacitor C30, the first end of the capacitor C34, and the first end of the capacitor C35; the power output terminal VOUT of the power chip U3 outputs the power supply +3.3VSW (3.3V); the second end of the capacitor C34 and the second end of the capacitor C35 are connected to the power ground;

[0197] The feedback terminal FB of the power chip U3 is connected to the second end of the resistor RO3, the second end of the capacitor C30, and the first end of the resistor RO1; the second end of the resistor RO1 is connected to the power ground;

[0198] The soft start terminal SS of the power chip U3 is connected to the first terminal of the capacitor C28, and the second terminal of the capacitor C28 is connected to the power ground.

[0199] The power input terminal VIN of the power chip U5, the first end of the resistor R27, the enable terminal EN of the power chip U5, the first end of the capacitor C36, and the first end of the capacitor C1 are connected to the power supply +5VSW; the second end of the capacitor C36 and the second end of the capacitor C1 are connected to the power ground; the second end of the resistor R27 is connected to the power indication terminal PG of the power chip U5;

[0200] The ground terminal GND of the power chip U5 is connected to the power ground;

[0201] The switching output terminal SW of the power chip U5 is connected to the first end of the inductor L4, and the second end of the inductor L4 is connected to the power output terminal VOUT of the power chip U5, the first end of the resistor RO6, the first end of the capacitor C39, the first end of the capacitor C32, and the first end of the capacitor C41; the power output terminal VOUT of the power chip U5 outputs a power supply of +1.8V; the second end of the capacitor C32 and the second end of the capacitor C41 are connected to the power ground;

[0202] The feedback terminal FB of the power chip U5 is connected to the second end of the resistor RO6, the second end of the capacitor C39, and the first end of the resistor RO5; the second end of the resistor RO5 is connected to the power ground;

[0203] The soft start terminal SS of the power chip U5 is connected to the first terminal of the capacitor C38, and the second terminal of the capacitor C38 is connected to the power ground.

[0204] The power input terminal VIN of the power chip U4, the first end of the resistor R26, the enable terminal EN of the power chip U4, the first end of the capacitor C25, and the first end of the capacitor C27 are connected to the power supply +5VSW; the second end of the capacitor C25 and the second end of the capacitor C27 are connected to the power ground; the second end of the resistor R26 is connected to the power indication terminal PG of the power chip U4;

[0205] The ground terminal GND of the power chip U4 is connected to the power ground;

[0206] The switching output terminal SW of the power chip U4 is connected to the first end of the inductor L3, and the second end of the inductor L3 is connected to the power output terminal VOUT of the power chip U4, the first end of the resistor RO4, the first end of the capacitor C31, the first end of the capacitor C33, and the first end of the capacitor C40; the power output terminal VOUT of the power chip U4 outputs a power supply of +1.2V; the second end of the capacitor C33 and the second end of the capacitor C40 are connected to the power ground;

[0207] The feedback terminal FB of the power chip U4 is connected to the second end of the resistor RO4, the second end of the capacitor C31, and the first end of the resistor RO2; the second end of the resistor RO2 is connected to the power ground;

[0208] The soft start terminal SS of the power chip U4 is connected to the first terminal of the capacitor C29, and the second terminal of the capacitor C29 is connected to the power ground.

[0209] The model of the power chip U3, U4, and U5 is SCT2130.

[0210] The circuit connection of CAN chip is as follows Figure 4 shown.

[0211] The data transmitting terminal TXD of the CAN chip U1 is connected to the data receiving terminal of the MCU chip; the ground terminal GND of the CAN chip U1 is connected to the power ground; the power terminal VCC of the CAN chip U1, the first end of the resistor R280, the first end of the capacitor C144, and the first end of the capacitor C142 are connected to the power supply +5VCAN; the data receiving terminal RXD of the CAN chip U1 is connected to the second end of the resistor R280 and the data transmitting terminal of the MCU chip;

[0212] The standby mode control input terminal STB of the CAN chip U1 is connected to the control signal terminal of the MCU chip;

[0213] The high-level signal terminal CANH of the CAN chip U1 is connected to the first end of the resistor R102, the first end of the resistor R104, and the first end of the inductor L5; the second end of the resistor R102 is connected to the first end of the resistor R297, the first end of the resistor R103, and the first end of the capacitor C79; the second end of the capacitor C79 is connected to the power ground;

[0214] The second end of the resistor R297 is connected to the first end of the resistor R296, the first end of the capacitor C145, and the power-frequency conversion voltage terminal VIO of the CAN chip U1; the second end of the resistor R296 is connected to the power supply +5VCAN; the second end of the capacitor C145 is connected to the power ground;

[0215] The second end of the resistor R103 is connected to the low-level signal terminal CANL of the CAN chip U1, the first end of the resistor R149, and the fourth end of the inductor L5; the second end of the resistor R149 and the third end of the inductor L5 output a low-level signal; the second end of the resistor R104 is connected to the second end of the inductor L5, and the second end of the inductor L5 outputs a high-level signal.

[0216] The model of CAN chip U1 is SIT1044.

[0217] The circuit connection of MCU chip is as follows Figure 5 (a) shown.

[0218] The power supply terminals VDD1 and VDDA of the MCU chip U12 are connected to the first end of the resistor R4, the first end of the capacitor C151, the first end of the capacitor C150, and the first end of the capacitor C149; the second end of the capacitor C151, the second end of the capacitor C150, and the second end of the capacitor C149 are connected to the power ground; the second end of the resistor R4 is connected to the power supply +5VCAN;

[0219] The data transmission terminal PA0 of the MCU chip U12 is connected to the first end of the resistor RR48;

[0220] The data transmission terminal PA1 of the MCU chip U12 is connected to the first end of the resistor RR45;

[0221] The data transmission terminal PB13 of the MCU chip U12 is connected to the first end of the resistor RR44;

[0222] The second end of the resistor RR48, the second end of the resistor RR45, and the second end of the resistor RR44 are connected to the control end of the AMP chip;

[0223] The power supply terminal VDD2 of the MCU chip U12, the first end of the capacitor C154, the first end of the capacitor C153, and the first end of the capacitor C152 are connected to the power supply +5VCAN; the second end of the capacitor C154, the second end of the capacitor C153, and the second end of the capacitor C152 are connected to the power ground;

[0224] The crystal oscillator input terminal PA12 of the MCU chip U12 is connected to the first end of the resistor R114, the third end of the crystal oscillator Y2, and the first end of the capacitor C146; the second end of the resistor R114 is connected to the crystal oscillator output terminal PA15 of the MCU chip U12, the first end of the capacitor C147, and the first end of the crystal oscillator Y2; the fourth end of the crystal oscillator Y2, the first end of the crystal oscillator Y2, the second end of the capacitor C146, and the second end of the capacitor C147 are all connected to the power ground.

[0225] The model of MCU chip U12 is AC78013FDLA.

[0226] Figure 5 (b) is a level conversion circuit for communication between the MCU chip and the SOC chip, which ensures the correct transmission of the signal through level conversion. Specifically: the signal receiving end of the SOC chip is connected to the first end of the resistor R562 and the collector of the transistor QG3, and the base of the transistor QG3 is connected to the first end of the capacitor CG4 and the first end of the resistor RG8; the emitter of the transistor QG3 is connected to the first end of the resistor RG9 and the data sending end of the MCU chip, and the second end of the resistor RG9, the second end of the capacitor CG4, and the second end of the resistor RG8 are connected to the power supply +5VCAN; the second end of the resistor R562 and the first end of the resistor R561 are connected to the power supply VDD33_IO; the second end of the resistor R561 is connected to the signal sending end of the SOC chip and the emitter of the transistor QG4;

[0227] The base of transistor QG4 is connected to the first end of capacitor CG3 and the first end of resistor RG6; the emitter of transistor QG4 is connected to the first end of resistor RG7 and the data receiving end of the MCU chip; the second end of capacitor CG3, the second end of resistor RG6, and the second end of resistor RG7 are connected to the power supply +5VCAN.

[0228] Through the above level conversion circuit, signal transmission is carried out between SOC chips and MCU chips of different voltage levels. Specifically, it converts the 3.3V signal of the SOC chip into a 5V signal that the MCU chip can recognize, and vice versa. The following is the control logic of the circuit:

[0229] (1) Signal transmission from SOC to MCU (through QG3 and RG9):

[0230] When the signal receiving end (ITE3966_SDA_RX) of the SOC chip outputs a high level (3.3V), the current flows into the collector of QG3 through R562. This turns on QG3, and its emitter voltage is close to 0V (grounded), and the voltage of the data transmitting end (MCU_SCL_TX) of the MCU chip is pulled down through RG9, causing it to output a low level (0V). When the SOC chip outputs a low level, QG3 is turned off, and RG9 pulls MCU_SCL_TX up to 5V, outputting a high level.

[0231] (2) Signal transmission from MCU to SOC (through QG4 and RG7):

[0232] When the data receiving end (MCU_SDA_RX) of the MCU chip outputs a high level (5V), the current flows into the emitter of QG4 through RG7. This turns on QG4, and its base voltage is close to 0V, which pulls down the voltage of the signal transmitting end (ITE3966_SCL_TX) of the SOC chip through RG6, causing it to output a low level. When the MCU chip outputs a low level, QG4 is turned off, and RG6 pulls ITE3966_SCL_TX up to 3.3V, outputting a high level.

[0233] The MCU chip also has some circuits for the debug port, such as Figure 5 (c) is shown. The key control circuit of the MCU chip is as follows Figure 5 (d) As shown. The power supply +5VCAN is connected to the first end of the resistor R100, the second end of the resistor R100 is connected to the first end of the resistor R98, the first end of the resistor R5, the first end of the resistor R6, the first end of the resistor R17, the first end of the resistor R97, and the first end of the resistor R99; the second end of the resistor R5 is connected to the first end of the first button, the second end of the resistor R6 is connected to the first end of the second button, the second end of the resistor R17 is connected to the first end of the third button, the second end of the resistor R97 is connected to the first end of the fourth button, and the second end of the resistor R99 is connected to the first end of the fifth button; the second end of the second button, the second end of the second button, the second end of the third button, the second end of the fourth button, and the second end of the fifth button are connected to the power ground;

[0234] The second end of the resistor R98 is connected to the first end of the capacitor C155 and the key input end of the MCU chip; the second end of the capacitor C155 is connected to the power ground.

[0235] The circuit connection of SOC chip is as follows Figure 6 shown.

[0236] The crystal oscillator output end of the SOC chip U6 is connected to the first end of the resistor RM502, the third end of the crystal oscillator Y1, and the first end of the capacitor C45; the second end of the resistor RM502 is connected to the crystal oscillator input end of the SOC chip U6, the first end of the crystal oscillator Y1, and the first end of the capacitor C44; the second end of the capacitor C44, the second end of the capacitor C45, and the fourth end of the crystal oscillator Y1 are connected to the power ground; the second end of the crystal oscillator Y1 is connected to the power ground;

[0237] The reset terminal of the SOC chip U6 is connected to the first terminal of the capacitor C43, the collector of the transistor Q7, and the first terminal of the resistor RB5. The second terminal of the capacitor C43 and the emitter of the transistor Q7 are connected to the power ground. The second terminal of the resistor RB5 is connected to the power supply VDD33_IO. The base of the transistor Q7 is connected to the first terminal of the resistor R131. The second terminal of the resistor R131 is connected to the reset control terminal of the MCU chip. The transistor Q7 is an NPN transistor.

[0238] The SOC chip U6 is also connected to the FLAH, such as Figure 8 As shown: the data transmission end of the FLAH chip U7 is connected to the data transmission end of the SOC chip U6 via a resistor; the power input end of the FLAH chip U7, the first end of the resistor R132, and the first end of the capacitor C48 are connected to the power supply VDD33_IO; the second end of the capacitor C48 is connected to the power ground.

[0239] The SOC chip U6 is also connected to the MIC, such as Fig. 9 As shown: the MIC first input terminal of the SOC chip U6 is connected to the first end of the MIC interface J12, the MIC second input terminal of the SOC chip U6 is connected to the first end of the capacitor C77, the first end of the transient diode LTVS10, the first end of the resistor R35, and the third end of the MIC interface J12; the second end of the resistor R35, the first end of the capacitor C63, the first end of the capacitor C64, and the first end of the resistor R36 are connected to the power supply +3.3VSW; the second end of the capacitor C63 and the second end of the capacitor C64 are connected to the power supply ground; the second end of the resistor R36 is connected to the fifth end of the MIC interface J12, the first end of the transient diode LTVS11, the first end of the capacitor C78, ​​and the microphone protocol terminal (MICRIP) of the SOC chip U6;

[0240] The fourth end of the MIC interface J12 is connected to the first end of the inductor LS325.

[0241] The sixth terminal of the MIC interface J12 is connected to the first terminal of the inductor LS1.

[0242] The second end of the MIC interface J12, the second end of the capacitor C77, the second end of the transient diode LTVS10, the second end of the inductor LS325, the second end of the inductor LS1, the second end of the transient diode LTVS11, and the second end of the capacitor C78 are connected to the power ground.

[0243] The model of SOC chip U6 is ITE9866.

[0244] The internal power supply circuit of the SOC chip is connected as follows Figure 7 As shown, there are three parts of internal power supply circuits, which respectively convert the power supply +1.2V into the power supply VDD1V2_CORE, the power supply +1.8V into +1.8V_MCU, and the power supply +3.3VSW into the power supply VDD33_IO; the third part of the internal power supply circuit also includes: converting the power supply VDD33_IO into the power supply VDD3.3V_SAR, the power supply VDD3V3A, and the power supply VCC_RTC.

[0245] The internal power supply circuit of the first part of the SOC includes: a first end of the inductor L6 is connected to the power supply +1.2V; the second end of the inductor L6 outputs the power supply VDD1V2_CORE, and is connected to the first end of the capacitor C50, the first end of the capacitor C51, the first end of the capacitor C52, the first end of the capacitor C53, the first end of the capacitor C54, the first end of the capacitor C55, the first end of the capacitor C56, the first end of the capacitor C57, the first end of the capacitor C58, the first end of the capacitor C59, the first end of the capacitor C60, the first end of the capacitor C61, and the first end of the capacitor C62; the second end of the capacitor C50, the second end of the capacitor C51, the second end of the capacitor C52, the second end of the capacitor C53, the second end of the capacitor C54, the second end of the capacitor C55, the second end of the capacitor C56, the second end of the capacitor C57, the second end of the capacitor C58, the second end of the capacitor C59, the second end of the capacitor C60, the second end of the capacitor C61, and the second end of the capacitor C62 are connected to the power ground;

[0246] The internal power supply circuit of the second part of the SOC includes: the first end of the inductor L8 is connected to the power supply +1.8V; the second end of the inductor L8 outputs the power supply +1.8V_MCU, and is connected to the first end of the capacitor C80, the first end of the capacitor C81, the first end of the capacitor C82, the first end of the capacitor C83, and the first end of the capacitor C84; the second end of the capacitor C80, the second end of the capacitor C81, the second end of the capacitor C82, the second end of the capacitor C83, and the second end of the capacitor C84 are connected to the power ground;

[0247] The internal power supply circuit of the third part of the SOC includes: the first end of the inductor L7 is connected to the power supply +3.3VSW; the second end of the inductor L7 outputs the power supply VDD33_IO, and is connected to the first end of the capacitor C65, the first end of the capacitor C66, the first end of the capacitor C67, the first end of the capacitor C68, and the first end of the capacitor C69, and the second end of the capacitor C65, the second end of the capacitor C66, the second end of the capacitor C67, the second end of the capacitor C68, and the second end of the capacitor C69 are connected to the power ground; in addition, the second end of the inductor L7 can also be connected to the first end of the capacitor C70, the first end of the capacitor C71, the first end of the capacitor C72, the first end of the capacitor C73, the first end of the capacitor C74, and the first end of the capacitor C75, and the second end of the capacitor C70, the second end of the capacitor C71, the second end of the capacitor C72, the second end of the capacitor C73, the second end of the capacitor C74, and the second end of the capacitor C75 are connected to the power ground.

[0248] The third part of the SOC internal power supply circuit also includes three sub-power supply circuits:

[0249] The first sub-power supply circuit includes: a power supply VDD33_IO is connected to a first end of a resistor R39, a second end of the resistor R39 outputs a power supply VDD3.3V_SAR and is connected to a first end of a capacitor C85 and a first end of a capacitor C86, and a second end of the capacitor C85 and a second end of the capacitor C86 are connected to a power ground;

[0250] The second sub-power supply circuit includes: a power supply VDD33_IO is connected to a first end of a resistor R40, a second end of the resistor R40 outputs a power supply VDD3V3A and is connected to a first end of a capacitor C87, a first end of a capacitor C88, and a first end of a capacitor C89, and a second end of the capacitor C87, a second end of the capacitor C88, and a second end of the capacitor C89 are connected to a power ground;

[0251] The third sub-power supply circuit includes: a power supply VDD33_IO is connected to a first end of a resistor R41, a second end of the resistor R41 outputs a power supply VCC_RTC and is connected to a first end of a capacitor CO5 and a first end of a capacitor C90, and a second end of the capacitor CO5 and a second end of the capacitor C90 are connected to a power ground.

[0252] The power supply +3.3VSW is converted into the power supply VDD33_IO; the third part of the internal power supply circuit also includes: converting the power supply VDD33_IO into the power supply VDD3.3V_SAR, the power supply VDD3V3A, and the power supply VCC_RTC respectively.

[0253] The circuit of DSP chip is as follows Fig.10 As shown:

[0254] The crystal oscillator input terminal XTALI of the DSP chip UR1 is connected to the first terminal of the capacitor CR7 and the third terminal of the crystal oscillator XR1.

[0255] The crystal oscillator output terminal XTALO of the DSP chip UR1 is connected to the first end of the resistor RR19, the second end of the resistor RR19 is connected to the first end of the capacitor CR6 and the first end of the crystal oscillator XR1, the second end of the capacitor CR6 and the second end of the capacitor CR7 are connected to the power ground; the second end and the fourth end of the crystal oscillator XR1 are both connected to the power ground;

[0256] A frequency screening circuit is required between the DSP chip and the FM socket to allow signals within a specific frequency range to pass through, while preventing other frequency signals from passing through. It is used to ensure that only useful signals are passed to subsequent processing units, thereby improving the overall performance and stability of the system. Specifically: the frequency modulation input terminal FMI of the DSP chip UR1 is connected to the first end of the capacitor CR5, the first end of the inductor LR1, and the first end of the inductor LR2, and the second end of the inductor LR2 and the second end of the capacitor CR5 are respectively connected to the power ground; the second end of the inductor LR1 is connected to the first end of the capacitor CR4, and the second end of the capacitor CR4 is connected to the first end of the capacitor CR2 and the first end of the capacitor CR3; the second end of the capacitor CR3 is connected to the first end of the inductor LR6 and the first end of the capacitor CR38; the second end of the inductor LR6 and the second end of the capacitor CR38 are connected to the first end of the capacitor CR39, the first end of the transient diode LTVS18, and the input end of the bandpass filter circuit, and the output end of the bandpass filter circuit is connected to the first end of the capacitor CR41; the bandpass filter circuit includes: a resistor RR31, an inductor LR8, and a capacitor CR40 connected in parallel;

[0257] The second end of the capacitor CR39 is connected to the first end of the inductor LR7, and the second end of the inductor LR7 is connected to the power ground; the second end of the transient diode LTVS18 is connected to the power ground;

[0258] The second end of the capacitor CR41 is connected to the amplitude modulation input terminal AMI of the DSP chip UR1;

[0259] The second end of the capacitor CR2, the first end of the transient diode LTVS17, and the antenna socket are connected to the power supply TUNER_RF; the power supply TUNER_RF is provided by the power chip U8. The second end of the transient diode LTVS17 is connected to the power ground;

[0260] The channel selection terminal ABYP of the DSP chip UR1 is connected to the first end of the capacitor CR42, the first end of the capacitor CR43, the first end of the capacitor CR44, the first end of the capacitor CR45, the first end of the capacitor CR46 and the first end of the inductor LR9, and the second end of the inductor LR9 is connected to the power supply +3.3VSW;

[0261] The analog input positive terminal AIN0P of the DSP chip UR1 is connected to the first end of the capacitor CR47, and the second end of the capacitor CR47 is connected to the first end of the resistor RR35.

[0262] The analog input negative terminal AIN0N of the DSP chip UR1 is connected to the first end of the capacitor CR48, and the second end of the capacitor CR48 is connected to the first end of the capacitor CR50, the first end of the capacitor CR52, the first end of the capacitor CR54, the first end of the capacitor CR55, the first end of the capacitor CR56, the first end of the capacitor CR57, the first end of the capacitor CR58, and the first end of the capacitor CR60 and the power ground;

[0263] The analog input positive terminal AIN1P of the DSP chip UR1 is connected to the first end of the capacitor CR49, and the second end of the capacitor CR49 is connected to the first end of the resistor RR36;

[0264] The analog input negative terminal AIN1N of the DSP chip UR1 is connected to the second end of the capacitor CR50.

[0265] The analog input positive terminal AIN2P of the DSP chip UR1 is connected to the first end of the capacitor CR51, the second end of the capacitor CR51 is connected to the first end of the resistor RR32, the second end of the resistor RR32 is connected to the first end of the capacitor C140, and the second end of the capacitor C140 is connected to the signal transmission end of the AMP chip and the signal transmission end of the SOC chip respectively;

[0266] The analog input negative terminal AIN2N of the DSP chip UR1 is connected to the second terminal of the capacitor CR52;

[0267] The analog input positive terminal AIN3P of the DSP chip UR1 is connected to the first end of the capacitor CR53, the second end of the capacitor CR53 is connected to the first end of the resistor RR33, the second end of the resistor RR33 is connected to the first end of the capacitor C141, and the second end of the capacitor C141 is connected to the signal transmission end of the AMP chip and the signal transmission end of the SOC chip respectively;

[0268] The analog input negative terminal AIN3N of the DSP chip UR1 is connected to the second terminal of the capacitor CR54;

[0269] The analog input positive terminal AIN4P of the DSP chip UR1 is connected to the second terminal of the capacitor CR55;

[0270] The analog input negative terminal AIN4N of the DSP chip UR1 is connected to the second terminal of the capacitor CR56;

[0271] The analog input positive terminal AIN5P of the DSP chip UR1 is connected to the second terminal of the capacitor CR57;

[0272] The analog input negative terminal AIN5N of the DSP chip UR1 is connected to the second end of the capacitor CR58 and the first end of the resistor RR39;

[0273] The analog input positive terminal AIN6P of the DSP chip UR1 is connected to the second end of the resistor RR39 and the first end of the capacitor CR59, and the second end of the capacitor CR59 is connected to the first end of the resistor RR34;

[0274] The analog input negative terminal AIN6N of the DSP chip UR1 is connected to the second terminal of the capacitor CR60;

[0275] The second end of the resistor RR35, the second end of the resistor RR36, the second end of the resistor RR37, the second end of the resistor RR38, and the second end of the resistor RR34 are connected to the power ground;

[0276] The reset signal terminal RSTB of the DSP chip UR1 is connected to the first end of the resistor RR42 and the reset control terminal of the SOC chip;

[0277] The mode selection terminal SMODE of the DSP chip UR1 is connected to the first end of the resistor RR40 and the first end of the resistor RR43; the second end of the resistor RR40 is connected to the power ground;

[0278] The interrupt request terminal INTB of the DSP chip UR1 is connected to the first end of the resistor RR41 and the interrupt request data terminal of the SOC chip;

[0279] The second end of the resistor RR41, the second end of the resistor RR42, and the second end of the resistor RR43 are connected to the power supply DSP_VIO1_3V3 / 1V8;

[0280] The data output terminal MISO / A0 of the DSP chip UR1 is connected to the first end of the resistor RB33, and the second end of the resistor RB33 is connected to the first end of the resistor RB29 and the data receiving end of the SOC chip;

[0281] The data receiving terminal MOSI / SDA of the DSP chip UR1 is connected to the first end of the resistor RB32, and the second end of the resistor RB32 is connected to the first end of the resistor RB28 and the data output terminal of the SOC chip;

[0282] The clock terminal SCLK / SCL of the DSP chip UR1 is connected to the first end of the resistor RB31, and the second end of the resistor RB31 is connected to the first end of the resistor RB27 and the clock control terminal of the SOC chip.

[0283] The chip select signal receiving terminal SSB / A1 of the DSP chip UR1 is connected to the first end of the resistor R0.1B30, and the second end of the resistor RB30 is connected to the first end of the resistor RB26 and the chip select control terminal of the SOC chip.

[0284] The second end of the resistor RB26, the second end of the resistor RB27, the second end of the resistor RB28, and the second end of the resistor RB29 are connected to the power supply +3.3VSW;

[0285] The digital bypass terminal DBYP of the DSP chip UR1 is connected to the first end of capacitor CR18, the first end of capacitor CR20, the first end of capacitor CR22, the first end of capacitor CR24, the first end of capacitor CR26, the first end of capacitor CR28, the first end of capacitor CR19, the first end of capacitor CR21, the first end of capacitor CR23, the first end of capacitor CR25, the first end of capacitor CR27, and the first end of capacitor CR29; the first end of capacitor CR30, the first end of capacitor CR31, the first end of capacitor CR32, the first end of capacitor CR33, the first end of capacitor CR34, the first end of capacitor CR35, the first end of capacitor CR36, and the first end of capacitor CR37;

[0286] The second end of capacitor CR19, the second end of capacitor CR21, the second end of capacitor CR23, the second end of capacitor CR25, the second end of capacitor CR27, the second end of capacitor CR29, and the first end of inductor LR3 are connected to the power supply DSP_DVDD1V8_250MA; the second end of inductor LR3 is connected to the first end of capacitor CR29 and the power supply +1.8V; the second end of capacitor CR29 is connected to the power supply ground;

[0287] The second end of capacitor CR30, the second end of capacitor CR31, the second end of capacitor CR32, the second end of capacitor CR33, the second end of capacitor CR34, the second end of capacitor CR35, the second end of capacitor CR36, the second end of capacitor CR37, and the first end of inductor LR5 are connected to power supply DSP_VIO1_3V3 / 1V8; the second end of inductor LR5 is connected to power supply +3.3VSW;

[0288] The second power input terminal VIO2 of the DSP chip UR1 is connected to the second end of the capacitor CR18, the second end of the capacitor CR20, the second end of the capacitor CR22, the second end of the capacitor CR24, the second end of the capacitor CR26, the second end of the capacitor CR28, the first end of the inductor LR4 and DSP_VIO2_3V3 / 1V8, and the second end of the inductor LR4 is connected to the power supply +3.3VSW;

[0289] The data input terminal NC of the DSP chip UR1 is connected to the first end of the resistor RR29, the second end of the resistor RR29 is connected to the first end of the resistor RR50 and the data output terminal of the Bluetooth WIFI chip, and the second end of the resistor RR50 is connected to the digital audio output terminal of the SOC chip.

[0290] The digital input frame synchronization terminal DIFS2 of the DSP chip UR1 is connected to the first end of the resistor RR28, the second end of the resistor RR28 is connected to the first end of the resistor RR51 and the frame synchronization clock signal output terminal of the Bluetooth WIFI chip, and the second end of the resistor RR51 is connected to the clock signal output terminal of the SOC chip.

[0291] The digital input clock terminal DICLK2 of the DSP chip UR1 is connected to the first end of the resistor RR27, the second end of the resistor RR27 is connected to the first end of the resistor RR52 and the data clock signal output end of the Bluetooth WIFI chip, and the second end of the resistor RR52 is connected to the clock signal control end of the SOC chip;

[0292] The first analog audio output terminal of the DSP chip UR1 is connected to the first end of the resistor RR23, the second end of the resistor RR23 is connected to the first end of the capacitor CR17 and the first end of the capacitor CR8, and the second end of the capacitor CR17 is connected to the audio left channel input terminal of the AMP chip;

[0293] The first analog audio output terminal of the DSP chip UR1 is connected to the first end of the resistor RR22, the second end of the resistor RR22 is connected to the first end of the capacitor CR16 and the first end of the capacitor CR9, and the second end of the capacitor CR16 is connected to the audio right channel input terminal of the AMP chip;

[0294] The third analog audio output terminal of the DSP chip UR1 is connected to the first end of the resistor RR21, and the second end of the resistor RR21 is connected to the first end of the capacitor CR10;

[0295] The fourth analog audio output terminal of the DSP chip UR1 is connected to the first end of the resistor RR20, and the second end of the resistor RR20 is connected to the first end of the capacitor CR11;

[0296] The second end of the capacitor CR8, the second end of the capacitor CR9, the second end of the capacitor CR10, and the second end of the capacitor CR11 are connected to the power ground;

[0297] The model of DSP chip UR1 is Si47920.

[0298] The power supply circuit of DSP chip is as follows Fig.11 As shown, it outputs two power supplies, power supply TUNER_RF and power supply CAMPOW+8V, of which power supply TUNER_RF is used to power the DSP chip. The details are as follows:

[0299] The power input terminal IN of the power chip U8, the first terminal of the capacitor CD1, and the first terminal of the capacitor C91 are connected to the power supply +VBATT, and the second terminal of the capacitor CD1 and the second terminal of the capacitor C91 are connected to the power ground;

[0300] The first enable terminal EN1 of the power chip U8 is connected to the first end of the resistor RO9, and the second end of the resistor RO9 is connected to the FM enable control terminal of the MCU chip.

[0301] The first enable terminal EN2 of the power chip U8 is connected to the first end of the resistor RO18, and the second end of the resistor RO18 is connected to the camera enable control terminal of the MCU chip;

[0302] The power supply terminal VCC of the power supply chip U8 is connected to the first terminal of the capacitor CO8.

[0303] The first current sensing output terminal SENSE1 of the power chip U8 is connected to the first end of the resistor RO7 and the first end of the capacitor CO6, and the second end of the resistor RO7, the second end of the capacitor CO6 and the second end of the capacitor CO8 are connected to the power ground;

[0304] The first current sensing output terminal SENSE2 of the power chip U8 is connected to the first end of the resistor RO8 and the first end of the capacitor CO7; the second end of the resistor RO8 and the second end of the capacitor CO7 are connected to the power ground;

[0305] The enable control terminal SENSE_SEL of the power chip U8 is connected to the first end of the resistor RO10, and the second end of the resistor RO10 is connected to the power ground.

[0306] The current sensing enable terminal SENSE_EN of the power chip U8 is connected to the first end of the resistor RO11, and the second end of the resistor RO11 is connected to the power ground.

[0307] The first power output terminal OUT1 of the power chip U8 is connected to the first end of the inductor LD1 and the first end of the resistor RO13, and the second end of the inductor LD1 is connected to the first end of the capacitor CD2, the first end of the capacitor CD3, and the first end of the inductor LD2; the second end of the inductor LD2 outputs the power supply TUNER_RF; the second end of the capacitor CD2 and the second end of the capacitor CD3 are connected to the power ground;

[0308] The first feedback terminal FB1 of the power chip U8 is connected to the second end of the resistor RO13 and the first end of the resistor RO15. The second end of the resistor RO15, the first end of the resistor RO17, the first end of the resistor RO16 and the first end of the resistor RO14 are connected to the power ground.

[0309] The first power output terminal OUT2 of the power chip U8 outputs the power supply CAMPOW+8V, and is connected to the first end of the resistor RO12, the first end of the capacitor CD6, and the first end of the capacitor CD5; the second end of the capacitor CD6 and the second end of the capacitor CD5 are connected to the power ground;

[0310] The first feedback terminal FB2 of the power chip U8 is connected to the second end of the resistor RO12 and the second end of the resistor RO17;

[0311] The ground terminal GND of the power chip U8 is connected to the power ground;

[0312] The first current limiting terminal LIM1 of the power chip U8 is connected to the second terminal of the resistor RO16;

[0313] The second current limiting terminal LIM2 of the power chip U8 is connected to the second end of the resistor RO14.

[0314] The model of the power chip U8 is TPS7B7702.

[0315] The circuit connection of AMP chip (audio power amplifier chip) is as follows Fig.12 shown.

[0316] The mode selection terminal MODSEL of the AMP chip U9 is connected to the power ground;

[0317] The input terminal SDZ of the audio amplifier of the AMP chip U9 and the fault terminal FAULTZ of the AMP chip U9 are connected to the first end of the resistor R129 and the first end of the resistor R130; the second end of the resistor R129 is connected to the control end of the MCU chip; the second end of the resistor R130 is connected to the power ground;

[0318] The right channel positive audio input terminal RINP of the AMP chip U9 is connected to the first end of the capacitor C94, the second end of the capacitor C94 is connected to the first end of the resistor R128 and the audio right channel data output terminal of the DSP chip, and the second end of the resistor R128 is connected to the SOC chip ADC signal right channel output terminal;

[0319] The right channel negative audio input terminal RINN of the AMP chip U9 is connected to the first terminal of the capacitor C95;

[0320] The power limiting terminal PLIMIT of the AMP chip U9 is connected to the first end of the resistor R126 and the first end of the resistor R127;

[0321] The internal power supply terminal GVDD of the AMP chip U9 is connected to the second end of the resistor R127, the first end of the resistor R42, and the first end of the capacitor C92;

[0322] The gain selection terminal GAIN / SLV of the AMP chip U9 is connected to the second end of the resistor R42 and the first end of the resistor R43;

[0323] The ground terminal GND of the AMP chip U9, the second end of the capacitor C95, the second end of the resistor R126, the second end of the capacitor C92, and the second end of the resistor R43 are connected to the power ground;

[0324] The left channel positive audio input terminal LINP of the AMP chip U9 is connected to the first end of the capacitor C93, the second end of the capacitor C93 is connected to the first end of the resistor R125 and the audio left channel data output terminal of the DSP chip, and the second end of the resistor R125 is connected to the SOC chip ADC signal right channel output terminal;

[0325] The left channel negative audio input terminal LINN of the AMP chip U9 is connected to the first end of the capacitor C96, and the second end of the capacitor C96 is connected to the power ground;

[0326] The mute control terminal MUTE of the AMP chip U9 is connected to the mute control terminal of the MCU chip and the first end of the resistor R45, and the second end of the resistor R45 is connected to the power supply +5VCAN;

[0327] The amplitude modulation frequency terminal AM2 of the AMP chip U9 is connected to the power ground;

[0328] The amplitude modulation frequency terminal AM1 of the AMP chip U9 is connected to the power ground;

[0329] The amplitude modulation frequency terminal AMO of the AMP chip U9 is connected to the amplitude modulation frequency terminal of the MCU chip;

[0330] The power supply terminal AVCC of the AMP chip U9, the power supply terminal PVCC of the AMP chip U9, the power supply terminal PVCC of the AMP chip U9, the first end of the capacitor CR62, the first end of the capacitor C104, the first end of the capacitor C106, and the positive electrode of the polarized capacitor C106 are connected to the power supply +VBATT; the second end of the capacitor CR62, the second end of the capacitor C104, the second end of the capacitor C106, and the positive electrode of the polarized capacitor C106 are connected to the power supply ground;

[0331] The bootstrap terminal BSNL of the left channel negative output of the AMP chip U9 is connected to the first end of the capacitor C103, the second end of the capacitor C103 is connected to the left channel negative output terminal OUTNL of the AMP chip U9 and the first end of the inductor L10, the second end of the inductor L10 outputs the left channel negative pole and is connected to the first end of the capacitor C111, the first end of the capacitor C115, and the first end of the resistor R50, the second end of the resistor R50 is connected to the first end of the capacitor C118, and the second end of the capacitor C118 is connected to the power ground; the second end of the capacitor C111 and the second end of the capacitor C115 are connected to the power ground;

[0332] The ground terminal GND of the AMP chip U9 is connected to the power ground;

[0333] The left channel positive output terminal OUTPL of the AMP chip U9 is connected to the first end of the capacitor C102 and the first end of the inductor L9. The second end of the inductor L9 outputs the left channel positive electrode and is connected to the first end of the capacitor C109, the first end of the capacitor C113, and the first end of the resistor R49. The second end of the resistor R49 is connected to the first end of the capacitor C117, and the second end of the capacitor C117 is connected to the power ground; the second end of the capacitor C109 and the second end of the capacitor C113 are connected to the power ground;

[0334] The bootstrap terminal BSPL of the left channel positive output of the AMP chip U9 is connected to the second end of the capacitor C102.

[0335] The bootstrap terminal BSNR of the negative right channel output of the AMP chip U9 is connected to the first end of the capacitor C101, the second end of the capacitor C101 is connected to the negative right channel output terminal OUTNR of the AMP chip U9 and the first end of the inductor L12, the second end of the inductor L12 outputs the negative pole of the right channel and is connected to the first end of the capacitor C110, the first end of the capacitor C114, and the first end of the resistor R48, the second end of the resistor R48 is connected to the first end of the capacitor C119, and the second end of the capacitor C119 is connected to the power ground; the second end of the capacitor C110 and the second end of the capacitor C114 are connected to the power ground;

[0336] The positive right channel output terminal OUTPR of the AMP chip U9 is connected to the first end of the capacitor C99 and the first end of the inductor L11. The second end of the inductor L11 outputs the positive electrode of the right channel and is connected to the first end of the capacitor C108, the first end of the capacitor C112, and the first end of the resistor R47. The second end of the resistor R47 is connected to the first end of the capacitor C116, and the second end of the capacitor C116 is connected to the power ground; the second end of the capacitor C108 and the second end of the capacitor C112 are connected to the power ground;

[0337] The bootstrap terminal BSPR of the positive right channel output of the AMP chip U9 is connected to the second terminal of the capacitor C99;

[0338] The power supply terminal PVCC of the AMP chip U9, the first end of the resistor R46, the first end of the capacitor CR61, the first end of the capacitor C98, the first end of the capacitor C100, and the positive electrode of the polarized capacitor C105 are connected to the power supply +VBATT, the second end of the resistor R46 is connected to the first end of the capacitor C97, and the second end of the capacitor C97 is connected to the power ground; the second end of the capacitor CR61, the second end of the capacitor C98, the second end of the capacitor C100, and the negative electrode of the polarized capacitor C105 are connected to the power ground.

[0339] The model of AMP chip U9 is TPA3116.

[0340] The circuit connection of Bluetooth WIFI chip is as follows Fig.13The RF signal transmission terminal WL_BT_ANT of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB54 and the first end of the capacitor CB11, the second end of the capacitor CB11 is connected to the power ground, the second end of the resistor RB54 is connected to the antenna interface JB1 and the first end of the capacitor CB12, and the second end of the capacitor CB12 is connected to the power ground;

[0341] The power input terminal VBAT of the Bluetooth WIFI chip UB1 is connected to the first end of the capacitor CB8, the first end of the capacitor CB10, the first end of the capacitor CB7, and the first end of the inductor LB1, and the second end of the inductor LB1 is connected to the power supply VCC_3V3;

[0342] The crystal oscillator input terminal XTAL_IN of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB60.

[0343] The crystal oscillator output terminal XTAL_OUT of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB61, the first end of the capacitor CB16, and the first end of the crystal oscillator XB2; ​​the second end of the resistor RB60, the second end of the resistor RB61, and the second end of the crystal oscillator XB2 are connected to the first end of the capacitor CB15; the second end of the capacitor CB15, the second end of the capacitor CB16, and the ground end of the crystal oscillator XB2 are connected to the power ground;

[0344] The internal regulator start-up terminal WL_REG_ON of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB51 and the first end of the resistor RB52, the second end of the resistor RB51 is connected to the enable terminal of the SOC chip; the second end of the resistor RB52 is connected to the power ground;

[0345] The power input terminal VDDIO of the Bluetooth WIFI chip UB1, the first end of the capacitor C84, and the first end of the capacitor C83 are connected to the power supply VCC_3V3, and the second end of the capacitor C84 and the second end of the capacitor C83 are connected to the power ground;

[0346] The internal buck terminal VIN_LDO of the Bluetooth WIFI chip UB1 is connected to the first end of the capacitor CB19 and the first end of the inductor LB2, the second end of the capacitor CB19 is connected to the power ground, and the second end of the inductor LB2 is connected to the internal buck terminal VIN_LDO_OUT of the Bluetooth WIFI chip UB1;

[0347] The PCM data output terminal LPO of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB62, the first end of the resistor RB63, and the first end of the resistor RB64. The second end of the resistor RB62 is connected to the power ground, the second end of the resistor RB64 is connected to the power supply VCC_3V3, the second end of the resistor RB63 is connected to the first end of the capacitor CB20 and the third end of the external crystal oscillator XB1, the second end of the capacitor CB20 and the second end of the external crystal oscillator XB1 are connected to the power ground; the first end of the external crystal oscillator XB1 is connected to the first end of the resistor RB67, the first end of the resistor RB68, the fourth end of the external crystal oscillator XB1, and the first end of the capacitor CB43, the second end of the capacitor CB43 is connected to the power ground, and the second end of the resistor RB68 is connected to the power supply VCC_3V3;

[0348] The ground terminal GND of the Bluetooth WIFI chip UB1 is connected to the power ground;

[0349] The internal regulator start-up terminal BT_REG_ON of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB57 and the first end of the resistor RB58, and the second end of the resistor RB58 is connected to the power ground;

[0350] The UART signal transmitting end UART_TXD of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB25 and the first end of the resistor RB55, the second end of the resistor RB25 is connected to the power ground, and the second end of the resistor RB55 is connected to the UART signal receiving end of the SOC chip;

[0351] The UART signal receiving terminal UART_RXD of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB23 and the first end of the resistor RB56, the second end of the resistor RB23 is connected to the power ground, and the second end of the resistor RB56 is connected to the UART signal sending terminal of the SOC chip;

[0352] The model of the Bluetooth WIFI chip UB1 is AP6256.

[0353] The power supply circuit of Bluetooth WIFI chip is as follows Fig.14 As shown. The power supply +3.3VSW is connected to the first end of the capacitor CB509, the first end of the resistor RB34, and the source of the P-MOS; the gate of the P-MOS is connected to the second end of the capacitor CB509, the second end of the resistor RB34, and the first end of the resistor RB35; the drain of the P-MOS outputs the power supply VCC_3V3 and is connected to the first end of the resistor RB36, and the second end of the resistor RB36 is connected to the power ground;

[0354] The second end of resistor RB35 is connected to the collector of transistor QB4; the base of transistor QB4 is connected to the first end of resistor RB43 and the first end of resistor RB44; the second end of resistor RB43 is connected to the WiFi enable end of the SOC chip; the second end of resistor RB44 is connected to the power ground; the emitter of transistor QB4 is connected to the power ground.

[0355] The SOC chip controls the conduction and cutoff of the transistor QB4 by controlling the level of the WiFi enable terminal, and then controls the conduction and cutoff of the P-MOS to realize the opening and closing of the power supply circuit of the Bluetooth WIFI chip. In this way, when the instrument panel is dormant, the SOC chip can turn off the power supply of the Bluetooth WIFI chip to save energy.

[0356] The circuit connection of CVBS chip is as follows Fig.15 shown.

[0357] The digital power supply terminal DVDDIO of the CVBS chip UI1 is connected to the first end of the capacitor CI4, the first end of the capacitor CI3, the first end of the capacitor CI5, and the first end of the isolation chip LI3 (used to solve the EMC problem); the second end of the capacitor CI4, the second end of the capacitor CI3, and the second end of the capacitor CI5 are connected to the power ground; the second end of the isolation chip LI3 is connected to the power supply +3.3VSW; the power supply terminal DVDD of the CVBS chip UI1 is connected to the first end of the capacitor CI24, the first end of the capacitor CI25, the first end of the capacitor CI9, the first end of the capacitor CI8, the first end of the capacitor CI7, and the first end of the isolation chip LI1; the second end of the capacitor CI24, the second end of the capacitor CI25, the second end of the capacitor CI9, the second end of the capacitor CI8, and the second end of the capacitor CI7 are connected to the power ground; the second end of the isolation chip LI3 is connected to the power supply +1.8V;

[0358] The power supply terminal AVDD of the CVBS chip UI1 and the PLL Supply Voltage terminal PVDD of the (18) CVBS chip UI1 are connected to the first end of the capacitor CI23, the first end of the capacitor CI22, the first end of the capacitor CI11, the first end of the capacitor CI21, the first end of the capacitor CI10, and the first end of the isolation chip LI2, which are connected to the power supply AVDD_1.8V, and the second end of the isolation chip LI2 is connected to the power supply +1.8V; the second end of the capacitor CI23, the second end of the capacitor CI22, the second end of the capacitor CI11, the second end of the capacitor CI21, and the second end of the capacitor CI10 are connected to the power ground; the filter terminal ELPF of the CVBS chip UI1 is connected to the first end of the capacitor CI5, the second end of the capacitor CI5 is connected to the first end of the resistor RI1, the first end of the resistor RI2, and the second end of the resistor RI2 is connected to the power ground; the second end of the resistor RI1 and the first end of the transient diode LTVS4 are connected to the interface J1; the second end of the transient diode LTVS4 is connected to the power ground;

[0359] The analog video input terminal AIN1 of the CVBS chip UI1 is connected to the first end of the capacitor CI6, the ground terminal AGND of the CVBS chip UI1 is connected to the first end of the capacitor CI18, the second end of the capacitor CI6 and the second end of the capacitor CI18 are connected to the power ground; the internal voltage reference output terminal VREFP of the CVBS chip UI1 is connected to the first end of the capacitor CI20, the first end of the resistor RI7, and the reset control terminal of the SOC chip, the second end of the capacitor CI20 is connected to the power ground, and the second end of the resistor RI7 is connected to the power supply +3.3VSW; the ground terminal AGND of the CVBS chip UI1 is connected to the capacitor C The first end of I19 is connected, the power supply terminal PVDD of the CVBS chip UI1 is connected to the second end of the capacitor CI19, the crystal oscillator terminal XTAL of the CVBS chip UI1 is connected to the first end of the resistor RI12, the second end of the resistor RI12 is connected to the first end of the crystal oscillator XI1, the first end of the resistor RI13, and the first end of the capacitor CI15, the clock signal terminal XTAL1 of the CVBS chip UI1 is connected to the second end of the resistor RI13, the second end of the crystal oscillator XI1, and the first end of the capacitor CI16, and the ground terminal of the crystal oscillator XI1, the second end of the capacitor CI15, and the second end of the capacitor CI16 are connected to the power ground;

[0360] The internal voltage reference output terminal VREFN of the CVBS chip UI1 is connected to the first end of the resistor RI20 and the first end of the resistor RI21, the second end of the resistor RI20 is connected to the power ground, and the second end of the resistor RI21 is connected to the power supply +3.3VSW; the ground terminal AGND of the CVBS chip UI1 is connected to the first end of the resistor RI22, and the second end of the resistor RI22 is connected to the serial clock of the SOC chip; the power supply terminal AVDD of the CVBS chip UI1 is connected to the first end of the resistor RI23, and the second end of the resistor RI23 is connected to the serial data of the SOC chip; the data transmission end of the CVBS chip UI1 is connected to the video data transmission end of the SOC chip, the output pixel data terminal LLC interrupt terminal of the CVBS chip UI1 is connected to the first end of the capacitor CI17 and the first end of the capacitor RI8, the second end of the capacitor CI17 is connected to the power ground, and the second end of the capacitor RI8 is connected to the power supply +3.3VSW; the video pixel output terminal P0 of the CVBS chip UI1 is connected to the first end of the resistor RI24 and the first end of the capacitor CI26; the resistor R The second end of I24 is connected to the first end of capacitor CI27; the second end of capacitor CI26 and the second end of capacitor CI27 are connected to the power supply AVDD_1.8V.

[0361] The model of CVBS chip UI1 is ADV7180.

[0362] The circuit connection of TFT screen is as follows Fig.16 As shown. The boost converter U10 is connected to the MCU chip and the interface J13. The boost converter U10 is a 4-channel current source boost converter, which uses a peak current controlled PWM control structure to adjust the boost converter. The 4-channel current source is applied to the LED cathode interface to adjust the LED brightness. In addition, the interface J13 is also connected to the MCU chip, the SOC chip, and the TFT screen.

[0363] The dimming terminal DIM of the boost converter U10 is connected to the first end of the resistor R57 and the backlight brightness adjustment terminal of the MCU chip, and the backlight brightness adjustment of the TFT screen is realized by the pulse width modulation signal output by the backlight brightness adjustment terminal of the MCU chip. The second end of the resistor R57 is connected to the power ground; the dimming mode setting terminal MIX / AD of the boost converter U10 is connected to the first end of the resistor R56, and the second end of the resistor R56 is connected to the power ground; the switching frequency setting / synchronization pin terminal FREQ / SYNC of the boost converter U10 is connected to the first end of the resistor R58, and the second end of the resistor R58 is connected to the power ground; the enable terminal EN of the boost converter U10 is connected to the first end of the resistor R55 and the enable control terminal of the MCU chip to control the switching state of the backlight module TFT screen. When the TFT_BL_EN signal is high, the backlight module is activated and lights up; when the signal is low, the backlight module TFT screen is turned off. The second end of the resistor R55 is connected to the power ground; the clock input terminal SCL / PSE of the boost converter U10 is connected to the first end of the resistor R60 and the first end of the resistor R53, and the second end of the resistor R53 is connected to the power supply VCC; the data input terminal SDA / PSE of the boost converter U10 is connected to the second end of the resistor R60 and the first end of the resistor R51, and the second end of the resistor R51 is connected to the power ground;

[0364] The compensation terminal COMP of the boost converter U10 is connected to the first end of the resistor R59 and the first end of the capacitor C120, the second end of the resistor R59 is connected to the first end of the capacitor C121, the second end of the capacitor C120 and the second end of the capacitor C121 are connected to the power ground; the fault flag terminal FF of the boost converter U10 is connected to the first end of the resistor R61 and the first end of the resistor R62, the second end of the resistor R61 is connected to the power supply +5VCAN, and the second end of the resistor R62 is connected to the backlight fault indication terminal of the MCU chip; when there is a power failure, abnormal brightness, overheating, etc., the MCU can receive the TFT_BL_FLT signal and take corresponding measures, such as shutting down the backlight system, issuing a warning signal or restarting the backlight system, etc., to ensure the safety and stable operation of the equipment. The LED current setting terminal ISET of the boost converter U10 is connected to the first end of the resistor R64 and the first end of the resistor R63, the second end of the resistor R64 and the second end of the resistor R63 are connected to the power ground; the ground terminal AGND of the boost converter U10 is connected to the power ground;

[0365] The string 4 current input terminal LED4 of the boost converter U10, the string 3 current input terminal LED3 of the boost converter U10, and the string 2 current input terminal LED2 of the boost converter U10 are all connected to the LED transmission interface of the interface J13; the string 1 current input terminal LED1 of the boost converter U10 and the boost converter ground terminal PGND of the boost converter U10 are connected to the power ground;

[0366] The power inductor connection terminal SW of the boost converter U10 is connected to the first end of the inductor L13, the first end of the resistor R71, and the positive electrode of the diode D11, the second end of the resistor R71 is connected to the first end of the capacitor C130, and the second end of the capacitor C130 is connected to the power ground;

[0367] The cathode of the diode D11 is connected to the first end of the capacitor C131, the first end of the capacitor C132, the first end of the capacitor C133, the first end of the capacitor C134, the first end of the resistor R78, and the first end of the resistor R80, and the second end of the resistor R80 outputs the power supply TFT_BL+; the second end of the capacitor C131, the second end of the capacitor C132, the second end of the capacitor C133, and the second end of the capacitor C134 are all connected to the power ground; the second end of the resistor R78 is connected to the first end of the resistor R79, the second end of the resistor R79 is connected to the first end of the resistor R77 and the overvoltage protection terminal OVP of the boost converter U10, and the second end of the resistor R77 is connected to the power ground; the capacitor C134 is a polar capacitor.

[0368] The configuration voltage terminal STH of the boost converter U10 is connected to the first end of the resistor R70 and the first end of the capacitor C129, and the second end of the resistor R70 and the second end of the capacitor C129 are connected to the power ground; the IC address setting terminal ADR of the boost converter U10 is connected to the first end of the resistor R69 and the first end of the capacitor C128, and the second end of the resistor R69 and the second end of the capacitor C128 are connected to the power ground; the power supply terminal VCC of the boost converter U10, the first end of the resistor R66, and the cathode of the diode D10 are connected to the power supply VCC; the second end of the resistor R66 and the anode of the diode D10 are connected to the capacitor C1 The first end of capacitor C127 is connected to the power ground; the power input terminal VIN of the boost converter U10 is connected to the first end of capacitor C125 and the first end of resistor R65, the second end of resistor R65, the second end of inductor L13, the first end of capacitor C122, the first end of capacitor C123, the first end of capacitor C124, and the first end of capacitor C126 are connected to the power +VBATT; the second end of capacitor C122, the second end of capacitor C123, the second end of capacitor C124, and the second end of capacitor C126 are connected to the power ground; the capacitor C122 is a polar capacitor. The heat dissipation end of the boost converter U10 and the second end of capacitor C125 are connected to the power ground.

[0369] Among them, capacitor C128 is a reserved component, and the model of boost converter U10 is MPQ3364.

[0370] The first end, the second end, the third end, the first end of the capacitor C137, the first end of the capacitor C138, and the first end of the capacitor C139 of the interface J13 are connected to the power supply TFT_BL+; the fifth end of the interface J13 is connected to the first end of the resistor R85 and the first end of the resistor R84, the second end of the resistor R85 is connected to the temperature signal end of the MCU chip, and the second end of the resistor R84 is connected to the power supply +5VCAN; the ground end of the interface J13 is connected to the power ground;

[0371] The eighth end of the interface J13 is connected to the first end of the resistor R81 and the second end of the capacitor C139, and the second end of the resistor R81 is connected to the string 2 current input terminal LED2 of the boost converter U10; the ninth end of the interface J13 is connected to the first end of the resistor R82 and the second end of the capacitor C138, and the second end of the resistor R82 is connected to the string 3 current input terminal LED3 of the boost converter U10; the tenth end of the interface J13 is connected to the first end of the resistor R83 and the second end of the capacitor C137, and the second end of the resistor R83 is connected to the string 4 current input terminal LED4 of the boost converter U10;

[0372] The twelfth and thirteenth terminals of the interface J13 are connected to the first terminal of the resistor R76, the first terminal of the capacitor C135, and the first terminal of the capacitor C136. The second terminal of the capacitor C135 and the second terminal of the capacitor C136 are connected to the power ground. The second terminal of the resistor R76 is connected to the power supply +3.3V_TFT.

[0373] The eighteenth end of the interface J13 is connected to the first end of the resistor R90 and the first end of the resistor R89, the nineteenth end of the interface J13 is connected to the first end of the resistor R92 and the first end of the resistor R91, the second end of the resistor R90 and the second end of the resistor R92 are connected to the power supply +3.3V_TFT; the second end of the resistor R89 ​​and the second end of the resistor R91 are connected to the power ground;

[0374] The twentieth end of the interface J13 is connected to the first end of the resistor R75 and the first end of the resistor R74, the second end of the resistor R75 is connected to the power ground, and the second end of the resistor R74 is connected to the standby mode control end of the MCU chip.

[0375] The 21st terminal of the interface J13 is connected to the collector of the transistor QB1, the first terminal of the resistor R72, and the first terminal of the capacitor CB13, and the second terminal of the resistor R72 is connected to the power supply +3.3V_TFT; the base of the transistor QB1 is connected to the first terminal of the resistor R73, and the second terminal of the resistor R73 is connected to the reset signal terminal of the MCU chip; the emitter of the transistor QB1 and the second terminal of the capacitor CB13 are connected to the power ground;

[0376] The 23rd, 24th, 26th, 27th, 29th, 30th, 32nd, 33rd, 35th and 36th terminals of the interface J13 are connected to the differential signal terminals of the SOC chip;

[0377] The thirty-eighth terminal of the interface J13 is connected to the first end of the resistor R93 and the first end of the resistor R94, the second end of the resistor R93 is connected to the power supply +5VCAN, and the second end of the resistor R94 is connected to the fault indication terminal of the MCU chip.

[0378] The power supply circuit of the TFT screen is connected as follows Fig.17 As shown: the emitter of transistor Q1, the first end of capacitor CB14, and the first end of resistor RB59 are connected to the power supply +3.3VSW; the collector of transistor Q1 outputs the power supply +3.3V_TFT and is connected to the first end of resistor RB21, and the second end of resistor RB21 is connected to the power ground;

[0379] The base of transistor Q1 is connected to the second end of capacitor CB14, the second end of resistor RB59, and the first end of resistor RB24. The second end of resistor RB24 is connected to the collector of transistor QB6. The base of transistor QB6 is connected to the first end of resistor RB23 and the first end of resistor RB22. The second end of resistor RB23 is connected to the TFT screen power enable end of the MCU chip; the second end of resistor RB22 is connected to the power ground, and the emitter of transistor QB6 is connected to the power ground.

[0380] The power supply +3.3V_TFT is the core power supply source of the TFT screen, and its switching state is precisely controlled by the MCU chip. When the MCU chip issues a startup command, it first triggers the conduction of transistor QB6. Subsequently, this conduction state further activates transistor Q1, causing it to also enter the conduction state. At this point, the power supply +3.3V_TFT is successfully output to the TFT screen to power it.

[0381] The circuit connection of USB charging management chip is as follows Fig.18 As shown:

[0382] The power input terminal IN of the USB charging management chip U13, the first end of the capacitor CP518, and the first end of the capacitor CP516 are connected to the power supply +5VSW, and the second end of the capacitor CP518 and the second end of the capacitor CP516 are connected to the power ground; the data output negative terminal DM_OUT of the USB charging management chip U13 is connected to the first end of the resistor RB65, and the second end of the resistor RB65 is connected to the negative signal end of the USB data line of the SOC chip; the data output positive terminal DP_OUT of the USB charging management chip U13 is connected to the first end of the resistor RB66, and the second end of the resistor RB66 is connected to the positive signal end of the USB data line of the SOC chip. The status output terminal STATUS of the USB charging management chip U13 is connected to the first end of the resistor RP10 and the first end of the resistor RP8, and the second end of the resistor RP8 is connected to the USB charging status output terminal of the SOC chip; the fault output terminal FAULT of the USB charging management chip U13 is connected to the first end of the resistor RP4 and the first end of the resistor RP5, and the second end of the resistor RP5 is connected to the USB system fault terminal of the SOC chip; the current detection selection terminal ILIM_SEL of the USB charging management chip U13 is connected to the first end of the resistor RP6, and the second end of the resistor RP6 is connected to the USB port current limiting terminal of the SOC chip ; The enable terminal EN of the USB charging management chip U13 is connected to the first end of the resistor RP3 and the first end of the resistor RP9, and the second end of the resistor RP9 is connected to the USB power enable terminal of the SOC chip; the control input terminal CTL1 of the USB charging management chip U13 is connected to the first end of the resistor RP2, the first end of the resistor RP16, and the first end of the resistor RP11, and the second end of the resistor RP11 is connected to the USB control logic input terminal of the SOC chip; the control input terminal CTL2 of the USB charging management chip U13 is connected to the first end of the resistor RP1, the first end of the resistor RP17, and the first end of the resistor RP12, and the first end of the resistor RP12 is connected to the first end of the resistor RP17. The two ends are connected to the USB control logic input end of the SOC chip; the control input end CTL3 of the USB charging management chip U13 is connected to the first end of the resistor RP7, the first end of the resistor RP18, and the first end of the resistor RP15, and the second end of the resistor RP15 is connected to the USB control logic input end of the SOC chip; the second end of the resistor RP10, the second end of the resistor RP4, the second end of the resistor RP3, the second end of the resistor RP2, the second end of the resistor RP1, and the second end of the resistor RP7 are connected to the power supply +3.3VSW; the second end of the resistor RP16, the second end of the resistor RP17, and the second end of the resistor RP18 are connected to the power supply ground;

[0383] The power switch output terminal OUT of the USB charging management chip U13 outputs the power supply USB1_+5V, and is connected to the first end of the capacitor CP1, the first end of the capacitor CP2, and the positive electrode of the polarized capacitor C169, and the second end of the capacitor CP1, the second end of the capacitor CP2, and the negative electrode of the polarized capacitor C169 are connected to the power ground;

[0384] The data input positive terminal DP_IN of the USB charging management chip U13 is connected to the first output terminal of the common mode inductor LL1; the data input negative terminal DM_IN of the USB charging management chip U13 is connected to the second output terminal of the common mode inductor LL1; the ground terminal GND of the USB charging management chip U13 is connected to the power ground; the low current limit threshold setting terminal ILIM_LO of the USB charging management chip U13 is connected to the first end of the resistor RP14, the high current limit threshold setting terminal ILIM_HI of the USB charging management chip U13 is connected to the first end of the resistor RP13, the second end of the resistor RP13 and the second end of the resistor RP14 are connected to the power ground; the heat dissipation terminal Exposed PAD of the USB charging management chip U13 is connected to the power ground. Among them, the data input positive terminal DP_IN and the data input negative terminal DM_IN can also be used as data output terminals, at this time, the data input positive terminal DP_OUT and the data output negative terminal DM_OUT are data input terminals.

[0385] The USB charging management chip is connected to the USB interface:

[0386] The first input end of the common-mode inductor LL1 is connected to the third end of the USB interface J14 and the first end of the transient diode LTV13; the second input end of the common-mode inductor LL1 is connected to the fourth end of the USB interface J14 and the first end of the transient diode LTVS12; the second end of the transient diode LTV12, the second end of the transient diode LTV13, and the first end of the capacitor C143 are connected to the power ground, the second end of the capacitor C143 and the first end of the USB interface J14 are connected to the power supply USB1_+5V; the second end of the USB interface J14 is connected to the power ground.

[0387] The data source of USB interface J14 is an external USB flash drive or an internal SOC chip, which is transmitted to the external USB flash drive or the internal device through the charging management chip U13.

[0388] The transient diode is preferably a transient diode that can provide protection under both forward and reverse voltages. The USB interface needs to transmit data and supply power, so it may face voltage shocks from different directions. When the USB charging management chip is connected to the USB interface, the bidirectional TVS tube and common mode inductor in the USB interface play an important role in protecting the circuit from electrostatic interference and electromagnetic interference. The addition of these components improves the anti-interference ability and stability of the circuit, ensuring the smooth progress of the USB charging process.

[0389] The model of USB charging management chip U13 is PI5USB2546.

[0390] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A three-in-one multifunctional instrument, characterized in that: Including MCU chip, SOC chip, CAN chip, AMP chip, DSP chip, CVBS chip, TFT screen, FLASH, Bluetooth WIFI chip, USB charging management chip, MIC and power module; The power module is respectively connected to the SOC chip (U6), DSP chip (UR1), Bluetooth WIFI chip (UB1), CVBS chip (UI1), USB charging management chip (U13), MCU (U12), and CAN chip (U1) to provide power for them; The SOC chip is connected to the MCU chip, TFT screen, FLASH, Bluetooth WIFI chip, MIC (microphone), DSP chip, USB charging management chip, and CVBS chip respectively; The MCU chip is also connected to the CAN chip, DET module, AMP chip, and TFT screen respectively; the CAN chip is used to receive internal signals of the car, and the DET module is used to receive external signals of the car; The DSP chip is connected to the AMP chip.

2. A three-in-one multifunctional instrument according to claim 1, characterized in that: The power module includes a primary power module and a secondary power module; the primary power module includes a power chip U2 and a power chip U11, and the primary power module converts the power supply +VBATT into the power supply +5VSW and the power supply +5VCAN; when the power supply +5VSW output by the power chip U2 meets the static low power consumption in the sleep state, there is no need to use the power chip U11, and the power supply +5VSW is connected through the resistor R3 to output the power supply +5VCAN; if it does not meet the requirements, the power chip U11 is used, and there is no resistor R3 at this time; the power chip U11 converts the power supply +VBATT into the power supply +5VCAN.

3. A three-in-one multifunctional instrument according to claim 2, characterized in that: The first-level power module includes power chip U2 and power chip U11: The power chip U2 includes: The self-boosting terminal BOOT of the power chip U2 is connected to the first end of the resistor R21, the second end of the resistor R21 is connected to the first end of the capacitor C17, the second end of the capacitor C17 is connected to the cathode of the diode D9, the first end of the resistor R22, the switch control terminal SW of U2, and the first end of the inductor L1; the cathode of the diode D9 is connected to the power ground; the second end of the resistor R22 is connected to the first end of the capacitor C19, and the second end of the capacitor C19 is connected to the power ground; The second end of the inductor L1 is connected to the first end of the capacitor C20, the first end of the capacitor C21, the first end of the capacitor C22, the first end of the capacitor C23, and the first end of the resistor R23, and the second end of the inductor L1 outputs the power supply +5VSW; the second end of the capacitor C20, the second end of the capacitor C21, the second end of the capacitor C22, and the second end of the capacitor C23 are connected to the power ground; The output voltage feedback terminal FB of the power chip U2, the second end of the resistor R23, and the first end of the resistor R24 ​​are connected, and the second end of the resistor R24 ​​is connected to the power ground; The ground terminal GND of the power chip U2 is connected to the power ground; The soft start terminal SS of the power chip U2 is connected to the first terminal of the capacitor C18, and the second terminal of the capacitor C18 is connected to the power ground; The power input terminal VIN of the power chip U2 is connected to the first end of the capacitor C14, the first end of the capacitor C15, the first end of the capacitor C16, and the first end of the resistor R18; the second end of the capacitor C14, the second end of the capacitor C15, and the second end of the capacitor C16 are connected to the power ground; the second end of the resistor R18 is connected to the power supply +VBATT; The enable terminal EN of the power chip U2 is connected to the first end of the resistor R19, the first end of the capacitor C13, and the first end of the resistor R16; the second end of the resistor R16 is connected to the enable terminal of the MCU chip, the second end of the capacitor C13 is connected to the power ground, and the second end of the resistor R19 is connected to the power ground; The frequency control terminal RT / CLK of the power chip U2 is connected to the first end of the resistor R20, and the second end of the resistor R20 is connected to the power ground; The power chip U11 includes: The power input terminal VIN of the power chip U11 is connected to the cathode of the diode D5, the anode of the polarized capacitor C7, and the first end of the capacitor C8. The cathode of the polarized capacitor C7 and the second end of the capacitor C8 are respectively connected to the power ground; the anode of the diode D5 is connected to the power supply +VBATT; The power output terminal OUT of the power chip U11 is connected to the first end of the capacitor C9, the first end of the capacitor C166, and the first end of the resistor R3. The power output terminal OUT of the power chip U11 outputs the power supply +5VCAN; the second end of the resistor R3 outputs the power supply +5VSW; the second end of the capacitor C9 and the second end of the capacitor C166 are connected to the power ground; The ground terminal GND of the power chip U11 is connected to the power ground.

4. A three-in-one multifunctional instrument according to claim 1, characterized in that: The secondary power module includes one or any combination of power chip U3, power chip U4, and power chip U5; The power chip U3 includes: The power input terminal VIN of the power chip U3, the first end of the resistor R25, the first end of the resistor R101, the first end of the capacitor C24, and the first end of the capacitor C26 are connected to the power supply +5VSW; the second end of the capacitor C24 and the second end of the capacitor C26 are connected to the power ground; the second end of the resistor R25 is connected to the power indication terminal PG of the power chip U3; the second end of the resistor R101 is connected to the first end of the capacitor C37 and the enable terminal EN of the power chip U3; the second end of the capacitor C37 is connected to the power ground; The ground terminal GND of the power chip U3 is connected to the power ground; The switching output terminal SW of the power chip U3 is connected to the first end of the inductor L2, and the second end of the inductor L2 is connected to the power output terminal VOUT of the power chip U3, the first end of the resistor RO3, the first end of the capacitor C30, the first end of the capacitor C34, and the first end of the capacitor C35; the power output terminal VOUT of the power chip U3 outputs the power supply +3.3VSW (3.3V); the second end of the capacitor C34 and the second end of the capacitor C35 are connected to the power ground; The feedback terminal FB of the power chip U3 is connected to the second end of the resistor RO3, the second end of the capacitor C30, and the first end of the resistor RO1; the second end of the resistor RO1 is connected to the power ground; The soft start terminal SS of the power chip U3 is connected to the first terminal of the capacitor C28, and the second terminal of the capacitor C28 is connected to the power ground; The power chip U5 includes: The power input terminal VIN of the power chip U5, the first end of the resistor R27, the enable terminal EN of the power chip U5, the first end of the capacitor C36, and the first end of the capacitor C1 are connected to the power supply +5VSW; the second end of the capacitor C36 and the second end of the capacitor C1 are connected to the power ground; the second end of the resistor R27 is connected to the power indication terminal PG of the power chip U5; The ground terminal GND of the power chip U5 is connected to the power ground; The switching output terminal SW of the power chip U5 is connected to the first end of the inductor L4, and the second end of the inductor L4 is connected to the power output terminal VOUT of the power chip U5, the first end of the resistor RO6, the first end of the capacitor C39, the first end of the capacitor C32, and the first end of the capacitor C41; the power output terminal VOUT of the power chip U5 outputs a power supply of +1.8V; the second end of the capacitor C32 and the second end of the capacitor C41 are connected to the power ground; The feedback terminal FB of the power chip U5 is connected to the second end of the resistor RO6, the second end of the capacitor C39, and the first end of the resistor RO5; the second end of the resistor RO5 is connected to the power ground; The soft start terminal SS of the power chip U5 is connected to the first terminal of the capacitor C38, and the second terminal of the capacitor C38 is connected to the power ground; The power chip U4 includes: The power input terminal VIN of the power chip U4, the first end of the resistor R26, the enable terminal EN of the power chip U4, the first end of the capacitor C25, and the first end of the capacitor C27 are connected to the power supply +5VSW; the second end of the capacitor C25 and the second end of the capacitor C27 are connected to the power ground; the second end of the resistor R26 is connected to the power indication terminal PG of the power chip U4; The ground terminal GND of the power chip U4 is connected to the power ground; The switching output terminal SW of the power chip U4 is connected to the first end of the inductor L3, and the second end of the inductor L3 is connected to the power output terminal VOUT of the power chip U4, the first end of the resistor RO4, the first end of the capacitor C31, the first end of the capacitor C33, and the first end of the capacitor C40; the power output terminal VOUT of the power chip U4 outputs a power supply of +1.2V; the second end of the capacitor C33 and the second end of the capacitor C40 are connected to the power ground; The feedback terminal FB of the power chip U4 is connected to the second end of the resistor RO4, the second end of the capacitor C31, and the first end of the resistor RO2; the second end of the resistor RO2 is connected to the power ground; The soft start terminal SS of the power chip U4 is connected to the first terminal of the capacitor C29, and the second terminal of the capacitor C29 is connected to the power ground.

5. The three-in-one multifunctional instrument according to claim 1, characterized in that: The circuit connections of the CAN chip include: The data transmitting terminal TXD of the CAN chip U1 is connected to the data receiving terminal of the MCU chip; The ground terminal GND of the CAN chip U1 is connected to the power ground; The power supply terminal VCC of the CAN chip U1, the first end of the resistor R280, the first end of the capacitor C144, and the first end of the capacitor C142 are connected to the power supply +5VCAN; The data receiving terminal RXD of the CAN chip U1 is connected to the second end of the resistor R280 and the data sending terminal of the MCU chip; The standby mode control input terminal STB of the CAN chip U1 is connected to the control signal terminal of the MCU chip; The high-level signal terminal CANH of the CAN chip U1 is connected to the first end of the resistor R102, the first end of the resistor R104, and the first end of the inductor L5; the second end of the resistor R102 is connected to the first end of the resistor R297, the first end of the resistor R103, and the first end of the capacitor C79; the second end of the capacitor C79 is connected to the power ground; The second end of the resistor R297 is connected to the first end of the resistor R296, the first end of the capacitor C145, and the power-frequency conversion voltage terminal VIO of the CAN chip U1; the second end of the resistor R296 is connected to the power supply +5VCAN; the second end of the capacitor C145 is connected to the power ground; The second end of the resistor R103 is connected to the low-level signal terminal CANL of the CAN chip U1, the first end of the resistor R149, and the fourth end of the inductor L5; the second end of the resistor R149 and the third end of the inductor L5 output a low-level signal; the second end of the resistor R104 is connected to the second end of the inductor L5, and the second end of the inductor L5 outputs a high-level signal.

6. A three-in-one multifunctional instrument according to claim 1, characterized in that: The circuit connections of the SOC chip include: The crystal oscillator output end of the SOC chip U6 is connected to the first end of the resistor RM502, the third end of the crystal oscillator Y1, and the first end of the capacitor C45; the second end of the resistor RM502 is connected to the crystal oscillator input end of the SOC chip U6, the first end of the crystal oscillator Y1, and the first end of the capacitor C44; the second end of the capacitor C44, the second end of the capacitor C45, and the fourth end of the crystal oscillator Y1 are connected to the power ground; the second end of the crystal oscillator Y1 is connected to the power ground; The reset end of the SOC chip U6 is connected to the first end of the capacitor C43, the collector of the transistor Q7, and the first end of the resistor RB5, and the second end of the capacitor C43 and the emitter of the transistor Q7 are connected to the power ground; the second end of the resistor RB5 is connected to the power supply VDD33_IO, the base of the transistor Q7 is connected to the first end of the resistor R131, and the second end of the resistor R131 is connected to the reset control end of the MCU chip; The SOC chip U6 is also connected to the FLAH: the data transmission end of the FLAH chip U7 is connected to the data transmission end of the SOC chip U6 via a resistor; the power input end of the FLAH chip U7, the first end of the resistor R132, and the first end of the capacitor C48 are connected to the power supply VDD33_IO; the second end of the capacitor C48 is connected to the power ground; The SOC chip U6 is also connected to the MIC, as shown in FIG9 : the MIC first input terminal of the SOC chip U6 is connected to the first end of the MIC interface J12, and the MIC second input terminal of the SOC chip U6 is connected to the first end of the capacitor C77, the first end of the transient diode LTVS10, the first end of the resistor R35, and the third end of the MIC interface J12; the second end of the resistor R35, the first end of the capacitor C63, the first end of the capacitor C64, and the first end of the resistor R36 are connected to the power supply +3.3VSW; the second end of the capacitor C63 and the second end of the capacitor C64 are connected to the power supply ground; the second end of the resistor R36 is connected to the fifth end of the MIC interface J12, the first end of the transient diode LTVS11, the first end of the capacitor C78, ​​and the microphone protocol end of the SOC chip U6; The fourth end of the MIC interface J12 is connected to the first end of the inductor LS325. The sixth terminal of the MIC interface J12 is connected to the first terminal of the inductor LS1. The second end of the MIC interface J12, the second end of the capacitor C77, the second end of the transient diode LTVS10, the second end of the inductor LS325, the second end of the inductor LS1, the second end of the transient diode LTVS11, and the second end of the capacitor C78 are connected to the power ground.

7. A three-in-one multifunctional instrument according to claim 1, characterized in that: The internal power supply circuit of the SOC chip includes the internal power supply circuit of the first part of the SOC, the internal power supply circuit of the second part of the SOC, and the internal power supply circuit of the third part of the SOC: The internal power supply circuit of the first part of the SOC includes: a first end of the inductor L6 is connected to the power supply +1.2V; the second end of the inductor L6 outputs the power supply VDD1V2_CORE, and is connected to the first end of the capacitor C50, the first end of the capacitor C51, the first end of the capacitor C52, the first end of the capacitor C53, the first end of the capacitor C54, the first end of the capacitor C55, the first end of the capacitor C56, the first end of the capacitor C57, the first end of the capacitor C58, the first end of the capacitor C59, the first end of the capacitor C60, the first end of the capacitor C61, and the first end of the capacitor C62; the second end of the capacitor C50, the second end of the capacitor C51, the second end of the capacitor C52, the second end of the capacitor C53, the second end of the capacitor C54, the second end of the capacitor C55, the second end of the capacitor C56, the second end of the capacitor C57, the second end of the capacitor C58, the second end of the capacitor C59, the second end of the capacitor C60, the second end of the capacitor C61, and the second end of the capacitor C62 are connected to the power ground; The internal power supply circuit of the second part of the SOC includes: the first end of the inductor L8 is connected to the power supply +1.8V; the second end of the inductor L8 outputs the power supply +1.8V_MCU, and is connected to the first end of the capacitor C80, the first end of the capacitor C81, the first end of the capacitor C82, the first end of the capacitor C83, and the first end of the capacitor C84; the second end of the capacitor C80, the second end of the capacitor C81, the second end of the capacitor C82, the second end of the capacitor C83, and the second end of the capacitor C84 are connected to the power ground; The internal power supply circuit of the third part of the SOC includes: a first end of the inductor L7 is connected to the power supply +3.3VSW; the second end of the inductor L7 outputs the power supply VDD33_IO, and is connected to the first end of the capacitor C65, the first end of the capacitor C66, the first end of the capacitor C67, the first end of the capacitor C68, and the first end of the capacitor C69, and the second end of the capacitor C65, the second end of the capacitor C66, the second end of the capacitor C67, the second end of the capacitor C68, and the second end of the capacitor C69 are connected to the power ground; the second end of the inductor L7 is connected to the first end of the capacitor C70, the first end of the capacitor C71, the first end of the capacitor C72, the first end of the capacitor C73, the first end of the capacitor C74, and the first end of the capacitor C75, and the second end of the capacitor C70, the second end of the capacitor C71, the second end of the capacitor C72, the second end of the capacitor C73, the second end of the capacitor C74, and the second end of the capacitor C75 are connected to the power ground.

8. The three-in-one multifunctional instrument according to claim 1, characterized in that: The third part of the SOC internal power supply circuit includes three sub-power supply circuits: The first sub-power supply circuit includes: a power supply VDD33_IO is connected to a first end of a resistor R39, a second end of the resistor R39 outputs a power supply VDD3.3V_SAR and is connected to a first end of a capacitor C85 and a first end of a capacitor C86, and a second end of the capacitor C85 and a second end of the capacitor C86 are connected to a power ground; The second sub-power supply circuit includes: a power supply VDD33_IO is connected to a first end of a resistor R40, a second end of the resistor R40 outputs a power supply VDD3V3A and is connected to a first end of a capacitor C87, a first end of a capacitor C88, and a first end of a capacitor C89, and a second end of the capacitor C87, a second end of the capacitor C88, and a second end of the capacitor C89 are connected to a power ground; The third sub-power supply circuit includes: a power supply VDD33_IO is connected to a first end of a resistor R41, a second end of the resistor R41 outputs a power supply VCC_RTC and is connected to a first end of a capacitor CO5 and a first end of a capacitor C90, and a second end of the capacitor CO5 and a second end of the capacitor C90 are connected to a power ground; The power supply +3.3VSW is converted into the power supply VDD33_IO; the third part of the internal power supply circuit also includes: converting the power supply VDD33_IO into the power supply VDD3.3V_SAR, the power supply VDD3V3A, and the power supply VCC_RTC respectively.

9. The three-in-one multifunctional instrument according to claim 1, characterized in that: The circuit of DSP chip includes: The crystal oscillator input terminal XTALI of the DSP chip UR1 is connected to the first terminal of the capacitor CR7 and the third terminal of the crystal oscillator XR1. The crystal oscillator output terminal XTALO of the DSP chip UR1 is connected to the first end of the resistor RR19, the second end of the resistor RR19 is connected to the first end of the capacitor CR6 and the first end of the crystal oscillator XR1, the second end of the capacitor CR6 and the second end of the capacitor CR7 are connected to the power ground; the second end and the fourth end of the crystal oscillator XR1 are both connected to the power ground; The frequency modulation input terminal FMI of the DSP chip UR1 is connected to the first end of the capacitor CR5, the first end of the inductor LR1, and the first end of the inductor LR2, and the second end of the inductor LR2 and the second end of the capacitor CR5 are respectively connected to the power ground; the second end of the inductor LR1 is connected to the first end of the capacitor CR4, and the second end of the capacitor CR4 is connected to the first end of the capacitor CR2 and the first end of the capacitor CR3; the second end of the capacitor CR3 is connected to the first end of the inductor LR6 and the first end of the capacitor CR38; the second end of the inductor LR6 and the second end of the capacitor CR38 are connected to the first end of the capacitor CR39, the first end of the transient diode LTVS18, and the input end of the band-pass filter circuit, and the output end of the band-pass filter circuit is connected to the first end of the capacitor CR41; the band-pass filter circuit includes: a resistor RR31, an inductor LR8, and a capacitor CR40 connected in parallel; The second end of the capacitor CR39 is connected to the first end of the inductor LR7, and the second end of the inductor LR7 is connected to the power ground; the second end of the transient diode LTVS18 is connected to the power ground; The second end of the capacitor CR41 is connected to the amplitude modulation input terminal AMI of the DSP chip UR1; The second end of the capacitor CR2, the first end of the transient diode LTVS17, the antenna socket and the power supply TUNER_RF are connected; the second end of the transient diode LTVS17 is connected to the power ground; The channel selection terminal ABYP of the DSP chip UR1 is connected to the first end of the capacitor CR42, the first end of the capacitor CR43, the first end of the capacitor CR44, the first end of the capacitor CR45, the first end of the capacitor CR46 and the first end of the inductor LR9, and the second end of the inductor LR9 is connected to the power supply +3.3VSW; The analog input positive terminal AIN0P of the DSP chip UR1 is connected to the first end of the capacitor CR47, and the second end of the capacitor CR47 is connected to the first end of the resistor RR35. The analog input negative terminal AIN0N of the DSP chip UR1 is connected to the first end of the capacitor CR48, and the second end of the capacitor CR48 is connected to the first end of the capacitor CR50, the first end of the capacitor CR52, the first end of the capacitor CR54, the first end of the capacitor CR55, the first end of the capacitor CR56, the first end of the capacitor CR57, the first end of the capacitor CR58, and the first end of the capacitor CR60 and the power ground; The analog input positive terminal AIN1P of the DSP chip UR1 is connected to the first end of the capacitor CR49, and the second end of the capacitor CR49 is connected to the first end of the resistor RR36; The analog input negative terminal AIN1N of the DSP chip UR1 is connected to the second end of the capacitor CR50. The analog input positive terminal AIN2P of the DSP chip UR1 is connected to the first end of the capacitor CR51, the second end of the capacitor CR51 is connected to the first end of the resistor RR32, the second end of the resistor RR32 is connected to the first end of the capacitor C140, and the second end of the capacitor C140 is connected to the signal transmission end of the AMP chip and the signal transmission end of the SOC chip respectively; The analog input negative terminal AIN2N of the DSP chip UR1 is connected to the second terminal of the capacitor CR52; The analog input positive terminal AIN3P of the DSP chip UR1 is connected to the first end of the capacitor CR53, the second end of the capacitor CR53 is connected to the first end of the resistor RR33, the second end of the resistor RR33 is connected to the first end of the capacitor C141, and the second end of the capacitor C141 is connected to the signal transmission end of the AMP chip and the signal transmission end of the SOC chip respectively; The analog input negative terminal AIN3N of the DSP chip UR1 is connected to the second terminal of the capacitor CR54; The analog input positive terminal AIN4P of the DSP chip UR1 is connected to the second terminal of the capacitor CR55; The analog input negative terminal AIN4N of the DSP chip UR1 is connected to the second terminal of the capacitor CR56; The analog input positive terminal AIN5P of the DSP chip UR1 is connected to the second terminal of the capacitor CR57; The analog input negative terminal AIN5N of the DSP chip UR1 is connected to the second end of the capacitor CR58 and the first end of the resistor RR39; The analog input positive terminal AIN6P of the DSP chip UR1 is connected to the second end of the resistor RR39 and the first end of the capacitor CR59, and the second end of the capacitor CR59 is connected to the first end of the resistor RR34; The analog input negative terminal AIN6N of the DSP chip UR1 is connected to the second terminal of the capacitor CR60; The second end of the resistor RR35, the second end of the resistor RR36, the second end of the resistor RR37, the second end of the resistor RR38, and the second end of the resistor RR34 are connected to the power ground; The reset signal terminal RSTB of the DSP chip UR1 is connected to the first end of the resistor RR42 and the reset control terminal of the SOC chip; The mode selection terminal SMODE of the DSP chip UR1 is connected to the first end of the resistor RR40 and the first end of the resistor RR43; the second end of the resistor RR40 is connected to the power ground; The interrupt request terminal INTB of the DSP chip UR1 is connected to the first end of the resistor RR41 and the interrupt request data terminal of the SOC chip; The second end of the resistor RR41, the second end of the resistor RR42, and the second end of the resistor RR43 are connected to the power supply DSP_VIO1_3V3 / 1V8; The data output terminal MISO / A0 of the DSP chip UR1 is connected to the first end of the resistor RB33, and the second end of the resistor RB33 is connected to the first end of the resistor RB29 and the data receiving end of the SOC chip; The data receiving terminal MOSI / SDA of the DSP chip UR1 is connected to the first end of the resistor RB32, and the second end of the resistor RB32 is connected to the first end of the resistor RB28 and the data output terminal of the SOC chip; The clock terminal SCLK / SCL of the DSP chip UR1 is connected to the first end of the resistor RB31, and the second end of the resistor RB31 is connected to the first end of the resistor RB27 and the clock control terminal of the SOC chip. The chip select signal receiving terminal SSB / A1 of the DSP chip UR1 is connected to the first end of the resistor R0.1B30, and the second end of the resistor RB30 is connected to the first end of the resistor RB26 and the chip select control terminal of the SOC chip. The second end of the resistor RB26, the second end of the resistor RB27, the second end of the resistor RB28, and the second end of the resistor RB29 are connected to the power supply +3.3VSW; The digital bypass terminal DBYP of the DSP chip UR1 is connected to the first end of capacitor CR18, the first end of capacitor CR20, the first end of capacitor CR22, the first end of capacitor CR24, the first end of capacitor CR26, the first end of capacitor CR28, the first end of capacitor CR19, the first end of capacitor CR21, the first end of capacitor CR23, the first end of capacitor CR25, the first end of capacitor CR27, and the first end of capacitor CR29; the first end of capacitor CR30, the first end of capacitor CR31, the first end of capacitor CR32, the first end of capacitor CR33, the first end of capacitor CR34, the first end of capacitor CR35, the first end of capacitor CR36, and the first end of capacitor CR37; The second end of capacitor CR19, the second end of capacitor CR21, the second end of capacitor CR23, the second end of capacitor CR25, the second end of capacitor CR27, the second end of capacitor CR29, and the first end of inductor LR3 are connected to the power supply DSP_DVDD1V8_250MA; the second end of inductor LR3 is connected to the first end of capacitor CR29 and the power supply +1.8V; the second end of capacitor CR29 is connected to the power supply ground; The second end of capacitor CR30, the second end of capacitor CR31, the second end of capacitor CR32, the second end of capacitor CR33, the second end of capacitor CR34, the second end of capacitor CR35, the second end of capacitor CR36, the second end of capacitor CR37, and the first end of inductor LR5 are connected to power supply DSP_VIO1_3V3 / 1V8; the second end of inductor LR5 is connected to power supply +3.3VSW; The second power input terminal VIO2 of the DSP chip UR1 is connected to the second end of the capacitor CR18, the second end of the capacitor CR20, the second end of the capacitor CR22, the second end of the capacitor CR24, the second end of the capacitor CR26, the second end of the capacitor CR28, the first end of the inductor LR4 and DSP_VIO2_3V3 / 1V8, and the second end of the inductor LR4 is connected to the power supply +3.3VSW; The data input terminal NC of the DSP chip UR1 is connected to the first end of the resistor RR29, the second end of the resistor RR29 is connected to the first end of the resistor RR50 and the data output terminal of the Bluetooth WIFI chip, and the second end of the resistor RR50 is connected to the digital audio output terminal of the SOC chip. The digital input frame synchronization terminal DIFS2 of the DSP chip UR1 is connected to the first end of the resistor RR28, the second end of the resistor RR28 is connected to the first end of the resistor RR51 and the frame synchronization clock signal output terminal of the Bluetooth WIFI chip, and the second end of the resistor RR51 is connected to the clock signal output terminal of the SOC chip. The digital input clock terminal DICLK2 of the DSP chip UR1 is connected to the first end of the resistor RR27, the second end of the resistor RR27 is connected to the first end of the resistor RR52 and the data clock signal output end of the Bluetooth WIFI chip, and the second end of the resistor RR52 is connected to the clock signal control end of the SOC chip; The first analog audio output terminal of the DSP chip UR1 is connected to the first end of the resistor RR23, the second end of the resistor RR23 is connected to the first end of the capacitor CR17 and the first end of the capacitor CR8, and the second end of the capacitor CR17 is connected to the audio left channel input terminal of the AMP chip; The first analog audio output terminal of the DSP chip UR1 is connected to the first end of the resistor RR22, the second end of the resistor RR22 is connected to the first end of the capacitor CR16 and the first end of the capacitor CR9, and the second end of the capacitor CR16 is connected to the audio right channel input terminal of the AMP chip; The third analog audio output terminal of the DSP chip UR1 is connected to the first end of the resistor RR21, and the second end of the resistor RR21 is connected to the first end of the capacitor CR10; The fourth analog audio output terminal of the DSP chip UR1 is connected to the first end of the resistor RR20, and the second end of the resistor RR20 is connected to the first end of the capacitor CR11; A second end of the capacitor CR8 , a second end of the capacitor CR9 , a second end of the capacitor CR10 , and a second end of the capacitor CR11 are connected to a power ground.

10. A working method of a three-in-one multifunctional instrument, characterized in that: A working method including one of the imaging function, Bluetooth WIFI function, USB charging function, and radio function or any combination thereof; The working method of the imaging function is as follows: when the CAN chip receives a signal from inside the vehicle, it transmits the signal to the MCU chip; or when the DET module receives a signal from outside the vehicle, it transmits the signal to the MCU chip; the MCU chip transmits the signal to the SOC chip; the SOC chip controls the CVBS chip, the CVBS chip decodes the current video signal of the vehicle to obtain video data, and transmits the data to the SOC chip; the SOC chip performs image processing on the video data, and then outputs the data to the TFT screen; How the Bluetooth WIFI function works: (1) How the Bluetooth function works: Implementation path 1: When the Bluetooth WIFI chip receives the data signal from the mobile terminal, it transmits the data signal to the SOC chip for decoding; then the decoded data is transmitted to the DSP chip for signal processing; the DSP chip transmits the digital signal processed data to the AMP chip; Implementation path two: receiving voice data through MIC, transmitting the voice data to the SOC chip for decoding operation; then transmitting the processed voice data to the Bluetooth WIFI chip, and then transmitting the voice data to the mobile terminal through the Bluetooth WIFI chip; (2) How the WIFI function works: When the Bluetooth WIFI chip receives the data signal from the mobile terminal, the Bluetooth WIFI chip transmits the data signal to the SOC chip; after the SOC chip performs decoding operation, the decoded data is output to the TFT screen for display; How the USB charging function works: The current is transmitted to the USB charging management chip through the USB socket and the USB cable. The chip first detects and identifies the input voltage and current specifications to ensure that they meet the charging requirements of the device. The USB charging management chip communicates with the SOC chip, which calculates the optimal charging current and voltage and feeds this information back to the USB charging management chip, which accurately regulates the charging process to ensure stable output of current and voltage, while monitoring the battery charging status; The working method of the radio function: when an external radio frequency signal RF is received, it is processed by the DSP chip, and the processed signal is transmitted to the SOC chip, and FM frequency tuning and station selection are performed through the SOC chip; then the DSP chip outputs the signal to the AMP chip.

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