Display substrate and display device
By designing the three subpixels of each pixel to share a data line on the display substrate and adjusting the length ratio of the subpixels, the problem of missing text edges of the TRD LCD display is solved, and higher text readability and clarity are achieved. At the same time, it reduces costs.
Patent Information
- Application Number
- CN202311055841.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-21
- Publication Date
- 2025-02-21
AI Technical Summary
When existing TRD LCD displays display text, there will be many missing edges of text, resulting in low readability.
A display substrate is designed in which three subpixels of each pixel share a data line and the length in the row direction of each subpixel is smaller than the length in the column direction. Under this structure, the pixel arrangement reduces the loss of text edges and improves the readability of text.
By reducing the number of source drive circuits, the cost of the display device is reduced, while improving the readability and clarity of the text.
Smart Images
Figure CN119493309A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display substrate and a display device. Background Art
[0002] Liquid crystal display technology With the development of driving methods and manufacturing processes, liquid crystal displays have greatly improved production costs and picture quality. In order to reduce production costs, a triple rate driving (TRD) technology has been proposed. In TRD technology, the number of source drive circuits is reduced to 1 / 3.
[0003] Please refer to Figure 1 In the pixel structure of the existing TRD liquid crystal display, the three sub-pixels (R sub-pixel, G sub-pixel, B sub-pixel) of each pixel are arranged in the column direction, and the width of the sub-pixel in the row direction is greater than the width in the column direction. When the TRD liquid crystal display with this structure displays text, there will be a lot of missing edges of the text, resulting in low readability. Summary of the invention
[0004] Embodiments of the present invention provide a display substrate and a display device, which are used to solve the problem of low readability of text displayed by an existing TRD liquid crystal display.
[0005] In order to solve the above-mentioned technical problems, the present invention is achieved as follows:
[0006] In a first aspect, an embodiment of the present invention provides a display substrate, comprising:
[0007] substrate substrate;
[0008] A plurality of gate lines extending in a row direction and a plurality of data lines extending in a column direction are arranged on the substrate;
[0009] A plurality of pixels, each of the pixels comprises three sub-pixels, a length of each of the sub-pixels in a row direction is smaller than a length in a column direction, and the three sub-pixels of each of the pixels share one data line.
[0010] Optionally, the three sub-pixels of each pixel are arranged in a row direction, and the sub-pixels of the same color are arranged in a column direction.
[0011] Optionally, the sub-pixels include a first sub-pixel, a second sub-pixel and a third sub-pixel, and a data line corresponding to each of the pixels is located between two of the sub-pixels of the pixel.
[0012] Optionally, the gate lines include a first gate line, a second gate line and a third gate line, the first gate line and the third gate line are respectively located on both sides of the sub-pixel and are respectively connected to the thin film transistor of the first sub-pixel and the thin film transistor of the second sub-pixel, and the second gate line is located between the first gate line and the third gate line and is connected to the thin film transistor of the third sub-pixel.
[0013] Optionally, a distance between the second gate line and the first gate line is equal to a distance between the second gate line and the third gate line.
[0014] Optionally, the thin film transistor of the first sub-pixel is located in an edge region of the first sub-pixel;
[0015] The thin film transistor of the second sub-pixel is located in an edge region of the second sub-pixel, and one of the thin film transistor of the second sub-pixel and the thin film transistor of the first sub-pixel is disposed close to the first gate line, and the other is disposed close to the third gate line;
[0016] The thin film transistor of the third sub-pixel is located in the middle area of the third sub-pixel, and the area of the third sub-pixel located above the thin film transistor of the third sub-pixel has the same aperture ratio as the area of the third sub-pixel located below the thin film transistor of the third sub-pixel.
[0017] Optionally, the thin film transistors in all the pixels are arranged in the same manner.
[0018] Optionally, the thin film transistors in the pixels in the same row are arranged in the same manner.
[0019] Optionally, the thin film transistors of two adjacent first sub-pixels in a column direction are arranged in a mirror image;
[0020] The thin film transistors of two adjacent second sub-pixels in the column direction are arranged in mirror image.
[0021] Optionally, the thin film transistors of two adjacent second sub-pixels in the column direction are arranged close to each other and share a same via hole to be connected to the data line.
[0022] Optionally, the gate lines include a first gate line, a second gate line and a third gate line, and the first gate line, the second gate line and the third gate line are all arranged close to one side of the pixel and are respectively connected to the thin film transistor of the first sub-pixel, the thin film transistor of the second sub-pixel and the thin film transistor of the third sub-pixel.
[0023] Optionally, at least two sub-pixels in the same pixel share the same via hole connected to the data line.
[0024] Optionally, the thin film transistors in all the pixels are arranged in the same manner.
[0025] In a second aspect, an embodiment of the present invention provides a display device, including:
[0026] The display substrate as described in the first aspect above;
[0027] The source driving circuit is connected to the data lines of the display substrate and provides data voltages to the data lines corresponding to three sub-pixels of the same pixel of the display substrate in a time-sharing manner.
[0028] In the embodiment of the present invention, the three sub-pixels of each pixel share one data line, which can reduce the number of source driving circuits, realize a display device with a three-speed driving structure, and reduce the cost of the display device. In addition, the length of each sub-pixel in the row direction is smaller than the length in the column direction. The pixel structure under this structure has less edge loss when displaying text, thereby improving the readability of the text and the clarity of the text displayed by the display device. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:
[0030] Figure 1 A schematic diagram of a TRD display device displaying text in the prior art;
[0031] Figure 2 is a schematic structural diagram of a display substrate according to a first embodiment of the present invention;
[0032] Figure 3 is a schematic structural diagram of a display substrate according to a second embodiment of the present invention;
[0033] Figure 4 is a schematic structural diagram of a display substrate according to a third embodiment of the present invention;
[0034] Figure 5 FIG. 1 is a schematic diagram of a TRD display device displaying text according to an embodiment of the present invention. DETAILED DESCRIPTION
[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0036] Please refer to Figure 2 , Figure 3 and Figure 4 , an embodiment of the present invention provides a display substrate, comprising:
[0037] Base substrate (not shown); optionally, the base substrate may be a hard substrate such as a glass substrate, or may be a flexible substrate.
[0038] A plurality of gate lines (Gate1, Gate2 ... Gaten, n is the total number of gate lines) extending along the row direction and a plurality of data lines (Data1, Data2 ... Datam, m is the total number of data lines) extending along the column direction are arranged on the substrate;
[0039] A plurality of pixels P, each of the pixels P comprises three sub-pixels (R (red) sub-pixel, G (green) sub-pixel and B (blue) sub-pixel), a length of each sub-pixel in the row direction is smaller than a length in the column direction, and the three sub-pixels of each pixel P share one data line.
[0040] In the embodiment of the present invention, three sub-pixels of each pixel share one data line, which can reduce the number of source driving circuits, realize a display device with a three-speed driving structure, and reduce the cost of the display device. In addition, the length of each sub-pixel in the row direction is smaller than the length in the column direction. The pixel structure under this structure has less edge loss when displaying text. Please refer to Figure 5 , which improves the readability of the text and the clarity of the text displayed on the display device.
[0041] In the embodiment of the present invention, optionally, the long side of the sub-pixel is parallel to the data line, and the short side is parallel to the gate line.
[0042] In the embodiment of the present invention, the pixel P includes three sub-pixels, namely, an R sub-pixel, a G sub-pixel and a B sub-pixel. Of course, in some other embodiments of the present invention, the colors of the sub-pixels in the pixel P may not be limited to red, green and blue.
[0043] In the embodiment of the present invention, optionally, the three sub-pixels of each pixel P are arranged in the row direction, and the sub-pixels of the same color are arranged in the column direction. In the above embodiment, the sub-pixels in the pixel P are arranged in the row direction according to the RGB method. In some other embodiments of the present invention, they can also be arranged in the row direction according to the RBG, or GBR method, etc., which is not limited by the present invention.
[0044] In the embodiment of the present invention, optionally, the length of each sub-pixel in the column direction is equal to three times the length in the row direction, that is, the ratio of the length in the column direction to the length in the row direction is 3:1, so that the entire pixel P is roughly a square. Of course, the ratio of the length in the column direction to the length in the row direction is not limited thereto.
[0045] In some embodiments of the present invention, optionally, the sub-pixel includes a first sub-pixel (such as an R sub-pixel), a second sub-pixel (such as a G sub-pixel) and a third sub-pixel (such as a B sub-pixel), and the data line corresponding to each of the pixels is located between two of the sub-pixels of the pixel P, so that the connection line between each sub-pixel of the pixel P and the data line is not too long. For example, please refer to Figure 2 , Figure 3 and Figure 4 The data line is located between the R sub-pixel and the G sub-pixel. Of course, it can also be set between the G sub-pixel and the B sub-pixel.
[0046] In some embodiments of the present invention, optionally, please refer to Figure 2 and Figure 3 , the gate lines include a first gate line (such as Figure 2 and Figure 3 Gate1, Gate4 in), the second gate line (such as Figure 2 and Figure 3 Gate2, Gate5) and the third gate line (such as Figure 2 and Figure 3 The first gate line and the third gate line are respectively located at two sides of the sub-pixel (such as Gate1 and Gate3), and are respectively connected to the thin film transistor (such as T1) of the first sub-pixel (such as the R sub-pixel) and the thin film transistor (such as T2) of the second sub-pixel (such as the G sub-pixel); the second gate line is located between the first gate line and the third gate line, and is connected to the thin film transistor (such as T3) of the third sub-pixel (such as the B sub-pixel).
[0047] In an embodiment of the present invention, each sub-pixel includes a thin film transistor and a capacitor connected to the thin film transistor, and the thin film transistor includes a gate, a source and a drain, wherein the gate is used to connect to the gate line, one of the source or the drain is connected to the data line, and the other is connected to the capacitor in the pixel.
[0048] In some embodiments of the present invention, optionally, please refer to Figure 2 and Figure 3 , the distance between the second gate line (such as Gate2) and the first gate line (such as Gate1) is equal to the distance between the second gate line and the third gate line (such as Gate2) (such as Gate3).
[0049] In some embodiments of the present invention, optionally, please refer to Figure 2 and Figure 3 , the thin film transistor (such as T1) of the first sub-pixel (such as R sub-pixel) is located in the edge area of the first sub-pixel; the thin film transistor (such as T2) of the second sub-pixel (such as G sub-pixel) is located in the edge area of the second sub-pixel, and one of the thin film transistor of the second sub-pixel and the thin film transistor of the first sub-pixel is arranged close to the first gate line (such as Gate1), and the other is arranged close to the third gate line (such as Gate3); the thin film transistor (such as T3) of the third sub-pixel (such as B sub-pixel) is located in the middle area of the third sub-pixel, and the area of the third sub-pixel above the thin film transistor of the third sub-pixel has the same aperture ratio as the area of the third sub-pixel below the thin film transistor of the third sub-pixel, that is, the area above the thin film transistor of the third sub-pixel and the area below the thin film transistor are the same, thereby improving the uniformity of display.
[0050] In some embodiments of the present invention, optionally, please refer to Figure 2 , the thin film transistors in all the pixels P are arranged in the same manner.
[0051] In some embodiments of the present invention, optionally, please refer to Figure 3 The arrangement of the thin film transistors in the pixels in the same row is the same, but the arrangement of the thin film transistors in the pixels in different rows is different.
[0052] In some embodiments of the present invention, optionally, please refer to Figure 3 The thin film transistors (such as T1) of two adjacent first sub-pixels (such as R sub-pixels) in the column direction are mirror-set; the thin film transistors (such as T2) of two adjacent second sub-pixels (such as G sub-pixels) in the column direction are mirror-set.
[0053] In some embodiments of the present invention, optionally, please refer to Figure 3, the thin film transistors (such as T2) of two adjacent second sub-pixels (such as G sub-pixels) in the column direction are arranged close to each other, and share the same via H to be connected to the data line. Alternatively, in some other examples of the present invention, the thin film transistors (such as T1) of two adjacent first sub-pixels (such as R sub-pixels) in the column direction are arranged close to each other, and share the same via H to be connected to the data line. Alternatively, in some other examples of the present invention, the thin film transistors (such as T1) of two adjacent first sub-pixels (such as R sub-pixels) in the column direction are arranged close to each other, and share the same via to be connected to the data line, and the thin film transistors (such as T2) of two adjacent second sub-pixels (such as G sub-pixels) in the column direction are arranged close to each other, and share the same via to be connected to the data line. Adjacent thin film transistors share a via, which can reduce the number of vias and improve the aperture ratio of the pixel.
[0054] In some embodiments of the present invention, optionally, please refer to Figure 4 , the gate lines include a first gate line (such as Figure 4 Gate1, Gate4 in), the second gate line (such as Figure 4 Gate2, Gate5) and the third gate line (such as Figure 4 In the embodiment of the present invention, the first gate line, the second gate line and the third gate line are all arranged close to one side of the pixel, and are respectively connected to the thin film transistor (such as T1) of the first sub-pixel (such as R sub-pixel), the thin film transistor (such as T2) of the second sub-pixel (such as G sub-pixel) and the thin film transistor (such as T3) of the third sub-pixel (such as B sub-pixel). That is to say, the thin film transistor of the first sub-pixel is located in the edge area of the first sub-pixel, the thin film transistor of the second sub-pixel is located in the edge area of the second sub-pixel, and the thin film transistor of the third sub-pixel is located in the edge area of the third sub-pixel, and the thin film transistors of the first sub-pixel, the second sub-pixel and the third sub-pixel are all located on the same side of the pixel P. Of course, in some other embodiments of the present invention, other arrangements may also be adopted, for example, the thin film transistors of the first sub-pixel and the second sub-pixel are both located on one side of the pixel P, and the thin film transistors of the third sub-pixel are both located on the other side of the pixel P, etc., and the present invention does not limit this.
[0055] In some embodiments of the present invention, optionally, when the thin film transistors of the first sub-pixel, the second sub-pixel, and the third sub-pixel are all located on the same side of the pixel P, at least two sub-pixels in the same pixel share the same via hole to be connected to the data line. For example, the thin film transistors of the first sub-pixel and the second sub-pixel share the same via hole to be connected to the data line, or the thin film transistors of the second sub-pixel and the third sub-pixel share the same via hole to be connected to the data line, or the thin film transistors of the first sub-pixel, the second sub-pixel, and the third sub-pixel share the same via hole to be connected to the data line, etc. Adjacent thin film transistors share a via hole, which can reduce the number of via holes and improve the aperture ratio of the pixel.
[0056] In some embodiments of the present invention, optionally, please refer to Figure 4 , the arrangement of the thin film transistors in all the pixels is the same. Of course, the present invention is not limited to this.
[0057] The display substrate in the embodiment of the present invention may be a liquid crystal display substrate or other types of display substrates.
[0058] An embodiment of the present invention further provides a display device, comprising:
[0059] Display substrate;
[0060] The source driving circuit is connected to the data lines of the display substrate and provides data voltages to the data lines corresponding to three sub-pixels of the same pixel of the display substrate in a time-sharing manner.
[0061] Wherein, the display substrate is the display substrate described in any of the above embodiments.
[0062] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.
Claims
1. A display substrate, characterized in that: include: substrate substrate; A plurality of gate lines extending in a row direction and a plurality of data lines extending in a column direction are arranged on the substrate; A plurality of pixels, each of the pixels comprises three sub-pixels, a length of each of the sub-pixels in a row direction is smaller than a length in a column direction, and the three sub-pixels of each of the pixels share one data line.
2. The display substrate according to claim 1, wherein: The three sub-pixels of each pixel are arranged in a row direction, and the sub-pixels of the same color are arranged in a column direction.
3. The display substrate according to claim 1, wherein: The sub-pixels include a first sub-pixel, a second sub-pixel and a third sub-pixel, and a data line corresponding to each of the pixels is located between two of the sub-pixels of the pixel.
4. The display substrate according to claim 3, wherein: The gate lines include a first gate line, a second gate line and a third gate line. The first gate line and the third gate line are respectively located on both sides of the sub-pixel and are respectively connected to the thin film transistor of the first sub-pixel and the thin film transistor of the second sub-pixel. The second gate line is located between the first gate line and the third gate line and is connected to the thin film transistor of the third sub-pixel.
5. The display substrate according to claim 4, wherein: The distance between the second gate line and the first gate line is equal to the distance between the second gate line and the third gate line.
6. The display substrate according to claim 5, wherein: The thin film transistor of the first sub-pixel is located in an edge region of the first sub-pixel; The thin film transistor of the second sub-pixel is located in an edge region of the second sub-pixel, and one of the thin film transistor of the second sub-pixel and the thin film transistor of the first sub-pixel is disposed close to the first gate line, and the other is disposed close to the third gate line; The thin film transistor of the third sub-pixel is located in the middle area of the third sub-pixel, and the area of the third sub-pixel located above the thin film transistor of the third sub-pixel has the same aperture ratio as the area of the third sub-pixel located below the thin film transistor of the third sub-pixel.
7. The display substrate according to claim 6, wherein: The thin film transistors in all the pixels are arranged in the same manner.
8. The display substrate according to claim 6, wherein: The thin film transistors in the pixels in the same row are arranged in the same manner.
9. The display substrate according to claim 8, wherein: The thin film transistors of two adjacent first sub-pixels in the column direction are arranged in mirror image; The thin film transistors of two adjacent second sub-pixels in the column direction are arranged in mirror image.
10. The display substrate according to claim 9, wherein: The thin film transistors of two adjacent second sub-pixels in the column direction are arranged close to each other and share the same via hole to be connected to the data line.
11. The display substrate according to claim 3, wherein: The gate lines include a first gate line, a second gate line and a third gate line, and the first gate line, the second gate line and the third gate line are all arranged close to one side of the pixel and are respectively connected to the thin film transistor of the first sub-pixel, the thin film transistor of the second sub-pixel and the thin film transistor of the third sub-pixel.
12. The display substrate according to claim 11, wherein: At least two sub-pixels in the same pixel share the same via hole and are connected to the data line.
13. The display substrate according to claim 11 or 12, characterized in that: The thin film transistors in all the pixels are arranged in the same manner.
14. A display device, characterized in that: include: The display substrate according to any one of claims 1 to 13; The source driving circuit is connected to the data lines of the display substrate and provides data voltages to the data lines corresponding to three sub-pixels of the same pixel of the display substrate in a time-sharing manner.