Logical interface for multi-layer

Abstract

The invention relates to a logical interface for a multi-tier architecture. In various examples, one or more logical interfaces are used to represent functional requirements of an architecture specification. The logical interface may indicate one or more dependencies of functions associated with a plurality of components of the architecture. Using the logical interface, one or more physical interfaces between the components may be recursively determined, and these physical interfaces may be used to perform operations using multiple components.

Description

Background Art

[0001] The development of software and hardware architectures can be very complex, especially when the development involves numerous teams of developers, each of which may be responsible for one or more different components and / or elements that need to function correctly with the other components. To facilitate the interoperability of these independently developed elements, documentation that defines how each element operates and interacts with the other elements must be generated and updated as more features and / or functionality are included in the architecture. Therefore, when developing and / or modifying the architecture, developers use documentation to determine the scope, interfaces, and / or manner of data exchange.

[0002] However, for large architectures produced by a hierarchy of different developer groups, the documents that define the interfaces between elements may be too large and complex to be effectively used and / or maintained. For example, the documentation for a development platform can contain thousands of pages and be cumbersome to use. For an architecture to be verified, the expectations of each element must be fully and clearly captured, which may require documenting the expected results of each element. Traditionally, application programming interfaces (APIs) attempt to capture the requirements of each element in the architecture. However, APIs typically do not provide enough information to easily discern what one element may require from another element (e.g., a sub-element), or which parts of the architecture may be critical to the correct operation of the application and which other parts may be less important. In addition, in order to fully specify the API for each possible interface, traditional methods of describing architectures are very complex and limit designers' understanding, analysis, and / or verification of the architecture. Summary of the invention

[0003] Embodiments of the present disclosure relate to logical interfaces for multi-tier architectures. Methods and systems are disclosed for defining high-level requirements of element functionality using logical interfaces. For example, a logical interface can define an architecture, obtaining requirements for each element and / or sub-element in the architecture. Thus, the requirements of each element in the architecture can be traced back to the physical interface details of the architecture through any sub-element.

[0004] Compared to traditional systems (such as the system described above), logical interfaces that define high-level requirements for the functionality of various elements within the architecture enable the architecture to specify only the properties of shared boundaries between elements when necessary to describe how the functionality is applied to meet the specified requirements. This can eliminate the need for additional specifications of the architecture that are not necessary for decomposition, analysis, and / or verification of elements within the architecture. In addition, the use of logical interfaces to define the relationships between elements enables the duplication of expectations and policies related to the elements to be reduced because higher-level elements will capture the requirements of lower-level elements. Architectures defined using logical interfaces allow for vertical and horizontal freedom when designing / modifying the architecture because higher-level architectures can define expectations or policies for shared boundaries between elements without limiting the specific mechanisms of each element used to meet the expectations. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The method and system for the logical interface of the multi-layer architecture are described in detail below with reference to the accompanying drawings, wherein:

[0006] Figure 1 A block diagram of an example architecture specification system according to some embodiments of the present disclosure is shown;

[0007] Figure 2 A diagram illustrating an interface specification according to some embodiments of the present disclosure;

[0008] Figure 3 A diagram illustrating a physical interface specification according to some embodiments of the present disclosure;

[0009] Figure 4 is an example diagram of an architectural traceability model according to some embodiments of the present disclosure;

[0010] Figure 5 is an example architectural design according to some embodiments of the present disclosure;

[0011] Figure 6 A flowchart of a method for performing interface concretization according to some embodiments of the present disclosure is shown;

[0012] Figure 7 A flow chart of a method for identifying a physical interface according to some embodiments of the present disclosure is shown;

[0013] Fig. 8A is a schematic diagram of an example autonomous driving vehicle according to some embodiments of the present disclosure;

[0014] Figure 8B According to some embodiments of the present disclosure Fig. 8A Examples of camera positions and fields of view for autonomous vehicles;

[0015] Figure 8C According to some embodiments of the present disclosure Fig. 8A A block diagram of an example system architecture for an example autonomous vehicle;

[0016] Fig.8D According to some embodiments of the present disclosure, a cloud server and Fig. 8A A system diagram of an example of communication between autonomous vehicles; and

[0017] Fig. 9 is a block diagram of an example computing device suitable for implementing some embodiments of the present disclosure. DETAILED DESCRIPTION

[0018] Methods and systems related to logical interfaces for multi-layer architectures are disclosed. The present application may define an architecture using one or more logical interfaces that define one or more high-level requirements for element functionality. For example, a logical interface may define an architecture that obtains the requirements of each element and / or sub-element (e.g., sub-element) in the architecture. For example, a logical interface may specify the requirements of one or more sub-elements without specifically defining the functions, instructions, and / or other parameters used by the sub-elements. For example, an element may require a sub-element to perform a specific task, but the element may not define how to perform the task. An architecture (e.g., an architectural design) may define and / or specify one or more elements and their interactions in one or more hierarchical structures. Therefore, the requirements of each element of the architecture may be traced back to the physical interface details of the architecture through any sub-element.

[0019] In at least one embodiment, an interface is a shared boundary (e.g., a relationship) between components (e.g., elements). For example, an interface may represent a possible interaction between a first component and a second component. In at least one embodiment, a component may represent one or more elements, units, and / or external entities. An element may represent a system and / or a part of a system, and the system includes: one or more sub-elements, hardware, software, hardware components, and / or software units. One or more components may provide an interface associated with one or more subordinate components (e.g., sub-elements), and the subordinate component may require the interface to perform one or more interactions between the subordinate component and the one or more components providing the interface. In at least one embodiment, an interface may be represented in a directed graph (e.g., a graph comprising a set of vertices connected by directed edges), wherein the vertices of the graph may represent one or more components, and one or more edges of the graph may represent one or more interfaces.

[0020] In some examples, the interface may be a physical interface. A physical interface (e.g. Figure 3The physical interface 304 in the example may define one or more design specifications for a shared boundary between two or more components. In some examples, the physical interface may specify one or more parameters required to implement a shared boundary between two or more components. In at least one embodiment, the interface may be a logical interface, such as Figure 2 The interface 202 in the example. A logical interface may be an architectural specification of a shared boundary between two or more components (e.g., elements) (e.g., one or more policies describing the shared boundary). For example, a logical interface may represent a connection between two or more elements based on dependencies between functions associated with the multiple elements. In some embodiments, a logical interface may expose a set of interfaces, which may be one or more logical interfaces and / or physical interfaces.

[0021] In at least one embodiment, an interface may be represented as one or more event groups, e.g. Figure 2 204 in. An event is one or more interactions between multiple components on a shared boundary (e.g., an interface). For example, an event may include one or more attributes that specify one or more preconditions, outcomes, and / or data flows for using an interface between multiple components. An event may include one or more preconditions, outcomes, concurrencies, and / or input / output data. For example, an event may include a prerequisite that describes a prerequisite for executing the event. In another example, an event may include one or more outcomes that describe one or more outcomes of executing the event. An event may include one or more concurrencies that represent strategies for other events to occur during the execution of the event. An event may include a description of input and / or output data that represent data flows when executing the event. In at least one embodiment, an event may be a physical event that represents the use of one or more procedures, such as data fields or methods, through one or more physical interfaces. For example, a physical interface may define a set of one or more physical events that specify one or more possible interactions through a shared boundary of the physical interface. In at least one embodiment, an event may be a logical event. A logical event may represent the utilization of one or more functions of an element exposed through one or more logical interfaces. For example, a logical event may specify one or more strategies for performing a function in the context of one or more elements.

[0022] Events can be specified according to event identifiers. For example, an event can have a unique identifier that is different from the identifiers of one or more other events. Events can be specified using one or more attributes.

[0023] In at least one embodiment, an interface control specification describes the specification of one or more interfaces. For example, an interface control specification may describe one or more elements and one or more interfaces corresponding to the one or more elements. In some examples, an interface control specification may include one or more events associated with one or more interfaces. In at least one embodiment, an interface control specification may ensure compatibility between two or more elements of an architecture. In some examples, an interface control specification may be a document, such as in the case of a document-based architecture. In at least one embodiment, an interface control specification may represent one or more work product relationships associated with one or more interfaces. An interface control document may include one or more attributes of an interface, which are defined during the specification of a parent architecture that requires the interface. In these examples, the concretization attributes of a logical interface may be defined during the specification of one or more components that concretize one or more logical events into events and / or one or more physical events between subcomponents. In at least one embodiment, the concretization of the interface is completed once the logical interface is concretized into a set of physical interfaces. In some examples, an interface control specification (e.g., as described below with respect to Figure 5 The architecture design 500 described herein may be represented as a version control project stored in association with one or more software and / or hardware corresponding to the architecture.

[0024] In at least one embodiment, the logical interface between two or more elements of the architecture can be transformed (e.g., concretized) into one or more interfaces. For example, the logical interface can be recursively analyzed to generate a set of one or more other interfaces (e.g., physical interfaces). The transformation interface can include a set of one or more physical interfaces between two or more sub-elements of the determined element. The logical event can be transformed into a set of physical events supported by one or more transformed events. In at least one embodiment, one or more prerequisites can be transformed into the combinatorial logic of the transformed event or one or more prerequisites. The result can be transformed into the combinatorial logic of the result of the transformed result. Concurrency can be transformed into the combinatorial logic of the concurrency of the transformed concurrency. The input and / or output object can be transformed into a set of input and / or output objects of the transformed event.

[0025] In at least one embodiment, one or more specializations of a logical interface may be specified when a logical interface is specialized as a set of interfaces between multiple subcomponents, a logical event is specialized as a set of events supported by a specialization interface, a precondition is specialized as the combinatorial logic of the preconditions of the specialization event, a result is specialized as the combinatorial logic of the result of the specialization event, concurrency is specialized as the combinatorial logic of the concurrency of the specialization event, and / or an input / output object is specialized as a set of input and / or output objects of the specialization event.

[0026] In at least one embodiment, one or more elements in the architecture can encapsulate one or more sub-elements. For example, an element can include one or more different sub-elements. For a specific element, the open-box specification of the element can define one or more expectations and / or one or more strategies for these sub-elements by specifying a closed-box specification for the sub-elements. In this way, the open-box specification of the sub-element can be postponed until the architecture is defined on the level corresponding to the sub-element. The open-box specification of the element can use one or more logical interfaces to define the expectations and / or strategies of one or more sub-elements. In some examples, the function of the sub-element of an element (e.g., a parent element) can be described as a dependency on one or more functions of one or more other sub-elements. The dependency between multiple sub-elements can be realized by the event on the interface between each corresponding sub-element.

[0027] The closed box specification of one or more elements in the architecture can include requirements for one or more elements by specifying the use of one or more functions disclosed between the elements. For example, the closed box specification can include an indication of one or more events defined by a parent architecture (e.g., a higher-level architecture). The functionality of an element can be decomposed into a set of functions associated with multiple child elements, with possible dependencies between the multiple child elements. Child elements can be interdependent with other child elements, with dependencies between child elements with different parent elements. Child elements can be internally dependent, with dependencies between multiple child elements with the same parent element.

[0028] At a specific architecture level (e.g., layer), each dependency of functions between two or more elements (e.g., parent elements) can be represented by a group of mutually dependent functions between the child elements of these two or more elements. This group of mutually dependent functions can be disclosed by one or more interfaces between these child elements. These mutually dependent functions can be disclosed according to one or more strategies of shared boundaries that have been determined between multiple parent elements. The interfaces determined between multiple child elements can be defined according to the strategies defined by one or more logical interfaces between these parent elements. In at least one embodiment, the open box specification of the parent element concretizes each logical event between the parent elements into a group of events between the child elements (e.g., defining a 1:N relationship for each logical event). The functions of internal dependencies can be disclosed by one or more interfaces between the various child elements of the parent element. In some examples, one or more requirements for multiple child elements can strengthen the closed box specifications of these child elements defined by the corresponding architecture and one or more events between them. By using the interfaces between the child elements of the lower level of the architecture to express the functions of the higher level elements of the architecture, the process of concretizing or otherwise decomposing the architecture can be performed recursively. This process can be performed until the specification of the architecture completes the subdivision of each level of child elements associated with the parent element. When the concretization process is complete, the logical interfaces of the highest level elements can be represented by a set of physical interfaces between these elements.

[0029] See also Figure 1 , Figure 1 A block diagram of an example architecture specification system 100 ("system 100") according to some embodiments of the present disclosure is shown. It should be understood that this arrangement and other arrangements described herein are presented as examples only. In addition to the arrangements and elements shown, other arrangements and elements (e.g., machines, interfaces, functions, sequences, functional groupings, etc.) may also be used, and certain elements may be omitted entirely. In addition, many of the elements described herein are functional entities that may be implemented as discrete or distributed components, or in combination with other components, and may be implemented in any suitable combination and location. The various functions performed by the entities described herein may be performed by hardware, firmware, and / or software. For example, the various functions may be performed by a processor executing instructions stored in a memory.

[0030] The system 100 may include a device 102 and / or one or more networks 108. The device 102 may include an application 110, a concretizer 116, one or more interface control documents (ICDs) 114, one or more architectural elements 130, one or more sensors 112, a storage device 120, and / or one or more processors 118.

[0031] The components of system 100 may be configured to span across one or more networks (e.g. Figure 1 108) and / or other network types described herein. Network 108 may include one or more networks of any number of network types. In some examples, network 108 includes one or more data bus protocols and / or topologies (e.g., controller area network (“CAN”), FlexRay, Ethernet, etc.). One or more components of system 100 may be configured to connect to one or more components of system 100 via network 108 using one or more network interfaces.

[0032] The device 102 may include one or more components for performing one or more operations (e.g., architecture specification, analysis, and / or validation, etc.) associated with an autonomous or semi-autonomous machine. For example, the device 102 may include one or more components for defining an architecture using one or more logical interfaces that define one or more high-level requirements for the functionality of an element, one or more components for performing computations (e.g., using the processor 118), and / or one or more components for making predictions corresponding to an autonomous or semi-autonomous machine. As an example, the device 102 may define an architecture for performing one or more operations associated with an autonomous machine, a semi-autonomous machine, and / or other hardware device.

[0033] The processor 118 may include one or more components for processing data associated with one or more autonomous or semi-autonomous machine operations. In some embodiments, the processor 118 may provide additional and / or alternative processing to the processing performed by the device 102. In some examples, the processor 118 may perform processing associated with the system 100. For example, the processor 118 may be configured to process measurement data from one or more inertial measurement unit sensors and / or other sensors (e.g., LiDAR and cameras associated with the device 102). In some embodiments, the processor 118 may be used to perform one or more operations associated with (one or more) architectural elements 130 and / or (one or more) sensors 112. The architectural elements may include one or more sub-elements, hardware, software, hardware components, and / or software components, and may be used to perform one or more computing operations.

[0034] The application 110 may include one or more components configured to define an architecture having one or more components (e.g., architecture elements 130). For example, the application 110 may access (one or more) interface control documents 114 to identify one or more logical and / or physical interfaces associated with a component (e.g., architecture element 130 and / or sensor 112). In some examples, the application 110 may use a concretizer 116 to determine a set of physical interfaces that concretize one or more logical interfaces into one or more processes (e.g., fields or methods) that can be executed by the architecture element 130 using a processor 118. These physical interfaces may include multiple physical events representing the utilization of a program on them (i.e., these physical interfaces). In this example, the set of physical events may specify possible interactions on a boundary shared by the architecture element 130.

[0035] Interface control document(s) 114 ("ICD") may include one or more components configured to indicate one or more specifications of an interface. For example, ICD 114 may include one or more logical and / or physical interfaces associated with an element of an architecture (e.g., architecture element 130 and / or sensor 112). ICD 114 may be used (e.g., by application 110) to identify one or more interfaces associated with architecture element 130 (e.g., architecture element 130 and / or sensor 112). Figure 2 In at least one embodiment, the ICD 114 may be used by the application 110 to ensure compatibility between the architecture elements 130. In at least one embodiment, the ICD 114 may be used to define work product relationships associated with one or more interfaces (see Figure 5 In at least one embodiment, ICD 114 may be used by application 110 and / or materializer 116 to determine the physical interfaces to materialize into a logical interface (e.g., Figure 3 In some examples, once a set of physical interfaces is determined, device 102 may perform one or more operations using the set of physical interfaces (eg, using architectural elements 130 associated with the physical interfaces).

[0036] The concretizer 116 may include one or more components configured to concretize one or more logical interfaces into a set of one or more physical interfaces. For example, the concretizer 116 may use the processor 118 to recursively process each of the multiple levels in the architecture to determine one or more physical interfaces between elements and sub-elements of the architecture (see Figure 41. The architectural traceability model 400 of FIG. 110 is shown in FIG. 111. The concretizer 116 can identify physical interfaces corresponding to the architectural element(s) 130. In some examples, once the concretizer 116 identifies one or more physical interfaces, these interfaces can be added to the ICD 114 and used to maintain the architectural specification.

[0037] Reification device 116 can transform the logical events indicated by ICD 114 into a set of physical events associated with (one or more) architectural elements 130. Reification device 116 can use combinatorial logic, and one or more logical interfaces (e.g., Figure 2 interface 202) to transform one or more preconditions, results, concurrency, and / or input / output values.

[0038] In at least one embodiment, the concretizer 116 may access an open box specification of (one or more) architectural elements 130, which may define one or more expectations and / or one or more policies on the sub-elements of (one or more) architectural elements 130 by specifying a closed box specification for the sub-elements. The concretizer 116 may use the decomposed functionality of the architectural element 130 represented by a set of functions associated with the sub-elements of (one or more) architectural elements 130, wherein there may be dependencies between these sub-elements. In at least one embodiment, the decomposition of the functions is used to transform one or more logical events into one or more other logical events and / or one or more physical events. The concretizer 116 may be used by the application 110 to define the functionality of the higher-level elements of (one or more) architectural elements 130 using the interfaces between the sub-elements of (one or more) architectural elements 130 at the lower level. This process may be performed recursively until the specification of the (one or more) architectural elements 130 completes the breakdown of each layer of sub-elements associated with the (one or more) architectural elements 130. For example, in an architecture with a hierarchy of four layers of elements, once the physical interfaces of the fourth layer (the lowest level layer) are concretized, the logical interfaces of the third layer can be concretized and then used to concretize the logical interfaces of the second layer into a set of physical interfaces corresponding to the second layer. In such an example, the set of physical interfaces determined for each level of the architecture can be used to recursively concretize the logical interfaces of higher levels until physical interfaces are determined for each level of the architecture. When the concretization process is complete, the logical interfaces of the highest level elements can be represented by a set of physical interfaces between multiple elements in the architecture elements 130.

[0039] Sensors 112 may include one or more components for collecting data related to system 100. For example, system 100 may include one or more sensors 112 that collect and / or generate sensor data related to the operation of one or more autonomous or semi-autonomous machines. As an example, sensors 112 may include one or more RADAR sensors, cameras, ultrasonic sensors, LiDAR sensors, accelerometers, gyroscopes, magnetometers, altimeters, and / or any other suitable sensors, such as those related to Figures 8A-8D The sensors described in connection with the vehicle 800 are described above. As described above, in some embodiments, one or more sensors 112 may include one or more processors that may be configured to perform one or more operations associated with the architecture. For example, the sensor 112 may measure one or more indicators in response to an event indicated by the architecture. In such an example, the sensor 112 may generate one or more sensor values ​​in response to a routine executed by one or more other components (e.g., the application 110). For example, a temperature sensor may generate temperature data in response to one or more function calls and / or instructions.

[0040] Device 102 may include a memory (not shown), which may be implemented as one or more non-transitory processor-readable media, storing processor-executable instructions that, when executed by processor 118, implement application 110, embodiment 116, ICD 114, etc. The memory (not shown) may be implemented as storage device 120 or use storage device 120. Processor 118 may include one or more circuits that execute at least a portion of the instructions. Using a main central processing unit (CPU) complex, processor 118 may be implemented as, for example, one or more microprocessors, one or more microcontrollers, one or more graphics processing units (GPUs), one or more data processing units (DPUs), etc. By way of additional non-limiting example, the memory (such as one or more non-transitory processor-readable media) may be implemented, for example, using volatile memory (such as dynamic random access memory (DRAM)) and / or non-volatile memory (such as a hard drive, solid-state device (SSD)), etc. Device 102 may include a user interface (not shown) that a user may use to enter user input into device 102. The user interface (not shown) may include a display device (not shown) that a user may use to view information generated and / or displayed by the device 102. The processor 118, the user interface, and / or the memory may communicate with each other via one or more connections (e.g., a bus, a Peripheral Component Interconnect Express (PCIe) connection (or bus), etc.).

[0041] Figure 2 200 , according to some embodiments of the present disclosure. Interface specification 200 may include interface 202 (e.g., an interface as described above). In at least one embodiment, interface 202 may include one or more data types 212 and / or (one or more) events 214. Event 214 may correspond to one or more events, such as event 204. Events, such as event 204, may include one or more preconditions 216, results 218, concurrency information 220, and / or input / output data 222.

[0042] In some examples, prerequisites 216 may represent one or more prerequisites for executing event 204. For example, prerequisites 216 may indicate one or more actions and / or operations that must be performed before executing event 204. Results 218 may include one or more indications of achievements generated in response to executing event 204. For example, results 218 may specify one or more status values ​​when executing event 204. As a further example, if event 204 is to read data associated with a sensor (e.g., Figure 1 112), the result 218 may indicate that the temperature value was successfully read, or alternatively, was not successfully read. Concurrency information 220 includes information indicating one or more policies associated with the occurrence of other events executed during the implementation and / or execution of event 204. For example, concurrency information 220 may indicate one or more other events that run concurrently with event 204 or are otherwise associated with it. Input / output data 222 may include one or more representations of data flows when executing event 204. For example, input / output data 222 may include indications of one or more input and / or output parameters input to event 204 or output from event 204 when executing event 204.

[0043] Figure 3 3 is a diagram showing a physical interface specification 300 according to some embodiments of the present disclosure. The physical interface specification may extend the interface specification, e.g. Figure 2 The physical interface specification 300 may include an interface 302 (e.g., such as the physical interface described above) and a physical interface 304. In at least one embodiment, the interface 302 may include one or more data types 312 and / or (one or more) events 314. The event 314 may correspond to one or more events, such as Figure 2 The physical interface 304 can include one or more procedures 316, signatures 318, and / or static mappings 320. In some examples, the physical interface 304 can extend the parameters of the interface 302.

[0044] In at least one embodiment, process 316 may include one or more fields or methods. For example, process 316 may include information indicating one or more methods and / or functions and associated data fields. Signature 318 may include one or more input and / or output parameters of process 316. For example, signature 318 may include input / output parameters of one or more methods indicated by process 316. Static mapping 320 may include one or more of the procedure value and / or signature value for executing a physical event. For example, static mapping 320 may include a procedure value associated with process 316 and / or a signature value associated with signature 318, and is used to execute a physical event associated with physical interface 304.

[0045] Figure 4 is an example diagram of an architectural traceability model 400 (“model 400”) according to some embodiments of the present disclosure. Model 400 may be composed at least in part of Figure 1 The model 400 may include one or more specifications of one or more layers of the architecture. For example, the model 400 may include one or more layers, such as the system context 410, the layer 2 architecture 424, the layer 3 architecture 434, and / or the layer 4 architecture 444, each of which specifies a different layer of the model 400.

[0046] Model 400 may include one or more requirement specifications, such as layer 2 requirements 422, layer 3 requirements 432, and / or layer 4 requirements 442. Model 400 may include one or more layer X definitions, such as layer 2 definitions 420, layer 3 definitions 430, and / or layer 4 definitions 440, which describe one or more interfaces associated with components at each layer of model 400.

[0047] In some embodiments, system context 410 may describe the highest level elements of the architecture represented by model 400. For example, system context 410 may represent an operating system and one or more interfaces provided by the operating system. System context 410 may include one or more lower layers of model 400, such as layer 2 architecture 424, layer 3 architecture 434, and / or layer 4 architecture 444. The lower layers of model 400 describe components that satisfy the functional expectations of the higher layers of model 400. For example, layer 2 architecture 424 may describe how to satisfy layer 2 requirements and may define one or more components of one or more lower layers (e.g., layer 3 architecture 434) of model 400. Layer 3 architecture 434 may describe how to satisfy layer 3 requirements and may define one or more components of one or more lower layers (e.g., layer 4 architecture 444) of model 400.

[0048] The functionality of each respective layer relative to one or more other layers may be specified by a requirements specification and / or layer definition. The layer requirements may specify the expected functionality to be provided by each layer of the model 400, and may also include an indication of one or more interfaces and / or interface characteristics for providing the indicated functionality. For example, the layer 2 requirements 422 may include information representing the expectations of the system context 410 for the functionality to be provided by the layer 2 architecture 424. Similarly, the layer 3 requirements 432 define expectations for functionality to be provided by the layer 3 architecture 434 to the layer 2 architecture 424. As a further example, the layer 4 requirements 442 define expectations for functionality to be provided by the layer 4 architecture 444 to the layer 3 architecture 434.

[0049] The layer definition may include information describing one or more interfaces associated with components on each layer of the model 400. For example, the layer definition may include one or more ICDs that formalize the expectations and / or characteristics of one or more interfaces. The layer definition may be concretized by the layer architecture into one or more definitions associated with different layers of the model 400. For example, one or more interfaces may be concretized by the layer 2 architecture 424 into interfaces associated with the layer 3 architecture 434 (e.g., the layer 3 architecture 434 satisfies one or more expectations of the layer 2 architecture 424). In some examples, one or more interfaces may be concretized by the layer 2 architecture 424 into one or more components associated with the layer 3 architecture 434. In a similar example, one or more interfaces may be concretized by the layer 3 architecture 434 into interfaces associated with the layer 4 architecture 444 (e.g., the layer 4 architecture 444 satisfies one or more expectations of the layer 3 architecture 434). In some examples, one or more interfaces may be materialized by layer 3 architecture 434 as one or more components associated with layer 4 architecture 444. Interfaces may be materialized at each layer of model 400 until a physical interface is defined.

[0050] Figure 5 is an example architecture design 500 according to some embodiments of the present disclosure. The architecture design 500 may be implemented at least in part by one or more processors (e.g., Figure 1The architecture design 500 may specify one or more relationships between one or more specifications for defining the architecture design 500. The architecture design 500 may include one or more interface control documents, such as interface control document 514, interface control document 824, and / or interface control document 528. The interface control document may be stored as a version control project in association with a work product that utilizes interface attributes defined in the ICD. For example, the interface control document 514 may define one or more logical interfaces 516 used by the parent architecture 510 and may be stored with the parent architecture 510 as part of the parent architecture project 502. Similarly, the interface control document 524 and / or the interface control document 528 may define one or more logical interface concretizations 526 and / or physical interfaces 530 used by the element architecture 520 and may be stored with the element architecture 520 as part of the element project 504, which may be maintained separately from the parent architecture project 502.

[0051] The architecture design 500 may include a logical interface concretization 526, which may specify event concretizations associated with the element item 504. The interface control document 528 may include one or more indications of a physical interface 530, which specifies properties of one or more physical interfaces of the element item 504. Once the physical interface 530 concretizes the logical interface 516 in the form of the logical interface concretization 526, the open-box element architecture 522 may be defined as part of the element architecture specification 520 and provided to the parent architecture 510 as the closed-box element architecture 512.

[0052] Reference now Figure 6 , each block of the method 600 described herein includes a computing process that can be performed using any combination of hardware, firmware, and / or software. For example, various functions can be implemented by a processor executing instructions stored in a memory. The method 600 can also be embodied as computer usable instructions stored on a computer storage medium. The method 600 can be provided by a stand-alone application, a service, or a hosted service (alone or in combination with another hosted service), or a plug-in to another product, to name a few. In addition, the method 600 is directed to Figure 1 The system 100 is described by way of example. However, these methods may additionally or alternatively be performed by any system or any combination of systems, including but not limited to the systems described herein.

[0053] Figure 6 is a flow chart of a method 600 for performing interface concretization according to certain embodiments of the present disclosure. At block 602, (see Figure 1 , for example, by Figure 1The application 110 (executable by the processor 118 shown in FIG. 1 ) accesses one or more logical interfaces, which indicate one or more dependencies of one or more functions associated with multiple components. For example, through the application 110, (executable by the processor 118 shown in FIG. 1 ), Figure 1 One or more logical interfaces (specified in ICD 114 in FIG. 1 ) may be accessed and / or provided to one or more processors, such as (see Figure 1 ) processor 118.

[0054] At block 604, based on the one or more logical interfaces accessed at block 602, the processor 118 (see Figure 1 ) can be used to determine one or more physical interfaces of multiple components. For example, Figure 1 The processor 118 may be used to recursively materialize one or more logical interfaces as a set of one or more physical interfaces between (one or more) architectural elements 130.

[0055] At block 606, the application 110 (see Figure 1 ) may perform and / or cause to be performed one or more operations using the plurality of physical interfaces determined at block 604. For example, application 110 may use processor 118 to perform one or more operations using parameters specified by one or more physical interfaces determined in association with architectural element(s) 130. After block 606, method 600 may terminate.

[0056] Reference now Figure 7 , each block of the method 700 described herein includes a computing process that can be performed using any combination of hardware, firmware, and / or software. For example, various functions can be performed by a processor executing instructions stored in a memory. The methods can also be embodied as computer usable instructions stored on a computer storage medium. The methods can be provided by a stand-alone application, a service or a hosted service (stand-alone or in combination with another hosted service), or a plug-in for another product, to name a few. In addition, the method 700 is directed to Figure 1 The systems are described by way of example. However, the methods may additionally or alternatively be performed by any one system or any combination of systems, including but not limited to those described herein.

[0057] Figure 7 7 is a flow diagram of a method 700 for identifying a physical interface according to some embodiments of the present disclosure. The method 700 includes accessing one or more architecture specifications having logical interfaces associated with multiple elements of an architecture at block 702. For example, the application 110 may access (one or more) ICDs 114 that specify one or more logical interfaces associated with the architecture element 130 and / or the sensor 112.

[0058] At block 704, one or more physical interfaces are identified that represent one or more processes to be performed in association with the plurality of elements. For example, the concretizer 116 may use the processor 118 to recursively identify physical interfaces and associated processes to perform one or more functions indicated by the logical interface using the architecture element 130.

[0059] At block 706, one or more processes are performed using the plurality of elements. For example, once one or more processes associated with the physical interface are identified, the architectural element 130 and / or the sensor 112 may perform the processes using the processor 118. After block 706, the method 700 may terminate.

[0060] The systems and methods described herein may be used by non-autonomous vehicles, semi-autonomous vehicles (e.g., in one or more adaptive driver assistance systems (ADAS)), manned and unmanned robots or robotic platforms, warehouse vehicles, off-road vehicles, vehicles coupled to one or more trailers, aircraft, boats, space shuttles, emergency response vehicles, motorcycles, electric or motorized bicycles, airplanes, construction vehicles, underwater vehicles, drones, and / or other vehicle types, but are not limited thereto. The systems and methods described herein may be used for augmented reality, virtual reality, mixed reality, robotics, security and surveillance, autonomous or semi-autonomous machine applications, and / or any other technical scenario where two or more clocks are synchronized.

[0061] The systems and methods described herein may be used by, but are not limited to, non-autonomous vehicles, semi-autonomous vehicles (e.g., in one or more adaptive driver assistance systems (ADAS)), manned and unmanned robots or robotic platforms, warehouse vehicles, off-road vehicles, vehicles connected to one or more trailers, flying boats, ships, space shuttles, emergency response vehicles, motorcycles, electric or motorized bicycles, aircraft, engineering vehicles, underwater vehicles, drones, and / or other vehicle types. In addition, the systems and methods described herein may be used for a variety of purposes, such as, but not limited to, machine control, machine motion, machine driving, synthetic data generation, model training, perception, augmented reality, virtual reality, mixed reality, robotics, security and surveillance, simulation and digital twins, autonomous or semi-autonomous machine applications, deep learning, environmental simulation, object or participant simulation and / or digital twins, data center processing, conversational artificial intelligence (AI), light transport simulation (e.g., ray tracing, path tracing, etc.), collaborative content creation of 3D assets, cloud computing, web hosting services or web hosting platforms, and / or any other suitable application.

[0062] The disclosed embodiments may be included in a variety of different systems as an application programming interface (API) between two or more separate applications or systems, such as automotive systems (e.g., control systems for autonomous or semi-autonomous machines, perception systems for autonomous or semi-autonomous machines), systems implemented using robots, aviation systems, medical systems, boating systems, smart area monitoring systems, systems for performing deep learning operations, systems for performing simulation operations, systems for performing digital twin operations, systems implemented using edge devices, systems including one or more virtual machines (VMs), systems for performing synthetic data generation operations, systems implemented at least in part in a data center, systems for performing conversational AI operations, systems implementing one or more language models—e.g., large language models (LLMs) that process text, images, sensors, audio, and / or other data types, systems for performing light transport simulations, systems for performing collaborative content creation for 3D assets, systems implemented at least in part using cloud computing resources, systems for implementing a web hosting service (e.g., for runtime program optimization) or a web hosting platform (e.g., an integrated development environment including program optimization as a service), and / or other types of systems.

[0063] Self-driving car example

[0064] Fig. 8A800 according to some embodiments of the present disclosure. The autonomous vehicle 800 (also referred to herein as "vehicle 800") may include, but is not limited to, a passenger vehicle, such as a car, a truck, a bus, an emergency vehicle, a shuttle, an electric or motorized bicycle, a motorcycle, a fire truck, a police car, an ambulance, a boat, a construction vehicle, an underwater vehicle, a drone, and / or other types of vehicles (e.g., unmanned and / or vehicles that can accommodate one or more passengers). Autonomous vehicles are typically described by automation levels, as defined by the National Highway Traffic Safety Administration (NHTSA) of the U.S. Department of Transportation and the Society of Automotive Engineer (SAE)'s "Classification and Definition of Terms Related to Road Vehicle Driving Automation Systems" (Standard J3016-201806 published on June 15, 2018, Standard J3016-201609 published on September 30, 2016, and prior and future versions of the standard). The vehicle 800 may be capable of implementing functions that comply with one or more of the autonomous driving levels 3 to 5. For example, depending on the embodiment, the vehicle 800 may be capable of conditional automation (level 3), high automation (level 4), and / or full automation (level 5).

[0065] The vehicle 800 may include components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. The vehicle 800 may include a propulsion system 850, such as an internal combustion engine, a hybrid power plant, an all-electric engine, and / or another propulsion system type. The propulsion system 850 may be connected to a transmission system (which may include a transmission) of the vehicle 800 to achieve propulsion of the vehicle 800. The propulsion system 850 may be controlled in response to receiving a signal from a throttle / accelerator 852.

[0066] A steering system 854, which may include a steering wheel, may be used to steer the vehicle 800 (e.g., along a desired path or route) when the propulsion system 850 is operating (e.g., when the vehicle is in motion). The steering system 854 may receive signals from a steering actuator 856. For fully automated (Level 5) functionality, a steering wheel may be optional.

[0067] Brake sensor system 846 may be used to operate vehicle brakes in response to signals received from brake actuator 848 and / or brake sensors.

[0068] (may include one or more CPUs, system on chip (SoC) 804 ( Figure 8C) and / or one or more controllers 836 of one or more GPUs may provide signals (e.g., representing commands) to one or more components and / or systems of the vehicle 800. For example, the one or more controllers may send signals to operate vehicle brakes via one or more brake actuators 848, to operate the steering system 854 via one or more steering actuators 856, and / or to operate the propulsion system 850 via one or more throttles / accelerators 852. The one or more controllers 836 may include one or more onboard (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operating commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving the vehicle 800. The one or more controllers 836 may include a first controller 836 for autonomous driving functions, a second controller 836 for functional safety functions, a third controller 836 for artificial intelligence functions (e.g., computer vision), a fourth controller 836 for infotainment functions, a fifth controller 836 for redundancy in emergency situations, and / or other controllers. In some examples, a single controller 836 may handle two or more of the above functions, two or more controllers 836 may handle a single function, and / or any combination thereof.

[0069] The one or more controllers 836 may provide signals for controlling one or more components and / or systems of the vehicle 800 in response to sensor data (e.g., sensor input) received from one or more sensors. The sensor data may be received from, for example and without limitation, a global navigation satellite system sensor 858 (e.g., a global positioning system sensor), a RADAR sensor 860, an ultrasonic sensor 862, a LIDAR sensor 864, an inertial measurement unit (IMU) sensor 866 (e.g., an accelerometer, a gyroscope, a magnetic compass, a magnetometer, etc.), a microphone 896, a stereo camera 868, a wide angle camera 870 (e.g., a fisheye camera), an infrared camera 872, a surround view camera 874 (e.g., a 360 degree camera), a long-range and / or mid-range camera 898, a speed sensor 844 (e.g., for measuring the velocity of the vehicle 800), a vibration sensor 842, a steering sensor 840, a brake sensor 846 (e.g., as part of a brake sensor system 846), and / or other sensor types.

[0070] One or more of the controllers 836 may receive inputs (e.g., represented by input data) from the instrument cluster 832 of the vehicle 800 and provide outputs (e.g., represented by output data, display data, etc.) via a human machine interface (HMI) display 834, an audible annunciator, a speaker, and / or via other components of the vehicle 800. These outputs may include information such as vehicle speed, velocity, time, map data (e.g., Figure 8CThe HMI display 834 may include information such as the HD map 822 of the vehicle 800, location data (e.g., the location of the vehicle 800 on the map), directions, locations of other vehicles (e.g., occupancy grid), information about objects and object states as sensed by the controller 836, etc. For example, the HMI display 834 may display information about the presence of one or more objects (e.g., street signs, warning signs, traffic light changes, etc.) and / or information about driving maneuvers that the vehicle has made, is making, or will make (e.g., changing lanes now, leaving 34B in two miles, etc.).

[0071] The vehicle 800 also includes a network interface 824 that can communicate via one or more networks using one or more wireless antennas 826 and / or a modem. For example, the network interface 824 may be capable of communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, etc. The one or more wireless antennas 826 may also enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using one or more local area networks such as Bluetooth, Bluetooth LE, Z-wave, ZigBee, etc. and / or one or more low power wide area networks (LPWANs) such as LoRaWAN, SigFox, etc.

[0072] Figure 8B According to some embodiments of the present disclosure, Fig. 8A 800. The cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, additional and / or replaceable cameras may be included and / or the cameras may be located at different locations on the vehicle 800.

[0073] The camera type for the camera may include, but is not limited to, a digital camera that may be suitable for use with components and / or systems of the vehicle 800. The camera may operate at an automotive safety integrity level (ASIL) B and / or at another ASIL. The camera type may have any image capture rate, such as 60 frames per second (fps), 120fps, 240fps, etc., depending on the embodiment. The camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In some examples, the color filter array may include a red, white, white, white (RCCC) color filter array, a red, white, white, blue (RCCB) color filter array, a red, blue, green, white (RBGC) color filter array, a Foveon X3 color filter array, a Bayer sensor (RGGB) color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In some embodiments, a clear pixel camera such as a camera with an RCCC, RCCB, and / or RBGC color filter array may be used in an effort to improve light sensitivity.

[0074] In some examples, one or more of the cameras can be used to perform advanced driver assistance system (ADAS) functions (e.g., as part of a redundant or fail-safe design). For example, a multi-function monocular camera can be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. One or more of the cameras (e.g., all of the cameras) can simultaneously record and provide image data (e.g., video).

[0075] One or more of the cameras may be mounted in a mounting assembly such as a custom designed (3-D printed) assembly to cut off stray light and reflections from within the car (e.g., reflections from the dashboard reflected in the windshield mirror) that may interfere with the camera's ability to capture image data. With respect to the wing mirror mounting assembly, the wing mirror assembly may be custom 3-D printed so that the camera mounting plate matches the shape of the wing mirror. In some examples, one or more cameras may be integrated into the wing mirror. For side view cameras, one or more cameras may also be integrated into the four pillars at each corner of the cab.

[0076] A camera (e.g., a front-facing camera) having a field of view including a portion of the environment in front of the vehicle 800 can be used for surround view to help identify the forward path and obstacles, as well as assist in providing information critical to generating an occupancy grid and / or determining a preferred vehicle path with the help of one or more controllers 836 and / or control SoCs. The front-facing camera can be used to perform many of the same ADAS functions as LIDAR, including emergency braking, pedestrian detection, and collision avoidance. The front-facing camera can also be used for ADAS functions and systems, including: Lane Departure Warning (LDW), Autonomous Cruise Control (ACC), and / or other functions, such as traffic sign recognition.

[0077] A variety of cameras may be used in the front-facing configuration, including, for example, a monocular camera platform including a CMOS (complementary metal oxide semiconductor) color imager. Another example may be a wide-angle camera 870, which may be used to sense objects (e.g., pedestrians, intersection traffic, or bicycles) entering the field of view from the periphery. Figure 8B Only one wide-angle camera is shown, but there may be any number of wide-angle cameras 870 on the vehicle 800. In addition, a long-range camera 898 (e.g., a long-view stereo camera pair) may be used for depth-based object detection, especially for objects for which a neural network has not been trained. The long-range camera 898 may also be used for object detection and classification and basic object tracking.

[0078] One or more stereo cameras 868 may also be included in the front configuration. The stereo camera 868 may include an integrated control unit including an expandable processing unit that may provide a multi-core microprocessor and programmable logic (e.g., FPGA) with an integrated CAN or Ethernet interface on a single chip. Such a unit may be used to generate a 3-D map of the vehicle environment, including distance estimates for all points in the image. An alternative stereo camera 868 may include a compact stereo vision sensor that may include two camera lenses (one on each side) and an image processing chip that may measure the distance from the vehicle to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. Other types of stereo cameras 868 may be used in addition to or alternatively to those described herein.

[0079] A camera having a field of view of a portion of the environment including the sides of the vehicle 800 (e.g., a side view camera) can be used for surround view, providing information used to create and update the occupancy grid and generate side impact collision warnings. For example, the surround view camera 874 (e.g., a side view camera) Figure 8B The four surround view cameras 874 shown in FIG. 8 may be placed around the vehicle 800. The surround view cameras 874 may include a wide angle camera 870, a fisheye camera, a 360 degree camera, and / or the like. For example, the four fisheye cameras may be placed in front, behind, and on the sides of the vehicle. In an alternative arrangement, the vehicle may use three surround view cameras 874 (e.g., left, right, and rear), and may utilize one or more other cameras (e.g., a forward facing camera) as a fourth surround view camera.

[0080] A camera having a field of view that includes a portion of the environment behind the vehicle 800 (e.g., a rear view camera) can be used to assist with parking, surround view, rear collision warning, and creating and updating occupancy grids. A variety of cameras can be used, including but not limited to cameras that are also suitable as front cameras as described herein (e.g., long-range and / or mid-range cameras 898, stereo cameras 868, infrared cameras 872, etc.).

[0081] Figure 8C According to some embodiments of the present disclosure Fig. 8ABlock diagram of an example system architecture of an example autonomous driving vehicle 800. It should be understood that this arrangement and other arrangements described herein are presented as examples only. In addition to the arrangements and elements shown, other arrangements and elements (e.g., machines, interfaces, functions, sequences, functional groupings, etc.) may also be used, and some elements may be omitted entirely. In addition, many of the elements described herein are functional entities that may be implemented as discrete or distributed components or in combination with other components, and may be implemented in any suitable combination and location. The various functions performed by the entities described herein may be performed by hardware, firmware, and / or software. For example, the various functions may be performed by a processor executing instructions stored in a memory.

[0082] Figure 8C Each component, feature, and system of the vehicle 800 is connected via a bus 802. The bus 802 may include a controller area network (CAN) data interface (also referred to herein as a "CAN bus"). The CAN may be a network inside the vehicle 800 that assists in controlling various features and functions of the vehicle 800, such as the actuation of brakes, acceleration, braking, steering, windshield wipers, and the like. The CAN bus may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., CAN ID). The CAN bus may be read to find steering wheel angle, ground speed, engine revolutions per minute (RPM), button position, and / or other vehicle status indications. The CAN bus may be ASILB compliant.

[0083] Although bus 802 is described as a CAN bus herein, this is not restrictive. For example, in addition to or as a substitute for the CAN bus, FlexRay and / or Ethernet can be used. In addition, although a single line is used to represent bus 802, this is not restrictive. For example, there can be any number of buses 802, which may include one or more CAN buses, one or more FlexRay buses, one or more Ethernet buses, and / or one or more other types of buses using different protocols. In some examples, two or more buses 802 can be used to perform different functions, and / or can be used for redundancy. For example, a first bus 802 can be used for collision avoidance functions, and a second bus 802 can be used for drive control. In any example, each bus 802 can communicate with any component of the vehicle 800, and two or more buses 802 can communicate with the same component. In some examples, each SoC 804, each controller 836, and / or each computer in the vehicle can access the same input data (e.g., input from sensors of the vehicle 800), and can be connected to a common bus such as a CAN bus.

[0084] The vehicle 800 may include one or more controllers 836, such as those described herein. Fig. 8A Controller 836 may be used for various functions. Controller 836 may be coupled to any of the various other components and systems of vehicle 800 and may be used to control vehicle 800, artificial intelligence of vehicle 800, infotainment of vehicle 800, etc.

[0085] The vehicle 800 may include one or more system on chip (SoC) 804. The SoC 804 may include a CPU 806, a GPU 808, a processor 810, a cache 812, an accelerator 814, a data store 816, and / or other components and features not shown. The SoC 804 may be used to control the vehicle 800 in a variety of platforms and systems. For example, one or more SoCs 804 may be combined with an HD map 822 in a system (e.g., a system of the vehicle 800), which map 822 may be obtained from one or more servers (e.g., Fig.8D Server 878) obtains map refreshes and / or updates.

[0086] The CPU 806 may include a CPU cluster or CPU complex (also referred to herein as a "CCPLEX"). The CPU 806 may include multiple cores and / or multiple L2 caches. For example, in some embodiments, the CPU 806 may include eight cores in a coherent multiprocessor configuration. In some embodiments, the CPU 806 may include four dual-core clusters, each with a dedicated L2 cache (e.g., a 2MB L2 cache). The CPU 806 (e.g., CCPLEX) may be configured to support simultaneous cluster operations, so that any combination of the CPU 806 clusters are active at any given time.

[0087] CPU 806 may implement power management functionality, including one or more of the following features: individual hardware blocks may be automatically clock gated when idle to save dynamic power; each core clock may be gated when the core is not actively executing instructions due to the execution of WFI / WFE instructions; each core may be independently power gated; each core cluster may be independently clock gated when all cores are clock gated or power gated; and / or each core cluster may be independently power gated when all cores are power gated. CPU 806 may further implement an enhanced algorithm for managing power states, which specifies the allowed power states and expected wakeup times, and the optimal power state to enter the core, cluster, and CCPLEX is determined by hardware / microcode. The processing core may support a simplified software power state entry sequence and offload work to microcode.

[0088] The GPU 808 may include an integrated GPU (also referred to herein as an "iGPU"). The GPU 808 may be programmable and may efficiently process parallel workloads. In some examples, the GPU 808 may use an enhanced tensor instruction set. The GPU 808 may include one or more streaming microprocessors, each of which may include an L1 cache (e.g., an L1 cache with at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512KB of storage capacity). In some embodiments, the GPU 808 may include at least eight streaming microprocessors. The GPU 808 may use a computer-based application programming interface (API). In addition, the GPU 808 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA).

[0089] In the case of automotive and embedded use, GPU 808 can be power optimized for optimal performance. For example, GPU 808 can be manufactured on Fin field-effect transistors (FinFET). However, this is not restrictive, and GPU 808 can be manufactured using other semiconductor manufacturing processes. Each streaming microprocessor can merge several mixed precision processing cores divided into multiple blocks. For example, non-limitingly, 64 PF32 cores and 32 PF64 cores can be divided into four processing blocks. In such an example, each processing block can be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed precision NVIDIA tensor cores (NVIDIATENSOR CORE) for deep learning matrix arithmetic, L0 instruction cache, warp scheduler, dispatch unit and / or 64KB register file. In addition, the streaming microprocessor may include independent parallel integer and floating point data paths to provide efficient execution of workloads using a mix of computation and addressing computations. The streaming microprocessor may include independent thread scheduling capabilities to allow for finer-grained synchronization and cooperation between parallel threads. The streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0090] GPU 808 may include high bandwidth memory (HBM) and / or a 16GB HBM2 memory subsystem that provides a peak memory bandwidth of approximately 900 GB / s in some examples. In some examples, synchronous graphics random-access memory (SGRAM), such as fifth generation graphics double data rate synchronous random-access memory (GDDR5), may be used in addition to or in lieu of HBM memory.

[0091] The GPU 808 may include unified memory technology that includes access counters to allow memory pages to be more accurately migrated to the processor that accesses them most frequently, thereby improving the efficiency of memory ranges shared between processors. In some examples, address translation service (ATS) support may be used to allow the GPU 808 to directly access the CPU 806 page table. In such an example, when the GPU 808 memory management unit (MMU) experiences a miss, an address translation request may be transmitted to the CPU 806. In response, the CPU 806 may look up the virtual-physical mapping for the address in its page table and transmit the translation back to the GPU 808. In this way, unified memory technology may allow a single unified virtual address space to be used for memory of both the CPU 806 and the GPU 808, thereby simplifying GPU 808 programming and porting applications to the GPU 808.

[0092] In addition, GPU 808 may include access counters that can track how often GPU 808 accesses the memory of other processors. Access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses them most frequently.

[0093] SoC 804 may include any number of caches 812, including those described herein. For example, cache 812 may include an L3 cache available to both CPU 806 and GPU 808 (e.g., connected to both CPU 806 and GPU 808). Cache 812 may include a write-back cache that may track the state of a line, for example, by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). Depending on the embodiment, the L3 cache may include 4MB or more, although smaller cache sizes may also be used.

[0094] The SoC 804 may include an arithmetic logic unit (ALU) that may be utilized in performing any of a variety of tasks or operations with respect to the vehicle 800, such as processing a DNN. Additionally, the SoC 804 may include a floating point unit (FPU) (or other math coprocessor or digital coprocessor type) for performing mathematical operations within the system. For example, the SoC 104 may include one or more FPUs integrated as execution units within the CPU 806 and / or GPU 808.

[0095] SoC 804 may include one or more accelerators 814 (e.g., hardware accelerators, software accelerators, or a combination thereof). For example, SoC 804 may include a hardware accelerator cluster, which may include optimized hardware accelerators and / or large on-chip memory. The large on-chip memory (e.g., 4MB SRAM) may enable the hardware accelerator cluster to accelerate neural networks and other calculations. The hardware accelerator cluster may be used to supplement GPU 808 and offload some tasks of GPU 808 (e.g., free up more cycles of GPU 808 for performing other tasks). As an example, accelerator 814 may be used for targeted workloads (e.g., perception, convolutional neural networks (CNNs), etc.) that are sufficiently stable to be easily controlled for acceleration. When used herein, the term "CNN" may include all types of CNNs, including region-based or regional convolutional neural networks (RCNNs) and fast RCNNs (e.g., for object detection).

[0096] Accelerator 814 (e.g., a hardware accelerator cluster) may include a deep learning accelerator (DLA). DLA may include one or more tensor processing units (TPUs) that may be configured to provide an additional 10 trillion operations per second for deep learning applications and reasoning. TPU may be an accelerator configured to perform image processing functions (e.g., for CNN, RCNN, etc.) and optimized for performing image processing functions. DLA may be further optimized for a specific set of neural network types and floating point operations and reasoning. The design of DLA may provide higher performance per millimeter than a general-purpose GPU, and far exceeds the performance of a CPU. TPU may perform several functions, including a single instance convolution function, support, for example, INT8, INT16, and FP16 data types for both features and weights, and post-processor functions.

[0097] The DLA can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a wide variety of functions, such as, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection and identification and detection using data from a microphone; a CNN for facial recognition and vehicle owner identification using data from a camera sensor; and / or a CNN for safety and / or security-related events.

[0098] The DLA can perform any function of the GPU 808, and by using an inference accelerator, for example, the designer can target any function to either the DLA or the GPU 808. For example, the designer can focus the processing of CNNs and floating point operations on the DLA, and leave other functions to the GPU 808 and / or other accelerators 814.

[0099] The accelerator 814 (e.g., a hardware accelerator cluster) may include a programmable vision accelerator (PVA), which may be alternatively referred to as a computer vision accelerator herein. The PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (ADAS), autonomous driving, and / or augmented reality (AR) and / or virtual reality (VR) applications. The PVA may provide a balance between performance and flexibility. For example, each PVA may include, for example and without limitation, any number of reduced instruction set computer (RISC) cores, direct memory access (DMA), and / or any number of vector processors.

[0100] The RISC core can interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, and / or the like. Each of these RISC cores can include any amount of memory. Depending on the embodiment, the RISC core can use any of a number of protocols. In some examples, the RISC core can execute a real-time operating system (RTOS). The RISC core can be implemented using one or more integrated circuit devices, application specific integrated circuits (ASICs), and / or storage devices. For example, the RISC core can include an instruction cache and / or a tightly coupled RAM.

[0101] The DMA may enable components of the PVA to access system memory independently of the CPU 806. The DMA may support any number of features used to provide optimizations for the PVA, including, but not limited to, support for multi-dimensional addressing and / or circular addressing. In some examples, the DMA may support addressing in up to six or more dimensions, which may include block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0102] A vector processor may be a programmable processor that may be designed to efficiently and flexibly perform programming for computer vision algorithms and provide signal processing capabilities. In some examples, a PVA may include a PVA core and two vector processing subsystem partitions. The PVA core may include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. The vector processing subsystem may operate as the main processing engine of the PVA and may include a vector processing unit (VPU), an instruction cache, and / or a vector memory (e.g., VMEM). The VPU core may include a digital signal processor, such as, for example, a single instruction multiple data (SIMD), a very long instruction word (VLIW) digital signal processor. The combination of SIMD and VLIW may enhance throughput and rate.

[0103] Each of the vector processors may include an instruction cache and may be coupled to a dedicated memory. As a result, in some examples, each of the vector processors may be configured to execute independently of the other vector processors. In other examples, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in some embodiments, multiple vector processors included in a single PVA may execute the same computer vision algorithm, but on different regions of an image. In other examples, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on the same image, or even execute different algorithms on a sequence of images or portions of an image. Among other things, any number of PVAs may be included in a hardware accelerator cluster, and any number of vector processors may be included in each of these PVAs. In addition, the PVA may include additional error correction code (ECC) memory to enhance overall system security.

[0104] The accelerator 814 (e.g., a hardware accelerator cluster) may include an on-chip computer vision network and SRAM to provide high bandwidth, low latency SRAM for the accelerator 814. In some examples, the on-chip memory may include at least 4MB of SRAM consisting of, for example and not limited to, eight field-configurable memory blocks, which may be accessed by both the PVA and the DLA. Each pair of memory blocks may include an Advanced Peripheral Bus (APB) interface, a configuration circuit system, a controller, and a multiplexer. Any type of memory may be used. The PVA and DLA may access the memory via a backbone that provides high-speed memory access to the PVA and DLA. The backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using APB).

[0105] The on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. Such an interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst communication for continuous data transmission. This type of interface may comply with ISO 26262 or IEC 61508 standards, but other standards and protocols may also be used.

[0106] In some examples, SoC 804 may include a real-time ray tracing hardware accelerator such as described in U.S. Patent Application No. 16 / 101,232 filed on August 10, 2018. The real-time ray tracing hardware accelerator may be used to quickly and efficiently determine the position and range of objects (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for SONAR system simulations, for general wave propagation simulations, for comparison with LIDAR data for the purpose of positioning and / or other functions, and / or for other purposes. In some embodiments, one or more Tree Traversal Units (TTUs) may be used to perform one or more ray tracing related operations.

[0107] The accelerator 814 (e.g., a hardware accelerator cluster) has a wide range of uses in autonomous driving. The PVA can be a programmable visual accelerator that can be used in key processing stages in ADAS and autonomous vehicles. The capabilities of the PVA are a good match for algorithmic domains that require predictable processing, low power, and low latency. In other words, the PVA performs well on semi-dense or dense rule computations, and even on small data sets that require predictable runtimes with low latency and low power. Therefore, in the context of a platform for autonomous vehicles, the PVA is designed to run classic computer vision algorithms because they are efficient at object detection and integer math.

[0108] For example, according to one embodiment of the technology, PVA is used to perform computer stereo vision. In some examples, algorithms based on semi-global matching can be used, but this is not intended to be limiting. Many applications for Level 3-5 autonomous driving require real-time motion estimation / stereo matching (e.g., structure from motion, pedestrian recognition, lane detection, etc.). PVA can perform computer stereo vision functions on input from two monocular cameras.

[0109] In some examples, PVA can be used to perform dense optical flow. For example, PVA can be used to process raw RADAR data (e.g., using a 4D fast Fourier transform) to provide a processed RADAR signal before transmitting the next RADAR pulse. In other examples, PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0110] DLAc can be used to run any type of network to enhance control and driving safety, including, for example, a neural network that outputs a confidence measure for each object detection. Such a confidence value can be interpreted as a probability, or as providing a relative "weight" of each detection compared to other detections. This confidence value enables the system to make further decisions about which detections should be considered true positive detections rather than false positive detections. For example, the system can set a threshold for confidence and only consider detections that exceed the threshold as true positive detections. In an Automatic Emergency Braking (AEB) system, a false positive detection will cause the vehicle to automatically perform emergency braking, which is obviously undesirable. Therefore, only the most confident detections should be considered triggers for AEB. DLA can run a neural network for regressing confidence values. The neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), an inertial measurement unit (IMU) sensor 866 output related to the orientation and distance of the vehicle 800, a 3D position estimate of an object obtained from a neural network and / or other sensors (e.g., a LIDAR sensor 864 or a RADAR sensor 860), etc.

[0111] SoC 804 may include one or more data stores 816 (e.g., memory). Data store 816 may be on-chip memory of SoC 804 that may store neural networks to be executed on the GPU and / or DLA. In some examples, data store 816 may be large enough to store multiple instances of the neural network for redundancy and safety. Data store 816 may include L2 or L3 cache 812. References to data store 816 may include references to memory associated with PVA, DLA, and / or other accelerators 814 as described herein.

[0112] SoC 804 may include one or more processors 810 (e.g., embedded processors). Processor 810 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and related safety implementations. The boot and power management processor may be part of the SoC 804 boot sequence and may provide runtime power management services. The boot power and management processor may provide clock and voltage programming, auxiliary system low power state transitions, SoC 804 thermal and temperature sensor management, and / or SoC 804 power state management. Each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to the temperature, and SoC 804 may use the ring oscillator to detect the temperature of CPU 806, GPU 808, and / or accelerator 814. If it is determined that the temperature exceeds a threshold, the boot and power management processor may enter a temperature fault routine and place SoC 804 in a lower power state and / or place the vehicle 800 in a driver safety parking mode (e.g., parking the vehicle 800 safely).

[0113] The processor 810 may also include a set of embedded processors that can be used as an audio processing engine. The audio processing engine can be an audio subsystem that allows full hardware support for multi-channel audio through multiple interfaces and a wide range of flexible audio I / O interfaces. In some examples, the audio processing engine is a dedicated processor core having a digital signal processor with dedicated RAM.

[0114] The processor 810 may also include an always-on processor engine that may provide the necessary hardware features to support low-power sensor management and wake-up use cases. The always-on processor engine may include a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0115] The processor 810 may also include a safety cluster engine, which includes a dedicated processor subsystem that handles safety management of automotive applications. The safety cluster engine may include two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In safety mode, the two or more cores may operate in lockstep mode and act as a single core with comparison logic to detect any differences between their operations.

[0116] Processor 810 may also include a real-time camera engine, which may include a dedicated processor subsystem for handling real-time camera management.

[0117] Processor 810 may also include a high dynamic range signal processor, which may include an image signal processor, which is a hardware engine that is part of a camera processing pipeline.

[0118] The processor 810 may include a video image compositer, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required for the video playback application to produce a final image for the player window. The video image compositer may perform lens distortion correction for the wide-angle camera 870, the surround view camera 874, and / or for an in-cab surveillance camera sensor. The in-cab surveillance camera sensor is preferably monitored by a neural network running on another instance of the advanced SoC, configured to recognize in-cab events and respond accordingly. The in-cab system may perform lip reading to activate mobile phone service and place a call, dictate an email, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. Certain functions are only available to the driver when the vehicle is operating in autonomous mode and are disabled in other circumstances.

[0119] The video image compositer may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in the case of motion in the video, the noise reduction appropriately weights the spatial information and reduces the weight of information provided by adjacent frames. In the case where an image or portion of an image does not include motion, the temporal noise reduction performed by the video image compositer may use information from previous images to reduce noise in the current image.

[0120] The video image compositor may also be configured to perform stereoscopic rectification on the input stereoscopic footage frames. The video image compositor may further be used for user interface composition when the operating system desktop is in use and the GPU 808 does not need to continuously render new surfaces. Even when the GPU 808 is powered on and is actively performing 3D rendering, the video image compositor may be used to offload the GPU 808 to improve performance and responsiveness.

[0121] SoC 804 may also include a Mobile Industry Processor Interface (MIPI) camera serial interface for receiving video and input from a camera, a high-speed interface, and / or a video input block that may be used for camera and related pixel input functions. SoC 804 may also include an input / output controller that may be controlled by software and may be used to receive I / O signals that are not committed to a specific role.

[0122] SoC 804 may also include a wide range of peripheral interfaces to enable communication with peripherals, audio codecs, power management and / or other devices. SoC 804 may be used to process data from cameras (connected via Gigabit multimedia serial links and Ethernet), sensors (e.g., LIDAR sensor 864, RADAR sensor 860, etc., which may be connected via Ethernet), data from bus 802 (e.g., speed of vehicle 800, steering wheel position, etc.), data from GNSS sensor 858 (connected via Ethernet or CAN bus). SoC 804 may also include dedicated high-performance mass storage controllers, which may include their own DMA engines, and which may be used to free up CPU 806 from routine data management tasks.

[0123] SoC 804 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that utilizes and efficiently uses computer vision and ADAS technologies to achieve diversity and redundancy, together with deep learning tools to provide a platform for a flexible and reliable driving software stack. SoC 804 can be faster, more reliable, and even more energy efficient and space efficient than conventional systems. For example, when combined with CPU 806, GPU 808, and data storage 816, accelerator 814 can provide a fast and efficient platform for level 3-5 autonomous driving vehicles.

[0124] The technology thus provides capabilities and functionality that cannot be achieved by conventional systems. For example, computer vision algorithms can be executed on CPUs, which can be configured using high-level programming languages ​​such as the C programming language to execute a wide variety of processing algorithms across a wide variety of visual data. However, CPUs often fail to meet the performance requirements of many computer vision applications, such as those related to, for example, execution time and power consumption. In particular, many CPUs are unable to execute complex object detection algorithms in real time, which is a requirement for in-vehicle ADAS applications and for practical Level 3-5 autonomous driving vehicles.

[0125] Compared to conventional systems, by providing a CPU complex, a GPU complex, and a cluster of hardware accelerators, the techniques described herein allow multiple neural networks to be executed simultaneously and / or sequentially, and the results to be combined together to achieve Level 3-5 autonomous driving functions. For example, a CNN executed on a DLA or dGPU (e.g., GPU820) may include text and word recognition, allowing the supercomputer to read and understand traffic signs, including signs for which a neural network has not been specifically trained. The DLA may also include a neural network that can recognize, interpret, and provide semantic understanding of the signs, and pass that semantic understanding to a path planning module running on the CPU complex.

[0126] As another example, as required for Level 3, 4, or 5 driving, multiple neural networks may be running simultaneously. For example, a warning sign consisting of "Caution: Flashing Lights Indicate Icing Conditions" along with electric lights may be interpreted by several neural networks independently or collectively. The sign itself may be recognized as a traffic sign by a deployed first neural network (e.g., a trained neural network), and the text "Flashing Lights Indicate Icing Conditions" may be interpreted by a deployed second neural network that informs the vehicle's path planning software (preferably executing on a CPU complex) that icing conditions exist when the flashing lights are detected. The flashing lights may be identified by operating a deployed third neural network over multiple frames that informs the vehicle's path planning software of the presence (or absence) of the flashing lights. All three neural networks may be running simultaneously, for example, within the DLA and / or on the GPU 808.

[0127] In some examples, a CNN for facial recognition and owner recognition can use data from a camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 800. An always-on sensor processing engine can be used to unlock the vehicle and turn on the lights when the owner approaches the driver's door, and in security mode, disable the vehicle when the owner leaves the vehicle. In this way, the SoC 804 provides security against theft and / or carjacking.

[0128] In another example, a CNN for emergency vehicle detection and identification can use data from microphone 896 to detect and identify emergency vehicle sirens. In contrast to conventional systems that use general classifiers to detect sirens and manually extract features, SoC 804 uses CNN to classify environmental and urban sounds and to classify visual data. In a preferred embodiment, the CNN running on the DLA is trained to identify the relative closing rate of emergency vehicles (e.g., by using the Doppler effect). The CNN can also be trained to identify emergency vehicles specific to the local area in which the vehicle is operating, as identified by the GNSS sensor 858. Thus, for example, when operating in Europe, the CNN will seek to detect European sirens, and when in the United States, the CNN will seek to identify only North American sirens. Once an emergency vehicle is detected, with the assistance of the ultrasonic sensor 862, the control program can be used to execute emergency vehicle safety routines to slow the vehicle, drive to the side of the road, stop the vehicle, and / or idle the vehicle until the emergency vehicle passes.

[0129] The vehicle may include a CPU 818 (e.g., a discrete CPU or dCPU) that may be coupled to the SoC 804 via a high-speed interconnect (e.g., PCIe). The CPU 818 may include, for example, an X86 processor. The CPU 818 may be used to perform any of a variety of functions, including, for example, arbitrating potentially inconsistent results between ADAS sensors and the SoC 804, and / or monitoring the status and health of the controller 836 and / or the infotainment SoC 830.

[0130] The vehicle 800 may include a GPU 820 (e.g., a discrete GPU or dGPU) that may be coupled to the SoC 804 via a high-speed interconnect (e.g., NVIDIA's NVLINK). The GPU 820 may provide additional artificial intelligence functionality, for example, by executing redundant and / or different neural networks, and may be used to train and / or update the neural network based at least in part on input from sensors of the vehicle 800 (e.g., sensor data).

[0131] The vehicle 800 may also include a network interface 824, which may include one or more wireless antennas 826 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). The network interface 824 can be used to enable wireless connections with the cloud (e.g., with a server 878 and / or other network devices), with other vehicles, and / or with computing devices (e.g., a passenger's client device) via the Internet. In order to communicate with other vehicles, a direct link can be established between the two vehicles, and / or an indirect link can be established (e.g., across a network and through the Internet). The direct link can be provided using a vehicle-to-vehicle communication link. The vehicle-to-vehicle communication link can provide the vehicle 800 with information about vehicles approaching the vehicle 800 (e.g., vehicles in front of, to the side of, and / or behind the vehicle 800). This functionality can be part of the collaborative adaptive cruise control functionality of the vehicle 800.

[0132] The network interface 824 may include a SoC that provides modulation and demodulation functions and enables the controller 836 to communicate over a wireless network. The network interface 824 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. The frequency conversion may be performed by a known process and / or may be performed using a super-heterodyne process. In some examples, the radio frequency front end function may be provided by a separate chip. The network interface may include a wireless function for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0133] The vehicle 800 may also include data storage 828, which may include off-chip storage (e.g., outside the SoC 804). The data storage 828 may include one or more storage elements, including RAM, SRAM, DRAM, VRAM, flash memory, hard disk, and / or other components and / or devices that can store at least one bit of data.

[0134] The vehicle 800 may also include a GNSS sensor 858 (e.g., GPS and / or assisted GPS sensor) for assisting mapping, perception, occupancy grid generation, and / or path planning functions. Any number of GNSS sensors 858 may be used, including, for example and without limitation, GPS using a USB connector with an Ethernet to serial (RS-232) bridge.

[0135] The vehicle 800 may also include a RADAR sensor 860. The RADAR sensor 860 may be used by the vehicle 800 for remote vehicle detection even in darkness and / or inclement weather conditions. The RADAR functional safety level may be ASIL B. The RADAR sensor 860 may use CAN and / or bus 802 (e.g., to transmit data generated by the RADAR sensor 860) for control and access to object tracking data, accessing Ethernet in some examples to access raw data. A variety of RADAR sensor types may be used. For example and without limitation, the RADAR sensor 860 may be suitable for front, rear, and side RADAR use. In some examples, a pulse Doppler RADAR sensor is used.

[0136] The RADAR sensor 860 may include different configurations, such as long-range with narrow field of view, short-range with wide field of view, short-range side coverage, and the like. In some examples, the long-range RADAR may be used for adaptive cruise control functions. The long-range RADAR system may provide a wide field of view (e.g., within 250m) achieved by two or more independent scans. The RADAR sensor 860 may help distinguish between static objects and moving objects, and may be used by the ADAS system for emergency braking assistance and forward collision warnings. The long-range RADAR sensor may include a single-station multimode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In an example with six antennas, the central four antennas may create a focused beam pattern designed to record the surroundings of the vehicle 800 at a higher rate with minimal traffic interference from adjacent lanes. The other two antennas may expand the field of view, making it possible to quickly detect vehicles entering or leaving the lane of the vehicle 800.

[0137] As an example, a medium-range RADAR system may include a range of up to 860m (front) or 80m (rear) and a field of view of up to 42 degrees (front) or 850 degrees (rear). A short-range RADAR system may include, but is not limited to, a RADAR sensor designed to be mounted on both ends of a rear bumper. When mounted on both ends of a rear bumper, such a RADAR sensor system may create two beams that continuously monitor the blind spots behind and beside the vehicle.

[0138] Short-range RADAR systems can be used in ADAS systems for blind spot detection and / or lane change assistance.

[0139] The vehicle 800 may also include ultrasonic sensors 862. Ultrasonic sensors 862, which may be placed on the front, rear, and / or sides of the vehicle 800, may be used for parking assistance and / or creating and updating occupancy grids. A variety of ultrasonic sensors 862 may be used, and different ultrasonic sensors 862 may be used for different detection ranges (e.g., 2.5 m, 4 m). The ultrasonic sensors 862 may operate at functional safety level ASIL B.

[0140] The vehicle 800 may include a LIDAR sensor 864. The LIDAR sensor 864 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. The LIDAR sensor 864 may be ASIL B for functional safety level. In some examples, the vehicle 800 may include multiple LIDAR sensors 864 (e.g., two, four, six, etc.) that may use Ethernet (e.g., to provide data to a Gigabit Ethernet switch).

[0141] In some examples, the LIDAR sensor 864 may be able to provide a list of objects and their distances for a 360-degree field of view. Commercially available LIDAR sensors 864 may have, for example, an advertised range of approximately 100m, an accuracy of 2cm-3cm, and support for 100Mbps Ethernet connections. In some examples, one or more non-protruding LIDAR sensors 864 may be used. In such examples, the LIDAR sensor 864 may be implemented as a small device that can be embedded in the front, back, side, and / or corner of the vehicle 800. In such examples, the LIDAR sensor 864 may provide a field of view of up to 120 degrees horizontally and 35 degrees vertically, with a range of 200m, even for low reflectivity objects. The front-mounted LIDAR sensor 864 may be configured for a horizontal field of view between 45 and 135 degrees.

[0142] In some examples, LIDAR technologies such as 3D flash LIDAR may also be used. 3D flash LIDAR uses a flash of laser as an emission source to illuminate the vehicle's surroundings up to about 200m. The flash LIDAR unit includes a receiver that records the laser pulse transmission time and the reflected light on each pixel, which in turn corresponds to the range from the vehicle to the object. Flash LIDAR can allow highly accurate and distortion-free images of the surrounding environment to be generated with each laser flash. In some examples, four flash LIDAR sensors can be deployed, one on each side of the vehicle 800. Available 3D flash LIDAR systems include solid-state 3D staring array LIDAR cameras (e.g., non-scanning LIDAR devices) with no moving parts other than fans. The flash LIDAR device can use 5 nanosecond Class I (eye-safe) laser pulses per frame, and can capture the reflected laser light in the form of a 3D range point cloud and co-registered intensity data. By using flash LIDAR, and because flash LIDAR is a solid-state device with no moving parts, the LIDAR sensor 864 may be less susceptible to motion blur, vibration, and / or shock.

[0143] The vehicle may also include an IMU sensor 866. In some examples, the IMU sensor 866 may be located at the center of the rear axle of the vehicle 800. The IMU sensor 866 may include, for example and without limitation, an accelerometer, a magnetometer, a gyroscope, a magnetic compass, and / or other sensor types. In some examples, for example, in a six-axis application, the IMU sensor 866 may include an accelerometer and a gyroscope, while in a nine-axis application, the IMU sensor 866 may include an accelerometer, a gyroscope, and a magnetometer.

[0144] In some embodiments, the IMU sensor 866 can be implemented as a miniature high-performance GPS-Aided Inertial Navigation System (GPS / INS) that combines a micro-electro-mechanical system (MEMS) inertial sensor, a high-sensitivity GPS receiver, and an advanced Kalman filter algorithm to provide estimates of position, velocity, and attitude. Thus, in some examples, the IMU sensor 866 can enable the vehicle 800 to estimate the direction (heading) by directly observing and correlating velocity changes from the GPS to the IMU sensor 866 without the need for input from a magnetic sensor. In some examples, the IMU sensor 866 and the GNSS sensor 858 can be combined into a single integrated unit.

[0145] The vehicle may include microphones 896 positioned in and / or around the vehicle 800. The microphones 896 may be used for, among other things, emergency vehicle detection and identification.

[0146] The vehicle may also include any number of camera types, including a stereo camera 868, a wide-angle camera 870, an infrared camera 872, a surround view camera 874, a long-range and / or mid-range camera 898, and / or other camera types. These cameras can be used to capture image data around the entire periphery of the vehicle 800. The type of camera used depends on the embodiment and the requirements of the vehicle 800, and any combination of camera types can be used to provide the necessary coverage around the vehicle 800. In addition, the number of cameras may vary depending on the embodiment. For example, the vehicle may include six cameras, seven cameras, ten cameras, twelve cameras, and / or another number of cameras. As an example and not limitation, the cameras may support Gigabit Multimedia Serial Link (GMSL) and / or Gigabit Ethernet. Each of the cameras described herein is described herein with respect to Fig. 8A and Figure 8B Described in more detail.

[0147] The vehicle 800 may also include a vibration sensor 842. The vibration sensor 842 may measure vibrations of components of the vehicle, such as axles. For example, changes in vibration may indicate changes in the road surface. In another example, when two or more vibration sensors 842 are used, the difference between the vibrations may be used to determine friction or slip of the road surface (e.g., when there is a vibration difference between a powered drive shaft and a freely rotating shaft).

[0148] The vehicle 800 may include an ADAS system 838. In some examples, the ADAS system 838 may include a SoC. The ADAS system 838 may include autonomous / adaptive / automatic cruise control (ACC), cooperative adaptive cruise control (CACC), forward collision warning (FCW), automatic emergency braking (AEB), lane departure warning (LDW), lane keeping assist (Lane Keep Assist, LKA), blind spot warning (BSW), rear cross-traffic warning (RCTW), collision warning system (CWS), lane centering (LC), and / or other features and functions.

[0149] The ACC system may use a RADAR sensor 860, a LIDAR sensor 864, and / or a camera. The ACC system may include a longitudinal ACC and / or a lateral ACC. The longitudinal ACC monitors and controls the distance to the vehicle immediately in front of the vehicle 800, and automatically adjusts the vehicle speed to maintain a safe distance from the vehicle in front. The lateral ACC performs distance keeping and suggests that the vehicle 800 change lanes when necessary. The lateral ACC is related to other ADAS applications such as LC and CWS.

[0150] CACC uses information from other vehicles, which can be received from other vehicles indirectly via a wireless link or through a network connection (e.g., through the Internet) via a network interface 824 and / or a wireless antenna 826. A direct link can be provided by a vehicle-to-vehicle (V2V) communication link, while an indirect link can be an infrastructure-to-vehicle (I2V) communication link. Typically, the V2V communication concept provides information about the vehicle immediately ahead (e.g., the vehicle immediately ahead of the vehicle 800 and in the same lane as it), while the I2V communication concept provides information about traffic farther ahead. The CACC system may include either or both of the I2V and V2V information sources. Given information about the vehicle ahead of the vehicle 800, CACC can be more reliable, and it is possible to improve the smoothness of traffic flow and reduce road congestion.

[0151] The FCW system is designed to alert the driver to hazards so that the driver can take corrective action. The FCW system uses a front camera and / or RADAR sensor 860 coupled to a dedicated processor, DSP, FPGA and / or ASIC, which is electrically coupled to driver feedback such as a display, speaker and / or vibrating components. The FCW system can provide warnings in the form of, for example, sound, visual warnings, vibrations and / or rapid brake pulses.

[0152] The AEB system detects an impending front collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. The AEB system can use a front camera and / or RADAR sensor 860 coupled to a dedicated processor, DSP, FPGA and / or ASIC. When the AEB system detects a hazard, it typically first alerts the driver to take corrective action to avoid the collision, and if the driver does not take corrective action, the AEB system can automatically apply the brakes in an effort to prevent or at least mitigate the effects of the predicted collision. The AEB system may include technologies such as dynamic brake support and / or collision approach braking.

[0153] The LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle 800 crosses a lane marking. When the driver indicates an intention to leave the lane, by activating a turn signal, the LDW system is not activated. The LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to driver feedback such as a display, speaker, and / or vibrating component.

[0154] The LKA system is a variation of the LDW system. If the vehicle 800 begins to leave the lane, the LKA system provides steering input or braking to correct the vehicle 800.

[0155] The BSW system detects and warns the driver of vehicles in the car's blind spot. The BSW system can provide visual, auditory and / or tactile alerts to indicate that it is unsafe to merge or change lanes. The system can provide additional warnings when the driver uses a turn signal. The BSW system can use a rear-facing camera and / or RADAR sensor 860 coupled to a dedicated processor, DSP, FPGA and / or ASIC, which is electrically coupled to driver feedback such as a display, speaker and / or vibration components.

[0156] The RCTW system may provide visual, audible, and / or tactile notifications when an object is detected outside the range of the rear camera while the vehicle 800 is in reverse. Some RCTW systems include AEB to ensure that the vehicle brakes are applied to avoid a crash. The RCTW system may use one or more rear RADAR sensors 860 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to driver feedback such as a display, speaker, and / or vibrating component.

[0157] Conventional ADAS systems may be prone to false positive results, which may annoy and distract the driver, but are typically not catastrophic because the ADAS system alerts the driver and allows the driver to decide whether the safety condition really exists and take action accordingly. However, in the autonomous vehicle 800, in the case of conflicting results, the vehicle 800 itself must decide whether to pay attention to the results from the main computer or the auxiliary computer (e.g., the first controller 836 or the second controller 836). For example, in some embodiments, the ADAS system 838 can be a backup and / or auxiliary computer for providing perception information to the backup computer rationality module. The backup computer rationality monitor can run redundant and diverse software on hardware components to detect faults in perception and dynamic driving tasks. The output from the ADAS system 838 can be provided to the supervisory MCU. If the outputs from the main computer and the auxiliary computer conflict, the supervisory MCU must determine how to coordinate the conflict to ensure safe operation.

[0158] In some examples, the master computer can be configured to provide a confidence score to the supervisory MCU, indicating the master computer's confidence in the selected result. If the confidence score exceeds a threshold, the supervisory MCU can follow the direction of the master computer, regardless of whether the auxiliary computer provides conflicting or inconsistent results. In the case where the confidence score does not meet the threshold and the master computer and the auxiliary computer indicate different results (e.g., conflicts), the supervisory MCU can arbitrate between these computers to determine the appropriate result.

[0159] The supervisory MCU can be configured to run a neural network that is trained and configured to determine conditions under which the auxiliary computer provides a false alarm based at least in part on outputs from the primary computer and the auxiliary computer. Thus, the neural network in the supervisory MCU can learn when the output of the auxiliary computer can be trusted and when it cannot. For example, when the auxiliary computer is a RADAR-based FCW system, the neural network in the supervisory MCU can learn when the FCW system is identifying a metal object that is not actually dangerous, such as a drainage grid or manhole cover that triggers an alarm. Similarly, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to ignore the LDW when a cyclist or pedestrian is present and lane departure is actually the safest strategy. In an embodiment that includes a neural network running on the supervisory MCU, the supervisory MCU may include at least one of a DLA or GPU suitable for running the neural network with associated memory. In a preferred embodiment, the supervisory MCU may include a component of SoC 804 and / or be included as a component of SoC 804.

[0160] In other examples, the ADAS system 838 may include an auxiliary computer that uses traditional computer vision rules to perform ADAS functions. In this way, the auxiliary computer can use classic computer vision rules (if-then), and the presence of a neural network in the supervisory MCU can improve reliability, safety, and performance. For example, diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functions. For example, if there is a software vulnerability or error in the software running on the main computer and the non-identical software code running on the auxiliary computer provides the same overall result, the supervisory MCU can be more confident that the overall result is correct and that the vulnerability in the software or hardware used by the main computer does not cause a substantial error.

[0161] In some examples, the output of the ADAS system 838 can be fed to the perception block of the main computer and / or the dynamic driving task block of the main computer. For example, if the ADAS system 838 indicates a forward collision warning due to an object immediately ahead, the perception block can use this information in identifying the object. In other examples, the auxiliary computer can have its own neural network that is trained and thus reduces the risk of false positives as described herein.

[0162] The vehicle 800 may also include an infotainment SoC 830 (e.g., an in-vehicle infotainment system (IVI)). Although illustrated and described as an SoC, an infotainment system may not be an SoC and may include two or more discrete components. The infotainment SoC 830 may include a combination of hardware and software that may be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation system, rear parking assistance, radio data system, vehicle-related information such as fuel level, total distance covered, brake fuel level, oil level, door open / closed, air filter information, etc.) to the vehicle 800. For example, the infotainment SoC 830 may include a radio, a disc player, a navigation system, a video player, USB and Bluetooth connectivity, an onboard computer, onboard entertainment, WiFi, steering wheel audio controls, hands-free voice controls, a head-up display (HUD), an HMI display 834, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. The infotainment SoC 830 may further be used to provide information (e.g., visual and / or auditory) to a user of the vehicle, such as information from an ADAS system 838, autonomous driving information such as planned vehicle maneuvers, trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0163] The infotainment SoC 830 may include GPU functionality. The infotainment SoC 830 may communicate with other devices, systems, and / or components of the vehicle 800 via a bus 802 (e.g., a CAN bus, Ethernet, etc.). In some examples, the infotainment SoC 830 may be coupled to a supervisory MCU so that in the event of a failure of a master controller 836 (e.g., a main and / or backup computer of the vehicle 800), the GPU of the infotainment system may perform some self-driving functions. In such an example, the infotainment SoC 830 may place the vehicle 800 in a driver safe parking mode as described herein.

[0164] The vehicle 800 may also include an instrument cluster 832 (e.g., a digital instrument panel, an electronic instrument cluster, a digital instrument panel, etc.). The instrument cluster 832 may include a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). The instrument cluster 832 may include a set of instruments, such as a speedometer, a fuel level, an oil pressure, a tachometer, an odometer, a turn indicator, a shift position indicator, a seat belt warning light, a parking brake warning light, an engine fault light, an airbag (SRS) system information, lighting controls, safety system controls, navigation information, and the like. In some examples, information may be displayed and / or shared between the infotainment SoC 830 and the instrument cluster 832. In other words, the instrument cluster 832 may be included as part of the infotainment SoC 830, or vice versa.

[0165] Fig.8D For a cloud-based server and Fig. 8A 800. System 876 may include a server 878, a network 890, and a vehicle including the vehicle 800. The server 878 may include a plurality of GPUs 884 (A) -884 (H) (collectively referred to herein as GPUs 884), PCIe switches 882 (A) -882 (H) (collectively referred to herein as PCIe switches 882), and / or CPUs 880 (A) -880 (B) (collectively referred to herein as CPUs 880). The GPUs 884, CPUs 880, and PCIe switches may be interconnected with high-speed interconnects and / or PCIe connections 886 such as, for example and without limitation, the NVLink interface 888 developed by NVIDIA. In some examples, the GPUs 884 are connected via NVLink and / or NVSwitch SoC, and the GPUs 884 and PCIe switches 882 are connected via PCIe interconnects. Although eight GPUs 884, two CPUs 880, and two PCIe switches are illustrated, this is not intended to be limiting. Depending on the embodiment, each of the servers 878 may include any number of GPUs 884, CPUs 880, and / or PCIe switches. For example, each of the servers 878 may include eight, sixteen, thirty-two, and / or more GPUs 884.

[0166] Server 878 may receive image data over network 890 and from a vehicle, the image data representing images showing unexpected or changed road conditions, such as recently begun road work. Server 878 may transmit neural network 892, updated neural network 892, and / or map information 894, including information about traffic and road conditions, over network 890 and to the vehicle. Updates to map information 894 may include updates to HD map 822, such as information about construction sites, potholes, curves, flooding, or other obstacles. In some examples, neural network 892, updated neural network 892, and / or map information 894 may have been generated from new training and / or data received from any number of vehicles in the environment and / or based on experience from training performed at a data center (e.g., using server 878 and / or other servers).

[0167] Server 878 can be used to train a machine learning model (e.g., a neural network) based on training data. The training data can be generated by the vehicle, and / or can be generated in a simulation (e.g., using a game engine). In some examples, the training data is labeled (e.g., when the neural network benefits from supervised learning) and / or undergoes other preprocessing, while in other examples, the training data is not labeled and / or preprocessed (e.g., when the neural network does not require supervised learning). Training can be performed according to any one or more categories of machine learning techniques, including but not limited to the following categories: supervised training, semi-supervised training, unsupervised training, self-learning, reinforcement learning, joint learning, transfer learning, feature learning (including main components and cluster analysis), multilinear subspace learning, manifold learning, representation learning (including alternate dictionary learning), rule-based machine learning, anomaly detection, and any variants or combinations thereof. Once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., transmitted to the vehicle via network 890), and / or the machine learning model can be used by server 878 to remotely monitor the vehicle.

[0168] In some examples, server 878 can receive data from the vehicle and apply the data to the latest real-time neural network for real-time intelligent reasoning. Server 878 may include a deep learning supercomputer and / or a dedicated AI computer powered by GPU 884, such as DGX and DGX Station machines developed by NVIDIA. However, in some examples, server 878 may include a deep learning infrastructure of a data center powered only by CPUs.

[0169] The deep learning infrastructure of server 878 may be capable of rapid real-time inference, and may use this capability to assess and verify the health of the processors, software, and / or associated hardware in vehicle 800. For example, the deep learning infrastructure may receive periodic updates from vehicle 800, such as a sequence of images and / or objects located in the sequence of images that vehicle 800 has located (e.g., via computer vision and / or other machine learning object classification techniques). The deep learning infrastructure may run its own neural network to identify objects and compare them to the objects identified by vehicle 800, and if the results do not match and the infrastructure concludes that the AI ​​in vehicle 800 has failed, then server 878 may transmit a signal to vehicle 800 instructing the fail-safe computer of vehicle 800 to take control, notify passengers, and complete a safe parking maneuver.

[0170] For reasoning, the server 878 may include a GPU 884 and one or more programmable reasoning accelerators (e.g., NVIDIA's TensorRT). The combination of GPU-powered servers and reasoning acceleration can make real-time responses possible. In other examples, such as when performance is not so important, CPU, FPGA, and other processor-powered servers can be used for reasoning.

[0171] Example computing device

[0172] Fig. 9 9 is a block diagram of an example computing device 900 suitable for implementing some embodiments of the present disclosure. The computing device 900 may include an interconnect system 902 that directly or indirectly couples the following devices: memory 904, one or more central processing units (CPUs) 906, one or more graphics processing units (GPUs) 908, communication interfaces 910, I / O ports 912, input / output components 914, power supplies 916, one or more presentation components 918 (e.g., display(s)), and one or more logic units 920.

[0173] although Fig. 9 The various blocks of are shown as being connected via interconnect system 902 using wires, but this is not intended to be limiting and is for clarity only. For example, in some embodiments, presentation component 918 (such as a display device) may be considered to be I / O component 914 (e.g., if the display is a touch screen). As another example, CPU 906 and / or GPU 908 may include memory (e.g., memory 904 may represent a storage device in addition to the memory of GPU 908, CPU 906, and / or other components). In other words, Fig. 9The computing devices in the present invention are illustrative only. No distinction is made between such categories as "workstations," "servers," "laptops," "desktop computers," "tablet computers," "client devices," "mobile devices," "handheld devices," "game consoles," "electronic control units (ECUs)," "virtual reality systems," "augmented reality systems," and / or other device or system types, as all are considered Fig. 9 within the range of computing devices.

[0174] The interconnection system 902 may represent one or more links or buses, such as an address bus, a data bus, a control bus, or a combination thereof. The interconnection system 902 may include one or more bus or link types, such as an industry standard architecture (ISA) bus, an extended industry standard architecture (EISA) bus, a video electronics standard association (VESA) bus, a peripheral component interconnect (PCI) bus, a peripheral component interconnect fast (PCIe) bus, and / or another type of bus or link. In some embodiments, there is a direct connection between components. As an example, CPU 906 may be directly connected to memory 904. Further, CPU 906 may be directly connected to GPU 908. In the case where there is a direct or point-to-point connection between components, the interconnection system 902 may include a PCIe link to perform the connection. In these examples, the PCI bus does not need to be included in the computing device 900.

[0175] The memory 904 may include any of a variety of computer-readable media. Computer-readable media may be any available media that can be accessed by the computing device 900. Computer-readable media may include volatile and non-volatile media, as well as removable and non-removable media. By way of example and not limitation, computer-readable media may include computer storage media and communication media.

[0176] Computer storage media may include volatile and nonvolatile media and / or removable and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules, and / or other data types. For example, memory 904 may store computer-readable instructions (e.g., representing (one or more) programs and / or (one or more) program elements, such as an operating system). Computer storage media may include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage devices or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by computing device 900. As used herein, computer storage media does not include the signals themselves.

[0177] Computer storage media may embody computer readable instructions, data structures, program modules, and / or other data types in a modulated data signal such as a carrier wave or other transport mechanism, and include any information delivery media. The term "modulated data signal" may refer to a signal that has one or more of its characteristics set or changed in a manner that encodes the information in the signal. By way of example, and not limitation, computer storage media may include wired media (such as a wired network or a direct wired connection) and wireless media (such as acoustic, RF, infrared, and other wireless media). Combinations of any of the above should also be included within the scope of computer readable media.

[0178] The CPU 906 may be configured to execute at least some of the computer-readable instructions to control one or more components of the computing device 900 to perform one or more of the methods and / or processes described herein. The CPUs 906 may each include one or more cores (e.g., one, two, four, eight, twenty-eight, seventy-two, etc.) capable of handling numerous software threads simultaneously. The CPU 906 may include any type of processor, and may include different types of processors (e.g., processors with fewer cores for mobile devices and processors with more cores for servers) depending on the type of computing device 900 implemented. For example, depending on the type of computing device 900, the processor may be an Advanced RISC Machine (ARM) processor implemented using Reduced Instruction Set Computing (RISC) or an x86 processor implemented using Complex Instruction Set Computing (CISC). In addition to one or more microprocessors or supplementary coprocessors (such as math coprocessors), the computing device 900 may also include one or more CPUs 906.

[0179] In addition to or in place of (one or more) CPUs 906, (one or more) GPUs 908 may be configured to execute at least some of the computer-readable instructions to control one or more components of the computing device 900 to perform one or more of the methods and / or processes described herein. One or more of the GPUs 908 may be an integrated GPU (e.g., with one or more of the CPUs 906) and / or one or more of the GPUs 908 may be a discrete GPU. In an embodiment, one or more of the GPUs 908 may be a coprocessor of one or more of the CPUs 906. The GPU 908 may be used by the computing device 900 to render graphics (e.g., 3D graphics) or perform general-purpose computing. For example, the GPU 908 may be used for general-purpose computing on a GPU (GPGPU). The GPU 908 may include hundreds or thousands of cores capable of handling hundreds or thousands of software threads simultaneously. The GPU 908 may generate pixel data for an output image in response to a rendering command (e.g., a rendering command received from the CPU 906 via a host interface). The GPU 908 may include graphics memory (e.g., display memory) for storing pixel data or any other suitable data (e.g., GPGPU data). The display memory may be included as part of the memory 904. The GPU 908 may include two or more GPUs operating in parallel (e.g., via a link). The link may connect the GPUs directly (e.g., using NVLINK) or may connect the GPUs through a switch (e.g., using NVSwitch). When combined together, each GPU 908 may generate pixel data or GPGPU data for different parts of the output or for different outputs (e.g., a first GPU for a first image and a second GPU for a second image). Each GPU may include its own memory, or may share memory with other GPUs.

[0180] In addition to or in lieu of the CPU 906 and / or GPU 908, the logic unit 920 may be configured to execute at least some of the computer-readable instructions to control one or more components of the computing device 900 to perform one or more of the methods and / or processes described herein. In embodiments, the (one or more) CPUs 906, (one or more) GPUs 908, and / or (one or more) logic units 920 may discretely or jointly perform any combination of methods, processes, and / or portions thereof. One or more of the logic units 920 may be a part of and / or integrated into one or more of the CPUs 906 and / or GPUs 908 and / or one or more of the logic units 920 may be discrete components or otherwise external to the CPUs 906 and / or GPUs 908. In embodiments, one or more of the logic units 920 may be a coprocessor of one or more of the CPUs 906 and / or GPUs 908.

[0181] Examples of logic unit 920 include one or more processing cores and / or components thereof, such as a Tensor Core (TC), a Tensor Processing Unit (TPU), a Pixel Visual Core (PVC), a Vision Processing Unit (VPU), a Graphics Processing Cluster (GPC), a Texture Processing Cluster (TPC), a Streaming Multiprocessor (SM), a Tree Traversal Unit (TTU), an Artificial Intelligence Accelerator (AIA), a Deep Learning Accelerator (DLA), an Arithmetic Logic Unit (ALU), an Application Specific Integrated Circuit (ASIC), a Floating Point Unit (FPU), an I / O element, a Peripheral Component Interconnect (PCI) or a Peripheral Component Interconnect Express (PCI express, PCIe) element, etc.

[0182] The communication interface 910 may include one or more receivers, transmitters, and / or transceivers that enable the computing device 900 to communicate with other computing devices via an electronic communication network (including wired and / or wireless communications). The communication interface 910 may include components and functionality that enable communication over any of a number of different networks, such as a wireless network (e.g., Wi-Fi, Z-Wave, Bluetooth, Bluetooth LE, ZigBee, etc.), a wired network (e.g., via Ethernet or wireless band communications), a low power wide area network (e.g., LoRaWAN, SigFox, etc.), and / or the Internet.

[0183] The I / O ports 912 may enable the computing device 900 to be logically coupled to other devices including I / O components 914, (one or more) presentation components 918, and / or other components, some of which may be built into (e.g., integrated into) the computing device 900. Illustrative I / O components 914 include microphones, mice, keyboards, joysticks, game pads, game controllers, satellite dishes, scanners, printers, wireless devices, and the like. The I / O components 914 may provide a natural user interface (NUI) that processes air gestures, voice, or other physiological inputs generated by a user. In some cases, the input may be transmitted to an appropriate network element for further processing. The NUI may implement any combination of voice recognition, stylus recognition, facial recognition, biometric recognition, gesture recognition on and near the screen, air gestures, head and eye tracking, and touch recognition (as described in more detail below) associated with the display of the computing device 900. The computing device 900 may include a depth camera for gesture detection and recognition, such as a stereo camera system, an infrared camera system, an RGB camera system, touch screen technology, and combinations of these. Additionally, computing device 900 may include an accelerometer or gyroscope that enables detection of motion (e.g., as part of an inertial measurement unit (IMU)). In some examples, computing device 900 may use the output of the accelerometer or gyroscope to render an immersive augmented reality or virtual reality.

[0184] The power supply 916 may include a hardwired power supply, a battery power supply, or a combination thereof. The power supply 916 may provide power to the computing device 900 to enable the components of the computing device 900 to operate.

[0185] The presentation component 918 may include a display (e.g., a monitor, a touch screen, a television screen, a head-up display (HUD), other display types, or a combination thereof), a speaker, and / or other presentation components. The presentation component 918 may receive data from other components (e.g., GPU 908, CPU 906, etc.) and output the data (e.g., as an image, video, sound, etc.).

[0186] The present disclosure may be described in the general context of machine-usable instructions or computer codes executed by a computer or other machine such as a personal digital assistant or other handheld device, including computer-executable instructions such as program modules. Typically, program modules including routines, programs, objects, components, data structures, etc. refer to codes that perform specific tasks or implement specific abstract data types. The present disclosure may be practiced in a variety of system configurations, including handheld devices, consumer electronics, general-purpose computers, more specialized computing devices, etc. The present disclosure may also be practiced in a distributed computing environment in which tasks are performed by remote processing devices linked through a communication network.

[0187] At least one embodiment of the present disclosure may be described according to the following clauses:

[0188] 1. A method comprising: accessing one or more logical interfaces indicating one or more dependencies of one or more functions associated with a plurality of components; recursively determining one or more physical interfaces of the plurality of components based on the one or more logical interfaces; and using the one or more physical interfaces to perform operations using the plurality of components.

[0189] 2. The method of clause 1, wherein the plurality of components corresponds to a first level of an architecture and the one or more physical interfaces are associated with a second plurality of components corresponding to a second level of the architecture.

[0190] 3. A method according to clause 1 or 2, wherein recursively determining the one or more physical interfaces further includes: identifying one or more interdependent functions associated with multiple sub-components of the multiple components; and identifying the one or more physical interfaces based on the one or more interdependent functions associated with the multiple sub-components of the multiple components.

[0191] 4. A method according to any one of clauses 1 to 3, wherein the one or more logical interfaces are defined in one or more documents, and the one or more documents include one or more requirements for the one or more functions associated with the multiple components.

[0192] 5. The method of any of clauses 1 to 4, wherein the one or more physical interfaces materialize the one or more logical interfaces.

[0193] 6. The method according to any one of clauses 1 to 5, wherein the operation is a verification operation, the verification operation verifying whether the one or more functions associated with the plurality of components are satisfied.

[0194] 7. A method according to any one of clauses 1 to 6, wherein the plurality of components comprises one or more of: hardware, software, hardware parts or software units.

[0195] 8. The method of any one of clauses 1 to 7, wherein the one or more logical interfaces include at least one event indicative of one or more preconditions, results, or concurrencies associated with the plurality of components.

[0196] 9. A method according to any of clauses 1 to 8, wherein the one or more physical interfaces include one or more processes to be performed by the plurality of components.

[0197] 10. A system comprising one or more processing units for: accessing one or more architecture specifications having logical interfaces associated with multiple elements of the architecture; using at least the logical interfaces to identify one or more physical interfaces representing processes to be executed in association with the multiple elements; and executing the processes in association with the multiple elements.

[0198] 11. The system of clause 10, wherein the one or more processing units are configured to:

[0199] One or more interdependent functions associated with a plurality of sub-elements of the plurality of elements are identified; and the one or more physical interfaces are identified based on the one or more interdependent functions associated with the plurality of sub-elements.

[0200] 12. The system of clause 10 or 11, wherein the one or more physical interfaces materialize the logical interface.

[0201] 13. The system of any of clauses 10 to 12, wherein the plurality of elements corresponds to a first level of an architecture and the one or more physical interfaces are associated with a second plurality of elements corresponding to a second level of the architecture.

[0202] 14. The system of any of clauses 10 to 13, wherein the first level of the architecture is associated with a requirements definition indicating one or more expectations of the plurality of elements corresponding to the second plurality of elements.

[0203] 15. The system of any of clauses 10 to 14, wherein the plurality of components comprises at least one of: hardware, software, hardware parts or software units.

[0204] 16. The system of any of clauses 10 to 15, wherein the process is a verification operation that verifies whether one or more functions associated with the plurality of components are satisfied.

[0205] 17. The system of any of clauses 10 to 16, wherein the logical interface comprises at least one event indicative of one or more preconditions, results, or concurrencies associated with the plurality of components.

[0206] 18. The system of any of clauses 10 to 17, wherein the logical interface is defined in one or more documents, the documents comprising one or more requirements for one or more functions associated with the plurality of elements.

[0207] 19. A processor comprising: one or more processing units for performing operations including: determining one or more physical events associated with the multiple components based on logical interface specifications associated with the multiple components; and using the one or more physical events to identify one or more processes associated with the multiple components.

[0208] 20. A processor according to clause 19, wherein the processor is included in at least one of the following: a control system for an autonomous or semi-autonomous machine; a perception system for an autonomous or semi-autonomous machine; a first system for performing simulation operations; a second system for performing deep learning operations; a third system implemented using an edge device; a fourth system implemented using a robot; a fifth system integrating one or more virtual machines (VMs); a sixth system implemented at least in part in a data center; a seventh system for performing digital twin operations; an eighth system for performing light transport simulations; a ninth system for performing collaborative content creation for 3D assets; a tenth system for performing conversational artificial intelligence operations; an eleventh system for generating synthetic data; a twelfth system for implementing a network hosting service for detecting program workload inefficiencies; an application as an application programming interface (API); a thirteenth system implemented at least in part using cloud computing resources; a fourteenth system for displaying one or more of virtual reality content, augmented reality content, or mixed reality content; or a fifteenth system implementing one or more large language models (LLMs).

[0209] As used herein, the statement of "and / or" with respect to two or more elements should be interpreted as referring to only one element or a combination of elements. For example, "element A, element B, and / or element C" may include only element A, only element B, only element C, element A and element B, element A and element C, element B and element C, or elements A, B, and C. In addition, "at least one of element A or element B" may include at least one of element A, at least one of element B, or at least one of element A and at least one of element B. Further, "at least one of element A and element B" may include at least one of element A, at least one of element B, or at least one of element A and at least one of element B.

[0210] The subject matter of the present disclosure is described in detail herein to meet statutory requirements. However, the description itself is not intended to limit the scope of the present disclosure. On the contrary, the present inventors have contemplated that the claimed subject matter may also be embodied in other ways to include steps different from the steps described herein in conjunction with other current or future technologies or combinations of similar steps. Moreover, although the terms "step" and / or "block" may be used herein to imply different elements of the method employed, these terms should not be interpreted as implying any particular order among or between the various steps disclosed herein, unless the order of the steps is explicitly described.

Claims

1. A method comprising: accessing one or more logical interfaces indicating one or more dependencies of one or more functions associated with a plurality of components; recursively determining one or more physical interfaces of the plurality of components based on the one or more logical interfaces; as well as The one or more physical interfaces are used to perform operations using the plurality of components.

2. The method according to claim 1, wherein: The plurality of components corresponds to a first level of an architecture, and the one or more physical interfaces are associated with a second plurality of components corresponding to a second level of the architecture.

3. The method according to claim 1, wherein: Recursively determining the one or more physical interfaces further comprises: identifying one or more interdependent functions associated with a plurality of subcomponents of the plurality of components; and The one or more physical interfaces are identified based on the one or more interdependent functions associated with the plurality of sub-components of the plurality of components.

4. The method according to claim 1, wherein: The one or more logical interfaces are defined in one or more documents including one or more requirements for the one or more functions associated with the plurality of components.

5. The method according to claim 1, wherein: The one or more physical interfaces materialize the one or more logical interfaces.

6. The method according to claim 1, wherein: The operation is a verification operation that verifies whether the one or more functions associated with the plurality of components are satisfied.

7. The method according to claim 1, wherein: The plurality of components include: one or more of hardware, software, hardware components or software units.

8. The method according to claim 1, wherein: The one or more logical interfaces include at least one event indicative of one or more preconditions, results, or concurrencies regarding the plurality of components.

9. The method according to claim 1, wherein: The one or more physical interfaces include one or more processes to be performed by the plurality of components.

10. A system comprising: One or more processing units for: accessing one or more architecture specifications having logical interfaces associated with a plurality of elements of the architecture, using at least the logical interface to identify one or more physical interfaces representing processes to be performed in association with the plurality of elements, and The process is performed in association with the plurality of elements.

11. The system according to claim 10, wherein: The one or more processing units are configured to: identifying one or more interdependent functions associated with a plurality of sub-elements of the plurality of elements; and The one or more physical interfaces are identified based on the one or more interdependent functions associated with the plurality of sub-elements.

12. The system according to claim 10, wherein: The one or more physical interfaces materialize the logical interface.

13. The system according to claim 10, wherein: The plurality of elements corresponds to a first level of an architecture, and the one or more physical interfaces are associated with a second plurality of elements corresponding to a second level of the architecture.

14. The system according to claim 13, wherein: The first level of the architecture is associated with a requirements definition that indicates one or more expectations of the plurality of elements corresponding to the second plurality of elements.

15. The system according to claim 10, wherein: The plurality of components include at least one of hardware, software, a hardware component or a software unit.

16. The system of claim 10, wherein: The process is a verification operation that verifies whether one or more functions associated with the plurality of components are satisfied.

17. The system according to claim 10, wherein: The logical interface includes at least one event indicative of one or more preconditions, results, or concurrencies regarding the plurality of components.

18. The system of claim 10, wherein: The logical interface is defined in one or more documents including one or more requirements for one or more functions associated with the plurality of elements.

19. A processor comprising: One or more processing units for performing operations including: determining one or more physical events associated with the plurality of components based on a logical interface specification associated with the plurality of components; and One or more processes associated with the plurality of components are identified using the one or more physical events.

20. The processor of claim 19, wherein: The processor is included in at least one of the following: control systems for autonomous or semi-autonomous machines; Perception systems for autonomous or semi-autonomous machines; a first system for performing simulation operations; a second system for performing deep learning operations; A third system implemented using edge devices; The fourth system is implemented using robots; a fifth system integrating one or more virtual machines VM; A sixth system implemented at least in part in a data center; a seventh system for performing digital twin operations; an eighth system for performing light transport simulations; A ninth system for performing collaborative content creation for 3D assets; a tenth system for performing conversational artificial intelligence operations; an eleventh system for generating synthetic data; a twelfth system for implementing a web hosting service for detecting program workload inefficiencies; Applications as application programming interfaces (APIs); A thirteenth system implemented at least in part using cloud computing resources; A fourteenth system for presenting one or more of virtual reality content, augmented reality content, or mixed reality content; or A fifteenth system implementing one or more Large Language Models (LLMs).

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