Data processing apparatus and method

Abstract

According to the data processing equipment and method provided by the invention, a processing circuit comprises a multi-core processor, and the multi-core processor comprises sub-processors with K cores and is used for participating in a target process of generating result data by performing N data processing on target data. Specifically, the processing circuit obtains the target data, determines N target computing power corresponding to the N-channel data processing, and determines the distribution of the K kernels on the execution of the N-channel data processing according to the N target computing power and a preset optimization purpose in the target process. Visibly, through the scheme provided by the invention, in the operation process of the data processing equipment, the computing power provided by the K kernels for the N channels of data processing respectively can be determined, and the corresponding target computing power is adaptively allocated to each channel of data processing, so that the flexibility of computing power allocation is improved.

Description

Technical Field

[0001] The present invention relates to the field of data processing, and in particular to a data processing device and method. Background Art

[0002] The data processing device can process multiple channels of data. For example, the data processing device that processes audio signals can perform sampling, noise reduction, Bluetooth sub-band coding (SBC), and Bluetooth radio frequency, etc. on the audio signals. It is understandable that the above-mentioned multi-channel data processing process can be implemented by hardware, some data processing can be implemented by algorithms, and some data processing can be implemented by hardware or by algorithms. For data processing implemented by algorithms, computing power must be provided for the processing. A chip of an existing data processing device provides at least two cores for the data processing process, and plans in advance the data processing that each core is responsible for. For example, core 1 provides computing power for sampling and noise reduction, and core 2 provides computing power for Bluetooth SBC and Bluetooth radio frequency.

[0003] The content of the background technology section is only the information known to the inventor personally, and does not mean that the above information has entered the public domain before the application date of this disclosure, nor does it mean that it can become the prior art of the present disclosure. Summary of the invention

[0004] This specification provides a data processing device and method that can improve the flexibility of computing power allocation for data processing.

[0005] In a first aspect, a data processing device is provided, comprising: at least one storage medium storing at least one set of instruction sets, wherein the at least one set of instruction sets is used to schedule computing power in a target process of generating result data by subjecting target data to N data processing steps; and a processing circuit comprising a multi-core processor and being communicatively connected to the at least one storage medium, wherein the multi-core processor comprises K core sub-processors to participate in the target process, K being an integer greater than 1, wherein when the data processing device is running, the processing circuit executes the at least one set of instruction sets to: obtain target data, determine N target computing powers corresponding to the N data processing steps, and in the target process, determine the allocation of the K cores in executing the N data processing steps according to the N target computing powers and a preset optimization purpose.

[0006] In some embodiments, in order to determine the allocation of the K cores in executing the N data processing, the processing circuit executes the at least one set of instruction sets to: determine M initial allocation schemes according to the N target computing powers to allocate corresponding cores to the N data processing, wherein each of the initial allocation schemes satisfies that the computing power that can be provided by each core is greater than or equal to the sum of the computing powers required for the corresponding data processing, and M is an integer greater than or equal to 1; and based on the optimization purpose, determine a first target allocation scheme from the M initial allocation schemes to execute.

[0007] In some embodiments, in order to determine the above-mentioned M initial allocation schemes, the above-mentioned processing circuit executes the above-mentioned at least one set of instruction sets to: determine the target total computing power required to execute the above-mentioned target process based on the above-mentioned N target computing powers; determine the initial operating frequency of the above-mentioned K cores based on the above-mentioned target total computing power; determine the K available computing powers corresponding to the above-mentioned K cores respectively based on the above-mentioned initial operating frequency; and determine M initial allocation schemes based on the above-mentioned N target computing powers and the above-mentioned K available computing powers.

[0008] In some embodiments, each of the above-mentioned M initial allocation schemes includes: at least one core participating in the above-mentioned target process, and the actual provided computing power of the at least one core participating in the above-mentioned target process and / or the actual operating frequency of the at least one core participating in the above-mentioned target process.

[0009] In some embodiments, in order to determine the allocation of the above-mentioned K cores in executing the above-mentioned N data processing, the above-mentioned processing circuit executes the above-mentioned at least one set of instruction sets to: based on a preset algorithm, according to the above-mentioned N target computing powers, the K computing powers that can be provided corresponding to the above-mentioned K cores respectively, and the above-mentioned optimization purpose, determine at least one core participating in the above-mentioned target process among the above-mentioned K cores, and determine the actual operating frequency of the above-mentioned at least one core participating in the above-mentioned target process.

[0010] In some embodiments, the optimization purpose is to select, from among multiple optional allocation schemes, an allocation scheme in which the target statistical value of the actual computing power provided by the K cores corresponding to the K cores is the smallest, where the statistical value is the variance or standard deviation.

[0011] In some embodiments, the optimization objectives include: keeping the overall power consumption of the K cores at a minimum and / or the load at a most balanced level.

[0012] In some embodiments, the processing circuit also executes at least one set of instruction sets to: determine that the K cores have insufficient computing power during the execution of the target; and increase the operating frequency of the K cores to increase the computing power provided by the sub-processor to avoid data processing jams.

[0013] In some embodiments, the processing circuit also executes at least one set of instruction sets to: determine, during execution of the target, that there are O cores among the K cores that have insufficient computing power, where O is a positive integer not greater than K; and increase the operating frequency of the O cores to increase the computing power of the qth core to avoid stalls in the data processing process.

[0014] In some embodiments, the insufficient computing power includes: a computing power occupancy rate of any one of the K cores exceeds a first threshold.

[0015] In some embodiments, the processing circuit further executes the at least one set of instruction sets to: determine, in the process of executing the target, that there is an idle core among the K cores whose computing power occupancy rate is less than a second threshold, and stop the idle core from executing corresponding data processing; determine L reallocation schemes according to the N target computing powers and at least one working core among the K cores other than the idle core, wherein under each of the reallocation schemes, the total computing power provided by the at least one working core is greater than or equal to the total computing power required to execute the target process, and L is an integer greater than or equal to 1; and

[0016] Based on the above optimization purpose, a second target allocation scheme is determined from the above L reallocation schemes, and the computing power of the above at least one working core in executing the above N data processing is allocated through the above second target allocation scheme.

[0017] In some embodiments, in order to achieve the above-mentioned optimization goals, the above-mentioned processing circuit also executes the above-mentioned at least one set of instruction sets to: in the process of executing the above-mentioned goals, determine that the computing power provided by the p-th core for the j-th data processing is insufficient; determine that the q-th core from the above-mentioned K cores provides computing power for the above-mentioned j-th data processing; and transfer the execution of the above-mentioned j-th data processing from the above-mentioned p-th core to the above-mentioned q-th core.

[0018] In some embodiments, the processing circuit further executes the at least one set of instruction sets to: before transferring the execution of the j-th data processing from the p-th core to the q-th core, increase the operating frequency of the q-th core to increase the computing power of the q-th core to avoid data processing jams.

[0019] In some embodiments, the processing circuit also executes at least one set of instruction sets to: in the process of executing the above-mentioned target, determine that there are R cores among the above-mentioned K cores that have insufficient computing power, where R is a positive integer not greater than K; when there are idle cores among the above-mentioned K cores whose computing power occupancy rate is less than a second threshold, transfer at least part of the data processing corresponding to the above-mentioned R cores to the above-mentioned idle cores, wherein after the transfer, the computing power that can be provided by each of the above-mentioned cores is greater than or equal to the sum of the computing power required for the corresponding data processing.

[0020] In some embodiments, the at least one storage medium is also associated with storing: attributes of the target data and target computing power corresponding to at least one data processing performed on the target data; in order to determine the N target computing powers corresponding to the N data processings, the processing circuit executes the at least one set of instruction sets to: search the at least one storage medium according to the attributes of the obtained target data, and obtain the N target computing powers corresponding to the N data processings performed on the target data.

[0021] In some embodiments, the processing circuit executes the at least one set of instruction sets to: calculate the N target computing powers required for the N data processing steps of the target data of the target attribute, respectively, when the at least one storage medium does not store the N target computing powers corresponding to the N data processing steps of the target data of the target attribute; and associate the N target computing powers corresponding to the N data processing steps of the target data of the target attribute with the target attribute, and store them in the at least one storage medium.

[0022] In some embodiments, the at least one storage medium further stores: for multiple attributes of the target data, the kernel identification of each of which processes the target data of each attribute and provides computing power for the N data processing respectively; in order to determine the allocation of the K kernels in executing the N data processing, the processing circuit executes the at least one set of instruction sets to: search the at least one storage medium according to the target attributes of the obtained target data, and obtain the kernel identification of each of which processes the target data of the target attribute and provides computing power for the N data processing respectively, thereby determining the allocation of the K kernels in executing the N data processing.

[0023] In some embodiments, the data processing device is a headset.

[0024] In a second aspect, the present application provides a data processing method, comprising: obtaining target data, determining N target computing powers corresponding to N data processings, and in the target process, determining the distribution of K cores in a multi-core processor participating in the above target process in executing the above N data processings based on the above N target computing powers and preset optimization purposes, where K is an integer greater than 1; wherein the above target process is a process of generating result data by subjecting the above target data to the above N data processings.

[0025] In some embodiments, the above-mentioned determination of the allocation of the above-mentioned K cores in executing the above-mentioned N data processing includes: according to the above-mentioned N target computing powers, M initial allocation schemes are determined to allocate corresponding cores to the above-mentioned N data processing, wherein each of the above-mentioned initial allocation schemes satisfies that the computing power provided by each of the above-mentioned cores is greater than or equal to the sum of the computing powers required for the corresponding data processing, and M is an integer greater than or equal to 1; and based on the above-mentioned optimization purpose, a first target allocation scheme is determined from the above-mentioned M initial allocation schemes for execution.

[0026] In some embodiments, determining the M initial allocation schemes includes: determining the target total computing power required to execute the target process based on the N target computing powers; determining the initial operating frequency of the K cores based on the target total computing power; determining the K available computing powers corresponding to the K cores respectively based on the initial operating frequency; and determining M initial allocation schemes based on the N target computing powers and the K available computing powers.

[0027] In some embodiments, each of the above-mentioned M initial allocation schemes includes: at least one core participating in the above-mentioned target process, and the actual provided computing power of the at least one core participating in the above-mentioned target process and / or the actual operating frequency of the at least one core participating in the above-mentioned target process.

[0028] In some embodiments, in order to determine the allocation of the above-mentioned K cores in executing the above-mentioned N data processing, the above-mentioned processing circuit executes the above-mentioned at least one set of instruction sets to: based on a preset algorithm, according to the above-mentioned N target computing powers, the K computing powers that can be provided corresponding to the above-mentioned K cores respectively, and the above-mentioned optimization purpose, determine at least one core participating in the above-mentioned target process among the above-mentioned K cores, and determine the actual operating frequency of the above-mentioned at least one core participating in the above-mentioned target process.

[0029] In some embodiments, the optimization purpose is to select, from among multiple optional allocation schemes, an allocation scheme in which the target statistical value of the actual computing power provided by the K cores corresponding to the K cores is the smallest, where the statistical value is the variance or standard deviation.

[0030] In some embodiments, the optimization objectives include: keeping the overall power consumption of the K cores at a minimum and / or the load at a most balanced level.

[0031] In some embodiments, the method further includes: determining that the K cores have insufficient computing power during the execution of the target; and increasing the operating frequency of the K cores to increase the computing power provided by the sub-processors to avoid data processing jams.

[0032] In some embodiments, the method further includes: in the process of executing the above-mentioned goal, determining that there are O cores among the above-mentioned K cores that have insufficient computing power, where O is a positive integer not greater than K; and increasing the operating frequency of the above-mentioned O cores to increase the computing power of the above-mentioned qth core to avoid jamming of the data processing process.

[0033] In some embodiments, the insufficient computing power includes: a computing power occupancy rate of any one of the K cores exceeds a first threshold.

[0034] In some embodiments, the above method also includes: in the process of executing the above target, determining that there is an idle core among the above K cores whose computing power occupancy rate is less than a second threshold, and stopping the above idle core from executing corresponding data processing; determining L reallocation schemes based on the above N target computing powers and at least one working core among the above K cores other than the above idle core, wherein under each of the above reallocation schemes, the total computing power provided by the above at least one working core is greater than or equal to the total computing power required to execute the above target process, and L is an integer greater than or equal to 1; and determining a second target allocation scheme from the above L reallocation schemes based on the above optimization purpose, and allocating the computing power of the above at least one working core in executing the above N data processing through the above second target allocation scheme.

[0035] In some embodiments, the method further includes: in the process of executing the above-mentioned goal, determining that the computing power provided by the p-th core for the j-th data processing is insufficient; determining that the q-th core from the K-th cores provides computing power for the j-th data processing; and transferring the execution of the j-th data processing from the p-th core to the q-th core.

[0036] In some embodiments, the method further includes: before transferring the execution of the j-th data processing from the p-th core to the q-th core, increasing the operating frequency of the q-th core to increase the computing power of the q-th core to avoid data processing jams.

[0037] It can be seen from the above technical solutions that the data processing device and method provided by the present application, wherein the processing circuit includes a multi-core processor, and the multi-core processor includes K core sub-processors for participating in the target process of processing the target data through N data processes to generate result data. Specifically, the processing circuit obtains the above target data, and determines the N target computing powers corresponding to the above N data processes, and in the above target process, determines the allocation of the above K cores in executing the above N data processes according to the above N target computing powers and the preset optimization purpose. It can be seen that the scheme provided by the present application can determine the computing power provided by the K cores for the N data processes respectively during the operation of the data processing device, and adaptively allocate the corresponding target computing power to each data process, which is conducive to improving the flexibility of computing power allocation.

[0038] Other functions of the data processing apparatus and method provided by this specification will be partially listed in the following description. Based on the description, the content introduced by the following figures and examples will be obvious to those of ordinary skill in the art. The creative aspects of the data processing apparatus and method provided by this specification can be fully explained by practicing or using the methods, devices and combinations described in the following detailed examples. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of this specification, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0040] Figure 1 A schematic diagram showing an application scenario provided according to an embodiment of the present application is shown;

[0041] Figure 2 A schematic diagram of the structure of a data processing device provided according to an embodiment of the present application is shown;

[0042] Figure 3A-3C A schematic diagram of a structure of a processing circuit provided according to an embodiment of the present application is respectively shown;

[0043] Figure 4 A schematic diagram of a data processing method according to an embodiment of the present application is shown;

[0044] Figure 5 A schematic diagram of a process of a method for initial allocation of computing power provided in accordance with an embodiment of the present application is shown;

[0045] Figure 6 A schematic diagram of a data processing method according to an embodiment of the present application is shown;

[0046] Figure 7 A schematic diagram of a process of a method for initial allocation of computing power provided in accordance with an embodiment of the present application is shown;

[0047] Figure 8 A schematic diagram showing a schematic diagram of a relationship between a processor core operating frequency and a processor power consumption, and a schematic diagram showing a relationship between a number of processor operating cores and a processor power consumption, provided according to an embodiment of the present application;

[0048] Fig. 9 A schematic diagram of a process for reallocating computing power in the case of insufficient computing power provided in accordance with an embodiment of the present application is shown;

[0049] Fig.10 A flow chart of a method for reallocating computing power in the event of excess computing power provided in accordance with an embodiment of the present application is shown. DETAILED DESCRIPTION

[0050] The following description provides specific application scenarios and requirements of this specification, with the purpose of enabling those skilled in the art to make and use the contents of this specification. Various local modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this specification. Therefore, this specification is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0051] The terms used herein are only used for the purpose of describing specific example embodiments and are not restrictive. For example, unless the context clearly indicates otherwise, as used herein, the singular forms "a", "an" and "the" may also include plural forms. When used in this specification, the terms "include", "comprise" and / or "contain" mean that the associated integers, steps, operations, elements and / or components exist, but do not exclude the existence of one or more other features, integers, steps, operations, elements, components and / or groups or that other features, integers, steps, operations, elements, components and / or groups may be added in the system / method.

[0052] In view of the following description, these and other features of the present specification, as well as the operation and function of the related elements of the structure, and the economy of the combination and manufacture of the parts can be significantly improved. Reference is made to the accompanying drawings, all of which form a part of this specification. However, it should be clearly understood that the drawings are for illustration and description purposes only and are not intended to limit the scope of this specification. It should also be understood that the drawings are not drawn to scale.

[0053] The flowcharts used in this specification illustrate the operations implemented by the system according to some embodiments in this specification. It should be clearly understood that the operations of the flowcharts may not be implemented in sequence. On the contrary, the operations may be implemented in reverse order or simultaneously. In addition, one or more other operations may be added to the flowchart. One or more operations may be removed from the flowchart.

[0054] The data processing device provided in the embodiment of the present application can be used for audio data processing, video data processing, text data processing, code processing, etc., and the embodiment of the present application does not limit this. Similarly, the data processing method provided in the embodiment of the present application is not limited to the audio data processing process, video data processing process, text data processing process, code processing process, etc. Take the data processing device for audio signal processing as an example, the above-mentioned data processing device can be a speaker for voice playback or various devices equipped with a speaker (such as headphones, stereos, televisions, smart phones, smart home devices, etc.), and can also be used for a microphone for voice reception or various devices equipped with a microphone (such as headphones, smart phones, phone watches, smart home devices, etc.). It can be understood that it can also be a device that includes both a microphone and a speaker, such as headphones, smart phones, etc. In the embodiment of the present application, the data processing device is described by taking headphones as an example.

[0055] Figure 1 1 is a schematic diagram showing an application scenario provided according to an embodiment of the present application. In this embodiment, the data processing device is a wireless headset 120 that performs audio signal processing. Figure 1 The scenario shown in the figure is a call scenario 001 after the electronic device 110 and the wireless headset 120 are connected for communication. It is understandable that the solution provided in the present application can also be applied to other scenarios in which a data processing device is used to send and receive audio, such as listening to music through headphones, listening to dialogues while watching videos, etc.

[0056] The electronic device 110 may be a handheld device, a vehicle-mounted device, a wearable device, a computing device or other device connected to a wireless modem. The electronic device 110 may include: a smartphone, a cellular phone, a tablet computer, a personal digital assistant (PDA), a laptop computer, a vehicle-mounted computer, a smart watch, a smart wristband, a pedometer and other electronic devices with a call function. In the embodiment of the present application, the frequency communication device is illustrated by taking a headset as an example. The headset can generally be divided into a wired headset (wired headset or wired headset) and a wireless headset (wireless headset). The wired headset is inserted into the jack of the electronic device through a connecting line to communicate with the electronic device. The wireless headset uses wireless communication technology (such as Bluetooth technology, infrared radio frequency technology, 2.4G wireless technology, ultrasound, etc.) to communicate with the electronic device 110. See FIG. Figure 1 In the illustrated call scenario 001 , the wireless headset 120 is connected to the electronic device 110 for communication via Bluetooth.

[0057] refer to Figure 1 In S1 shown, the wireless headset 120 can be used as a receiving end of the audio signal. The speaker of the wireless headset 120 receives the audio signal sent by the electronic device 110 during the call, and converts the received audio signal into sound waves that the user can hear after performing a series of processing (such as digital-to-analog conversion, signal amplification, etc.). Figure 1 As shown in S2, the wireless headset 120 can be used as a transmitter of an audio signal. The microphone of the wireless headset 120 receives the audio signal sent by the user during a call, and performs a series of processing (such as analog-to-digital converter (ADC) sampling, noise reduction processing, Bluetooth SBC, and Bluetooth radio frequency) on the received audio signal before sending it to the electronic device 110.

[0058] With the expansion of application scenarios, data processing methods have gradually diversified, such as audio signal mixing, resampling modules, Advanced Audio Coding (AAC) encoding and decoding, echo cancellation, noise suppression, etc. At the same time, the computing power required for audio signal processing continues to increase, so the cores used for audio signal processing in the chip of the data processing device are generally set to multiple. In the related art, the data processing that each core is responsible for is generally planned in advance. For example, core 1 provides computing power for sampling and noise reduction, core 2 provides computing power for Bluetooth SBC and Bluetooth radio frequency, core 3 provides computing power for echo cancellation, and so on. However, the above-mentioned computing power allocation method provided by the related art has the problem of inflexible computing power allocation, resulting in insufficient utilization of the core computing power and / or insufficient core computing power. For example, core 1 is planned in advance to provide computing power for sampling and noise reduction, but there is a situation where the computing power required for sampling and noise reduction of audio a is greater than the total computing power that core 1 can provide, that is, there is a problem of insufficient computing power of core 1; for another example, core 3 is planned in advance to provide computing power for echo cancellation, but there is a situation where audio a does not need echo cancellation, that is, there is a problem of insufficient utilization of the computing power of core 3.

[0059] Figure 2 A structural schematic diagram of a data processing device provided according to an embodiment of the present application is shown. The data processing device 002 can be used for a device for processing audio data, a device for processing video data, a device for processing text data, etc. Taking the device for processing audio data as an example, it can be a wired headset or a wireless headset. The data processing device 002 can be applied to Figure 1 In the call scenario shown, it can be understood that the data processing device 002 can also be applied to other scenarios in which audio is sent and received using an audio communication device.

[0060] refer to Figure 2, the data processing device 002 may include: at least one storage medium 210, wherein the storage medium 210 may be a non-temporary storage medium or a temporary storage medium. For example, the data storage device may include: one or more of: Flash Memory 2100, disk 2101, read-only memory (ROM) 2102, and random access memory (RAM) 2103. The above storage contains at least one set of instruction sets, which include instructions. The above instructions are computer program codes, and the computer program codes may include programs, routines, objects, components, data structures, processes, modules, etc. for executing the data processing method provided in the embodiment of the present application. Specifically, the at least one set of instruction sets stored in the storage medium 210 is used for computing power scheduling in the data processing process. It should be noted that in the embodiment of the present application, the data processing process of generating result data through N data processing of the target data is recorded as the target process, and N is an integer greater than 1. That is, the at least one set of instruction sets stored in the storage medium 210 is used to provide computing power for the N data processing in the above target process.

[0061] refer to Figure 2 , the data processing device 002 also includes: a processing circuit 220. The processing circuit 220 is used to determine or adjust the computing power allocation for N data processing in the above-mentioned target process. Specifically, when the data processing device 002 is running, the processing circuit 220 reads at least one set of instruction sets stored in the storage medium 210 to obtain the target data, determine the N target computing powers corresponding to the above-mentioned N data processing, and determine or adjust the computing power allocation for the N data processing in the above-mentioned target process. In some embodiments, further, when the data processing device 002 is running, the processing circuit 220 reads at least one set of instruction sets stored in the storage medium 210 to perform the above-mentioned N processing, thereby processing the above-mentioned target data into result data.

[0062] Specifically, the processing circuit 220 includes a multi-core processor 220-A, and the multi-core processor 220-A is used to provide computing power for N data processing in the above-mentioned target process. More specifically, the K cores of the sub-processor 240 included in the multi-core processor 220-A are used to provide computing power for N data processing in the above-mentioned target process, and K is an integer greater than 1. It can be understood that the above-mentioned K cores can be all cores of the sub-processor 240, or can be part of the cores of the sub-processor 240, and the embodiment of the present application does not limit this. Among them, the multi-core processor 220-A can be: a quad-core processor, an octa-core processor, etc., and the embodiment of the present application does not limit the number of multi-cores. The embodiment of the present application does not limit the type of the multi-core processor 220-A. Specifically, the type of the multi-core processor 220-A may include, for example: central processing unit (CPU), graphics processing unit (GPU), physical processing unit (PPU), microcontroller unit, digital signal processor (DSP), field programmable gate array (FPGA), programmable logic device (PLD), microcontroller, microprocessor, reduced instruction set computer (RISC), advanced RISC machine (ARM), application specific integrated circuit (ASIC), that is, the multi-core processor 220-A is any circuit or processor capable of performing one or more functions, or any combination thereof.

[0063] Specifically, the processing circuit 220 is in communication with the storage medium 210. Figure 2 In some embodiments, the data processing device 002 may further include an internal communication bus 230, which may connect different system components in the data processing device 002. For example, the processing circuit 220 and the storage medium 210 may be connected via the internal communication bus 230, so that the processing circuit 210 may read at least one set of instructions in the storage medium 210 to obtain target data, determine the N target computing powers corresponding to the N data processing, and determine or adjust the computing power allocation for the N data processing in the target process, so as to adaptively provide the computing power of the K cores in the sub-processor 240 to the N data processing, thereby facilitating the improvement of the flexibility of computing power allocation of the data processing device.

[0064] Figure 3A A structural schematic diagram of a processing circuit provided according to an embodiment of the present application is shown. Referring to the processing circuit 003 shown in the figure, in some embodiments, specifically, the multi-core processor 220-A in the processing circuit 220 includes a processor 220-B in addition to a sub-processor 240 for providing computing power. The processor 220-B can be specifically used to read at least one set of instruction sets stored in the storage medium 210 to obtain target data, determine the N target computing powers corresponding to the above-mentioned N data processing, and determine or adjust the computing power allocation for the N data processing in the above-mentioned target process, and, after determining the computing power allocation in the above-mentioned target process, perform the above-mentioned N data processing, so as to process the above-mentioned target data into result data.

[0065] Figure 3B Another structural schematic diagram of a processing circuit provided according to an embodiment of the present application is shown. Referring to the processing circuit 004 shown in the figure, in some embodiments, specifically, the processing circuit 220 includes, in addition to the multi-core processor 220-A, a processor 220-C independent of the multi-core processor 220-A. The processor 220-C can be specifically used to read at least one set of instruction sets stored in the storage medium 210 to obtain target data, determine the N target computing powers corresponding to the above-mentioned N data processing, and determine or adjust the computing power allocation for the N data processing in the above-mentioned target process, and, after determining the computing power allocation in the above-mentioned target process, perform the above-mentioned N data processing, so as to process the above-mentioned target data into result data.

[0066] Figure 3C Another structural schematic diagram of a processing circuit provided according to an embodiment of the present application is shown. Referring to the processing circuit 005 shown in the figure, in some embodiments, specifically, the processing circuit 220 includes a processor 220-C independent of the multi-core processor 220-A in addition to the multi-core processor 220-A; at the same time, the multi-core processor 220-A includes a processor 220-B in addition to a sub-processor 240 for providing computing power. In this embodiment, the processor 220-C and / or the processor 220-B can be specifically used to read at least one set of instruction sets stored in the storage medium 210 to obtain target data, determine the N target computing powers corresponding to the above-mentioned N data processing, and determine or adjust the computing power allocation for the N data processing in the above-mentioned target process, and, after determining the computing power allocation in the above-mentioned target process, perform the above-mentioned N data processing, so as to process the above-mentioned target data into result data. That is to say, the above process of the data processing device can be implemented by processor 220-B alone, or by processor 220-C alone, or by processor 220-B and processor 220-C working together to execute the above process.

[0067] The embodiment of the present application does not limit the types of processors 220-B and 220-C, which may be any type of processor or a combination thereof as described above. It is understandable that: Figure 2 The data processing device 002 shown in the figure exemplifies the case where it includes only one processor 220-B and one processor 220-C. However, it should be noted that the data processing device 002 provided in the embodiment of the present application may also include multiple processors 220-B and multiple processors 220-C.

[0068] It can be understood by those skilled in the art that the processing circuit 220 may also include other hardware circuit structures, which are not limited in the embodiments of the present application, as long as they can meet the functions mentioned in the present application without deviating from the spirit of the present application.

[0069] Figure 4 1 shows a flow chart of a data processing method provided according to an embodiment of the present application. The data processing method P100 can be applied to the data processing device 002 as described above. Specifically, the processing circuit 220 can execute the data processing method P100. For example, the processor 220-B in the processing circuit 220 can execute the data processing method P100. Figure 4 As shown, the data processing method P100 may include: S410-S430, wherein the execution order of S410 and S420 is not particular, the processor 220-B may execute S410 first and then S420, the processor 220-B may also execute S420 first and then S410, and the processor 220-B may also execute S410 and S420 at the same time, and the embodiments of the present application are not limited to this.

[0070] S410: Obtain target data.

[0071] In some embodiments, processor 220 -B obtains target data.

[0072] In an exemplary embodiment, the target data is an audio signal to be processed by a data processing device, specifically, an original audio electrical signal received by the data processing device and not processed by the device, such as from an electronic device or a user. Specifically, the processor 220-B determines the original audio signal from the electronic device 110 or the user as the target data.

[0073] In another exemplary embodiment, for the processing operation performed on the audio signal, the "target data" is the intermediate audio signal to be subjected to the processing operation. For example, the audio signal is subjected to ADC sampling processing and noise reduction processing in sequence. For the noise reduction processing, the target data is the signal after ADC sampling processing. Similarly, the audio signal is subjected to noise reduction processing and Bluetooth SBC processing in sequence. For the Bluetooth SBC processing, the target data is the signal after A noise reduction processing. In some embodiments, specifically, after reading the execution data processing command, the processor 220-B determines a certain intermediate audio signal in the processing process as the target data of the data processing to be performed.

[0074] That is, since the processing object of the data processing method provided in the embodiment of the present application can be the original audio electrical signal received by the data processing device and not processed by the data processing device, the data processing device can perform the following operations on the received original audio signal: Figure 4 The data processing method shown in the embodiment of the present application; since the processing object of the data processing method provided in the embodiment of the present application can also be an intermediate audio signal after the audio processing device receives the original audio electrical signal and performs at least one audio signal processing, that is, the data processing device can perform the following processing on the intermediate audio signal during the processing. Figure 4 It can be seen that the data processing method provided by the embodiment of the present application has a wide range of applications and a flexible application mode, and can be applied to the original audio signal that has just been received and has not been processed, and can also be applied to the intermediate audio signal in the processing process.

[0075] In S420, N target computing powers corresponding to N data processing are determined.

[0076] Exemplarily, processor 220-B determines N target computing powers corresponding to N data processing operations.

[0077] In the case where the processing object is the original audio signal, the N-channel data processing may refer to a series of processing performed on the original audio signal. Figure 1 The microphone of the wireless headset 120 receives the original audio signal sent by the user during a call. Further, the processor 220-B determines a series of processing of the original audio signal and the computing power required for each processing (i.e., the target computing power). For example, the series of processing of the original audio signal includes: ADC sampling, noise reduction processing, Bluetooth SBC and Bluetooth radio frequency. In this embodiment, the target computing power p1 corresponding to ADC sampling, the target computing power p2 corresponding to noise reduction processing, the target computing power p3 corresponding to Bluetooth SBC and the target computing power p4 corresponding to Bluetooth radio frequency will be determined.

[0078] When the processing object is the intermediate audio signal, the N-channel data processing may refer to a series of processing performed on the intermediate audio signal. Figure 1 During a call, the microphone of the wireless headset 120 receives the original audio signal sent by the user and performs ADC sampling on the original audio signal. Further, the processor 220-B determines a series of processing of the intermediate audio signal after ADC sampling and the computing power required for each processing (i.e., the target computing power). For example, the series of processing of the intermediate audio signal after ADC sampling includes: noise reduction processing, Bluetooth SBC and Bluetooth radio frequency. In this embodiment, the target computing power p2 corresponding to the noise reduction processing, the target computing power p3 corresponding to the Bluetooth SBC and the target computing power p4 corresponding to the Bluetooth radio frequency will be determined.

[0079] Among them, the computing power measurement indicators can be Million Instructions Per Second (MIPS), Dhrystone Million Instructions executed Per Second (DMIPS), Operations Per Second (OPS), Floating point Operations Per Second (FLOPS), or Hash Per Second (Hash / s), etc.

[0080] In an embodiment of the present application, the method in which the processor 220-B obtains the target computing power corresponding to the target data processing in the N-channel data processing may be: determine the corresponding target computing power according to the actual operation of the above-mentioned target data processing. Specifically, the processor 220-B may determine the actual time required to run the above-mentioned target data processing on one core × MIPS when the system is initialized, thereby obtaining the precise value of the target computing power required to run each data processing to process the target data. In an exemplary embodiment, the above-mentioned storage medium 210 includes a storage area for "scheduling records". After determining the target computing power corresponding to the target data processed by the above-mentioned target data processing, the above-mentioned target primary processing may be associated with the target computing power corresponding to it and the attributes of the processed target data and stored in the above-mentioned "scheduling record" storage area (as shown in Table 1).

[0081] Table 1

[0082] N-channel data processing Target data attributes Target computing power ADC Sampling 16-bit audio signal x1 ADC Sampling 32-bit audio signal x2 Noise reduction 16-bit audio signal X3 …… …… ……

[0083] Taking the audio signal as an example, the attribute of the target data is related to the size of the space it occupies, for example, the attribute of the audio signal as the target data is 16 bits, 32 bits, etc. Referring to Table 1, in some embodiments, the processor 220-B determines that the computing power required to run the above ADC sampling process on one core to process a 16-bit audio signal is x1, and the processor 220-B determines that the computing power required to run the above ADC sampling process on one core to process a 32-bit audio signal is x2.

[0084] In the embodiment of the present application, the target computing power shown in Table 1 can be determined by actually running each data processing channel, and can also be manually set during the system initialization process. For example, the computing power required for the above-mentioned ADC sampling processing to process a 32-bit audio signal is set to x4, thereby providing a rich way to determine the target computing power corresponding to each data processing channel. It should be noted that for target data of the same attribute, the computing power required for the same data processing channel is certain. For example, the computing power required for the above-mentioned ADC sampling processing to process a 32-bit audio signal recorded in the storage area of ​​the storage medium 210 containing the "scheduling record" can only be x4, while the computing power required for the above-mentioned ADC sampling processing to process a 32-bit audio signal when there are different ADC sampling processings at the same time can only be x4 and x5, so as to ensure the smooth execution of the data processing method.

[0085] In some embodiments, the target computing power required for each data processing can be determined by searching the storage area of ​​the storage medium for the "scheduling record". Specifically, according to the attributes of the target data to be processed, the storage area of ​​the "scheduling record" (such as Table 1) can be searched to quickly obtain the target computing power required for processing multiple data of the target data with the above attributes, thereby helping to improve the processing efficiency of data (such as audio signals).

[0086] If there is no record in the storage area of ​​the above-mentioned "scheduling record", the processor 220-B cannot determine the target computing power by searching the storage area of ​​the "scheduling record". In some embodiments, for this situation, another method is provided for the processor 220-B to obtain the target computing power corresponding to the target channel data processing in the N channel data processing:

[0087] Processor 220-B determines the length of the code segment corresponding to the target data processing × the coefficient as the required computing power for running the target data processing, that is, obtaining the target computing power corresponding to the target data processing. The above coefficient is related to the properties of the processed target data, and can be set according to actual needs, which is not limited in the embodiment of the present application. Furthermore, the calculated target computing power can also be stored in the storage area of ​​the "scheduling record" in the format shown in Table 1, thereby enriching the storage area of ​​the "scheduling record" and facilitating subsequent searches for the target computing power.

[0088] Continue to refer Figure 4 , S430: In the target process, according to the N target computing powers and the preset optimization purpose, determine the allocation of the K cores in the multi-core processor participating in the target process in executing the N data processing.

[0089] As mentioned above, the target process refers to the process of generating result data by subjecting the target data to the N data processing. In the embodiment provided in the present application, in the target process, the processor 220-B determines the allocation of the K cores of the sub-processor in executing the N data processing according to the N target computing power and the preset optimization purpose. It should be noted that the cores participating in the target process may be part of the K cores of the sub-processor, or may be all the K cores.

[0090] Figure 5 FIG. 1 shows a schematic diagram of a processing circuit according to an embodiment of the present application. Figure 5 After obtaining the above-mentioned target data 500 and determining the N target computing powers 510 corresponding to the N data processing, the processing circuit 006 provided in the embodiment of the present application further allocates the core computing power to smoothly execute the N data processing (S30), and then the processing circuit 220 (specifically the processor 220-B) outputs the result data 520.

[0091] Exemplarily, the N data processing steps for the target data may be regarded as a data processing link for the target data. Figure 5 , the computing power executed by the processing circuit 220 (specifically, the processor 220-B) includes two allocation methods: initial allocation of computing power S10 and redistribution of computing power S20. Among them, the initial allocation of computing power refers to the allocation of computing power to the data processing link that has not been allocated computing power according to the computing power required for each data processing in a data processing link and the preset optimization target, so as to achieve the optimization purpose of maximizing the overall power consumption of the sub-processor and / or the most balanced load, while ensuring that each data processing can be executed smoothly to ensure the user's experience of the data processing device; after at least one computing power allocation, the computing power required for a certain data processing in a data processing link may change, and there may be insufficient computing power or excess computing power. Further, it is necessary to perform computing power redistribution according to the computing power required for each data processing after the change and the preset optimization target, which can be understood as adjusting the current computing power allocation of the data processing link to maintain the optimization purpose of maximizing the overall power consumption of the sub-processor and / or the most balanced load.

[0092] It should be noted that there may be a serial relationship in a data processing link for the target data. For example, when the above-mentioned target data is an audio signal, Bluetooth SBC is performed first and then Bluetooth RF. However, considering the timeliness of audio signal processing, the embodiment of the present application ensures that in the above-mentioned target process of a data processing link, sufficient computing power is continuously provided for all channel data processing, thereby ensuring the timeliness of audio signal processing and improving the user experience of the data processing device.

[0093] Figure 6 200 is a flowchart of a data processing method provided according to an embodiment of the present application. The data processing method P200 can be applied to the data processing device 002 as described above. Specifically, the processing circuit 220 can execute the data processing method P200. For example, the processor 220-B in the processing circuit 220 can execute the data processing method P200. Figure 6 As shown, S410 and S420 in the data processing method P200 are Figure 4 The specific implementation of the data processing method P100 is the same as that of the method P100, which will not be described in detail here; in addition, Figure 6 The data processing method P200 shown provides a specific implementation of S430, including S10, S610-S630.

[0094] S10: Execute the initial allocation of computing power.

[0095] Combination Figure 5 To illustrate, after obtaining the above-mentioned target data 500 and determining the N target computing powers 510 corresponding to the N data processing, the processing circuit 220 (for example, the processor 220-B) further executes S10 to perform an initial allocation of computing power to determine a target allocation plan. Based on the target allocation plan, the processor 220-B allocates the computing power of the K cores to the above-mentioned N data processing, and then performs the N data processing.

[0096] Figure 7 A flow chart of a method for initial allocation of computing power provided according to an embodiment of the present application is shown. The method for initial allocation of computing power P300 can be used as an implementation of the method for initial allocation of computing power S10, and can be applied to the data processing device 002 as described above. Specifically, in order to determine the allocation of the above-mentioned K cores in executing the above-mentioned N data processing, at least one set of instruction sets stored in the above-mentioned at least one storage medium corresponds to the method for initial allocation of computing power P300, wherein the processing circuit 220 can execute the method for initial allocation of computing power P300. For example, the processor 220-C in the processing circuit 220 can execute the method for initial allocation of computing power P300. As Figure 7 As shown, the data processing method P300 may include: S1010-S1020.

[0097] S1010: According to N target computing powers, M initial allocation schemes are determined to allocate corresponding cores for N data processing, wherein each initial allocation scheme satisfies that the computing power provided by each core is greater than or equal to the sum of the computing powers required for its corresponding data processing, and M is an integer greater than or equal to 1.

[0098] Exemplarily, in order to determine the above-mentioned M initial allocation schemes, at least one set of instruction sets stored in the above-mentioned at least one storage medium specifically includes: S1, determining the target total computing power required to execute the above-mentioned target process based on the above-mentioned N target computing powers; S2, determining the initial operating frequency of the above-mentioned K cores based on the above-mentioned target total computing power and the number K of cores providing computing power; S3, determining the K available computing powers corresponding to the above-mentioned K cores respectively based on the above-mentioned initial operating frequency; and S4, determining the above-mentioned M initial allocation schemes based on the above-mentioned N target computing powers and the K available computing powers.

[0099] Each of the M initial allocation schemes includes: at least one core participating in the target process, and the actual computing power provided by the at least one core participating in the target process and / or the actual operating frequency of the at least one core participating in the target process. In each initial allocation scheme, the maximum number of cores participating in the target process is K. Exemplarily, in an initial allocation scheme, the operating frequencies of all cores participating in the target process may be the same (such as the initial operating frequency), and of course, the operating frequencies of different cores participating in the target process may also be the same.

[0100] Specifically, the processor 220-B in the processing circuit 220 can execute the above S1-S4. Taking the data processing link of the audio signal received by the microphone of the wireless headset 120 during the call as an example, the processor 220-B of the aforementioned embodiment determines the target computing power corresponding to each data processing: the target computing power p1 corresponding to ADC sampling, the target computing power p2 corresponding to the noise reduction processing, the target computing power p3 corresponding to the Bluetooth SBC, and the target computing power p4 corresponding to the Bluetooth radio frequency, then the processor 220-B can determine the target total computing power required for the data processing link: P = p1 + p2 + p3 + p4. It can be understood that the factors affecting the FLOPS of the computing power include: the number of cores of the sub-processor providing computing power, the operating main frequency of the single core, and the floating-point calculation value of a single cycle of the sub-processor. During the initial allocation of computing power, if the initial operating frequencies of the cores in the sub-processor are consistent, and since the target total computing power P required by the data processing link, the number of cores K providing computing power for the sub-processor, and the floating-point calculation value of a single cycle of the sub-processor are known, the initial operating frequency of the above K cores can be determined, assuming it is f0.

[0101] Furthermore, processor 220-B determines the computing power that each core can provide according to the initial operating frequency f0, and the computing power that each core can provide is: f0×the floating-point calculation value of a single cycle of the sub-processor. Processor 220-B can determine M initial allocation schemes (as shown in Table 2) according to the target computing powers p1, p2, p3 and p4 required for N data processing, and the computing powers that K (assuming the value is 3) cores can provide. In this embodiment, each initial allocation scheme includes: the kernel identifier participating in the above target process, and the actual computing power provided by each core participating in the above target process when the operating frequency is f0.

[0102] Table 2

[0103] Kernel 1 Kernel 2 Kernel 3 Initial Allocation Plan 1 p1, p2 p3 p4 Initial Allocation Plan 2 p1, p2 p4 p3 Initial Allocation Plan 3 p3 p1 p2, p4 …… …… …… ……

[0104] It should be noted that, in order to ensure the smooth execution of the audio processing process, each initial allocation scheme satisfies that the computing power that each core can provide is greater than or equal to the sum of the computing power required by the target process, and the computing power that each core can provide is greater than or equal to the actual computing power provided. For example, referring to Table 2, in the initial allocation scheme 1, the computing power that core 1 can provide is greater than the actual computing power provided p1+p2, the computing power that core 2 can provide is greater than the actual computing power provided p3, and the computing power that core 3 can provide is greater than the actual computing power provided p4.

[0105] Continue to refer Figure 7 , S1020: Based on the optimization purpose, a first target allocation scheme is determined from the above M initial allocation schemes for execution.

[0106] In this embodiment, the first target allocation scheme determined based on the above-mentioned optimization purpose specifically refers to selecting an allocation scheme in which the target statistical value of the K cores actually providing computing power is the smallest among the optional multiple initial allocation schemes, wherein the above-mentioned statistical value is the variance or standard deviation. Alternatively, the first target allocation scheme determined by the above-mentioned optimization purpose specifically refers to the first target scheme selected from the optional multiple initial allocation schemes that can keep the overall power consumption of the K cores providing computing power in the sub-processor at the lowest level and / or the load most balanced. Through the above-mentioned optimization goal, a first target allocation scheme that meets the above-mentioned optimization goal can be determined from the above-mentioned M initial allocation schemes, and computing power is allocated based on the selected first target scheme. If the first target allocation scheme determined based on the above optimization objectives is initial allocation scheme 3 among the multiple initial allocation schemes shown in Table 2, then computing power is provided for Bluetooth SBC through core 1, computing power is provided for ADC sampling through core 2, and computing power is provided for noise reduction processing and Bluetooth radio frequency through core 3, and compared with other initial matching schemes shown in Table 2, the actual computing power provided by the three cores in initial allocation scheme 3 is: p3, p1 and p2+p4, and its statistical value is the smallest. Or compared with other initial matching schemes shown in Table 2, the actual computing power provided by the three cores in initial allocation scheme 3 is: p3, p1 and p2+p4, in which case the overall power consumption of the K cores providing computing power in the sub-processor can be kept lowest and / or the load is most balanced.

[0107] In an exemplary embodiment, the storage medium 210 includes a storage area for "scheduling records". After determining the first target allocation scheme, the relevant information of the first target allocation scheme can be stored in the storage area of ​​the "scheduling records". Exemplarily, referring to Table 3, the relevant information of the first target allocation scheme stored in the storage area of ​​"scheduling records" may include: the relationship between each data processing in the data processing link and the core that provides computing power for it, the attributes of the target data processed by the data processing link, and the identification of the data processing link.

[0108] Table 3

[0109] Link ID Kernel 1 Kernel 2 Kernel 3 Target data attributes Target allocation plan s1 p3 p1 p2, p4 16-bit audio signal …… …… …… ……

[0110] It should be noted that after the computing power is redistributed for the data processing link s1, if the relevant information of the target allocation scheme changes, the relevant information of the target allocation scheme obtained after the computing power is redistributed is used to update the record of the link in the storage area of ​​the "scheduling record". This can be used as another implementation method of the initial computing power allocation S10. When computing power is subsequently allocated to the data processing link s1, the computing power allocation scheme can be determined by searching from the above scheduling record, which is conducive to improving the processing efficiency of data (such as audio signals).

[0111] In summary, one implementation method for allocating computing power to the data processing link s1 can be to first determine the initial allocation scheme and then select from the initial allocation scheme as in the above embodiment; another implementation method for allocating computing power to the data processing link s1 is to determine by searching the table shown in Table 3 in the storage medium. At the same time, the embodiments of this specification also provide another implementation method for allocating computing power to the data processing link s1: based on a preset algorithm, and with the above optimization target as a constraint condition, according to the above N target computing powers and the K available computing powers corresponding to the above K cores, calculations are performed to determine at least one core participating in the above target process among the K cores, and to determine the actual operating frequency of at least one core participating in the above target process. Among them, the above preset algorithm is any algorithm that can implement the above process, and the embodiments of this application do not limit this.

[0112] Reference again Figure 6 After executing the initial allocation of computing power in S10, or after executing a certain redistribution of computing power, in the above-mentioned target process, the processing circuit (e.g., processor 220-B) also obtains monitoring results. In the exemplary embodiment of the present application, at least one of the following multiple monitoring methods is executed so that the processing circuit (e.g., processor 220-B) can obtain monitoring results and then determine whether the computing power allocation needs to be adjusted. The above-mentioned multiple monitoring methods include: 1) In the above-mentioned target process, the processing circuit 220 (for example, specifically the processor 220-B) is used to monitor whether the computing power required for each data processing has changed. Specifically, each data processing provides a monitoring interface for monitoring and outputting the current input data volume, current output data volume and current processed data volume of the data processing channel, so as to determine whether the computing power required for the data processing channel has changed; 2) In the above-mentioned target process, through hardware such as direct memory access (DMA), monitor whether "missing frames" occur; 3) In the above-mentioned target process, the processing circuit 220 (for example, specifically the processor 220-B) monitors the occupancy rate of the K cores that provide computing power. The occupancy rate of a core can be determined by the following formula.

[0113]

[0114] The monitoring method provided by the above embodiment can determine in real time whether there is a change in the computing power required for N-channel data processing, so as to dynamically determine whether computing power needs to be redistributed, thereby achieving the lowest power consumption of the device while ensuring that data (such as audio signals) are processed smoothly. Among them, the computing power required for N-channel data processing in the data processing link may increase or decrease, so it is necessary to determine whether computing power needs to be redistributed based on the monitoring results. For specific reference, Figure 5If the computing power required for processing N data channels does not change during the above-mentioned target process, the processing circuit 220 can allocate computing power based on the initial allocation of computing power (i.e., S10), and the result data 520 can be obtained; if the computing power required for processing N data channels changes during the above-mentioned target process, it is necessary to determine whether computing power needs to be allocated again based on the monitoring results. If computing power needs to be allocated again (i.e., executing S20), it is necessary to determine what computing power reallocation plan to execute based on the above-mentioned monitoring results.

[0115] The monitoring results of the above-mentioned monitoring method 1) include that in the above-mentioned target process, if the computing power required for the i-th (i is 1, 2, ..., N) channel data processing changes, and it is further determined that the core that provides computing power for the i-th channel data processing is the j-th (j is 1, ..., K) core, the method for determining whether the j-th core has insufficient computing power is: if the audio processing for which the computing power is provided by the j-th core is the i-th and i+1-th channels, further, based on the required computing power after the change in the i-th channel data processing and the required computing power after the change in the i+1-th channel data processing, the occupancy rate of the j-th core is determined; if the occupancy rate is greater than a first threshold value (e.g., 80%), the core that provides computing power for the channel data processing may have insufficient computing power; if the occupancy rate is less than a second threshold value (e.g., 40%), the core that provides computing power for the channel data processing may have excess computing power.

[0116] The monitoring results of the above monitoring method 2) include: in the above target process, there is no "missing frame" phenomenon, indicating that all cores providing computing power in the data processing link do not have insufficient computing power, that is, the current target allocation plan for the data processing link can be maintained; in the above target process, there is a "missing frame" phenomenon, indicating that at least one core providing computing power in the data processing link has insufficient computing power, and computing power needs to be redistributed in order to avoid the user's poor experience of audio stuttering. Among them, the specific implementation method of computing power redistribution will be described in detail in subsequent embodiments.

[0117] The monitoring results of the above-mentioned monitoring method 3) include that in the above-mentioned target process, if the kernel occupancy rate of any of the K kernels is greater than the first threshold value (such as 80%), it means that the kernel has insufficient computing power; in the above-mentioned target process, if the kernel occupancy rate of any of the K kernels is less than the second threshold value (such as 40%), it means that the kernel has excess computing power. In order to avoid users from having a bad experience of audio stuttering in the event of insufficient computing power, and to optimize computing power allocation in the event of excess computing power, computing power redistribution is required. Among them, the specific implementation method of computing power redistribution will be described in detail in subsequent embodiments.

[0118] According to the above monitoring results, the following situations may exist in the above target process: situation 1, there are cores with insufficient computing power but no cores with excess computing power, situation 2, there are both cores with insufficient computing power and cores with excess computing power, situation 3, there are cores with excess computing power but no cores with insufficient computing power, and situation 4, there are neither cores with insufficient computing power nor cores with excess computing power (it is possible that the computing power required for accessing N-channel data processing does not change, or the occupancy rate of each core after the change is still within the preset range).

[0119] Since the existence of a core with insufficient computing power may affect the smooth execution of N-channel data processing, in order to avoid data (such as audio signal) processing jams, the situation of the core with insufficient computing power (i.e., situation 1 and situation 2) is given priority. Figure 6 , execute S620: determine whether there is a core with insufficient computing power according to the monitoring result. If yes, execute embodiment A, or execute embodiment B, or execute embodiment C, or execute embodiment D. The following embodiments will respectively introduce embodiment A, embodiment B, embodiment C and embodiment D in detail.

[0120] When it is determined that at least one core has insufficient computing power, in order to ensure the user experience of the data processing device and avoid data (such as audio signal processing) process jams, the operating frequency of the sub-processor 240 is increased. The specific implementation methods for increasing the operating frequency of the sub-processor can be divided into the following two (ie, embodiment A and embodiment B).

[0121] In exemplary embodiment A for solving the problem of insufficient computing power of at least one core, when it is determined that there is insufficient computing power of at least one core, the operating frequency of the above-mentioned K cores is increased to increase the computing power provided by the above-mentioned sub-processor 240 as a whole, thereby quickly solving the problem of jamming in the data (such as audio signal) processing process.

[0122] In exemplary embodiment B for solving the problem of insufficient computing power of at least one core, when it is determined that at least one core has insufficient computing power, the core with insufficient computing power is further located, and the operating frequency of the core with insufficient computing power is further increased to specifically improve the computing power provided by the relevant core in the above-mentioned sub-processor 240, thereby being able to solve the problem of jamming in the data (such as audio signal) processing process while avoiding excessive power consumption of the data processing device.

[0123] It can be understood that if the core with insufficient computing power can be accurately located (such as the monitoring results of monitoring method 1) or the monitoring results of monitoring method 3), then exemplary embodiment B for solving the problem of insufficient computing power of at least one core can be executed, so as to solve the problem of data (such as audio signal) processing jams while avoiding excessive power consumption of the data processing device.

[0124] It is understandable that if the core with insufficient computing power cannot be accurately located (e.g., the monitoring result of monitoring mode 2 is "missing frames"), then exemplary embodiment A for solving the problem of insufficient computing power of at least one core is executed to quickly solve the problem of data (e.g., audio signal) processing jams. Of course, the use of exemplary embodiment A for solving the problem of insufficient computing power of at least one core has the problem of power consumption to be optimized, but the problem of excess computing power of at least one core can be solved by executing exemplary embodiment E, which will be described in detail below.

[0125] Figure 8 A schematic diagram showing the relationship between the operating frequency of the processor core and the power consumption of the processor, as well as a schematic diagram showing the relationship between the number of operating cores of the processor and the power consumption of the processor, provided according to an embodiment of the present application. Referring to the relationship diagram 007, the four curves respectively represent the situations of 1 to 4 operating cores from bottom to top. It can be seen that the operating frequency of the core in the processor is positively correlated with the power consumption of the processor, and the number of operating cores in the processor is also positively correlated with the power consumption of the processor. According to the aforementioned embodiment A and embodiment B, when it is determined that at least one core has insufficient computing power, the computing power that can be provided by the core is increased by increasing the core frequency, thereby ensuring the user experience of the data processing device. However, according to Figure 8 As shown in the relationship diagram 007, it can be seen that the above-mentioned embodiment A and embodiment B increase the core operating frequency may cause the problem of excessive power consumption of the data processing device. In order to avoid excessive power consumption of the data processing device, in the case of insufficient computing power, the following can also be used Fig. 9 The computing power redistribution scheme shown.

[0126] Fig. 9 A flow chart of a method for reallocating computing power in the case of insufficient computing power provided according to an embodiment of the present application is shown. The computing power reallocation method P400 can be used as an exemplary embodiment C for solving the problem of insufficient computing power of at least one core, and can be applied to the data processing device 002 as described above. Among them, the processing circuit 220 can execute P400 in the case of insufficient computing power. For example, the processor 220-B in the processing circuit 220 can execute the computing power reallocation method P400. Fig. 9 As shown, the data processing method P400 may include: S2010-S2030.

[0127] S2010: Determine that the computing power provided by the p-th core for processing the j-th data channel is insufficient.

[0128] In some embodiments, the processor 220-B can determine that the occupancy rate of the second core is 91% according to the monitoring result of monitoring method 1) or according to the monitoring result of monitoring method 3), indicating that the computing power of the second core is insufficient. The second core provides computing power for the first data processing and the third data processing. If the occupancy rate of the second core that only provides computing power for the first data processing is less than the first threshold, if the occupancy rate of the second core that only provides computing power for the third data processing is still greater than the first threshold, it can be explained that the computing power provided by the second core for the third data processing is insufficient.

[0129] In this embodiment, the processor 220-B can move the third data processing from the second core to another core, that is, adjust the cores other than the second core to provide computing power for the third data processing, so that the second core is only used to provide computing power for the first data processing, which can ensure the smooth execution of the first data processing. Specifically, S2020 can be executed: determine the qth core from the K cores to provide computing power for the jth data processing, and execute S2030: transfer the execution of the jth data processing from the pth core to the qth core.

[0130] Specifically, processor 220-B calculates which core's occupancy rate is less than the first threshold if computing power is provided to the second core based on the current occupancy rates of cores other than the second core and the target computing power required for the third data processing. If it is determined that the occupancy rate of the fifth core will reach 70% (less than the first threshold) if it provides computing power for the third data processing in addition to providing computing power for one or more data processing originally assigned to it, then processor 220-B determines the fifth core from the K cores to provide computing power for the third data processing, and transfers the execution of the third data processing from the second core to the fifth core. Obviously, in this example, p takes the value of 2, j takes the value of 3, and q takes the value of 5.

[0131] In this embodiment, after the processor 220-B determines that the 5th core from the above-mentioned K cores provides computing power for the above-mentioned 3rd data processing, and before transferring the execution of the above-mentioned 3rd data processing from the above-mentioned 2nd core to the above-mentioned 5th core, the operating frequency of the 5th core can be increased to increase the computing power of the 5th core, thereby avoiding the data (such as audio signal) processing process from being stuck due to the instantaneous increase in the occupancy rate of the 5th core after the 3rd data processing is transferred.

[0132] In this embodiment, after the processor 220-B determines that the computing power provided by the second core for the third data processing is insufficient, the processor 220-B can directly increase the operating frequency of the second core to increase the computing power of the second core, thereby avoiding the jamming problem caused by the third data processing or the first data processing. Of course, when the operating frequency of the second core cannot be increased, the embodiments provided in S2020 and S2030 can be executed to ensure the smooth execution of the data processing link.

[0133] In the case where it is determined based on the monitoring results that there are kernels with insufficient computing power, an embodiment D is also provided: the above-mentioned M kinds of initial allocation schemes can be screened to determine whether there is an initial allocation scheme that can provide sufficient computing power for the current computing power demand after the computing power changes. If there is an initial allocation scheme that can provide sufficient computing power for the current computing power demand, computing power is allocated according to the initial allocation scheme, and it can be further determined whether there is room for computing power optimization. If there are two or more initial allocation schemes that can provide sufficient computing power for the current computing power demand, the initial allocation schemes that meet the above-mentioned optimization purpose are further screened out for computing power allocation, and it can be further determined whether there is room for computing power optimization. Specifically, in the case where there is room for computing power optimization, the following embodiment E can be executed to achieve the purpose of reducing equipment power consumption while ensuring the smooth execution of N-channel data processing.

[0134] It should be noted that when it is determined based on the monitoring results that there is a core with insufficient computing power, one or more of Embodiment A, Embodiment B, Embodiment C and Embodiment D may be executed based on actual needs, and the embodiments of the present application are not limited to this.

[0135] Reference again Figure 6 , when it is determined through S620 that there are no kernels with insufficient computing power (case 3, case 4), S630 is further executed: determine whether there are kernels with excess computing power based on the monitoring results. That is to say, while giving priority to ensuring the smooth execution of each data processing process, consider optimizing the computing power allocation of N data processing to minimize the power consumption of the device. If it is determined through S630 that there are kernels with excess computing power, the current situation is that there are kernels with excess computing power but no kernels with insufficient computing power. The embodiment of the present application can execute embodiment E or embodiment F to optimize the computing power allocation to achieve the effect of reducing the power consumption of the device.

[0136] Fig.10The flowchart of the method for reallocating computing power in the case of excess computing power provided in accordance with an embodiment of the present application is shown. The computing power reallocation method P500 can be used as an exemplary embodiment E for the case where there are cores with excess computing power, and can be applied to the data processing device 002 as described above. Among them, the processing circuit 220 can execute P500 in the case where there are cores with excess computing power and there are no cores with insufficient computing power. For example, the processor 220-B in the processing circuit 220 can execute the computing power reallocation method P500. Fig.10 As shown, the data processing method P500 may include: S2010'-S2030'.

[0137] S2010': In the process of executing the above-mentioned target, it is determined that there is an idle core whose computing power occupancy rate is less than a second threshold value among the above-mentioned K cores, and the idle core is stopped from executing corresponding data processing.

[0138] When processor 220-B determines that there is a core with excess computing power, that is, there is a core whose occupancy rate is less than the second threshold (referred to as: idle core), in order to optimize device power consumption while ensuring the user's audio listening experience, this embodiment of the application will execute 'S2020' and S2030'.

[0139] In S2020', L reallocation schemes are determined based on the target computing power corresponding to the above-mentioned N data processings and at least one working core other than the idle core among the above-mentioned K cores, wherein under each reallocation scheme, the total computing power provided by the above-mentioned at least one working core is greater than or equal to the total computing power required to execute the above-mentioned target process, and L is an integer greater than or equal to 1.

[0140] In an exemplary embodiment, K takes a value of 4. If there is a core whose occupancy rate is less than the second threshold, the reallocation scheme is determined based on the computing power that can be provided by the other three cores except the idle core and the target computing power required for the above-mentioned N-channel data processing. If 5 reallocation schemes are determined, for each of the 5 reallocation schemes, the total computing power provided by the other three cores except the idle core is greater than or equal to the total computing power required for executing the above-mentioned target process, that is, each reallocation scheme can ensure the smooth execution of the target process.

[0141] Specifically, if the number of cores other than the idle core that can provide computing power is Q (an integer greater than 1), determine the specific implementation methods of the above-mentioned L reallocation schemes: In order to determine the above-mentioned M initial allocation schemes, the at least one set of instruction sets stored in the above-mentioned at least one storage medium specifically includes: S1', based on the above-mentioned N target computing powers, determine the target total computing power required to execute the above-mentioned target process; S2', based on the above-mentioned target total computing power, calculate the operating frequency of the above-mentioned Q cores; S3', based on the above-mentioned determined operating frequency and the number of cores Q that provide computing power, determine the Q computing powers that can be provided corresponding to the above-mentioned Q cores respectively; and S4', determine the above-mentioned L initial allocation schemes based on the above-mentioned N target computing powers and the Q computing powers that can be provided.

[0142] Specifically, the processor 220-B in the processing circuit 220 can execute the above S1'-S4'. Taking the data processing link of the microphone of the wireless headset 120 for the audio signal received and sent by the user during the call as an example, the processor 220-B of the aforementioned embodiment determines the target computing power corresponding to each data processing: the target computing power q1 corresponding to ADC sampling, the target computing power q2 corresponding to the noise reduction processing, the target computing power q3 corresponding to the Bluetooth SBC, and the target computing power q4 corresponding to the Bluetooth radio frequency, then the processor 220-B can determine the target total computing power required for the data processing link: P'=q1+q2+q3+q4. It can be understood that the factors affecting the FLOPS of the computing power include: the number of cores of the sub-processor providing computing power, the operating main frequency of the single core, and the floating-point calculation value of a single cycle of the sub-processor. In the process of redistributing the computing power, if the initial operating frequencies of the cores in the sub-processor are consistent, and since the target total computing power P' required by the data processing link, the number of cores Q providing computing power by the sub-processor, and the floating-point calculation value of a single cycle of the sub-processor are known, the operating frequencies of the above Q cores can be determined, suppose to be f0'.

[0143] Furthermore, processor 220-B determines the computing power that can be provided by each of the Q cores according to the operating frequency f0', and the computing power provided by each core is: f0'×the floating-point calculation value of a single cycle of the sub-processor. Processor 220-B can determine L initial allocation schemes (as shown in Table 4) according to the target computing power q1, q2, q3 and q4 required for N data processing and the computing power that can be provided by Q (assuming the value is 3) cores.

[0144] Table 4

[0145] Kernel 1 Kernel 2 Kernel 3 Redistribution Scheme 1 q1 q3, q2 q4 Redistribution Scheme 2 q1 q4, q2 q3 Redistribution Scheme 3 q3 q1 q2, q4 …… …… …… ……

[0146] It should be noted that in order to ensure the smooth execution of the audio processing process, each reallocation scheme satisfies that the computing power that each core can provide is greater than or equal to the sum of the computing power required for its corresponding data processing. For example, referring to Table 4, in reallocation scheme 1, the computing power that core 1 can provide is greater than q3, the computing power that core 2 can provide is greater than q3+q2, and the computing power that core 3 can provide is greater than q4. Of course, in reallocation scheme 1, the sum of the computing power that cores 1, 2, and 3 can provide is greater than the target total computing power P' required for the data processing link.

[0147] In S2030′, based on the optimization objective, a second target allocation scheme is determined from the L reallocation schemes, and the computing power of the at least one working core in executing the N data processing is allocated by the second target allocation scheme.

[0148] In this embodiment, the second target allocation scheme determined based on the above-mentioned optimization purpose specifically refers to selecting an allocation scheme in which the target statistical value of the K cores actually providing computing power corresponding to the above-mentioned K cores is the smallest among the optional multiple reallocation schemes, wherein the above-mentioned statistical value is the variance or standard deviation. Alternatively, the second target allocation scheme determined by the above-mentioned optimization purpose specifically refers to the second target scheme selected from the optional multiple reallocation schemes that can keep the overall power consumption of the K cores providing computing power in the sub-processor at the lowest level and / or the load most balanced. Through the above-mentioned optimization goal, a second target allocation scheme that meets the above-mentioned optimization goal can be determined from the above-mentioned L reallocation schemes, and computing power is allocated based on the selected second target scheme. If the second target allocation scheme determined based on the above optimization objectives is the reallocation scheme 2 among the multiple reallocation schemes shown in Table 4, then the computing power is provided for Bluetooth SBC through core 1, the computing power is provided for ADC sampling and Bluetooth radio frequency through core 2, and the computing power is provided for noise reduction processing through core 3, and compared with other reallocation schemes shown in Table 4, the actual computing power provided by the three cores in the reallocation scheme 2 is: q1, p2+p4 and q3, and its statistical value is the smallest. Or compared with other reallocation schemes shown in Table 4, the actual computing power provided by the three cores in the reallocation scheme 2 is: q1, p2+p4 and q3, in which case the overall power consumption of the Q cores providing computing power in the sub-processor can be kept lowest and / or the load is most balanced.

[0149] When it is determined based on the monitoring results that there is no core with insufficient computing power and that there is a core with excess computing power, embodiment F is also provided: locating the core with excess computing power, and further, based on the first threshold (e.g., 80%) and the second threshold (e.g., 40%) set for the occupancy rate, reducing the operating frequency of the core so that the occupancy rate of the core after the operating frequency is reduced is between the second threshold and the first threshold, that is, there is no excess or insufficient computing power, thereby reducing the power consumption of the sub-processor while ensuring that each data processing channel has sufficient computing power, which is beneficial to reducing the power consumption of the audio processing device.

[0150] As in the above embodiment, the storage medium 210 includes a storage area for "scheduling records". After determining the second target allocation scheme, the previous target allocation scheme that uses the same data processing link to process the same target data and has been stored in the storage area of ​​"scheduling records" can be updated through the second target allocation scheme. Exemplary 3, the relevant information of the second target allocation scheme stored in the storage area of ​​"scheduling records" may include, for example, the relationship between each data processing in the data processing link and the core that provides computing power for it, the attributes of the target data processed by the data processing link, and the data processing link, etc.

[0151] Continue to refer Figure 6 If it is determined through S630 that there are no cores with excess computing power, and the current situation is that there are neither cores with excess computing power nor cores with insufficient computing power, then the embodiment of the present application executes S610 again to continuously monitor the computing power required for each data processing channel during the above-mentioned target process, so as to minimize the power consumption of the device while ensuring that sufficient computing power is allocated to each data processing channel during the entire target process.

[0152] In summary, the data processing device and data processing method provided by the embodiment of the present application, wherein the processing circuit 220 includes a multi-core processor 220-A, and the multi-core processor 220-A includes a sub-processor 240 of K cores for participating in the target process of generating result data by processing the target data through N data. Specifically, the processing circuit 220 obtains the above-mentioned target data, and determines the N target computing powers corresponding to the above-mentioned N data processing, and in the above-mentioned target process, according to the above-mentioned N target computing powers and the preset optimization purpose, determines the allocation of the above-mentioned K cores in executing the above-mentioned N data processing. It can be seen that the scheme provided by the present application can determine the computing power provided by the K cores for the N data processing respectively during the operation of the data processing device, and adaptively allocate the corresponding target computing power to each data processing. For example, if one or more data processing is added, replaced, or deleted for a certain data processing link, the data processing device can adaptively adjust the computing power allocation. It can be seen that the scheme provided by the embodiment of the present application is conducive to adapting to the expansion of the data processing link. At the same time, compared with the related art that requires advance planning of one or more data processing channels that each core is responsible for, the method provided by the present application is conducive to improving the flexibility of computing power allocation.

[0153] On the other hand, the present application provides a non-transitory storage medium storing at least one set of executable instructions for data processing. When the executable instructions are executed by the processor, the executable instructions instruct the processor to implement the steps of the data processing method P100 described in the present application. In some possible implementations, various aspects of the present application can also be implemented in the form of a program product, which includes a program code. When the program product is run on an acoustic system, the program code is used to make the acoustic system perform the steps of the data processing method P100 described in the present application. The program product for implementing the above method can use a portable compact disk read-only memory (CD-ROM) to include program code and can be run on an acoustic system. However, the program product of the present application is not limited to this. In the present application, a readable storage medium can be any tangible medium containing or storing a program, which can be used by an instruction execution system or used in combination with it. The program product can use any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of readable storage media include: an electrical connection with one or more conductors, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. The computer-readable storage medium may include a data signal propagated in a baseband or as part of a carrier wave, wherein a readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The readable storage medium may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, device, or device. The program code contained on the readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination of the above. Program code for performing the operations of the present application may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the acoustic system, partially on the acoustic system, as a stand-alone software package, partially on the acoustic system and partially on a remote computing device, or entirely on a remote computing device.

[0154] The above describes specific embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require a specific order or a continuous order to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0155] In summary, after reading this detailed disclosure, those skilled in the art will appreciate that the foregoing detailed disclosure may be presented only by way of example and may not be restrictive. Although not explicitly stated herein, those skilled in the art will appreciate that the requirements of this application encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are intended to be proposed by the present application and are within the spirit and scope of the exemplary embodiments of the present application.

[0156] In addition, certain terms in this application have been used to describe embodiments of the present application. For example, "one embodiment", "embodiment" and / or "some embodiments" mean that a particular feature, structure or characteristic described in conjunction with the embodiment may be included in at least one embodiment of the present application. Therefore, it can be emphasized and should be understood that two or more references to "embodiment" or "one embodiment" or "alternative embodiment" in various parts of the present application do not necessarily refer to the same embodiment. In addition, specific features, structures or characteristics can be appropriately combined in one or more embodiments of the present application.

[0157] It should be understood that in the foregoing description of the embodiments of the present application, in order to help understand a feature and for the purpose of simplifying the present application, the present application combines various features in a single embodiment, drawing or its description. However, this does not mean that the combination of these features is necessary. When reading the present application, it is entirely possible for a person skilled in the art to mark out a part of the devices as a separate embodiment. In other words, the embodiments in the present application can also be understood as the integration of multiple secondary embodiments. This is also true when the content of each secondary embodiment is less than all the features of a single aforementioned disclosed embodiment.

[0158] Each patent, patent application, patent application publication, and other material, such as articles, books, specifications, publications, documents, articles, etc., cited herein, except any historical prosecution documents to which it is relevant, any equivalent that may be inconsistent or conflicting with this document, or any equivalent historical prosecution documents that may have a limiting effect on the broadest scope of the claims, may be incorporated herein by reference and used for all purposes now or hereafter associated with this document. In addition, in the event of any inconsistency or conflict between the descriptions, definitions, and / or use of terms associated with any of the incorporated materials and the terminology, descriptions, definitions, and / or use associated with this document, the terminology in this document shall control.

[0159] Finally, it should be understood that the embodiments of the application disclosed herein are explanations of the principles of the embodiments of the present application. Other modified embodiments are also within the scope of the present application. Therefore, the embodiments disclosed in the present application are merely examples and not limitations. Those skilled in the art can adopt alternative configurations according to the embodiments in the present application to implement the application in the present application. Therefore, the embodiments of the present application are not limited to the embodiments accurately described in the application.

Claims

1. A data processing device, characterized in that: include: at least one storage medium storing at least one set of instruction sets, wherein the at least one set of instruction sets is used to perform computing power scheduling in a target process of generating result data by subjecting target data to N data processing steps; and A processing circuit includes a multi-core processor and is communicatively connected to the at least one storage medium, wherein the multi-core processor includes K core sub-processors to participate in the target process, K is an integer greater than 1, Wherein, when the data processing device is running, the processing circuit executes the at least one set of instruction sets to: Get the target data, Determine N target computing powers corresponding to the N data processing, and In the target process, the allocation of the K cores in executing the N data processing is determined according to the N target computing powers and the preset optimization purpose.

2. The data processing device according to claim 1, characterized in that To determine the allocation of the K cores to perform the N data processing, the processing circuit executes the at least one set of instruction sets to: According to the N target computing powers, M initial allocation schemes are determined to allocate corresponding cores to the N data processing, wherein each of the initial allocation schemes satisfies that the computing power provided by each core is greater than or equal to the sum of the computing powers required for the corresponding data processing, and M is an integer greater than or equal to 1; as well as Based on the optimization purpose, a first target allocation scheme is determined from among the M initial allocation schemes for execution.

3. The data processing device according to claim 2, characterized in that To determine the M initial allocation schemes, the processing circuit executes the at least one set of instruction sets to: Determining a target total computing power required to execute the target process according to the N target computing powers; Determining initial operating frequencies of the K cores according to the target total computing power; Determine, according to the initial operating frequency, the K computing powers that correspond to the K cores respectively; as well as M initial allocation schemes are determined according to the N target computing powers and the K available computing powers.

4. The data processing device according to claim 2, characterized in that Each of the M initial allocation schemes includes: at least one core participating in the target process, and the actual provided computing power of the at least one core participating in the target process and / or the actual operating frequency of the at least one core participating in the target process.

5. The data processing device according to claim 1, characterized in that To determine the allocation of the K cores to perform the N data processing, the processing circuit executes the at least one set of instruction sets to: Based on a preset algorithm, according to the N target computing powers, the K computing powers that can be provided respectively corresponding to the K cores, and the optimization purpose, at least one core participating in the target process is determined among the K cores, and the actual operating frequency of the at least one core participating in the target process is determined.

6. The data processing device according to claim 1, characterized in that The optimization purpose is to select, from among multiple optional allocation schemes, an allocation scheme in which the target statistical value of the K cores actually providing computing power is the smallest, wherein the statistical value is the variance or standard deviation.

7. The data processing device according to claim 1, characterized in that The optimization objectives include: The overall power consumption of the K cores is kept to be the lowest and / or the load is kept to be the most balanced.

8. The data processing device according to claim 1, characterized in that The processing circuitry also executes the at least one set of instructions to: During the execution of the target, determining that the K cores have insufficient computing power; and The operating frequencies of the K cores are increased to increase the computing power provided by the sub-processors to avoid data processing stalls.

9. The data processing device according to claim 1, characterized in that The processing circuitry also executes the at least one set of instructions to: In the process of executing the target, determining that there are O cores among the K cores that have insufficient computing power, where O is a positive integer not greater than K; as well as Increase the operating frequency of the O cores to increase the computing power of the qth core to avoid data processing jams.

10. The data processing device according to claim 9, characterized in that The insufficient computing power includes: a computing power occupancy rate of any one of the K cores exceeds a first threshold.

11. The data processing device according to claim 1, characterized in that The processing circuitry also executes the at least one set of instructions to: In the process of executing the target, determining that there is an idle core whose computing power occupancy rate is less than a second threshold value among the K cores, and stopping the idle core from executing corresponding data processing; Determine L reallocation schemes according to the N target computing powers and at least one working core among the K cores except the idle core, wherein under each of the reallocation schemes, a total computing power provided by the at least one working core is greater than or equal to a total computing power required to execute the target process, and L is an integer greater than or equal to 1; as well as Based on the optimization purpose, a second target allocation scheme is determined from the L reallocation schemes, and the computing power of the at least one working core in executing the N data processing is allocated through the second target allocation scheme.

12. The data processing device according to claim 1, characterized in that To achieve the optimization goal, the processing circuit further executes the at least one set of instruction sets to: In the process of performing the objective, it is determined that the computing power provided by the pth core for processing the jth data channel is insufficient; Determine the qth kernel from the K kernels to provide computing power for the jth data processing; as well as The execution of the j-th data processing is transferred from the p-th core to the q-th core.

13. The data processing device according to claim 12, characterized in that The processing circuitry also executes the at least one set of instructions to: Before transferring the execution of the j-th data processing from the p-th core to the q-th core, increasing the operating frequency of the q-th core to increase the computing power of the q-th core to avoid data processing stalls.

14. The data processing device according to claim 1, characterized in that The processing circuitry also executes the at least one set of instructions to: In the process of executing the target, determining that there are R cores among the K cores that have insufficient computing power, where R is a positive integer not greater than K; When there is an idle core whose computing power utilization rate is less than the second threshold value among the K cores, at least part of the data processing corresponding to the R cores is transferred to the idle core, wherein after the transfer, the computing power that can be provided by each core is greater than or equal to the sum of the computing powers required for the corresponding data processing.

15. The data processing device according to claim 1, characterized in that The at least one storage medium is further associated with storing: attributes of target data and target computing power corresponding to at least one data processing step for the target data; In order to determine the N target computing powers corresponding to the N data processing, the processing circuit executes the at least one set of instruction sets to: According to the attributes of the obtained target data, the at least one storage medium is searched to obtain N target computing powers corresponding to the N data processing operations on the target data.

16. The data processing device according to claim 15, characterized in that The processing circuitry executes the at least one set of instructions to: In a case where the at least one storage medium does not store N target computing powers corresponding to N data processings of the target data of the target attribute, calculating the N target computing powers respectively required for processing the N data processings of the target data of the target attribute; as well as The N target computing powers corresponding to the N data processing steps performed on the target data of the target attribute are associated with the target attribute and stored in the at least one storage medium.

17. The data processing device according to claim 1, characterized in that The at least one storage medium further stores: for multiple attributes of target data, kernel identifiers for processing the target data of each attribute and providing computing power for the N data processing respectively; To determine the allocation of the K cores to perform the N data processing, the processing circuit executes the at least one set of instruction sets to: According to the target attribute of the obtained target data, the at least one storage medium is searched to obtain the kernel identification that processes the target data with the target attribute and provides computing power for the N data processing respectively, thereby determining the allocation of the K kernels in executing the N data processing.

18. The data processing device according to claim 1, characterized in that The data processing device is a headset.

19. A data processing method, characterized in that: include: Get the target data, Determine the N target computing power corresponding to N data processing, and In the target process, according to the N target computing powers and the preset optimization purpose, determining the allocation of K cores in the multi-core processor participating in the target process in executing the N data processing, where K is an integer greater than 1; The target process is a process of generating result data by subjecting the target data to the N data processing steps.

20. The data processing method according to claim 19, characterized in that: The determining of the allocation of the K cores for executing the N data processing comprises: According to the N target computing powers, determine M initial allocation schemes to allocate corresponding cores to the N data processing, wherein each of the initial allocation schemes satisfies that the computing power that can be provided by each core is greater than or equal to the sum of the computing powers required for the corresponding data processing, and M is an integer greater than or equal to 1; and Based on the optimization purpose, a first target allocation scheme is determined from among the M initial allocation schemes for execution.

21. The data processing method according to claim 20, characterized in that: Wherein, determining the M initial allocation schemes comprises: Determining a target total computing power required to execute the target process according to the N target computing powers; Determining initial operating frequencies of the K cores according to the target total computing power; Determine, according to the initial operating frequency, the K computing powers that correspond to the K cores respectively; and M initial allocation schemes are determined according to the N target computing powers and the K available computing powers.

22. The data processing method according to claim 20, characterized in that: Each of the M initial allocation schemes includes: at least one core participating in the target process, and the actual provided computing power of the at least one core participating in the target process and / or the actual operating frequency of the at least one core participating in the target process.

23. The data processing method according to claim 19, characterized in that: To determine the allocation of the K cores to perform the N data processing, the processing circuit executes the at least one set of instruction sets to: Based on a preset algorithm, according to the N target computing powers, the K computing powers that can be provided respectively corresponding to the K cores, and the optimization purpose, at least one core participating in the target process is determined among the K cores, and the actual operating frequency of the at least one core participating in the target process is determined.

24. The data processing method according to claim 19, characterized in that: The optimization purpose is to select, from among multiple optional allocation schemes, an allocation scheme in which the target statistical value of the K cores actually providing computing power is the smallest, wherein the statistical value is the variance or standard deviation.

25. The data processing method according to claim 19, characterized in that: The optimization objectives include: The overall power consumption of the K cores is kept to be the lowest and / or the load is kept to be the most balanced.

26. The data processing method according to claim 19, characterized in that: Also includes: During the execution of the target, it is determined that the K cores have insufficient computing power; as well as The operating frequencies of the K cores are increased to increase the computing power provided by the sub-processors to avoid data processing stalls.

27. The data processing method according to claim 19, characterized in that: Also includes: In the process of executing the target, determining that there are O cores among the K cores that have insufficient computing power, where O is a positive integer not greater than K; as well as Increase the operating frequency of the O cores to increase the computing power of the qth core to avoid data processing jams.

28. The data processing method according to claim 27, characterized in that: The insufficient computing power includes: a computing power occupancy rate of any one of the K cores exceeds a first threshold.

29. The data processing method according to claim 19, characterized in that: Also includes: In the process of executing the target, determining that there is an idle core whose computing power occupancy rate is less than a second threshold value among the K cores, and stopping the idle core from executing corresponding data processing; Determine L reallocation schemes according to the N target computing powers and at least one working core among the K cores except the idle core, wherein under each of the reallocation schemes, a total computing power provided by the at least one working core is greater than or equal to a total computing power required to execute the target process, and L is an integer greater than or equal to 1; as well as Based on the optimization purpose, a second target allocation scheme is determined from the L reallocation schemes, and the computing power of the at least one working core in executing the N data processing is allocated through the second target allocation scheme.

30. The data processing method according to claim 19, characterized in that: Also includes: In the process of performing the objective, it is determined that the computing power provided by the pth core for processing the jth data channel is insufficient; Determine the qth kernel from the K kernels to provide computing power for the jth data processing; as well as The execution of the j-th data processing is transferred from the p-th core to the q-th core.

31. The data processing method according to claim 30, characterized in that: Also includes: Before transferring the execution of the j-th data processing from the p-th core to the q-th core, increasing the operating frequency of the q-th core to increase the computing power of the q-th core to avoid data processing stalls.

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