Secondary radar original decoding data recording device

Abstract

The invention relates to the technical field of secondary radars, and provides a secondary radar original decoding data recording device, which comprises an FPGA (Field Programmable Gate Array), and a CPU (Central Processing Unit), a decoding module, a storage module and a bottom plate which are connected with the FPGA, or, the storage module is arranged in the main control module, and the storage module does not need to be placed on each processing module; or, each task system does not need to place a storage module, but carries out data storage through a storage space provided by the platform special storage extension set. According to the method, the secondary radar original decoding data is recorded, the data size can meet the capacity of the current storage module, important data support can be provided in the secondary radar project design and research and development process, design and research and development personnel can effectively carry out software iteration according to the stored data, and the iteration accuracy and the design and research and development efficiency are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of secondary radar, in particular to a secondary radar original decoding data recording device. Background Art

[0002] As my country's industrial capabilities increase, air traffic control secondary radars have been used on various sea, land and air platforms in accordance with the professional needs of various industries, and new secondary radar projects are constantly being designed and developed.

[0003] In the application process of secondary radar on different platforms, based on the respective characteristics of different platforms, the data recording of existing secondary radar has the following main shortcomings:

[0004] 1. The current record of test flight data is mainly the record of point track / track data, and the recorded data is not "basic" enough;

[0005] 2. Due to the large amount of original decoded data and the small storage space of the module, the current method is mainly for the participants to record the original decoding of one or several A codes according to their needs, or there is no recording plan at all;

[0006] 3. Debuggers cannot understand the entire system load and data flow packet loss from the recorded data.

[0007] Due to the above shortcomings, the design and development personnel cannot obtain sufficient iteration basis from the test flight data, which reduces the detection quality and affects the operator's interpretation. In order to obtain better detection performance and ensure the integrity of the track, it is necessary to conduct a detailed analysis of the detected data and make improvements based on the analysis results. Summary of the invention

[0008] The present invention aims to provide a secondary radar original decoding data recording device to overcome the above-mentioned shortcomings of the data recording of the existing secondary radar.

[0009] In a first aspect, the present invention provides a secondary radar raw decoding data recording device, comprising an FPGA and a CPU connected to the FPGA, a decoding module, a storage module and a baseboard.

[0010] In a second aspect, the present invention provides a secondary radar original decoded data recording device, comprising a main control module and a processing module; the processing module has one or more;

[0011] The main control module includes a first FPGA and a storage module and a first baseboard connected to the first FPGA;

[0012] The processing module includes a second FPGA and a CPU, a decoding module and a second baseboard connected to the second FPGA;

[0013] The first bottom plate is connected to the second bottom plate.

[0014] In a third aspect, the present invention provides a secondary radar original decoded data recording device, comprising a main control module, a processing module and a platform-specific storage extension;

[0015] The main control module includes a first FPGA and a data transmission module and a first baseboard connected to the first FPGA;

[0016] The processing module includes a second FPGA and a CPU, a decoding module and a second baseboard connected to the second FPGA;

[0017] The first baseboard is connected to the second baseboard, and the platform-specific storage extension is connected to the data transmission module.

[0018] In the above-mentioned secondary radar original decoding data recording devices, the relevant contents of the reply signal recorded in the original decoding data packaged by the CPU are designed to include distance, azimuth, mode, A code, altitude, S mode address, sidelobe flag, sum amplitude, difference amplitude, confidence, interleaving bit and sign bit; and the system operation status data is also recorded in the original decoding data packaged by the CPU.

[0019] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0020] 1. The present invention realizes the recording of the original decoded data of the secondary radar and the data volume can meet the capacity of the current storage module, which can provide important data support in the design and development process of the secondary radar project. The design and development personnel can effectively iterate the software according to the stored data, thereby improving the accuracy of iteration and the efficiency of design and development.

[0021] 2. The present invention also records system operation data, and can grasp the packet loss and system load of the data link in the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a schematic diagram of the structure of a secondary radar original decoding data recording device according to solution one of the embodiments of the present invention.

[0023] Figure 2 It is a structural schematic diagram of the secondary radar original decoding data recording device of scheme 2 in the embodiment of the present invention.

[0024] Figure 3 This is a schematic diagram of the structure of the secondary radar original decoding data recording device of scheme three in the embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0026] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] Combined with the platform application requirements and the commonly used domestic hardware design habits, any of the following three hardware design schemes can be used to realize the recording of the secondary radar original decoding data according to the actual situation.

[0028] Option 1:

[0029] like Figure 1 As shown, this solution provides a secondary radar original decoding data recording device based on this board, including FPGA and a CPU connected to the FPGA, a decoding module, a storage module and a baseboard.

[0030] The signal flow of the secondary radar original decoding data recording device is as follows:

[0031] S101, IQ data is transmitted from the connector on the backplane to the FPGA;

[0032] S102, after the FPGA performs operations such as modulus calculation and amplitude filtering on the IQ data, the obtained video data is transmitted to the decoding module for decoding, and the original decoded data after decoding is sent to the CPU via the FPGA;

[0033] S103, the CPU decodes the relevant information from the original decoded data and packages it to the FPGA;

[0034] S104, the FPGA stores the original decoded data of the group into a storage module, preferably in a hexadecimal data format.

[0035] After the test flight is completed, the original decoded data in the storage module can be downloaded to the PC for processing through a data reading port (such as a network cable) at an appropriate time.

[0036] Option 2:

[0037] like Figure 1As shown, this solution provides a secondary radar original decoding data recording device based on a main control module in the system, including a main control module and a processing module; there are one or more processing modules.

[0038] The main control module includes a first FPGA and a storage module and a first baseboard connected to the first FPGA;

[0039] The processing module includes a second FPGA and a CPU, a decoding module and a second baseboard connected to the second FPGA;

[0040] The first bottom plate is connected to the second bottom plate.

[0041] In the second solution, the storage module is arranged in the main control module, instead of being placed on each processing module, which is convenient for overall arrangement of resources and cost reduction. The signal flow of the secondary radar original decoding data recording device is as follows:

[0042] S201, IQ data is transmitted from the connector on the second baseboard to the second FPGA;

[0043] S202, after the second FPGA performs operations such as modulus calculation and amplitude filtering on the IQ data, the obtained video data is transmitted to the decoding module for decoding, and the original decoded data after decoding is sent to the CPU via the second FPGA;

[0044] S203, the CPU decodes the relevant information from the original decoded data and packages it to send to the second FPGA;

[0045] S204, the second FPGA reports the packaged original decoded data to the first FPGA of the main control module via the second baseboard and the first baseboard in sequence, wherein the data transmission protocol may adopt a general transmission protocol such as Rapidio or GTX;

[0046] S205, the first FPGA of the main control module stores the original decoded data into the storage module, preferably in a hexadecimal data format.

[0047] After the test flight is completed, the original decoded data in the storage module can be downloaded to the PC for processing through a data reading port (such as a network cable) at an appropriate time.

[0048] Option 3:

[0049] like Figure 3 As shown, the present solution provides a secondary radar original decoding data recording device based on a platform-specific storage extension, including a main control module, a processing module and a platform-specific storage extension;

[0050] The main control module includes a first FPGA and a data transmission module and a first baseboard connected to the first FPGA;

[0051] The processing module includes a second FPGA and a CPU, a decoding module and a second baseboard connected to the second FPGA;

[0052] The first baseboard is connected to the second baseboard, and the platform-specific storage extension is connected to the data transmission module.

[0053] In the third solution, each task system does not need to place a storage module, but stores data through the storage space provided by the platform-specific storage extension. The signal flow of the secondary radar original decoded data recording device is as follows:

[0054] S301, IQ data is transmitted from the connector on the second baseboard to the second FPGA;

[0055] S302, after the second FPGA performs operations such as modulus calculation and amplitude filtering on the IQ data, the obtained video data is transmitted to the decoding module for decoding, and the original decoded data after decoding is sent to the CPU via the second FPGA;

[0056] S303, the CPU decodes the relevant information from the original decoded data and packages it to send to the second FPGA;

[0057] S304, the second FPGA reports the packaged original decoded data to the first FPGA of the main control module via the second baseboard and the first baseboard in sequence, wherein the data transmission protocol may adopt a general transmission protocol such as Rapidio or GTX;

[0058] S305, the first FPGA of the main control module transmits the original decoded data to the platform-specific storage extension via the data transmission module, and stores it in hexadecimal data format. In order to reduce platform interference, the data transmission module generally adopts an optical signal transmission module to transmit the original decoded data by optical signal. Of course, the data transmission module can also be implemented as an electrical signal transmission module.

[0059] After the test flight is completed, the original decoded data of the platform-specific storage extension can be downloaded to the PC for processing at an appropriate time.

[0060] In the above three schemes, the relevant contents of the response signal recorded in the original decoded data of the group package are shown in Table 1.

[0061] Table 1, list of response signal related contents:

[0062]

[0063] In order to understand the packet loss and system load of the data link in the system, the system operation data is also recorded in the original decoded data of the group packet, see Table 2.

[0064] Table 2, system operation data record list:

[0065]

[0066]

[0067] After the content recorded in the original decoded data is packaged by the CPU, the system timestamp is added to the data packet after packaging, and then the next recording process is carried out (such as step S104 in scheme one, steps S204~S205 in scheme two, and steps S304~S305 in scheme three).

[0068] Complete data recording according to the above process. Taking a single mission time of 4 hours as an example, the secondary radar recorded data is generally no more than 600MB, which is 2.5MB per minute and 42KB per second, which can meet the capacity of the current mainstream storage modules.

[0069] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A secondary radar original decoded data recording device, characterized in that: It includes FPGA and a CPU, a decoding module, a storage module and a baseboard connected with the FPGA.

2. The secondary radar original decoded data recording device according to claim 1, characterized in that: The signal flow of the secondary radar original decoding data recording device is as follows: S101, IQ data is transmitted from the connector on the backplane to the FPGA; S102, after the FPGA operates the IQ data, the obtained video data is transmitted to the decoding module for decoding, and the original decoded data after decoding is sent to the CPU via the FPGA; S103, the CPU decodes the relevant information from the original decoded data and packages it to the FPGA; S104, FPGA stores the packaged original decoded data into the storage module.

3. The secondary radar original decoded data recording device according to claim 2, characterized in that: The relevant contents of the reply signal recorded in the original decoded data of the package include distance, azimuth, mode, A code, altitude, S mode address, sidelobe flag, sum amplitude, difference amplitude, confidence, interleaving bit and sign bit; the original decoded data of the package also records system operation status data.

4. A secondary radar original decoded data recording device, characterized in that: It includes a main control module and a processing module; there are one or more processing modules; The main control module includes a first FPGA and a storage module and a first baseboard connected to the first FPGA; The processing module includes a second FPGA and a CPU, a decoding module and a second baseboard connected to the second FPGA; The first bottom plate is connected to the second bottom plate.

5. The secondary radar original decoded data recording device according to claim 1, characterized in that: The signal flow of the secondary radar original decoding data recording device is as follows: S201, IQ data is transmitted from the connector on the second baseboard to the second FPGA; S202, after the second FPGA operates the IQ data, the obtained video data is transmitted to the decoding module for decoding, and the original decoded data after decoding is sent to the CPU via the second FPGA; S203, the CPU decodes the relevant information from the original decoded data and packages it to send to the second FPGA; S204, the second FPGA reports the packaged original decoded data to the first FPGA of the main control module via the second baseboard and the first baseboard in sequence; S205, the first FPGA of the main control module stores the original decoded data into the storage module.

6. The secondary radar original decoded data recording device according to claim 5, characterized in that: The relevant contents of the reply signal recorded in the original decoded data of the package include distance, azimuth, mode, A code, altitude, S mode address, sidelobe flag, sum amplitude, difference amplitude, confidence, interleaving bit and sign bit; the original decoded data of the package also records system operation status data.

7. A secondary radar original decoded data recording device, characterized in that: Includes main control module, processing module and platform-specific storage extension; The main control module includes a first FPGA and a data transmission module and a first baseboard connected to the first FPGA; The processing module includes a second FPGA and a CPU, a decoding module and a second baseboard connected to the second FPGA; The first baseboard is connected to the second baseboard, and the platform-specific storage extension is connected to the data transmission module.

8. The secondary radar original decoded data recording device according to claim 7, characterized in that: The data transmission module adopts an optical signal transmission module or an electrical signal transmission module.

9. The secondary radar original decoded data recording device according to claim 7 or 8, characterized in that: The signal flow of the secondary radar original decoding data recording device is as follows: S301, IQ data is transmitted from the connector on the second baseboard to the second FPGA; S302, after the second FPGA operates the IQ data, the obtained video data is transmitted to the decoding module for decoding, and the original decoded data after decoding is sent to the CPU via the second FPGA; S303, the CPU decodes the relevant information from the original decoded data and packages it to send to the second FPGA; S304, the second FPGA reports the packaged original decoded data to the first FPGA of the main control module via the second baseboard and the first baseboard in sequence; S305, the first FPGA of the main control module transmits the original decoded data to the platform-specific storage extension via the data transmission module.

10. The secondary radar original decoded data recording device according to claim 9, characterized in that: The relevant contents of the reply signal recorded in the original decoded data of the package include distance, azimuth, mode, A code, altitude, S mode address, sidelobe flag, sum amplitude, difference amplitude, confidence, interleaving bit and sign bit; the original decoded data of the package also records system operation status data.

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