Memory, memory system and operation method of memory

Abstract

The invention provides a memory, a memory system and an operation method of the memory, and relates to the technical field of semiconductor chips. The memory comprises a plurality of memory strings, each memory string comprises a source electrode layer, a bottom selection tube layer and a grid electrode layer, the bottom selection tube layer is located between the source electrode layer and the grid electrode layer, and the bottom selection tube layer comprises a plurality of bottom selection tubes; and the bottom selection tube of the first memory string and the bottom selection tube of the second memory string are connected with the same bottom selection grid line. The invention aims to solve the problem that the programming time is longer and longer under the condition that the density of the memory cells is higher and higher.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a memory, a memory system, and a memory operation method. Background Art

[0002] At present, with the continuous development of augmented reality (3D NAND), the density of storage cells is getting higher and higher. In order to improve the performance of the product, manufacturers hope that the programming time is as short as possible during programming. However, the size of complementary metal oxide semiconductor (CMOS) circuit design is also shrinking. The reduction in the area of ​​the peripheral circuit limits the driving ability of the array voltage, resulting in an increase in programming time. The programming operation requires gradually increasing the voltage to the target value within a specified time to correctly program the storage cell. If the array voltage does not rise quickly enough, the programming time will increase.

[0003] Therefore, how to reduce the programming time when the density of storage cells is getting higher and higher and the size of CMOS circuit design is getting smaller and smaller is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The embodiments disclosed in the present disclosure provide a memory, a memory system and a memory operation method, aiming to solve the problem that the programming time becomes longer and longer when the density of memory cells becomes higher and higher.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] In a first aspect, a memory is provided, comprising: a plurality of memory strings, the memory strings comprising a source layer, a bottom selection tube layer and a gate layer, the bottom selection tube layer being located between the source layer and the gate layer, wherein the bottom selection tube layer comprises a plurality of bottom selection tubes;

[0007] The bottom selection tube of the first storage string and the bottom selection tube of the second storage string are connected to the same bottom selection gate line.

[0008] In the memory provided by the present disclosure, the bottom selection tube layer has no bottom gate selection cutout to separate it, and the bottom selection tubes corresponding to different finger storage areas are connected to the same bottom selection gate line, so each layer of bottom selection tubes only needs one circuit lead-out. This design simplifies the structure, reduces circuit complexity and wiring difficulty, and reduces manufacturing and maintenance costs. When each layer of bottom selection tubes is connected to the same bottom selection gate line, the bottom selection tubes of different storage strings can be programmed to different threshold voltages, and the voltage applied to the bottom selection gate line can be used to select and turn on the bottom selection tubes of different storage strings.

[0009] In some embodiments, the memory string includes a first bottom selection tube and a second bottom selection tube, the second bottom selection tube is disposed between the first bottom selection tube and the source layer, the first bottom selection tube of the first memory string and the first bottom selection tube of the second memory string are connected to the first bottom selection gate line, and the second bottom selection tube of the first memory string and the second bottom selection tube of the second memory string are connected to the second bottom selection gate line.

[0010] In some embodiments, the threshold voltage of the first bottom selection tube in the first storage string is greater than the threshold voltage of the first bottom selection tube in the second storage string, and the threshold voltage of the second bottom selection tube in the first storage string is less than the threshold voltage of the second bottom selection tube in the second storage string.

[0011] The memory provided by the embodiment of the present disclosure sets different threshold voltages for different bottom selection tube layers and bottom selection tubes on different storage strings, so that the bottom selection tubes can be selectively turned off by applying different conduction voltages during the programming verification stage. Therefore, during the programming verification process of the memory cell, the signal transmission delay can be reduced by reducing the influence of the parasitic RC effect of the non-programming storage string on the programming storage string, thereby reducing the programming time.

[0012] In some embodiments, the storage string also includes a third bottom selection tube, the third bottom selection tube of the first storage string and the third bottom selection tube of the second storage string are connected to a third bottom selection gate line, the third bottom selection tube is arranged between the second bottom selection tube and the source layer of the memory, and the threshold voltages of the third bottom selection tubes connected to the third bottom selection gate line are the same.

[0013] In some embodiments, the threshold voltage of the first bottom selection tube and the threshold voltage of the second bottom selection tube are smaller than the threshold voltage of the third bottom selection tube.

[0014] In the memory provided by the embodiment of the present disclosure, the threshold voltage of the third bottom selection tube is higher than the threshold voltages of the first bottom selection tube and the second bottom selection tube, thereby playing a shut-off role when programming the first bottom selection tube and the second bottom selection tube in the bottom selection tube layer.

[0015] In some embodiments, the multiple bottom selection tubes also include a virtual selection tube, at least one virtual selection tube is arranged between any two bottom selection tubes with different threshold voltages, and the virtual selection tube of the first storage string and the virtual selection tube of the second storage string are connected to the pseudo word line.

[0016] The memory provided by the embodiment of the present disclosure buffers the potential difference by setting a virtual selection tube, thereby reducing the possibility of hot carrier injection problems, thereby increasing the life of the selection tube.

[0017] In some embodiments, the number of the first bottom selection tubes and the second bottom selection tubes in the storage string is one or more.

[0018] In some embodiments, the number of the third bottom selection tubes in the storage string is one or more.

[0019] In some embodiments, the first storage string and the second storage string are located in different finger storage areas.

[0020] The memory provided by the embodiments of the present disclosure can realize the selective separation of the bottom selection pipe layer by taking the finger storage area or storage string as the minimum unit.

[0021] In a second aspect, a method for operating a memory is provided, the method comprising:

[0022] Programming the first bottom selection tube and the second bottom selection tube so that the first bottom selection tube and the second bottom selection tube are programmed to different target threshold voltages;

[0023] Different voltages are applied to the first bottom selection gate line and the second bottom selection gate line, wherein the first bottom selection gate line is coupled to the first bottom selection tube, and the second bottom selection gate line is coupled to the second bottom selection tube.

[0024] In some embodiments, the threshold voltage of the first bottom selection tube in the first storage string is greater than the threshold voltage of the first bottom selection tube in the second storage string, the threshold voltage of the second bottom selection tube in the first storage string is less than the threshold voltage of the second bottom selection tube in the second storage string, and applying different voltages to the first bottom selection gate line and the second bottom selection gate line includes:

[0025] A first voltage is applied to the first bottom selection gate line and a second voltage is applied to the second bottom selection gate line, or a second voltage is applied to the first bottom selection gate line and a first voltage is applied to the second bottom selection gate line, wherein the first voltage is greater than the second voltage.

[0026] In some embodiments, the method further comprises:

[0027] Applying a third voltage to a third bottom selection gate line, wherein the third bottom selection gate line is coupled to a third bottom selection transistor;

[0028] A pass voltage is applied to the dummy word line, wherein the dummy word line is coupled to the dummy selection tube.

[0029] In some embodiments, programming the first bottom selection tube and the second bottom selection tube to program the first bottom selection tube and the second bottom selection tube to different target threshold voltages includes:

[0030] When a first programming voltage is applied to the first bottom selection gate line, the first bottom selection tube of the first storage string and the first bottom selection tube of the second storage string are programmed; when a second programming voltage is applied to the first bottom selection gate line, the first bottom selection tube of the first storage string is programmed, and programming of the first bottom selection tube of the second storage string is prevented.

[0031] In some embodiments, programming the first bottom selection transistor of the first memory string and the first bottom selection transistor of the second memory string includes:

[0032] A conduction voltage is applied to a first top selection gate line and a second top selection gate line, wherein the first top selection gate line is coupled to a top selection transistor of a first storage string, and the second top selection gate line is coupled to a top selection transistor of a second storage string.

[0033] In some embodiments, programming a first bottom selection transistor of a first memory string and preventing programming of a first bottom selection transistor of a second memory string includes:

[0034] A turn-on voltage is applied to the first top selection gate line, and a turn-off voltage is applied to the second top selection gate line, wherein the first top selection gate line is coupled to the top selection transistor of the first storage string, and the second top selection gate line is coupled to the top selection transistor of the second storage string.

[0035] According to a third aspect, a memory system is provided. The memory system comprises a memory controller and the memory according to the first aspect, wherein the memory controller is configured to control the memory.

[0036] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer-executable instructions; after the computer-executable instructions are executed, any one of the methods in the second aspect above can be implemented.

[0037] In a fifth aspect, a computer device is provided, comprising a processor and a readable storage medium coupled to the processor, wherein the readable storage medium stores executable instructions, and when the executable instructions are executed by the processor, any one of the methods in the second aspect can be implemented.

[0038] It can be understood that the technical effects of the second to fifth aspects refer to the technical effects of the first aspect and any embodiment thereof, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a block diagram of an electronic device according to some embodiments of the present disclosure;

[0040] Figure 2 is a block diagram of a storage system according to some embodiments of the present disclosure;

[0041] Figure 3is a block diagram of another storage system according to some embodiments of the present disclosure;

[0042] Figure 4 is a schematic diagram of a floating gate field effect transistor according to some embodiments of the present disclosure;

[0043] Figure 5 A schematic diagram of storing data of a floating gate field effect transistor according to some embodiments of the present disclosure;

[0044] Figure 6 A schematic diagram of the electrical connection structure of a memory cell array provided in an embodiment of the present disclosure;

[0045] Figure 7 is a schematic diagram of a planar structure of the memory disclosed in the present invention;

[0046] Figure 8 A schematic diagram of the electrical connection structure of another memory cell array provided in an embodiment of the present disclosure;

[0047] Fig. 9 is another schematic diagram of a planar structure of the memory disclosed in the present invention;

[0048] Fig.10 A schematic diagram of a cross-sectional structure of the memory disclosed in the present invention;

[0049] Fig.11 A schematic diagram of the selective shutdown process disclosed in the present invention;

[0050] Fig.12 is another schematic diagram of the memory disclosed in the present invention;

[0051] Fig.13 is another schematic diagram of the memory disclosed in the present invention;

[0052] Fig.14 is another schematic diagram of the memory disclosed in the present invention;

[0053] Fig.15 is another schematic diagram of the memory disclosed in the present invention;

[0054] Fig.16 A schematic diagram of the structure of the memory and peripheral circuits provided in the embodiment of the present disclosure

[0055] Fig.17 The flowchart of the operating method of the memory disclosed in the present invention is shown in FIG. DETAILED DESCRIPTION

[0056] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0057] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0058] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0059] When describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. In this case, "coupled" may also be described as "connected". In addition, the term "coupled" may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0060] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0061] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B. The use of "suitable for" or "configured to" herein is meant to be open and inclusive language, which does not exclude devices that are suitable for or configured to perform additional tasks or steps. In addition, the use of "based on" is meant to be open and inclusive, because a process, step, calculation or other action "based on" one or more conditions or values ​​can be based on additional conditions or beyond values ​​in practice.

[0062] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0063] The embodiments of the present disclosure provide an electronic device, which may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc. Figure 1 , Figure 1 A schematic diagram of an electronic device 10 provided by an embodiment of the present disclosure is shown, including a host 100 and a storage system 110. The host 100 is coupled to the storage system 110 to write data to the storage system 110 or read data stored in the storage system 110. The host is also called a master device, and the storage system is also called a slave device. In an electronic device, a slave device can be accessed by different master devices. For example, taking the electronic device as a mobile phone as an example, the central processing unit (CPU) and digital signal processor (DSP) of the mobile phone can all access the storage system as a host.

[0064] For example, see Figure 2 , Figure 2 A schematic diagram of a storage system 110 provided in an embodiment of the present disclosure is shown, the storage system 110 includes a storage controller 111 and a memory 112, the storage controller 111 is coupled to the memory 112 to control the memory 112 to store data. The memory 112 may be a two-dimensional (2-dimension, 2D) memory or a three-dimensional (3-dimension, 3D) memory.

[0065] The storage system 110 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an embedded multimedia card (eMMC) package). That is, the storage system 110 may be applied to and packaged into different types of electronic products, for example, mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0066] In some embodiments, the storage system 110 includes a storage controller 111 and a memory 112, and the storage system 110 can be integrated into a memory card. The memory card includes any one of a personal computer memory card international association (PCMCIA) card (abbreviated as PC card), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), a secure digital memory card (SD) card, and a UFS.

[0067] In other embodiments, see Figure 3 The storage system 110 includes a storage controller 111 and a plurality of memories 112 , and the storage system 110 is integrated into solid state drives (SSDs).

[0068] In the storage system 110, in some embodiments, the storage controller 111 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0069] In other embodiments, the storage controller 111 is configured to operate in a high duty cycle environment SSD or eMMC, which is used for data storage in mobile devices such as smartphones, tablets, laptops, and enterprise storage arrays.

[0070] In some embodiments, the storage controller 111 may be configured to manage data stored in the memory 112 and communicate with an external device such as the host 100. In some embodiments, the storage controller 111 may also be configured to control operations of the memory 112 such as read, erase, and program operations.

[0071] In some embodiments, the storage controller 111 may also be configured to manage various functions regarding data stored or to be stored in the memory 112, including at least one of bad block management, garbage collection (GC), logical to physical address conversion, and wear leveling. In some embodiments, the storage controller 111 is also configured to process error correction codes regarding data read from or written to the memory 112.

[0072] In addition, the storage controller 111 can communicate with an external device (e.g., the host 100) through at least one of various interface protocols. It should be noted that the interface protocol includes at least one of a universal serial bus (USB) protocol, a Microsoft Management Console (MMC) protocol, a peripheral component interconnect (Peripheral Component Interconnect), a PCI protocol, a PCI Express (Peripheral Component Interconnect Express, PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronic (IDE) protocol, and a FireWire protocol.

[0073] Exemplarily, taking the storage medium of the memory 112 as a flash memory, the basic storage unit of the flash memory includes a floating gate field effect transistor or a charge trapping transistor, etc. The embodiment of the present disclosure takes the charge trapping transistor as an example for introduction.

[0074] See also Figure 4 , Figure 4 The schematic diagram of the structure of the charge trapping transistor is shown, including a control gate 211, a charge trapping layer 212, a source 213, a drain 214, a substrate 215, an oxide layer 216 and a tunnel oxide layer 217. The source 213 and the drain 214 are arranged on the substrate 215. The embodiment of the present disclosure takes an N-channel charge trapping layer field effect transistor as an example, the substrate 215 is a P-type semiconductor material, and the source 213 and the drain 214 are N-type semiconductor materials. The substrate material between the source 213 and the drain 214 can form a conductive channel 218, the charge capture layer 212 covers the conductive channel 218, the tunnel oxide layer 217 is located between the charge capture layer 212 and the conductive channel 218, and the charge capture layer 212 is separated from the source 213, the drain 214 and the conductive channel 218. The control gate 211 is arranged on the charge capture layer 212, and an oxide layer 216 is arranged between the control gate 211 and the charge capture layer 212 to separate the control gate 211 from the charge capture layer 212. The oxide layer 216 and the tunnel oxide layer 217 are both made of insulating materials, such as silicon dioxide (SiO2).

[0075] The charge capture layer 212 is made of an insulating material with a high charge capture density. When writing data, the charge capture layer 212 captures electrons, and the threshold voltage of the field effect transistor changes. Data is stored with such characteristics. When erasing data, holes in the channel are injected into the charge capture layer 212 and neutralized with the electrons in the charge capture layer 212 to achieve erasure.

[0076] When the charge trapping layer captures electrons, a higher threshold voltage is required to open the conductive channel due to the shielding effect of the electrons. If the threshold voltage when there are no electrons captured in the charge trapping layer is recorded as V th1 , the threshold voltage when electrons are captured in the charge trapping layer is recorded as V th2 , then assuming that a larger than V th1 And less than V th2 A voltage is applied to try to turn on the charge capture transistor. If the charge capture field effect transistor is turned on, it can be determined that no electrons are captured in the charge capture layer. If the charge capture transistor is not turned on, it can be determined that electrons are captured in the charge capture layer. Based on this logic, when no electrons are captured on the charge capture layer, the charge capture transistor is in the on state, indicating 1. When electrons are captured on the charge capture layer, the charge capture transistor is in the off state, indicating 0. Therefore, such different states can be used to store data, and the storage function is achieved by injecting or capturing electrons in the charge capture layer to change the threshold voltage of the charge capture transistor.

[0077] When a voltage is applied to the control gate, a tunneling effect occurs based on the potential difference between the control gate and the channel, and electrons can be injected into the charge trapping layer or captured by the charge trapping layer. When storing data, the data is stored in the charge trapping layer, and the presence or absence of charge in the charge trapping layer can be used to indicate the data currently stored in the storage unit. For example, see Figure 5 ,like Figure 5 As shown in a, the state of the charge trapping layer with charge is 0, such as Figure 5 As shown in b, the state where the charge trapping layer has no charge is 1.

[0078] In order to continuously improve the density and capacity of memory, many memory designers and manufacturers have changed the traditional 2D integration mode and adopted three-dimensional stacking technology to improve the storage density of NAND flash memory. In this context, manufacturers hope to achieve shorter programming time during programming, because this brings many advantages. First of all, shorter programming time can significantly speed up the reading and writing of data. Programming is the process of writing to a single storage unit in the memory, and using a shorter programming time can quickly complete these operations, improve the response speed of the memory and the efficiency of data transmission, thereby improving the overall performance of the system.

[0079] Secondly, shorter programming time is crucial to improving the performance of memory devices. In 3D NAND memory, memory cells are stacked on multiple levels, which greatly improves the storage density. However, the long programming process may cause mutual interference and cross-interference between memory cells, thus affecting the stability of the memory and data reliability. By shortening the programming time, the possibility of such interference can be reduced, the stability of the memory can be improved, and problems such as data loss and miswrite can be avoided, thereby enhancing the performance and reliability of the memory device.

[0080] Finally, shorter programming time helps reduce the chance of electron migration, thereby extending the life of the memory. In the memory, long programming operations may cause electron migration in small structures, causing data loss and bit flipping, which in turn reduces the life of the flash memory chip. By shortening the programming time, the loss caused by electron migration can be reduced, the life of the memory can be extended, and thus the durability and reliability of the memory can be improved.

[0081] Therefore, how to reduce the programming time under the conditions of increasing storage density and smaller and smaller size of CMOS circuit design is a key concern of the industry. One possible implementation method is to improve the programming time by reducing the influence of the parasitic RC (Resistor-Capacitor) effect of the non-programmed storage string on the programmed storage string. The RC effect is a non-ideal effect that is prevalent in integrated circuits, which refers to the influence of the mutual coupling between resistors and capacitors. This effect can cause delays in circuit signal transmission and response, thereby affecting the performance of the entire circuit. For example, when programming, the parasitic RC effect of the non-programmed storage string will affect the programmed storage string, thereby affecting the programming time of the programmed storage string. Therefore, by reducing the RC effect, the signal transmission delay can be reduced, thereby improving the programming time.

[0082] In some embodiments, for example, see Figure 6 , Figure 6 A schematic diagram of the electrical connection structure of a possible memory cell array 300 is shown. The memory cell array 300 includes a plurality of memory cell strings 310. Each memory cell string is coupled to a peripheral circuit through a top select gate line (String select line, SSL), a word line (word line, WL), a bit line (bit line, BL), a bottom select gate line (ground select line, GSL), a source line (Source line, SL), etc. The memory cell string 310 includes a top select gate (TSG), a plurality of memory cells, and a bottom select gate (BSG). Continue to refer to Figure 7 , Figure 7 for Figure 6 In the Y direction, the memory includes a top selection tube layer 301, a word line 302 connected to the memory cell, and a bottom selection tube layer 303. The top selection tube layer 301 includes all top selection tubes connected to the same top selection gate line, and the bottom selection tube layer 303 includes all bottom selection tubes connected to the same bottom selection gate line. The bottom selection tube layer 303 is separated by setting a bottom gate selection cutout between the bottom selection tube layers 303, so that the storage string corresponding to each separation area in the bottom selection tube layer will not affect the storage string corresponding to other separation areas during programming. However, each separation area needs to lead out a driving circuit. Figure 7 In the example, since there are two separation regions, two driving circuits are required, namely, driving circuit CMOS Driver 1 and driving circuit CMOS Driver 2. The driving circuit CMOS Driver 1 and the driving circuit CMOS Driver 2 can realize the separate operation of each separation region, and improve the electrical performance of the three-dimensional memory, such as reducing the parasitic capacitance and the coupling effect between the bottom selection tube layer and the adjacent dielectric layer, and reducing the erasing time and data transmission time.

[0083] Furthermore, when the bottom selection tube layer 303 is separated by the separation method of the above-mentioned bottom gate selection cutout to generate N separation areas, it is necessary to set corresponding N driving circuits. Therefore, reducing the parasitic RC effect by physical means requires improvements in circuit design and manufacturing, and the process workload brought by making the bottom gate selection cutout is very large. Therefore, although the programming time can be improved by reducing the parasitic RC effect by the separation method of the bottom gate selection cutout, the production cost is relatively high due to the increase in area cost and material cost. And it is impossible to separate the bottom selection tube with the storage string as the smallest unit.

[0084] Based on this, the inventors proposed the inventive concept of the present disclosure: without making bottom gate selection cuts between storage strings in the bottom selection tube layer, different bottom selection tubes in the bottom selection tube layer are programmed to different threshold voltages, and in the programming verification process of the storage unit, different voltages are applied to different bottom selection tubes, thereby realizing the selection conduction of the bottom selection tubes, that is, the parasitic RC effect of the non-programmed storage string will not affect the programmed storage string, thereby achieving the effect of electrical isolation.

[0085] In order to improve the problem of difficulty in design and high process cost of the separation method using the bottom gate selection cutout, an embodiment of the present disclosure provides a memory, including: a plurality of memory strings, the memory strings include a source layer ACS, a bottom selection tube layer and a gate layer, the bottom selection tube layer is located between the source layer ACS and the gate layer, wherein the bottom selection tube layer includes a plurality of bottom selection tubes. The bottom selection tube of the first memory string and the bottom selection tube of the second memory string are connected to the same bottom selection gate line.

[0086] See also Figure 8 The bottom selection tube layer disclosed in the present invention is multi-layered, and the bottom selection tubes located in different storage strings are all connected to the same bottom selection gate line. And in the same bottom selection tube layer, refer to Fig. 9 , for the bottom selection tubes located in different storage strings, there is no bottom gate selection cutout to separate them. As an example, the first bottom selection tubes of multiple storage strings are all connected to the first bottom selection gate line GSL1, and the second bottom selection tubes are all connected to the second bottom selection gate line GSL2. That is, the bottom selection tubes located in different storage strings are not isolated by using the bottom gate selection cutout.

[0087] As an example, continue to see Fig. 9 The memory includes a top selection tube layer 301, a word line 302 connected to the memory cell and a bottom selection tube layer 303, a first bottom selection gate line GSL1 is connected to the driving circuit CMOSDriver1, and a second bottom selection gate line GSL2 is connected to the driving circuit CMOSDriver2.

[0088] Compared with the existing memory device using the bottom gate selection cutout for separation, the solution provided by the embodiment of the present disclosure can reduce the number of corresponding driving circuits, reduce power consumption and simplify the signal route, thereby improving the performance and reliability of the overall system. The present disclosure isolates the bottom selection tube by not using the bottom gate selection cutout. Although the number of layers of the selection tube is increased, the production cost required is much less than the production cost required by using the bottom gate selection cutout, and the potential manufacturing defects and reliability problems caused by the bottom gate selection cutout can also be reduced.

[0089] In a possible embodiment of the present disclosure, a storage string includes a first bottom selection tube and a second bottom selection tube, and the first bottom selection tube of the first storage string and the first bottom selection tube of the second storage string are connected to a first bottom selection gate line. The second bottom selection tube of the first storage string and the second bottom selection tube of the second storage string are connected to a second bottom selection gate line. The threshold voltage of the first bottom selection tube located in the first storage string is greater than the threshold voltage of the first bottom selection tube located in the second storage string, and the threshold voltage of the second bottom selection tube located in the first storage string is less than the threshold voltage of the second bottom selection tube located in the second storage string.

[0090] See also Fig.10 , taking the storage string Str1 as the first storage string and the storage string Str2 as the second storage string as an example, the storage string Str1 and the storage string Str2 both include a first bottom selection tube and a second bottom selection tube.

[0091] In one example, the first bottom selection tube is close to one side of the storage unit, then the first bottom selection tubes on the storage string Str1 and the storage string Str2 are both connected to the first bottom selection gate line GSL1, the second bottom selection tubes on the storage string Str1 and the storage string Str2 are both connected to the second bottom selection gate line GSL2, the first bottom selection tube layer a1 includes all the first bottom selection tubes connected by the first bottom selection gate line GSL1, and the second bottom selection tube layer b1 includes all the second bottom selection tubes connected by the second bottom selection gate line GSL2.

[0092] In a possible embodiment, the threshold voltage of the corresponding bottom selection tube is shown in FIG. Fig.11 As shown, the threshold voltage of the first bottom selection transistor close to the storage unit on the storage string Str1 is the first threshold voltage V a , the threshold voltage of the second bottom selection transistor near the source layer ACS on the storage string Str1 is the second threshold voltage V b , the threshold voltage of the first bottom selection tube close to the storage unit on the storage string Str2 is the second threshold voltage V b , the threshold voltage of the second bottom selection transistor near the source layer ACS on the storage string Str2 is the first threshold voltage V a .

[0093] It should be noted that, in this embodiment, the first threshold voltage V a and the second threshold voltage V b is a relative value, the first threshold voltage V a Greater than the second threshold voltage V b The threshold voltage of the bottom selection tube close to the storage cell on the storage string Str1 may be the same as the threshold voltage of the bottom selection tube close to the source layer ACS on the storage string Str2, and the threshold voltage of the bottom selection tube close to the source layer ACS on the storage string Str1 may be the same as the threshold voltage of the bottom selection tube close to the source layer ACS on the storage string Str2.

[0094] The following will further combine Fig.11 The content shown illustrates the case where the storage string Str1 and the storage string Str2 are selectively shut down.

[0095] For the convenience of subsequent description, the naming method of the bottom selection tube is explained, and the bottom selection tube is named according to the bottom selection gate line position and the storage string position where the bottom selection tube is located. If the bottom selection tube is located on Str1 and the first bottom selection gate line GSL1, the bottom selection tube is marked as G1Str1, and similarly, if the bottom selection tube is located on Str2 and the first bottom selection gate line GSL2, the bottom selection tube is marked as G2Str2.

[0096] As an example, the threshold voltages of the first bottom selection tube G1Str1 on the storage string Str1 and the second bottom selection tube G2Str2 on the storage string Str2 are both V a The threshold voltages of the second bottom selection tube G2Str1 on the storage string Str1 and the first bottom selection tube G1Str2 on the storage string Str2 are both V b In the process of programming and verifying the memory cells on the memory string Str1, when the memory string Str2 is selectively turned off, a first voltage V is applied to the first bottom selection gate line GSL1. A , applying a second voltage V to the second bottom selection gate line GSL2 B , the first voltage V A Greater than the second voltage V B , the first voltage V A Greater than the threshold voltage V a , the second voltage V B Greater than the threshold voltage V b , and the second voltage V B Less than the threshold voltage V a .

[0097] When the memory string Str1 is turned on and the memory string Str2 is selected to be turned off, a first voltage V is applied to the first bottom selection gate line. A When the first voltage V A Greater than the threshold voltage V of the first bottom selection tube G1Str1 on the storage string Str1 a and the threshold voltage V of the first bottom selection tube G1Str2 on the storage string Str2 b , so the first bottom selection tubes on the storage string Str1 and the storage string Str2 are both turned on.

[0098] When the second voltage V is applied to the second bottom selection gate line GSL2 B When the second voltage V B Greater than the threshold voltage V of the second bottom selection tube G2Str1 on the storage string Str1 b , so the second bottom selection tube G2Str1 on the storage string Str1 is turned on, and due to the second voltage V BLess than the threshold voltage V of the second bottom selection tube G2Str2 on the storage string Str2 a , so the second bottom selection tube G2Str2 on the storage string Str2 is turned off.

[0099] Based on the above operation process, the first bottom selection tube G1Str1 and the second bottom selection tube G2Str1 on the storage string Str1 are both turned on, so the storage string Str1 is turned on, and the first bottom selection tube G1Str2 on the storage string Str2 is turned on, and the second bottom selection tube G2Str2 is turned off, so the storage string Str2 is selected to be turned off.

[0100] When the memory string Str2 is turned on and the memory string Str1 is selected to be turned off, a second voltage V is applied to the first bottom selection gate line GSL1. B , since the second voltage V B Less than the threshold voltage V of the first bottom selection tube G1Str1 on the storage string Str1 a , so the first bottom selection tube G1Str1 on the storage string Str1 is turned off, and due to the second voltage V B Greater than the threshold voltage V of the first bottom selection tube G1Str2 on the storage string Str2 b , so the first bottom selection tube G1Str2 on the storage string Str2 is turned on.

[0101] When the first voltage V is applied to the second bottom selection gate line GSL2 A When the first voltage V A Greater than the threshold voltage V of the second bottom selection tube G2Str1 on the storage string Str1 b and the threshold voltage V of the second bottom selection tube G2Str2 on the storage string Str2 a , so the second bottom selection tubes on the storage string Str1 and the storage string Str2 are turned on, that is, G2Str1 and G2Str2 are turned on.

[0102] Based on the above operation process, the first bottom selection tube G2Str1 and the second bottom selection tube G2Str2 on the storage string Str2 are both turned on, so the storage string Str2 is turned on, while the first bottom selection tube G1Str1 on the storage string Str1 is turned off, and the second bottom selection tube G1Str2 is turned on, so the storage string Str1 is selected to be turned off.

[0103] The solution provided by the embodiments of the present disclosure sets different threshold voltages for different bottom selection tubes in different bottom selection tube layers, thereby achieving selective shutoff of the selection tubes during programming verification of the storage cells. After the selection tubes are selectively shut off, the programming storage string will be turned on and the non-programming storage string will be turned off, thereby achieving the influence of the parasitic RC effect of the non-programming storage string on the programming storage string, thereby achieving the effect of reducing the programming time.

[0104] In a possible implementation of the present disclosure, the bottom selection tube layer of the memory does not have a bottom gate selection cutout structure, and all the bottom selection tubes located in the same bottom selection tube layer are connected to the same bottom selection gate line. By programming the bottom selection tubes to different threshold voltages, different voltages are applied to multiple bottom selection gate lines to achieve selective conduction of the bottom selection tubes, thereby achieving control of each storage string and achieving the purpose of electrical separation. However, before this, the bottom selection tubes need to be programmed to different threshold voltages. The principle of programming the bottom selection tubes is basically the same as the principle of programming the storage cells. In order to avoid affecting the data stored in the storage cells by programming the bottom selection tubes, a switch needs to be set to turn off the storage string when programming the bottom selection tubes. Exemplarily, in the memory provided by the embodiment of the present disclosure, the storage string also includes a third bottom selection tube, and the third bottom selection tube is set between the second bottom selection tube and the source layer ACS.

[0105] See also Fig.12 , the storage string also includes a third bottom selection tube, and the third bottom selection tubes on different storage strings are connected to the same third bottom selection gate line GSLn. That is, the third bottom selection tube layer c1 includes all the third bottom selection tubes connected by the third bottom selection gate line GSLn. The position of the third bottom selection tube on the storage string is between the second bottom selection tube and the source layer ACS. The first bottom selection tube layer composed of the first bottom selection tube and the second bottom selection tube layer composed of the second bottom selection tube can realize the selective shutdown of the bottom selection tube through the combination of different threshold voltages, so the threshold voltages of the first bottom selection tubes in the first bottom selection tube layer are not all the same, and the threshold voltages of the second bottom selection tubes in the second bottom selection tube layer are not all the same. For example, in combination Fig.12 , the threshold voltage of the first bottom selection tube on the storage string Str1 and the storage string Str2 is V a , the threshold voltage of the first bottom selection tube of the storage string Str3 and the storage string Str4 is V b , that is, the threshold voltages of the first bottom selection tubes in the first bottom selection tube layer are not all the same. The threshold voltages of the second bottom selection tubes on the storage string Str1 and the storage string Str2 are V b , the second bottom selection transistor threshold voltage of storage string Str3 and storage string Str4 is V a, that is, the threshold voltages of the second bottom selection tubes in the second bottom selection tube layer are not all the same. The threshold voltages of the third selection tubes in the storage strings Str1, Str2, Str3, and Str4 are all V h That is, the threshold voltages of all third bottom selection tubes in the third bottom selection tube layer are the same. When the third bottom selection tube is programming the bottom selection tubes in the bottom selection tube layer, the third bottom selection tube can play the role of shutting down the storage string.

[0106] In a possible implementation manner of the present disclosure, a threshold voltage of the first bottom selection tube and a threshold voltage of the second bottom selection tube are smaller than a threshold voltage of the third bottom selection tube.

[0107] As an example, since the third bottom selection tube needs to play a shutoff role when programming the bottom selection tubes in the bottom selection tube layer, the threshold voltage of the third bottom selection tube needs to be much greater than the threshold voltage of the first bottom selection tube and the threshold voltage of the second bottom selection tube. As an example, the threshold voltage of the third bottom selection tube is V h , that is, the threshold voltage is V h >>V a >V b .

[0108] In a possible implementation manner of the present disclosure, the number of the first bottom selection tubes and the second bottom selection tubes in the storage string is one or more.

[0109] When the number of the first bottom selection tube layer and the second bottom selection tube is one, the specific implementation process is as shown in the above embodiment. When the number of the first bottom selection tube layer and the second bottom selection tube is multiple, the first bottom selection tube layer and the second bottom selection tube layer need to be stacked. Fig.13, the first storage string can be any one of the storage string Str1, storage string Str2, storage string Str3 and storage string Str4, and the second storage string can be any one of the storage string Str1, storage string Str2, storage string Str3 and storage string Str4, but the first storage string and the second storage string cannot be the same. As an example, the storage string Str1 includes a first bottom selection tube on the first bottom selection tube layer a1, a second bottom selection tube on the second bottom selection tube layer b1, a first bottom selection tube on the first bottom selection tube layer a2, and a second bottom selection tube on the second bottom selection tube layer b1. Similarly, the storage string Str2 includes a first bottom selection tube on the first bottom selection tube layer a1, a second bottom selection tube on the second bottom selection tube layer b1, a first bottom selection tube on the first bottom selection tube layer a2, and a second bottom selection tube on the second bottom selection tube layer b1. The storage string Str3 includes a first bottom selection tube on the first bottom selection tube layer a1, a second bottom selection tube on the second bottom selection tube layer b1, a first bottom selection tube on the first bottom selection tube layer a2, and a second bottom selection tube on the second bottom selection tube layer b1. The storage string Str4 includes a first bottom selection tube on the first bottom selection tube layer a1, a second bottom selection tube on the second bottom selection tube layer b1, a first bottom selection tube on the first bottom selection tube layer a2, and a second bottom selection tube on the second bottom selection tube layer b1.

[0110] In this case, when the storage string Str1 is turned on, the storage strings Str2, Str3 and Str4 can be selectively turned off; when the storage string Str2 is turned on, the storage strings Str1, Str3 and Str4 can be selectively turned off; when the storage string Str3 is turned on, the storage strings Str1, Str2 and Str4 can be selectively turned off; when the storage string Str4 is turned on, the storage strings Str1, Str2 and Str3 can be selectively turned off. This separation method separates the bottom selection tube layer based on a single storage string.

[0111] For the convenience of subsequent description, the naming method of the bottom selection tube is explained, and the bottom selection tube is named according to the bottom selection gate line position and the storage string position where the bottom selection tube is located. If the bottom selection tube is located on Str1 and the first bottom selection gate line GSL1, the bottom selection tube is marked as G1Str1, and similarly, if the bottom selection tube is located on Str3 and the first bottom selection gate line GSL3, the bottom selection tube is marked as G3Str3.

[0112] The following will be combined with the attached Fig.13The conduction process of each memory string is described. When the memory string Str1 is turned on and the memory strings Str2, Str3 and Str4 are selectively turned off, the specific implementation process is as follows: a first voltage V is applied to the first bottom selection gate line GSL1 corresponding to the first bottom selection tube layer a1. A , applying a first voltage V to the second bottom selection gate line GSL2 corresponding to the second bottom selection tube layer b1 A , applying a second voltage V to the first bottom selection gate line GSL3 corresponding to the first bottom selection tube layer a2 B , applying a second voltage V to the second bottom selection gate line GSL4 corresponding to the second bottom selection tube layer b2 B The first voltage V A Greater than the threshold voltage V a , the second voltage V B Greater than the threshold voltage V b , and the second voltage V B Less than V A .

[0113] When the storage string Str1 is turned on and the storage strings Str2, Str3 and Str4 are selectively turned off, the specific implementation process is as follows:

[0114] Apply a first voltage V to the first bottom selection gate line GSL1 A When the threshold voltages of the first bottom selection tubes G1Str1, G1Str2, G1Str3 and G1Str4 in the first bottom selection tube layer are all lower than the first voltage V A Therefore, the first bottom selection tube G1Str1, the first bottom selection tube G1Str2, the first bottom selection tube G1Str3, and the first bottom selection tube G1Str4 are all turned on.

[0115] Apply a first voltage V to the second bottom selection gate line GSL2 A When the threshold voltages of the second bottom selection tubes G2Str1, G2Str2, G2Str3, and G2Str4 in the second bottom selection tube layer are all lower than the first voltage V A Therefore, the second bottom selection tube G2Str1, the second bottom selection tube G2Str2, the second bottom selection tube G2Str3, and the second bottom selection tube G2Str4 are all turned on.

[0116] Apply a second voltage V to the first bottom selection gate line GSL3 B When the threshold voltage of the first bottom selection tube G3Str1 and the first bottom selection tube G3Str4 in the first bottom selection tube layer is less than the second voltage VB Therefore, the first bottom selection tube G3Str1 and the first bottom selection tube G3Str4 are turned on. Since the threshold voltage of the first bottom selection tube G3Str2 and the first bottom selection tube G3Str3 is greater than the second voltage V B , therefore the first bottom selection tube G3Str2 and the first bottom selection tube G3Str3 are not turned on.

[0117] A second voltage V is applied to the second bottom selection gate line GSL4. B When the threshold voltage of the second bottom selection tube G4Str1 and the second bottom selection tube G4Str2 in the second bottom selection tube layer is less than the second voltage V B Therefore, the second bottom selection tube G4Str1 and the second bottom selection tube G4Str2 are turned on. Since the threshold voltage of the second bottom selection tube G4Str3 and the second bottom selection tube G4Str4 is greater than the second voltage V B , therefore the second bottom selection tube G4Str3 and the second bottom selection tube G4Str4 are not turned on.

[0118] Based on the above operation process, the first bottom selection tubes G1Str1 and G3Str1, and the second bottom selection tubes G2Str1 and G4Str1 on the storage string Str1 are all turned on, so the storage string Str1 is turned on. The first bottom selection tube G1Str2 on the storage string Str2 is turned on, the first bottom selection tube G3Str2 is turned off, and the second bottom selection tubes G2Str2 and G4Str2 are turned on, so the storage string Str2 is selected to be turned off. The first bottom selection tube G1Str3 on the storage string Str3 is turned on, the second bottom selection tube G2Str3 is turned on, the first bottom selection tube G3Str3 is turned off, and the second bottom selection tube G4Str3 is turned off, so the storage string Str3 is selected to be turned off. The first bottom selection tubes G1Str4 and G3Str4 on the storage string Str4 are turned on, the second bottom selection tube G2Str4 is turned on, and the second bottom selection tube G4Str4 is turned off, so the storage string Str4 is selected to be turned off.

[0119] When the storage string Str2 is turned on and the storage strings Str1, Str3 and Str4 are selectively turned off, the specific implementation process is: applying a second voltage V to the first bottom selection gate line GSL1 corresponding to the first bottom selection tube layer a1 B , applying a first voltage V to the second bottom selection gate line GSL2 corresponding to the second bottom selection tube layer b1 A , applying a first voltage V to the first bottom selection gate line GSL3 corresponding to the first bottom selection tube layer a2 A , applying a second voltage V to the second bottom selection gate line GSL4 corresponding to the second bottom selection tube layer b2B .

[0120] Apply a first voltage V to the first bottom selection gate line GSL1 B When the threshold voltage of the first bottom selection tube G1Str2 and the first bottom selection tube G1Str3 in the first bottom selection tube layer is less than the second voltage V B Therefore, the first bottom selection tube G1Str2 and the first bottom selection tube G1Str3 are turned on. Since the threshold voltage of the first bottom selection tube G1Str1 and the first bottom selection tube G1Str4 is greater than the second voltage V B , therefore the first bottom selection tube G1Str1 and the first bottom selection tube G1Str4 are not turned on.

[0121] Apply a first voltage V to the second bottom selection gate line GSL2 A When the threshold voltages of the second bottom selection tubes G2Str1, G2Str2, G2Str3, and G2Str4 in the second bottom selection tube layer are all lower than the first voltage V A Therefore, the second bottom selection tube G2Str1, the second bottom selection tube G2Str2, the second bottom selection tube G2Str3, and the second bottom selection tube G2Str4 are all turned on.

[0122] Apply a first voltage V to the first bottom selection gate line GSL3 A When the threshold voltages of the first bottom selection tubes G3Str1, G3Str2, G3Str3 and G3Str4 in the first bottom selection tube layer are all lower than the first voltage V A Therefore, the first bottom selection tube G3Str1, the first bottom selection tube G3Str2, the first bottom selection tube G3Str3, and the first bottom selection tube G3Str4 are all turned on.

[0123] A second voltage V is applied to the second bottom selection gate line GSL4. B When the threshold voltage of the second bottom selection tube G4Str1 and the second bottom selection tube G4Str2 is less than the second voltage V B Therefore, the second bottom selection tube G4Str1 and the second bottom selection tube G4Str2 are turned on. Since the threshold voltage of the second bottom selection tube G4Str3 and the second bottom selection tube G4Str4 is greater than the second voltage V B , therefore the second bottom selection tube G4Str3 and the second bottom selection tube G4Str4 are not turned on.

[0124] Based on the above operation process, the first bottom selection tube G1Str1 on the storage string Str1 is turned off, G3Str1 is turned on, and the second bottom selection tubes G2Str1 and G4Str1 are both turned on, so the storage string Str1 is selected to be turned off. The first bottom selection tubes G1Str2 and G3Str2 on the storage string Str2 are both turned on, and the second bottom selection tubes G2Str2 and G4Str2 are both turned on, so the storage string Str2 is turned on. The first bottom selection tube G1Str3 on the storage string Str3 is turned on, the second bottom selection tube G2Str3 is turned on, the first bottom selection tube G3Str3 is turned on, and the second bottom selection tube G4Str3 is turned off, so the storage string Str3 is selected to be turned off. The first bottom selection tube G1Str4 on the storage string Str4 is turned off, the first bottom selection tube G3Str4 is turned on, the second bottom selection tube G2Str4 is turned on, and the second bottom selection tube G4Str4 is turned off, so the storage string Str4 is selected to be turned off.

[0125] When the storage string Str3 is turned on and the storage strings Str1, Str2 and Str4 are selectively turned off, the specific implementation process is: applying a second voltage V to the first bottom selection gate line GSL1 corresponding to the first bottom selection tube layer a1 B , applying a second voltage V to the second bottom selection gate line GSL2 corresponding to the second bottom selection tube layer b1 B , applying a first voltage V to the first bottom selection gate line GSL3 corresponding to the first bottom selection tube layer a2 A , applying a first voltage V to the second bottom selection gate line GSL4 corresponding to the second bottom selection tube layer b2 A .

[0126] A second voltage V is applied to the first bottom selection gate line GSL1. B When the threshold voltage of the first bottom selection tube G1Str2 and the first bottom selection tube G1Str3 in the first bottom selection tube layer is less than the second voltage V B Therefore, the first bottom selection tube G1Str2 and the first bottom selection tube G3Str3 are turned on. Since the threshold voltage of the first bottom selection tube G1Str1 and the first bottom selection tube G1Str4 is greater than the second voltage V B , therefore the first bottom selection tube G1Str1 and the first bottom selection tube G1Str4 are not turned on.

[0127] A second voltage V is applied to the second bottom selection gate line GSL2. B When the threshold voltage of the second bottom selection tube G2Str3 and the second bottom selection tube G2Str4 is less than the second voltage V BTherefore, the second bottom selection tube G2Str3 and the second bottom selection tube G2Str4 are turned on. Since the threshold voltage of the second bottom selection tube G2Str1 and the second bottom selection tube G2Str2 is greater than the second voltage V B , therefore the second bottom selection tube G2Str1 and the second bottom selection tube G2Str2 are not turned on.

[0128] Apply a first voltage V to the first bottom selection gate line GSL3 A When the threshold voltages of the first bottom selection tubes G3Str1, G3Str2, G3Str3 and G3Str4 in the first bottom selection tube layer are all lower than the first voltage V A Therefore, the first bottom selection tube G3Str1, the first bottom selection tube G3Str2, the first bottom selection tube G3Str3, and the first bottom selection tube G3Str4 are all turned on.

[0129] Apply a first voltage V to the second bottom selection gate line GSL4 A When the threshold voltages of the second bottom selection tubes G4Str1, G4Str2, G4Str3, and G4Str4 in the second bottom selection tube layer are all lower than the first voltage V A Therefore, the second bottom selection tube G4Str1, the second bottom selection tube G4Str2, the second bottom selection tube G4Str3, and the second bottom selection tube G4Str4 are all turned on.

[0130] Based on the above operation process, the first bottom selection tube G1Str1 on the storage string Str1 is turned off, G3Str1 is turned on, the second bottom selection tube G2Str1 is turned off, and the second bottom selection tube G4Str1 is turned on, so the storage string Str1 is selected to be turned off. The first bottom selection tubes G1Str2 and G3Str2 on the storage string Str2 are both turned on, the second bottom selection tube G2Str2 is turned off, and the second bottom selection tube G4Str2 is turned on, so the storage string Str2 is selected to be turned off. The first bottom selection tubes G1Str3 and G3Str3 on the storage string Str3 are both turned on, and the second bottom selection tubes G2Str3 and G4Str3 are both turned on, so the storage string Str3 is turned on. The first bottom selection tube G1Str4 on the storage string Str4 is turned off, the first bottom selection tube G3Str4 is turned on, and the second bottom selection tubes G2Str4 and G4Str4 are turned on, so the storage string Str4 is selected to be turned off.

[0131] When the storage string Str4 is turned on, the storage strings Str1, Str2 and Str3 are selectively turned off. The specific implementation process is: applying a first voltage V to the first bottom selection gate line GSL1 corresponding to the first bottom selection tube layer a1. A , applying a second voltage V to the second bottom selection gate line GSL2 corresponding to the second bottom selection tube layer b1 B , applying a second voltage V to the first bottom selection gate line GSL3 corresponding to the first bottom selection tube layer a2 B , applying a first voltage V to the second bottom selection gate line GSL4 corresponding to the second bottom selection tube layer b2 A .

[0132] Apply a first voltage V to the first bottom selection gate line GSL1 A When the threshold voltages of the first bottom selection tubes G1Str1, G1Str2, G1Str3 and G1Str4 in the first bottom selection tube layer are all lower than the first voltage V A Therefore, the first bottom selection tube G1Str1, the first bottom selection tube G1Str2, the first bottom selection tube G1Str3, and the first bottom selection tube G1Str4 are all turned on.

[0133] A second voltage V is applied to the second bottom selection gate line GSL2. B When the threshold voltage of the second bottom selection tube G2Str3 and the second bottom selection tube G2Str4 is less than the second voltage V B Therefore, the second bottom selection tube G2Str3 and the second bottom selection tube G2Str4 are turned on. Since the threshold voltage of the second bottom selection tube G2Str1 and the second bottom selection tube G2Str2 is greater than the second voltage V B , therefore the second bottom selection tube G2Str1 and the second bottom selection tube G2Str2 are not turned on.

[0134] Apply a second voltage V to the first bottom selection gate line GSL3 B When the threshold voltage of the first bottom selection tube G3Str1 and the first bottom selection tube G3Str4 in the first bottom selection tube layer is less than the second voltage V B Therefore, the first bottom selection tube G3Str1 and the first bottom selection tube G3Str4 are turned on. Since the threshold voltage of the first bottom selection tube G3Str2 and the first bottom selection tube G3Str3 is greater than the second voltage V B , therefore the first bottom selection tube G3Str2 and the first bottom selection tube G3Str3 are not turned on.

[0135] Apply a first voltage V to the second bottom selection gate line GSL4A When the threshold voltages of the second bottom selection tubes G4Str1, G4Str2, G4Str3, and G4Str4 in the second bottom selection tube layer are all lower than the first voltage V A Therefore, the second bottom selection tube G4Str1, the second bottom selection tube G4Str2, the second bottom selection tube G4Str3, and the second bottom selection tube G4Str4 are all turned on.

[0136] Based on the above operation process, the first bottom selection tubes G1Str1 and G3Str1 on the storage string Str1 are both turned on, the second bottom selection tube G2Str1 is turned off, and the second bottom selection tube G4Str1 is turned on, so the storage string Str1 is selected to be turned off. The first bottom selection tube G1Str2 on the storage string Str2 is turned on, the second bottom selection tube G2Str2 is not turned on, the first bottom selection tube G3Str2 is turned off, and the second bottom selection tube G4Str2 is turned on, so the storage string Str2 is selected to be turned off. The first bottom selection tube G1Str3 on the storage string Str3 is turned on, the second bottom selection tube G2Str3 is turned on, the first bottom selection tube G3Str3 is turned off, and the second bottom selection tube G4Str3 is turned on, so the storage string Str3 is selected to be turned off. The first bottom selection tubes G1Str2 and G3Str2 on the storage string Str2 are both turned on, and the second bottom selection tubes G2Str2 and G4Str2 are both turned on, so the storage string Str4 is turned on.

[0137] During the programming and verification process of the memory cell, a potential difference is generated in the channel, and the main reason for its generation is that data is read from the memory cell during the verification operation, which leads to a change in potential. When a potential difference is generated during the verification process, electrons obtain enough energy under a high electric field to pass through the insulating region of the semiconductor device and enter the insulating oxide layer or other insulating materials, resulting in a hot carrier injection (HCI) problem. In insulating materials, the hot carrier injection problem causes high-energy electrons to collide with lattice atoms, resulting in bond breakage and damage in the insulating material. These damages may cause the insulating material to gradually lose its insulating properties, thereby reducing the reliability and life of the transistor. When the carriers in the transistor migrate, causing charge accumulation or leakage, the threshold voltage of the transistor drifts.

[0138] In order to avoid the problem of hot carrier injection, a virtual selection tube layer composed of virtual selection tubes is set to buffer the potential difference. The function of the virtual selection tube layer is to absorb, buffer and balance these potential differences. Since the virtual selection tube layer does not participate in the actual circuit function, it can serve as a buffer area for the potential difference. When a potential difference is generated, the virtual selection tube layer will absorb part of the impact of the potential difference, thereby reducing the possibility of them propagating to other functional circuit parts and reducing the possibility of hot carrier injection problems.

[0139] In a possible implementation of the present disclosure, the multiple bottom selection tubes also include a virtual selection tube, at least one virtual selection tube is arranged between any two bottom selection tubes with different threshold voltages, and the virtual selection tube of the first storage string and the virtual selection tube of the second storage string are connected to a pseudo word line.

[0140] For example, combining Fig.14 , the virtual selection tubes on different storage strings are connected to the same pseudo word line DWL, that is, the virtual selection tube layer includes all virtual selection tubes connected by the pseudo word line DWL. A first virtual selection tube layer d1 is arranged between the first bottom selection tube layer a1 and the second bottom selection tube layer b1, and the virtual selection tube layer d1 includes all virtual selection tubes connected by the pseudo word line DWL1. A second virtual selection tube layer d2 is arranged between the second bottom selection tube layer b1 and the first bottom selection tube layer a2, and the virtual selection tube layer d2 includes all virtual selection tubes connected by the pseudo word line DWL2. A third virtual selection tube layer d3 is arranged between the first bottom selection tube layer a2 and the second bottom selection tube layer b2, and the virtual selection tube layer d3 includes all virtual selection tubes connected by the pseudo word line DWL3. A fourth virtual selection tube layer d4 is arranged between the second bottom selection tube layer b2 and the third bottom selection tube layer c, and the virtual selection tube layer d4 includes all virtual selection tubes connected by the pseudo word line DWL4.

[0141] Through this structure of stacking virtual selection tube layers and selection tube layers, the energy of electrons in the vertical direction will be effectively isolated into different energy levels. There are energy gaps between these energy levels, and electrons cannot easily jump to other energy levels, thus achieving the effect of step potential.

[0142] By programming the first bottom selection tube and the second bottom selection tube and adjusting their threshold voltages to target values, the goal of selective shutdown is successfully achieved without using the traditional separation method based on bottom gate selection cutouts.

[0143] In the above implementation, in order to avoid the situation where a single bottom selection tube is damaged and the storage string fails, each first bottom selection tube layer, each second bottom selection tube layer and each third bottom selection tube layer may also include multiple layers of redundant bottom selection tubes, the first bottom selection gate line may be connected to the multiple layers of redundant bottom selection tubes of the first bottom selection tube layer, the second bottom selection gate line may be connected to the multiple layers of redundant bottom selection tubes of the second bottom selection tube layer, and the third bottom selection gate line may be connected to the multiple layers of redundant bottom selection tubes of the third bottom selection tube layer, that is, the first bottom selection gate line may include multiple word lines, and applying a turn-off voltage to the first bottom selection gate line may be understood as applying the same turn-off voltage to multiple word lines. Fig.15 The first bottom selection tube layer a1, the first bottom selection tube layer a2, the second bottom selection tube layer b1, the second bottom selection tube layer b2 and the third bottom selection tube layer c all include at least one layer of bottom selection tubes, and the application does not limit the specific number of redundant layers of the first bottom selection tube layer, the second bottom selection tube layer and the third bottom selection tube layer.

[0144] The memory provided by the embodiment of the present disclosure adopts an electrical separation method instead of a separation method of a bottom gate selection cutout, thereby simplifying the manufacturing process of the memory. The separation method of a bottom gate selection cutout requires special processing steps, while programming control can be achieved through voltage control, reducing the complex manufacturing process, thereby reducing production costs and improving the manufacturing efficiency and reliability of the memory.

[0145] Fig.16 A schematic diagram of the structure of a memory array and peripheral circuits is shown. Fig.16 In the embodiment, the peripheral circuit 400 includes an I / O interface 410, a control logic unit 420, a row decoder 430, a voltage generator 440, a column decoder 450, a page buffer 460, a data bus 470, and a register 480. It should be understood that in some examples, the peripheral circuit 400 may also include Fig.16 Additional circuitry not shown.

[0146] The I / O interface 410 may be coupled to the control logic unit 420 and act as a control buffer to buffer data from a storage controller (eg, Figure 2 The I / O interface 410 may receive control commands received from the memory controller 111 in the memory cell array 300 and relay them to the control logic unit 420, and buffer status information received from the control logic unit 420 and relay them to the host. The I / O interface 410 may also be coupled to the page buffer 460 via the data bus 470, and act as a data I / O interface 410 and a data buffer to buffer data and relay them to or from the memory cell array 300.

[0147] The control logic unit 420 may be coupled to the voltage generator 440, the page buffer 460, the column decoder 450, the row decoder 430, the I / O interface 410, etc., and is configured to control the operation of each peripheral circuit. The control logic unit 420 may generate an operation signal to control the operation of the row decoder 430, the column decoder 450, the page buffer 460, and the voltage generator 440 in response to a command (CMD) or a control signal from the memory controller 111; wherein the command may be a program command, a read command, etc.

[0148] The row decoder 430 may supply the word line voltage generated from the voltage generator 440 to the selected word lines and the unselected word lines of the memory cell array 300 in response to the control of the control logic unit 420. As described in detail below, the row decoder 430 is configured to perform a program operation on the memory cells coupled to one or more selected word lines in the memory cell array 300.

[0149] The voltage generator 440 can use an external power supply voltage or an internal power supply voltage to generate various voltages for performing operations such as erasing, programming, reading, and verifying on the memory cell array 300. As an example, in the present application, the voltage generator 440 is also used to apply a first programming voltage and a second programming voltage to the first bottom selection gate line in the erasing stage so that the first bottom selection tube and the second bottom selection tube are programmed to different target threshold voltages, and in the verification stage, a first conduction voltage is applied to the first bottom selection gate line and a second conduction voltage is applied to the second bottom selection gate line to achieve selective shutoff of the bottom selection tube.

[0150] The column decoder 450 may be controlled in response to the control logic unit 420 , and select one or more memory cell strings 310 in the memory cell array 300 by applying a bit line voltage generated from the voltage generator 440 .

[0151] The page buffer 460 can read data from the memory cell array 300 and program (write) data to the memory cell array 300 according to the control signal from the control logic unit 420. In one example, the page buffer 460 can store the programming data (write data) to be programmed into the memory cell array 300. In another example, the page buffer 460 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, the page buffer 460 can also detect a low-power signal from a bit line representing a data bit stored in the memory cell, and amplify a small voltage swing to a recognizable logic level in a read operation.

[0152] The register 480 may be coupled to the control logic unit 420 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit.

[0153] It should be understood by those skilled in the art that the operations performed by the row decoder 430, the page buffer 460, the control logic unit 420, and the voltage generator 440 described in the present application may be performed by a processing circuit, wherein the processing circuit may include but is not limited to hardware of a logic circuit or a hardware / software combination of a processor that executes software.

[0154] See also Fig.17 , the memory operation method provided by the embodiment of the present disclosure includes:

[0155] S510: applying different voltages to the first bottom selection gate line and the second bottom selection gate line.

[0156] During the programming verification process of the memory cell, different voltages are applied to the first bottom selection gate line and the second bottom selection gate line, so that the programming memory string can be turned on and the non-programming memory string can be selectively turned off, thereby reducing the influence of the parasitic RC effect of the non-programming memory string on the programming memory string, reducing the signal transmission delay, and thus reducing the programming time.

[0157] In some embodiments, applying different voltages to the first bottom selection gate line and the second bottom selection gate line comprises:

[0158] S5101: Apply a first voltage to the first bottom selection gate line and a second voltage to the second bottom selection gate line; or apply a second voltage to the first bottom selection gate line and a first voltage to the second bottom selection gate line.

[0159] As an example, the first voltage is greater than the second voltage. Fig.10 and Fig.11 The threshold voltages of the first bottom selection tube on the storage string Str1 and the second bottom selection tube on the storage string Str2 are both V a The threshold voltages of the second bottom selection tube on the storage string Str1 and the first bottom selection tube on the storage string Str2 are both V b Apply a first voltage V to the first bottom selection gate line GSL1 A , applying a second voltage V to the second bottom selection gate line GSL2 B , the first voltage V A Greater than the second voltage V B , the first voltage V A Greater than the threshold voltage V a , the second voltage V B Greater than the threshold voltage Vb , and the second voltage V B Less than the threshold voltage V a .

[0160] When the memory string Str1 is turned on and the memory string Str2 is selected to be turned off, a first voltage V is applied to the first bottom selection gate line. A When the first voltage V A Greater than the first bottom selection tube threshold voltage V on the storage string Str1 a and the first bottom selection tube threshold voltage V on the storage string Str2 b , so the first bottom selection tubes on the storage string Str1 and the storage string Str2 are turned on.

[0161] When the second voltage V is applied to the second bottom selection gate line GSL2 B When the second voltage V B Greater than the second bottom selection tube threshold voltage V on the storage string Str1 b , so the second bottom selection tube on the storage string Str1 is turned on, and due to the second voltage V B Less than the second bottom selection tube threshold voltage V on the storage string Str1 a , so the second bottom selection tube on the storage string Str2 is turned off.

[0162] When the memory string Str2 is turned on and the memory string Str1 is selected to be turned off, a second voltage V is applied to the first bottom selection gate line. B , since the second voltage V B Less than the first bottom selection tube threshold voltage V on the storage string Str1 a , so the first bottom selection tube on the storage string Str1 is turned off, and due to the second voltage V B Greater than the first bottom selection tube threshold voltage V on the storage string Str2 b , so the first bottom selection tube on the storage string Str2 is turned on.

[0163] When a first voltage V is applied to the second bottom selection gate line A When the first voltage V A Greater than the second bottom selection tube threshold voltage V on the storage string Str1 b and the second bottom selection tube threshold voltage V on the storage string Str2 a , so the second bottom selection tubes on the storage string Str1 and the storage string Str2 are turned on.

[0164] Based on the above operation process, the selective shutoff of the storage string Str2 can be achieved during the programming verification of the storage cells on the storage string Str1, that is, the parasitic RC effect of the non-programmed storage string Str2 will not affect the programmed storage string Str1, achieving the effect of electrical isolation, thereby improving the programming time.

[0165] In some embodiments, the method provided by the present disclosure further comprises:

[0166] S5102: Apply a third voltage to the third bottom selection gate line, and apply a pass voltage to the dummy word line.

[0167] Continue reading Fig.14 When the memory strings Str2, Str3 and Str4 are selectively turned off, the specific implementation process is as follows: a first voltage VA is applied to the first bottom selection gate line GSL1 corresponding to the first bottom selection tube layer a1, and a first voltage V is applied to the second bottom selection gate line GSL2 corresponding to the second bottom selection tube layer b1. A , applying a second voltage V to the first bottom selection gate line GSL3 corresponding to the first bottom selection tube layer a2 B , applying a second voltage V to the second bottom selection gate line GSL4 corresponding to the second bottom selection tube layer b2 B The first voltage V A Greater than the threshold voltage V a , the second voltage V B Greater than the threshold voltage V b , and the second voltage V B Less than V A .

[0168] The third bottom selection gate line is applied with a third voltage V H , and the third voltage V H Greater than v h , so that during the above operation, the third bottom selection tubes are all in a conducting state, and the pass voltage Vpass is applied to the pseudo word lines DWL1, DWL2, DWL3 and DWL4.

[0169] Before applying different voltages to the bottom selection gate line, the bottom selection transistor is further programmed. Exemplarily, the method provided by the present disclosure further includes:

[0170] S501: Program the first bottom selection tube and the second bottom selection tube to make the first bottom selection tube and the second bottom selection tube be programmed to different target threshold voltages.

[0171] In the existing memory using the bottom gate selection cutout separation method, the threshold voltages of the bottom selection tubes are all the same, which makes it impossible to control the conduction or shutdown of a specific selection tube without affecting other selection tubes, so it is impossible to achieve selective shutdown. Therefore, in order to achieve selective shutdown without using the bottom gate selection cutout separation method, different bottom selection tubes in the bottom selection tube layer need to be programmed to different threshold voltages. Through precise programming control, the required selection tubes can be programmed to different target threshold voltages.

[0172] During the programming verification process of the memory cell, different voltages are applied to the first bottom selection gate line and the second bottom selection gate line, so that the programming memory string can be turned on and the non-programming memory string can be selectively turned off, thereby reducing the influence of the parasitic RC effect of the non-programming memory string on the programming memory string, reducing the signal transmission delay, and thus reducing the programming time.

[0173] In some embodiments, programming the first bottom selection tube and the second bottom selection tube to program the first bottom selection tube and the second bottom selection tube to different target threshold voltages includes:

[0174] S5011: When a first programming voltage is applied to the first bottom selection gate line, the first bottom selection tube of the first storage string and the first bottom selection tube of the second storage string are programmed; when a second programming voltage is applied to the first bottom selection gate line, the first bottom selection tube of the first storage string is programmed, and programming of the first bottom selection tube of the second storage string is prevented.

[0175] As an example, taking the programming of the selection tube of the first bottom selection tube layer as an example, first, when programming the selection tube of the first bottom selection tube layer, when the first programming voltage is applied to the first bottom selection gate line GSL1, the threshold voltages of all the selection tubes of the first bottom selection tube layer are adjusted to the voltage value corresponding to the second threshold voltage state, so that the threshold voltage of the second bottom selection tube on the storage string Str2 reaches the target value, and then when the second programming voltage is applied to the first bottom selection gate line GSL1, the programming of the first bottom selection tube on the storage string Str2 is prohibited at the same time, and the first bottom selection tube on the storage string Str1 is adjusted to the voltage value corresponding to the first threshold voltage state, and the second programming voltage needs to be greater than the first programming voltage.

[0176] In some embodiments, the operation process of programming the first bottom selection tube and the second bottom selection tube to have different threshold voltages will be specifically described below.

[0177] S50111: Apply a turn-on voltage to the first top selection gate line and the second top selection gate line.

[0178] S50112: Applying an on voltage to the first top selection gate line, and applying an off voltage to the second top selection gate line.

[0179] As an example, the first top selection gate line SSL1 is coupled to the top selection tube of the first storage string, and the second top selection gate line is coupled to the top selection tube of the second storage string SSL2. Continuing with the above embodiment, when the first programming voltage is applied to the first bottom selection gate line GSL1, a turn-on voltage is applied to the first top selection gate line SSL1 and the second top selection gate line SSL2 at the same time, so that the threshold voltages of the first bottom selection tube on the storage string Str1 and the first bottom selection tube on the storage string Str2 are adjusted to the voltage value V corresponding to the second threshold voltage state. b When the second programming voltage is applied to the first bottom selection gate line GSL1, the on voltage is applied to the first top selection gate line SSL1, and the off voltage is applied to the second top selection gate line SSL2, the first bottom selection transistor on the storage string Str1 is adjusted to the voltage value V corresponding to the first threshold voltage state. a .

[0180] The present application also provides a memory system in an embodiment. For example, the memory system includes the memory and the controller as described in the above embodiment, and the memory is coupled to the controller. Figure 2 or Figure 3 The memory system shown.

[0181] The present application also provides an electronic device, which includes a host and the aforementioned memory system, wherein the host is connected to the memory system. Figure 1 The electronic device shown.

[0182] In the present disclosure, the memory provided has no bottom gate selection cutout to separate the bottom selection tube layer, and the bottom selection tubes corresponding to different finger storage areas are connected to the same bottom selection gate line, so each layer of bottom selection tubes only needs one circuit lead-out, and this design simplifies the structure, reduces circuit complexity and wiring difficulty, and reduces manufacturing and maintenance costs. By setting different threshold voltages for different bottom selection tube layers and bottom selection tubes on different storage strings, and in the programming verification stage, by applying different conduction voltages, the selective shutdown of the bottom selection tube is achieved. Therefore, in the programming verification process of the storage unit, by reducing the influence of the parasitic RC effect of the non-programmed storage string on the programmed storage string, the signal transmission delay can be reduced, thereby reducing the programming time.

[0183] Those skilled in the art can clearly understand that, for the convenience and brevity of description, in the above embodiments, the description of each embodiment has different emphases, and the parts that are not described in detail in a certain embodiment can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0184] In the several embodiments provided in the present disclosure, it should be understood that the provided programming method and memory can be implemented in other ways. For example, the division of a module is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0185] Those of ordinary skill in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this disclosure.

[0186] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory, characterized in that: include: A plurality of memory strings, each memory string comprising a source layer, a bottom selection tube layer and a gate layer, wherein the bottom selection tube layer is located between the source layer and the gate layer, wherein the bottom selection tube layer comprises a plurality of bottom selection tubes; The bottom selection tube of the first storage string and the bottom selection tube of the second storage string are connected to the same bottom selection gate line.

2. The memory according to claim 1, characterized in that: The storage string includes a first bottom selection tube and a second bottom selection tube, wherein the second bottom selection tube is arranged between the first bottom selection tube and the source layer; The first bottom selection transistor of the first storage string and the first bottom selection transistor of the second storage string are connected to a first bottom selection gate line; and The second bottom selection transistor of the first storage string and the second bottom selection transistor of the second storage string are connected to a second bottom selection gate line.

3. The memory according to claim 2, characterized in that: A threshold voltage of the first bottom selection tube located in the first storage string is greater than a threshold voltage of the first bottom selection tube located in the second storage string; and A threshold voltage of the second bottom selection tube located in the first storage string is lower than a threshold voltage of the second bottom selection tube located in the second storage string.

4. The memory according to claim 3, characterized in that: The memory string further includes a third bottom selection tube, and the third bottom selection tube of the first memory string and the third bottom selection tube of the second memory string are connected to a third bottom selection gate line; The third bottom selection tube is arranged between the second bottom selection tube and the source layer of the memory, and the threshold voltages of the third bottom selection tubes connected to the third bottom selection gate lines are the same.

5. The memory according to claim 4, characterized in that: The threshold voltage of the first bottom selection tube and the threshold voltage of the second bottom selection tube are smaller than the threshold voltage of the third bottom selection tube.

6. The memory according to any one of claims 1 to 5, characterized in that: The multiple bottom selection tubes also include a virtual selection tube, at least one of which is arranged between any two bottom selection tubes with different threshold voltages, and the virtual selection tube of the first storage string and the virtual selection tube of the second storage string are connected to a pseudo word line.

7. The memory according to claim 6, characterized in that: The number of the first bottom selection tubes and the second bottom selection tubes in the storage string is one or more.

8. The memory according to claim 6, characterized in that: The number of the third bottom selection tubes in the storage string is one or more.

9. The memory according to claim 6, characterized in that: The first storage string and the second storage string are located in different finger storage areas.

10. A method for operating a memory, characterized in that: The method comprises: Programming the first bottom selection tube and the second bottom selection tube so that the first bottom selection tube and the second bottom selection tube are programmed to different target threshold voltages; Different voltages are applied to a first bottom selection gate line and a second bottom selection gate line, wherein the first bottom selection gate line is coupled to the first bottom selection tube, and the second bottom selection gate line is coupled to the second bottom selection tube.

11. The operating method according to claim 10, characterized in that: The threshold voltage of the first bottom selection tube located in the first storage string is greater than the threshold voltage of the first bottom selection tube located in the second storage string, and the threshold voltage of the second bottom selection tube located in the first storage string is less than the threshold voltage of the second bottom selection tube located in the second storage string, and applying different voltages to the first bottom selection gate line and the second bottom selection gate line includes: Applying a first voltage to the first bottom selection gate line and applying a second voltage to the second bottom selection gate line; or A second voltage is applied to the first bottom selection gate line, and a first voltage is applied to the second bottom selection gate line, wherein the first voltage is greater than the second voltage.

12. The operating method according to claim 11, characterized in that: The method further comprises: Applying a third voltage to a third bottom selection gate line, wherein the third bottom selection gate line is coupled to a third bottom selection transistor; A pass voltage is applied to a dummy word line, wherein the dummy word line is coupled to a dummy selection tube.

13. The operating method according to claim 10, characterized in that: The step of programming the first bottom selection tube and the second bottom selection tube so that the first bottom selection tube and the second bottom selection tube are programmed to different target threshold voltages includes: When a first programming voltage is applied to the first bottom selection gate line, the first bottom selection transistor of the first storage string and the first bottom selection transistor of the second storage string are programmed; When a second programming voltage is applied to the first bottom selection gate line, the first bottom selection transistor of the first memory string is programmed, and the first bottom selection transistor of the second memory string is prevented from being programmed.

14. The memory operation method according to claim 13, characterized in that: The programming of the first bottom selection tube of the first storage string and the first bottom selection tube of the second storage string includes: A conduction voltage is applied to a first top selection gate line and a second top selection gate line, wherein the first top selection gate line is coupled to a top selection transistor of the first storage string, and the second top selection gate line is coupled to a top selection transistor of the second storage string.

15. The memory operation method according to claim 13, characterized in that: The step of programming the first bottom selection transistor of the first storage string and preventing the first bottom selection transistor of the second storage string from being programmed comprises: A turn-on voltage is applied to the first top selection gate line, and a turn-off voltage is applied to the second top selection gate line, wherein the first top selection gate line is coupled to the top selection tube of the first storage string, and the second top selection gate line is coupled to the top selection tube of the second storage string.

16. A storage system, characterized in that: The storage system includes a storage controller and a memory, wherein the storage controller is coupled to the memory; the memory includes a plurality of storage strings, wherein the storage strings include a source layer, a bottom selection tube layer and a gate layer, wherein the bottom selection tube layer is located between the source layer and the gate layer, wherein the bottom selection tube layer includes a plurality of bottom selection tubes; The bottom selection tube of the first storage string and the bottom selection tube of the second storage string are connected to the same bottom selection gate line.

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