Semiconductor structure, preparation method thereof and insulated gate bipolar transistor

Abstract

The invention relates to a semiconductor structure, a preparation method thereof and an insulated gate bipolar transistor, and the preparation method of the semiconductor structure comprises the steps: providing a substrate which comprises a semiconductor substrate and a dielectric layer located on the semiconductor substrate; forming a contact hole extending from the dielectric layer to the semiconductor substrate on the substrate, wherein the size of the contact hole is greater than a preset size; forming an adhesion layer on the bottom and the side wall of the contact hole; circularly depositing a barrier layer on one side, far away from the substrate, of the adhesion layer; and carrying out heat treatment on the adhesion layer to enable the adhesion layer to react with the substrate to form the metal silicide. By adopting the preparation method of the semiconductor structure, the contact resistance of the device can be reduced, the situation that cracks are generated on the side wall of the contact hole in the heat treatment process can be avoided, and the performance of the device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof, and an insulated gate bipolar transistor. Background Art

[0002] IGBT (Insulate-Gate Bipolar Transistor) is widely used in new energy, photovoltaics, energy storage and other fields due to its advantages of high input impedance, low on-voltage and low driving power.

[0003] In the process of manufacturing IGBT devices, the key dimensions of the back plug are designed to be larger due to the need to withstand high voltage. However, when forming a large-sized plug, cracks are easily generated on the side wall of the plug during the rapid thermal treatment process due to the large stress between the film layers. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof, and an insulated gate bipolar transistor to address the problem that cracks are easily generated on the sidewalls of the plug during the rapid thermal processing process in the prior art.

[0005] In a first aspect, the present application provides a method for preparing a semiconductor structure, comprising:

[0006] Providing a substrate, the substrate comprising a semiconductor substrate and a dielectric layer located on the semiconductor substrate;

[0007] forming a contact hole extending from the dielectric layer to the semiconductor substrate on the base, wherein the size of the contact hole is larger than a preset size;

[0008] forming an adhesion layer on the bottom and sidewalls of the contact hole;

[0009] cyclically depositing a barrier layer on a side of the adhesion layer away from the substrate;

[0010] The adhesion layer is heat treated so that the adhesion layer reacts with the substrate to form a metal silicide.

[0011] In one embodiment, the cyclically depositing the barrier layer on the side of the adhesion layer away from the substrate comprises:

[0012] A chemical vapor deposition process is adopted to cyclically deposit a barrier layer on a side of the adhesion layer away from the substrate.

[0013] In one embodiment, the chemical vapor deposition process includes a metal organic chemical vapor deposition process, and the number of layers of the barrier layer is at least three.

[0014] In one embodiment, the chemical vapor deposition process is used to cyclically deposit a barrier layer on a side of the adhesion layer away from the substrate, comprising:

[0015] The loop repeats the following steps:

[0016] Using a chemical vapor deposition process, a barrier layer material is deposited on a side of the adhesion layer away from the substrate to form a barrier layer;

[0017] The barrier layer is subjected to plasma surface treatment.

[0018] In one embodiment, depositing an adhesion layer on the bottom and sidewalls of the contact hole includes:

[0019] The adhesion layer is formed on the bottom and sidewall of the contact hole by using an ionized metal plasma process.

[0020] In one embodiment, before depositing an adhesion layer on the bottom and sidewalls of the contact hole, the method further includes:

[0021] The natural oxide layer at the bottom and sidewall of the contact hole is removed.

[0022] In one embodiment, before heat treating the adhesion layer so that the adhesion layer reacts with the substrate to form metal silicide, the method further includes:

[0023] A conductive layer is formed on a side of the barrier layer away from the adhesion layer.

[0024] In one embodiment, the preset size is 0.4 microns.

[0025] In a second aspect, the present application also provides a semiconductor structure, which is prepared by the semiconductor structure preparation method provided by any of the above embodiments.

[0026] In a third aspect, the present application also provides an insulated gate bipolar transistor, comprising the semiconductor structure provided by any of the above embodiments.

[0027] In the semiconductor structure and its preparation method, and the insulated gate bipolar transistor, a contact hole extending from the dielectric layer to the semiconductor substrate is formed on the substrate by providing a substrate including a semiconductor substrate and a dielectric layer located on the semiconductor substrate. The size of the contact hole is larger than the preset size, which can increase the contact area between the metal layer subsequently filled in the contact hole and the semiconductor substrate, thereby reducing the contact resistance; further, an adhesion layer is formed at the bottom and sidewall of the contact hole, a barrier layer is cyclically deposited on the side of the adhesion layer away from the substrate, and the adhesion layer is heat-treated so that the adhesion layer reacts with the substrate to form a metal silicide. The metal silicide has a low resistivity, which can further reduce the contact resistance. In addition, by forming the barrier layer by cyclic deposition, compared with forming the barrier layer by one deposition, each deposition layer will form a relatively independent stress field, which can offset the stress of the film layer formed subsequently, thereby reducing the overall stress. In addition, the gaps between the interfaces of different film layers can also be used as stress release channels to reduce stress, thereby avoiding the increase of stress due to the volume change caused by the reaction of the adhesion layer with the substrate to form metal silicide during the heat treatment process, thereby causing cracks to appear at the bottom and sidewall of the contact hole, thereby improving product performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 is a flow chart of a method for preparing a semiconductor structure provided in an embodiment;

[0030] Figure 2 A schematic diagram of a cross-sectional structure of a structure obtained in step S120 in a method for preparing a semiconductor structure provided in an embodiment;

[0031] Figure 3 A schematic diagram of a cross-sectional structure of a structure obtained in step S130 in a method for preparing a semiconductor structure provided in an embodiment;

[0032] Figure 4 A schematic diagram of a cross-sectional structure of a structure obtained in step S140 in a method for preparing a semiconductor structure provided in an embodiment;

[0033] Figure 5 A schematic cross-sectional view of a structure obtained by forming a conductive layer on a side of a barrier layer away from an adhesion layer in a step of a method for preparing a semiconductor structure provided in an embodiment;

[0034] Figure 6is a flow chart of a method for preparing a semiconductor structure provided in a more specific embodiment;

[0035] Figure 7 HAADF (High Angle Annular Dark Field Scanning Transmission Electron Microscope) image of a barrier layer formed by a single deposition using the conventional method;

[0036] Figure 8 FIG. 4 is a HADDF image of a semiconductor structure formed in a more specific embodiment.

[0037] Description of reference numerals:

[0038] 100 - base, 110 - substrate, 120 - dielectric layer, 200 - contact hole, 300 - adhesion layer, 400 - barrier layer, 500 - conductive layer. DETAILED DESCRIPTION

[0039] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0041] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0042] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0043] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0045] In one embodiment, Figure 1 As shown, the present application provides a method for preparing a semiconductor structure, including steps S110-S150.

[0046] S110, providing a substrate, wherein the substrate includes a semiconductor substrate and a dielectric layer located on the semiconductor substrate.

[0047] The material of the semiconductor substrate 110 may be any suitable substrate material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or double-side polished silicon wafers (DSP), ceramic substrates such as aluminum oxide, quartz or glass substrates, etc., which are not limited in this embodiment. A gate structure, an interconnect structure, etc. may also be provided on the other side of the semiconductor substrate 110 away from the dielectric layer 120.

[0048] The material of the dielectric layer 120 may be any suitable insulating material known in the art, for example, at least one of silicon oxide, silicon oxynitride, silicon oxycarbide and silicon oxynitride and carbonitride.

[0049] S120, forming a contact hole on the base extending from the dielectric layer to the semiconductor substrate, wherein the size of the contact hole is larger than a preset size.

[0050] like Figure 2 As shown, a contact hole 200 extending from the dielectric layer 120 to the semiconductor substrate 110 can be formed on the substrate 100 by photolithography and etching processes. Exemplarily, the preset size is 0.4 microns. The size of the contact hole 200 refers to the diameter of the contact hole 200, that is, Figure 2 Designing a contact hole 200 with a larger size can increase the contact area between the conductive layer subsequently filled in the contact hole 200 and the semiconductor substrate 110, increase the number of current channels on the contact interface, thereby reducing the current density per unit contact area, and further reducing the contact resistance.

[0051] S130, forming an adhesion layer on the bottom and sidewall of the contact hole.

[0052] like Figure 3As shown, a deposition process may be used to form an adhesion layer 300 at the bottom and sidewall of the contact hole 200. The adhesion layer 300 may be made of a material having good adhesion to the semiconductor substrate 110 to ensure that the subsequently formed metal layer is stably connected to the semiconductor substrate 110. Exemplarily, the material of the adhesion layer 300 may be titanium. The thickness of the adhesion layer 300 may be less than or equal to 500 angstroms, for example, 380 angstroms, 400 angstroms, 420 angstroms, 440 angstroms, 460 angstroms, 480 angstroms or 500 angstroms, etc.

[0053] S140, cyclically depositing a barrier layer on a side of the adhesion layer away from the substrate.

[0054] like Figure 4 As shown, a deposition process can be used to cyclically deposit a barrier layer 400 on a side of the adhesion layer 300 away from the substrate 100. The barrier layer 400 can be used to prevent the metal compound from corroding the semiconductor substrate 110 during the subsequent formation of the metal layer. It can be understood that the number of barrier layers 400 is greater than or equal to 2. Exemplarily, the material of the barrier layer 400 can be a titanium-containing compound, such as titanium nitride.

[0055] S150, performing heat treatment on the adhesion layer so that the adhesion layer reacts with the substrate to form metal silicide.

[0056] The adhesion layer 300 may be subjected to rapid heat treatment, and the adhesion layer 300 may react with the substrate 110 to form metal silicide. For example, when the adhesion layer 300 is made of titanium (Ti), the adhesion layer 300 may be subjected to heat treatment, and titanium may react with the substrate 110 to form titanium-silicide.

[0057] In an embodiment of the present application, a base 100 including a semiconductor substrate 110 and a dielectric layer 120 located on the semiconductor substrate 110 is provided, and a contact hole 200 extending from the dielectric layer 120 to the semiconductor substrate 110 is formed on the base 100. The size of the contact hole 200 is larger than a preset size, which can increase the contact area between the metal layer subsequently filled in the contact hole 200 and the semiconductor substrate 110, thereby reducing the contact resistance. Furthermore, an adhesion layer 300 is formed on the bottom and sidewalls of the contact hole 200, and a barrier layer 400 is cyclically deposited on a side of the adhesion layer 300 away from the base 100. The adhesion layer 300 is heat-treated so that the adhesion layer 300 reacts with the substrate 110 to form a metal silicide. The metal silicide has a low resistivity, which can further reduce the contact resistance. In addition, compared with forming the barrier layer 400 by a single deposition, each deposition of a barrier layer 400 forms a relatively independent stress field, which can offset the stress of the subsequently formed film layer and reduce the overall stress. In addition, the gaps between the interfaces of different film layers can also serve as stress release channels to reduce stress and avoid stress increase caused by volume changes when the adhesion layer 300 reacts with the substrate 110 to form metal silicide during heat treatment, thereby causing cracks to appear at the bottom and side walls of the contact hole 200, thereby improving product performance.

[0058] In one embodiment, cyclically depositing the barrier layer on the side of the adhesion layer away from the substrate comprises the step of cyclically depositing the barrier layer on the side of the adhesion layer away from the substrate using a chemical vapor deposition process.

[0059] Compared with other deposition processes, the chemical vapor deposition process can obtain a more uniform step coverage, so that the stress distribution inside the barrier layer 400 is also more uniform.

[0060] In one embodiment, the chemical vapor deposition process includes a metal organic chemical vapor deposition process, and the number of layers of the barrier layer 400 is at least three.

[0061] The metal organic chemical vapor deposition process is to introduce tetradimethylaminotide (TDMAT), helium and nitrogen into the reaction chamber. Helium and nitrogen are used as carriers to bring TDMAT to the surface of the adhesion layer 300. TDMAT is decomposed into titanium nitride (TiN) at a certain pressure and a certain temperature to form a barrier layer 400. Exemplarily, the temperature of forming a barrier layer 400 by the metal organic chemical vapor deposition process can be 380°C-410°C, for example, 380°C, 390°C, 400°C or 410°C. The pressure of forming a barrier layer 400 by the metal organic chemical vapor deposition process is 3torr-6torr, for example, 3torr, 4torr, 5torr or 6torr. The flow rate of nitrogen is 2400sccm-2700sccm, for example, 2400sccm, 2500sccm, 2600sccm or 2700sccm. The flow rate of helium gas may be 500 sccm-600 sccm, for example, 500 sccm, 540 sccm, 580 sccm or 600 sccm, etc. The specific temperature, pressure, flow rate of carrier gas, etc. may be reasonably set according to the actual business scenario, and the embodiment of the present application is not limited here.

[0062] In one embodiment, a chemical vapor deposition process is used to cyclically deposit a barrier layer on a side of the adhesion layer away from the substrate, including repeatedly using a chemical vapor deposition process to deposit a barrier layer material on a side of the adhesion layer away from the substrate to form a barrier layer, and performing plasma surface treatment on the barrier layer.

[0063] A barrier layer 400 material is deposited on the side of the adhesion layer 300 away from the substrate 100 by using a chemical vapor deposition process to form a barrier layer 400. Afterwards, the barrier layer 400 is subjected to plasma surface treatment to remove impurities such as C, O, and H in the barrier layer 400, thereby obtaining a low-resistance, dense barrier layer 400. The above steps are repeated for multiple times to obtain multiple layers of dense barrier layers 400. The thickness of the barrier layer 400 deposited in each cycle can be the same or different. For example, the thickness of the barrier layer 400 deposited in each cycle can be 30 angstroms, and the cycle is repeated three times to form three barrier layers 400 with a thickness of 30 angstroms.

[0064] The temperature of plasma surface treatment can be 380℃-410℃, for example, 380℃, 390℃, 400℃ or 410℃, etc., the power can be 1700W-1800W, for example, 1700W, 1740W, 1780W or 1800W, etc., the pressure can be 2torr-3torr, for example, 2torr, 2.4torr, 2.8torr or 3torr, etc., the introduced reaction gas can be hydrogen, nitrogen, etc., the flow rate of hydrogen can be 1700sccm-1800sccm, for example, 1700sccm, 1740sccm, 1780sccm or 1800sccm, etc., the flow rate of nitrogen can be 1100sccm-1200sccm, for example, 1100sccm, 1140sccm, 1180sccm or 1200sccm, etc., and the embodiments of the present application are not limited here.

[0065] In one embodiment, an adhesion layer is deposited on the bottom and sidewalls of the contact hole, including the step of depositing adhesion layer material on the bottom and sidewalls of the contact hole using an ionized metal plasma process to form the adhesion layer.

[0066] Ionized Metal Plasma (IMP) is a technology that uses plasma to perform sputtering deposition on a metal target. By exciting the sputtered metal ions to form a high-density plasma, the deposited adhesion layer 300 is made more uniform. In some embodiments, the power of forming the adhesion layer 300 using the metallized plasma process is 2300W-2500W, for example, 2300W, 2350W, 2400W, 2450W or 2500W, etc. The reaction gas introduced may be argon or other inert gas, and the flow rate of the reaction gas may be 30sccm-35sccm, for example, 30sccm, 33sccm or 35sccm, etc., which is not limited in this embodiment.

[0067] In one embodiment, before depositing an adhesion layer on the bottom and sidewalls of the contact hole, the method for preparing the semiconductor structure of the present application further includes a step of removing the natural oxide layer on the bottom and sidewalls of the contact hole.

[0068] An ion sputtering process can be used to remove the natural oxide layer at the bottom and side walls of the contact hole 200. For example, argon ion sputtering can be used to remove the natural oxide layer at the bottom and side walls of the contact hole 200 to ensure that the subsequently deposited adhesion layer 300 is in direct contact with the semiconductor substrate 110, further reducing the contact resistance of the device and improving the conductivity of the device.

[0069] In one embodiment, before heat treating the adhesion layer so that the adhesion layer reacts with the substrate to form metal silicide, the method for preparing the semiconductor structure of the present application further includes the step of forming a conductive layer on a side of the barrier layer away from the adhesion layer.

[0070] like Figure 5 As shown, a deposition process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD) or high density plasma deposition (HDP) can be used to form a conductive layer 500 on a side of the barrier layer 400 away from the adhesion layer 300. The conductive layer 500 can be made of conductive materials such as tungsten, copper or aluminum.

[0071] In a more specific embodiment, Figure 6 As shown, the method for preparing a semiconductor structure provided in the present application includes steps S610-S690.

[0072] S610, providing a substrate, wherein the substrate includes a semiconductor substrate and a dielectric layer located on the semiconductor substrate.

[0073] S620, forming a contact hole on the base extending from the dielectric layer to the semiconductor substrate, wherein the size of the contact hole is larger than a preset size.

[0074] S630, using argon ion sputtering process to remove the natural oxide layer at the bottom and sidewall of the contact hole.

[0075] S640, depositing an adhesion layer material on the bottom and sidewalls of the contact hole using an ionized metal plasma process to form an adhesion layer.

[0076] S650, using a metal organic chemical vapor deposition process, depositing a barrier layer material on a side of the adhesion layer away from the substrate to form a barrier layer.

[0077] S660, performing plasma surface treatment on the barrier layer.

[0078] S670, repeat steps S650-S660 at least three times in a loop.

[0079] S680, forming a conductive layer on a side of the barrier layer away from the adhesion layer.

[0080] S690, performing heat treatment on the adhesion layer so that the adhesion layer reacts with the substrate to form metal silicide.

[0081] The above steps have been described in the above embodiments and will not be repeated here.

[0082] Figure 7The HAADF (High Angle Annular Dark Field Scanning Transmission Electron Microscope) image of the barrier layer 400 formed by less than or equal to two depositions using a conventional method shows that there is an obvious crack at the bottom of the contact hole 200 . Figure 8 The HAADF image of the three-layer barrier layer 400 formed by three cycles of metal organic chemical vapor deposition process in this embodiment shows that the bottom and side wall film of the contact hole 200 are uniform without cracks.

[0083] In this embodiment, the natural oxide layer at the bottom and sidewalls of the contact hole 200 is removed by an argon ion sputtering process, which can ensure that the subsequently deposited adhesion layer 300 is in direct contact with the semiconductor substrate 110, thereby reducing the contact resistance of the device; further, the adhesion layer 300, the multi-layer barrier layer 400, and the conductive layer 500 are sequentially formed in the contact hole 200, and the adhesion layer 300 is heat-treated so that the adhesion layer 300 reacts with the substrate 110 to form a metal silicide. The metal silicide has a lower resistivity than the adhesion layer 300 material, thereby further reducing the contact resistance of the device. In addition, since the size of the contact hole 200 is larger than the preset size, the thickness of the adhesion layer 300 is also relatively thick, and the stress between the film layers is large. By repeatedly performing the metal organic chemical vapor deposition process at least three times, a barrier layer 400 material is deposited on the side of the adhesion layer 300 away from the substrate 100 to form a barrier layer 400, and the barrier layer 400 is subjected to a plasma surface treatment step. In the process of forming a barrier layer 400 in each cycle, each barrier layer 400 can be used as a stress buffer area for the barrier layer 400 formed subsequently, thereby reducing the overall stress. Moreover, the gaps between different film layers can also be used as stress release spaces, thereby further reducing the overall stress and avoiding the occurrence of cracks caused by the volume change caused by the reaction of the adhesion layer 300 with the substrate 110 to form metal silicide during the subsequent heat treatment, thereby improving the device performance.

[0084] It should be understood that, although the steps in the above-mentioned flowcharts are sequentially displayed in the order shown in the figure, these steps are not necessarily executed sequentially in this order. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0085] In one embodiment, the present application further provides a semiconductor structure, which is prepared by the method for preparing a semiconductor structure provided by any of the above embodiments.

[0086] In one embodiment, the present application further provides an insulated gate bipolar transistor, which includes the semiconductor structure provided by any of the above embodiments.

[0087] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0088] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0089] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a semiconductor substrate and a dielectric layer located on the semiconductor substrate; forming a contact hole extending from the dielectric layer to the semiconductor substrate on the base, wherein the size of the contact hole is larger than a preset size; forming an adhesion layer on the bottom and sidewalls of the contact hole; cyclically depositing a barrier layer on a side of the adhesion layer away from the substrate; The adhesion layer is heat treated so that the adhesion layer reacts with the substrate to form a metal silicide.

2. The method according to claim 1, characterized in that The step of cyclically depositing a barrier layer on a side of the adhesion layer away from the substrate comprises: A chemical vapor deposition process is adopted to cyclically deposit a barrier layer on a side of the adhesion layer away from the substrate.

3. The method according to claim 2, characterized in that The chemical vapor deposition process includes a metal organic chemical vapor deposition process, and the number of layers of the barrier layer is at least three.

4. The method according to claim 2, characterized in that: The chemical vapor deposition process is used to cyclically deposit a barrier layer on a side of the adhesion layer away from the substrate, comprising: The loop repeats the following steps: Using a chemical vapor deposition process, a barrier layer material is deposited on a side of the adhesion layer away from the substrate to form a barrier layer; The barrier layer is subjected to plasma surface treatment.

5. The method according to claim 1, characterized in that Depositing an adhesion layer on the bottom and sidewall of the contact hole comprises: The adhesion layer is formed on the bottom and sidewall of the contact hole by using an ionized metal plasma process.

6. The method according to claim 1, characterized in that Before depositing an adhesion layer on the bottom and sidewall of the contact hole, the method further comprises: The natural oxide layer at the bottom and sidewall of the contact hole is removed.

7. The method according to claim 1, characterized in that Before the adhesion layer is subjected to heat treatment so that the adhesion layer reacts with the substrate to form metal silicide, the method further includes: A conductive layer is formed on a side of the barrier layer away from the adhesion layer.

8. The method according to claim 1, characterized in that The preset size is 0.4 microns.

9. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method for preparing the semiconductor structure according to any one of claims 1 to 8.

10. An insulated gate bipolar transistor, characterized in that: Comprising the semiconductor structure as claimed in claim 9.

Images