Low common-mode noise driver and manufacturing method thereof

Abstract

The invention discloses a low common mode noise driver and a manufacturing method thereof. Comprising two cascaded current mode logic drivers; the input end of the first-stage current mode logic driver is used as the input end of the low common mode noise driver, the output end of the first-stage current mode logic driver is electrically connected with the input end of the second-stage current mode logic driver, and the output end of the second-stage current mode logic driver is used as the output end of the low common mode noise driver; the manufacturing method comprises the following steps: determining an equivalent circuit model containing parasitic capacitance according to a field effect transistor used by the driver; predicting the output common-mode noise of the driver based on the equivalent circuit model; and circuit parameters are optimized based on a driver common-mode noise prediction result. Compared with a traditional sending end driver, the low common-mode noise driver provided by the invention is greatly improved in the aspect of output common-mode noise suppression.

Description

Technical Field

[0001] The invention relates to the field of integrated circuits and electromagnetic compatibility, and in particular to a low common mode noise driver and a manufacturing method thereof. Background Art

[0002] With the development and application of artificial intelligence and big data technologies, the amount of data has shown explosive growth. In this situation, how to efficiently and quickly process and transmit massive amounts of data has become an urgent problem to be solved, so various interface technologies have also emerged. In mainstream interface technologies such as serial deserializers, drivers, as the key to connecting the interface transmitter and the channel, play an important role in logic level conversion and impedance matching.

[0003] As a circuit module for outputting direct-connected channels, the common-mode noise output by the driver is a very critical indicator. Fluctuations in the common-mode voltage output by the driver can cause crosstalk between channels, affecting signal quality. Considering design speed and area efficiency, current-mode logic drivers are widely used in existing interface technologies. However, due to the influence of the parasitic capacitance of the field-effect transistor, the traditional current-mode logic driver has inconsistent response speeds to the rising and falling edges of the input signal under high-frequency inputs of gigahertz, resulting in large fluctuations in the common-mode voltage output. This fluctuation in common-mode voltage creates a large common-mode noise. This problem is a key issue in the field of electromagnetic compatibility of interfaces.

[0004] There have been related studies that reduce output common-mode voltage fluctuations by adding bypass capacitors at the output. However, the bypass capacitors used in this method are at the microfarad level, and their huge area overhead makes it difficult to integrate the bypass capacitors in the transmitter. They can only be mounted on the board between the transmitter chip and the channel. The bypass capacitors mounted in this way will introduce additional parasitic parameters, greatly increasing the complexity of the interface design. Therefore, a driver common-mode noise suppression technology that can be integrated into the transmitter chip is needed. Summary of the invention

[0005] In order to solve the problem of common mode noise output by the high-speed interface transmitter driver, the present invention provides a low common mode noise driver and a manufacturing method thereof. The present invention uses a cascaded current mode logic driver as a low common mode noise driver, and utilizes the characteristics of the current mode logic driver output and input being inverted, so that the high-speed input signal undergoes a rising edge response and a falling edge response when passing through the designed low common mode noise driver, so as to achieve the purpose of balancing the mismatch of the rising and falling edge responses of the field effect tube to the high-speed signal, and reduce the common mode noise at the output end.

[0006] The technical solution adopted by the present invention is as follows: 1. A low common-mode noise driver The low common-mode noise driver includes two cascaded current mode logic drivers; the input end of the first-level current mode logic driver serves as the input end of the low common-mode noise driver, the output end of the first-level current mode logic driver is electrically connected to the input end of the second-level current mode logic driver, and the output end of the second-level current mode logic driver serves as the output end of the low common-mode noise driver.

[0007] The current mode logic driver includes two N-type field effect transistors with a common source, the common source is grounded through a constant current source, the drains of the two field effect transistors are respectively connected to a power supply through two load resistors with the same resistance, the gates of the two field effect transistors serve as input terminals of the current mode logic driver, and the drains of the two field effect transistors serve as output terminals of the current mode logic driver.

[0008] The drains of the two field effect transistors of the first-stage current mode logic driver are electrically connected to the gates of the two field effect transistors of the second-stage current mode logic driver respectively.

[0009] 2. A manufacturing method for the above-mentioned low common mode noise driver The manufacturing method comprises the following steps: S1. Establish a parasitic capacitance model of the field effect tube according to the performance parameters of the field effect tube, and establish an equivalent circuit model of the low common mode noise driver according to the parasitic capacitance model; In the step S1, the parasitic capacitance model of the field effect transistor includes the gate-drain parasitic capacitance, the gate-source parasitic capacitance, the drain junction capacitance and the source junction capacitance of the field effect transistor at each DC operating point.

[0010] In step S1, the circuit equation of the equivalent circuit model is specifically: V op1 =V DD -R L1 I p1 V on1 =V DD -R L1 I n1 I p1 =I ds (V ip -V s1 ,V op1-V s1 ) I n1 =I ds (V in -V s1 ,V on1 -V s1 ) I ss1 =I p1 + I n1 V op2 =V DD -R L2 I p2 V on2 =V DD -R L2 I n2 I p2 =I ds (V op1 -V s2 ,V op2 -V s2 ) I p2 =I ds (V on1 -V s2 ,V op2 -V s2 ) I ss2 =I p2 + I n2 In the formula, VDD is the power supply voltage, R L1 , R L2 are the load resistances of the first-stage current mode logic driver and the second-stage current mode logic driver, V op1 、V on1 are the drain voltages of the two field effect transistors in the first-stage current mode logic driver, V s1 is the voltage of the common source of the two field effect transistors in the first-stage current mode logic driver, I p1 ,I n1 are the source and drain currents of the two field effect transistors in the first-stage current mode logic driver, V ip 、V in are the gate voltages of the two field effect transistors in the first-stage current mode logic driver, I ss1 is the tail current source of the first-stage current mode logic driver; V op2 、V on2 are the drain voltages of the two field effect transistors in the second-stage current mode logic driver, V s2 is the voltage of the common source of the two field effect transistors in the second-stage current mode logic driver, I p2 and I n2 are the source and drain currents of the two field effect transistors in the second-stage current mode logic driver, I ss2 is the tail current source for the second-stage current mode logic driver, I ds （V gs ,V ds ） is the source-drain current of the field effect transistor with respect to the gate-source voltage V gs and source-drain voltage V ds The functional relationship of .

[0011] S2. Performing circuit analysis on an equivalent circuit model of the low common-mode noise driver to obtain a time domain waveform of the common-mode noise of the output signal under a plurality of different sets of circuit parameters to be optimized; In the step S2, the circuit analysis is specifically a dynamic response analysis of the driver during the input signal flipping process and a critical swing analysis of the current mode logic driver.

[0012] In step S2, each group of circuit parameters to be optimized is mainly composed of the load resistance and tail current of the first-level current mode logic driver.

[0013] Further, in the step S2, before performing the circuit analysis, the range of the product of the load resistance and tail current of the second-level current mode logic driver and the load resistance and tail current of the first-level current mode logic driver is set; The load resistance of the second-stage current mode logic driver is matched to the channel impedance; The product of the load resistance and tail current of the second-stage current mode logic driver matches the target output swing of the low common-mode noise driver; The product of the load resistance and tail current of the first-stage current mode logic driver is greater than or equal to the critical swing of the second-stage current mode logic driver, wherein the critical swing refers to the input swing that can just make the output swing of the current mode logic driver reach the maximum swing.

[0014] S3. Predict the output common-mode noise according to the time domain waveform of the output signal common-mode noise under each group of circuit parameters to be optimized, obtain the relationship function between the circuit parameters to be optimized and the output signal common-mode noise, obtain the circuit parameters to be optimized corresponding to the minimum value of the output signal common-mode noise from the relationship function, use them as the optimal circuit parameters, and manufacture a low common-mode noise driver according to the optimal circuit parameters.

[0015] In step S3, the process of output common-mode noise prediction is specifically as follows: Fourier transform is performed on the time domain waveform of the output signal common-mode noise under each set of circuit parameters to be optimized to obtain the frequency spectrum of the output signal common-mode noise, and the maximum value of the AC component in the common-mode part frequency spectrum of the output signal common-mode noise is used as the output signal common-mode noise corresponding to the circuit parameters to be optimized, so as to obtain the functional relationship between the circuit parameters to be optimized and the output signal common-mode noise.

[0016] Compared with the prior art, the present invention has the following beneficial effects: 1. The low common-mode noise driver designed by the present invention can be integrated into the chip like the traditional transmitter driver, which not only makes the circuit have good integrity, but also does not introduce additional parasitic parameter problems. And compared with the traditional transmitter driver, the driver designed by the present invention has better output common-mode noise suppression effect.

[0017] 2. The low common-mode noise driver used in the present invention has good process compatibility and area efficiency. Compared with the traditional large capacitor and common-mode choke solution, the present invention is based on the original current mode logic driver for cascading, does not introduce additional circuit components, and has good process compatibility. In addition, the present invention also avoids the use of large capacitors and large inductors that occupy a large area of ​​resources in the integrated circuit, and has a higher area efficiency.

[0018] 3. The driver circuit parameter optimization method proposed in the present invention uses high-precision driver equivalent circuit modeling with parasitic capacitance, derives the detailed functional relationship between output common-mode noise and driver circuit parameters, and improves the efficiency of the circuit parameter optimization process. And the obtained circuit parameter optimization results have high accuracy.

[0019] 4. The low common-mode noise driver proposed in the present invention has a significant improvement in output common-mode noise suppression compared to the traditional transmitter driver. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 FIG. 4 is a schematic diagram of a current mode logic driver in an exemplary implementation of the present invention.

[0021] Figure 2 is a schematic diagram of a low common-mode noise driver in an exemplary implementation of the present invention.

[0022] Figure 3 FIG. 4 is an equivalent circuit model including parasitic parameters of a low common mode noise driver in an exemplary embodiment of the present invention.

[0023] Figure 4 FIG. 1 is a graph showing the functional relationship between the output swing of a current mode logic driver and the input swing in accordance with an exemplary embodiment of the present invention.

[0024] Figure 5 FIG. 1 is a graph showing the output common mode noise with respect to the load resistance of the first stage current mode logic driver in an exemplary embodiment of the present invention. R L1 and tail current I SS1 Function relationship diagram of .

[0025] Figure 6 It is a time domain waveform diagram of the common mode voltage output by a low common mode noise driver after circuit parameter optimization when the input voltage is reversed in an exemplary implementation of the present invention.

[0026] Figure 7 The frequency spectrum of the common-mode voltage output by a low common-mode noise driver after circuit parameter optimization when the input voltage is reversed in an exemplary implementation of the present invention. DETAILED DESCRIPTION

[0027] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments, but the present invention is not limited to the following embodiments.

[0028] A first aspect of the present invention provides a low common mode noise driver. The low common mode noise driver is used to receive a differential input signal from an output end of a digital processing module at a high-speed interface transmitting end, generate a differential output signal, and output it to a channel.

[0029] like Figure 1 and Figure 2 As shown, the low common mode noise driver is mainly composed of two current mode logic drivers cascaded. The input end of the first current mode logic driver serves as the input end of the low common mode noise driver, the output end of the first current mode logic driver is electrically connected to the input end of the second current mode logic driver, and the output end of the second current mode logic driver serves as the output end of the low common mode noise driver. The first current mode logic driver receives a pair of differential input signals from the output end of the digital processing module at the sending end of the high-speed interface, and pre-processes the differential input signals. The first current mode logic driver outputs a first differential output signal and serves as the differential input of the second current mode logic driver. The second current mode logic driver serves as an output driver and outputs a pair of differential output signals to the channel.

[0030] The present invention uses two levels of current mode logic drivers for cascading, and utilizes the characteristics of the current mode logic driver output and input being inverted, so that the differential input signal undergoes a rising edge and a falling edge response, thereby balancing the characteristics of the field effect tube response mismatch.

[0031] like Figure 1 As shown, the current mode logic driver includes two N-type field effect transistors with a common source, the common source is grounded through a constant current source, the drains of the two field effect transistors are respectively connected to the power supply through two load resistors with the same resistance, the gates of the two field effect transistors serve as the input ends of the current mode logic driver, and respectively receive two differential signals input to the current mode logic driver, and the drains of the two field effect transistors serve as the output ends of the current mode logic driver.

[0032] The drains of the two field effect transistors of the first-stage current mode logic driver are electrically connected to the gates of the two field effect transistors of the second-stage current mode logic driver respectively.

[0033] Thus, the gates of the two field effect transistors of the first current mode logic driver serve as the input terminals of the low common mode noise driver to receive a pair of differential input signals. The drains of the two field effect transistors of the second current mode logic driver serve as the output terminals of the low common mode noise driver to output a pair of differential output signals.

[0034] In the two current mode logic drivers, other circuit parameters of the N-type field effect transistor depend on the integrated circuit manufacturing process used and are not involved in the subsequent circuit parameter design optimization.

[0035] Specifically, the drains of the two field effect transistors are connected to the power supply means that the drains of the two field effect transistors are connected in parallel to the same power supply.

[0036] The second invention of the present invention provides a manufacturing method for the above-mentioned low common-mode noise driver. The manufacturing method of the present invention optimizes the circuit parameters of the low common-mode noise driver by establishing an equivalent circuit model containing parasitic capacitance, performing circuit analysis and common-mode noise prediction in sequence, and then using the optimal circuit parameters for the manufacture of the low common-mode noise driver.

[0037] The manufacturing method of the present invention specifically comprises the following steps: S1. Establish an equivalent circuit model containing parasitic capacitance: Establish a parasitic capacitance model of the field effect tube according to the performance parameters of the field effect tube selected by the low common mode noise driver, and establish an equivalent circuit model containing parasitic capacitance of the low common mode noise driver according to the parasitic capacitance model. Among them, the parasitic capacitance model of the field effect tube is an equivalent model of a voltage-controlled current source and four parasitic capacitances, and the four parasitic capacitances are gate-drain parasitic capacitance (gate-drain capacitance), gate-source parasitic capacitance (gate-source capacitance), drain junction capacitance and source junction capacitance.

[0038] In step S1, the circuit equation of the equivalent circuit model is specifically: V op1 =V DD -R L1 I p1 V on1 =V DD -R L1 I n1 I p1 =I ds (V ip -V s1 ,V op1 -V s1 ) I n1 =I ds (V in -V s1 ,V on1 -V s1 ) I ss1 =I p1 +I n1 V op2 =V DD -R L2 I p2 V on2 =V DD -R L2 I n2 I p2 =I ds (V op1 -V s2 ,V op2 -V s2 ) I p2 =I ds (V on1 -V s2 ,V op2 -V s2 ) I ss2 =I p2 +I n2 Where V DD is the power supply voltage, R L1 , R L2 are the load resistances of the first-stage current mode logic driver and the second-stage current mode logic driver, V op1 、V on1 They are the drain voltages of the two field effect transistors in the first-stage current mode logic driver, and are also the first-stage differential output signals of the first-stage current mode logic driver. s1 is the voltage of the common source of the two field effect transistors in the first-stage current mode logic driver, Ip1 ,I n1 are the source and drain currents of the two field effect transistors in the first-stage current mode logic driver, V ip 、V in are the gate voltages of the two field effect transistors in the first-stage current mode logic driver, and are also the differential input signals of the first-stage current mode driver / low common-mode noise driver, I ss1 is the tail current source of the first-stage current mode logic driver; V op2 、V on2 They are the drain voltages of the two field effect transistors in the second-stage current mode logic driver, and are also the differential output signals of the low common-mode noise driver. s2 is the voltage of the common source of the two field effect transistors in the second-stage current mode logic driver, I p2 and I n2 are the source and drain currents of the two field effect transistors in the second-stage current mode logic driver, respectively. The gates of the two field effect transistors are connected to the drains of the first-stage current mode logic driver, and the voltages are V op1 、V on1 , I ss2 is the tail current source for the second-stage current mode logic driver, I ds (V gs ,V ds ) is the source-drain current of the field effect transistor with respect to its gate-source voltage V gs and source-drain voltage V ds The functional relationship of .

[0039] The voltage and current symbols of each node are shown in Figure 3 Indicated in the middle, I ds (V gs ,V ds ) is the source-drain current of the field effect transistor with respect to its gate-source voltage V gs and source-drain voltage V ds The solution of the above circuit equation is used as the initial condition for circuit analysis.

[0040] S2. Perform circuit analysis on the equivalent circuit model of the low common-mode noise driver to obtain the time domain waveform of the common-mode noise of the output signal under multiple sets of different circuit parameters to be optimized; wherein the circuit parameters to be optimized include the load resistance of the first-stage current mode logic driver and the size of the tail current; the circuit analysis is specifically the dynamic response analysis of the driver during the input signal flipping process and the critical swing analysis of the current mode logic driver, and more specifically, the dynamic response analysis of the driver during the input signal flipping process is the input differential signal rising and falling edge response analysis.

[0041] Step S2 is specifically as follows: S2.1, setting the values ​​of the load resistance and tail current of the second-level current mode logic driver, and the optimization range of the product of the load resistance and tail current of the first-level current mode logic driver; The load resistor of the second-stage current-mode logic driver matches the channel impedance at the output of the low common-mode noise driver; The product of the load resistance and tail current of the second-stage current-mode logic driver matches the target output swing of the low common-mode noise driver; The product of the load resistance and the tail current of the first-stage current mode logic driver is greater than or equal to the critical swing of the second-stage current mode logic driver.

[0042] S2.2, according to the circuit parameters set in step S2.1 and the optimization range of the circuit parameters to be optimized, under different values ​​of the circuit parameters to be optimized, the dynamic response analysis of the driver during the input signal flipping process is performed on the equivalent circuit model of the low common mode noise driver, and the time domain response waveform of the output node voltage when the input signal flips is obtained; In this process, the influence of all parasitic capacitances is considered, based on V op1 , V on1 , V s1 , V op2 , V on2 , V s2 Kirchhoff's current law for the six output node voltages gives the equations for dynamic analysis: I p1 +I n1 =I gsp1 +I jsp1 +I gsn1 +I jsn1 +Iss1 I p2 +I n2 =I gsp2 +I jsp2 +I gsn2 +I jsn2 +I ss2 I op1 =I gdp1 +I p1 +I gdp2 +I gsp2 +I jdp1 I on1 =I gdn1 +I n1 +I gdn2 +I gsn2 +I jdn1 I op2 +I gdp2 =I jdp2 +I p2 I on2 +I gdn2 =I jdn2 +I n2 In the formula, I p1 and I n1 is the source-drain current of the two field effect transistors in the first-stage current mode logic driver, I p2 and I n2 is the source-drain current of the two field effect transistors in the second-stage current mode logic driver. The relationship between the source-drain current of the field effect transistor and the output voltage to be solved is: Ip1 =I ds (V ip -V s1 ,V op1 -V s1 ) I n1 =I ds (V in -V s1 ,V on1 -V s1 ) I p2 =I ds (V op1 -V s2 ,V op2 -V s2 ) I n2 =I ds (V on1 -V s2 ,V on2 -V s2 ) I op1 and I on1 is the current flowing through the load resistor in the first-stage current mode logic driver, I op2 and I on2 is the current flowing through the load resistor in the second-stage current mode logic driver. The relationship between the above current and the output voltage to be solved is: I op1 =(V DD -V op1 ) / RL1 I on1 =(V DD -V on1 ) / R L1 I op2 =(V DD -V op2 ) / R L2 I on2 =(V DD -V on2 ) / R L2 Remaining I gsp1 , I gsp2 The current is the current flowing through the parasitic capacitors with the same subscript, with the capacitor C gsp1 Upper current I gsp1 For example, the relationship between the output voltage to be solved is: I gsp1 =C gsp1 ·d(V ip -V s1 ) / dt The remaining current values ​​can be obtained in the same way.

[0043] The above equations are solved by numerical methods, and then the output time domain waveform of the low common mode noise driver proposed in the present invention, that is, the time domain response waveform of the output node voltage when the input signal is flipped, is predicted to obtain the output time domain waveform of the low common mode noise driver.

[0044] S2.3, according to the time domain response waveform of the output node voltage when the input signal is flipped under each set of circuit parameters to be optimized, by V op2 and V on2 ) take the common-mode component and obtain the time domain waveform of the output signal common-mode noise, that is, the time domain variation waveform of the output signal common-mode noise.

[0045] S3. Predict the output common-mode noise according to the time domain waveform of the common-mode noise of the output signal under each group of circuit parameters to be optimized, and obtain a relationship curve between the circuit parameters to be optimized and the common-mode noise of the output signal. Obtain the circuit parameters to be optimized corresponding to the minimum value of the common-mode noise of the output signal from the relationship curve as the optimal circuit parameters, and manufacture a low common-mode noise driver according to the optimal circuit parameters.

[0046] In step S3, the process of output common-mode noise prediction is specifically as follows: Fourier transform is performed on the time domain waveform of the output signal common-mode noise under each set of circuit parameters to be optimized to obtain the frequency spectrum of the output differential signal, and the maximum value of the AC component (i.e., the non-DC part) in the common-mode part spectrum of the output differential signal is used as the output signal common-mode noise corresponding to the circuit parameters to be optimized, and a relationship curve between the circuit parameters to be optimized and the output signal common-mode noise is obtained.

[0047] In the specific implementation, it is also necessary to determine the size parameters according to the values ​​of the circuit parameters. The specific process is as follows: First, the minimum length that can be achieved by the process used is used as the length of the two current mode logic drivers, which can pass the tail current required by the second level current mode logic driver. I SS2 The minimum width is the width of two current mode logic drivers.

[0048] The principle of the low common mode noise driver of the present invention is as follows: The present invention proposes a low common mode noise driver including two cascaded current mode logic drivers. The basic principle diagram of the current mode logic driver is shown in FIG. Figure 1 As shown in the figure, the current mode logic driver includes two N-type field effect transistors with a common source, whose source is connected to a constant current source. I SS The drains of the two field effect tubes are connected to the ground through two load resistors with the same resistance. R Connect to power V DD , the gates of the two field effect transistors receive two differential input signals respectively V ip , V in The design of the current mode logic driver forms a push-pull structure. When the current mode logic driver is working normally, a pair of differential input signals ( V ip and V in ) One is at a high level and the other is at a low level, so that the two field effect transistors alternately provide tail current I SS .assumed V ip At high level,V in At low level, then there is I SS The current flows through the left field effect tube, and no current flows through the right field effect tube. The corresponding output voltage V op The difference is obtained by subtracting the product of the load resistance and the tail current from the supply voltage. V DD -RI SS , V on for V DD Theoretically, the maximum output swing is the product of the load resistance and the tail current. RI SS . It is worth noting that the difference between the differential amplifier and the current mode logic driver, which are also based on this push-pull structure, lies in the region where their field effect tubes work. For the current mode logic driver, when it is working normally, one field effect tube must be in the saturation region, and the other field effect tube must be in the cut-off region, ensuring that only one of the field effect tubes supplies power to the tail current in the steady state, while the other field effect tube does not generate any current. Under such normal working conditions, the current mode logic driver will definitely reach the maximum output swing, and the input swing requirement for the differential signal is as large as possible. For the differential amplifier, when it is working normally, it requires the DC operating points of the two field effect tubes to be as stable as possible and close to each other. Under ideal conditions, the two field effect tubes each supply half the current size for the tail current. Under the condition that the two field effect tubes are balanced, the differential amplifier has the best linearity and amplification effect. Therefore, compared with the current mode logic driver, the differential amplifier has smaller requirements for the input swing.

[0049] Figure 2 The design principle diagram of the low common-mode noise driver proposed in the present invention is shown. Since there is parasitic capacitance in the field effect tube, and the value of the parasitic capacitance has a great correlation with the working state of the field effect tube. Generally speaking, the field effect tube in the saturation region will have a larger gate-source parasitic capacitance than the field effect tube in the cut-off region. This is because the field effect tube will form a conductive channel when it is turned on, and the extension of the conductive channel will increase the area of ​​the equivalent flat capacitor between the gate and the source. This mismatch of parasitic capacitance will cause the field effect tube to have inconsistent turn-on and turn-off response speeds for high-speed signals, resulting in fluctuations in common-mode voltage at the output end, which becomes a source of output common-mode noise. On the other hand, the parasitic capacitance at the common source terminals of the two field effect tubes in the current mode logic driver will also cause output common-mode fluctuations when the signal is flipped. When the differential input signal is in a steady state, the DC operating points of the two field effect tubes are at the zero current position and the zero current position of their transfer characteristic curves, respectively. I SSWhen the differential input signal flips, the DC operating point of the field effect tube will swap positions along the transfer characteristic curve. During the swap process, if the common source voltage of the two field effect tubes remains unchanged, and the rise and fall rates of the gate input signal are the same, the DC operating point change process of the two field effect tubes will not be perfectly balanced due to the nonlinear characteristics of the transfer characteristic curve of the field effect tube. It can be analyzed through the actual transfer characteristic curve that in the early stage of the input signal flip, the operating point is I SS The source-drain current of the field effect transistor moving toward the zero current position decreases faster than the operating point moving from the zero current position to I SS The source-drain current increase rate of the field effect tube whose current position moves. At this time, the sum of the currents of the two field effect tubes will be less than the tail current of the current mode logic driver, which does not conform to Kirchhoff's current law at the source node of the field effect tube, that is, the sum of the source-drain current of the two field effect tubes should be equal to the tail current of the current mode logic driver. In the later stage of the differential input signal flipping, the situation is opposite to the initial stage of the flipping. At this time, the sum of the source-drain current of the two field effect tubes will be greater than the tail current of the current mode logic driver. Therefore, in the ideal case where there is no parasitic capacitance between the source and the drain, the common source terminal voltage of the two field effect tubes must respond to decrease in the initial stage of the input signal flipping to increase the gate-source voltage of the field effect tube, so that the working point of the field effect tube shifts to the right as a whole on the transfer characteristic curve to increase the source-drain current of the field effect tube, thereby ensuring that the sum of the source-drain current of the two field effect tubes is equal to the tail current at any time. Similarly, in the later stage of the input signal flipping, the common source terminal voltage responds to increase so that the working point of the field effect tube shifts to the left as a whole on the transfer characteristic curve to reduce the source-drain current of the field effect tube to achieve the same effect. However, in actual design, the parasitic capacitance of the field effect transistor at the source end will have a certain impact on the response of its source voltage: first, the parasitic capacitance will cause the common source end response amplitude of the field effect transistor to attenuate. The common source end voltage after the attenuation of the response amplitude is not sufficient to make the sum of the source-drain current of the two field effect transistors equal to the size of the tail current at all times, but is smaller than the size of the tail current in the early stage of the input signal flipping, and is larger than the size of the tail current in the later stage of the input signal flipping. Secondly, the parasitic capacitance will cause the common source end voltage response of the field effect transistor to be delayed, which makes the source end voltage unable to respond to the change of the gate input signal in time. The attenuation and delay of the parasitic capacitance on the common source end voltage response causes the final output common mode voltage to fluctuate, and the output common mode voltage increases in the early stage of the input signal flipping, and decreases in the later stage of the input signal flipping.

[0050] exist Figure 2 In the design schematic of the low common-mode noise driver shown in the figure, the differential input signal V ip and Von The gates of the two field effect transistors of the first-stage current mode logic driver (left) are input respectively to control the current flowing through the two field effect transistors. Then, the first-stage differential output signal of the first-stage current mode logic driver V op1 and V on1 The gates of the two field effect transistors of the second-stage current mode logic driver (right) are input respectively to control the current flowing through them. Finally, the secondary differential output signal of the second-stage current mode logic driver V op2 and V on2 The differential output signal is sent to the channel as a low common-mode noise driver. The benefit of this structure is that, from a holistic perspective, assuming the input signal V ip On the rising edge, the input signal V on At the falling edge, the first-level output signal V op1 After the rising edge response of the primary field effect tube, and due to the output inversion characteristics of the current mode logic driver, it is at the falling edge. V op1 After the falling edge response of the field effect tube of the second-stage current mode driver, the final secondary output signal V op2 It experiences a rising edge response and a falling edge response, and is itself on the rising edge. Conversely, the other side of the differential signal is the same, and the secondary output signal V on2 After experiencing a falling edge response and a rising edge response, it is itself on the falling edge. So far, the output signal has experienced a rising edge and a falling edge response, and the response mismatch problem of the field effect tube has been balanced. From the perspective of separation, the first-level current mode logic driver can be regarded as a signal preprocessing module. In the traditional current mode logic driver, when the input signal flips, due to the nonlinear characteristics of the field effect tube transfer characteristic curve, the common source terminal voltage of the field effect tube used by the driver needs to respond to make the sum of the source and drain currents of the two field effect tubes equal to the tail current. Here, the first-level current mode logic driver performs a targeted preprocessing on the ideal symmetrical differential input signal, and the preprocessed first-level differential output signal is used as the input signal of the second-level current mode logic driver, which can reduce the response required by the common source terminal voltage of the field effect tube of the second-level current mode logic driver, that is, the voltage at this location does not need to change too much, and can also make the sum of the source and drain currents of the two field effect tubes equal to the tail current, greatly reducing the influence of the source terminal parasitic capacitance on the output common mode voltage.

[0051] Figure 2 The load resistor of the first stage current mode logic driver in the low common mode noise driver shown is R L1 、 Load resistor for the second stage current mode logic driver R L2 、 Tail current of the first stage current mode logic driver I SS1 , the tail current of the second-stage current mode logic driver I SS2 It is a circuit parameter that can be optimized. Considering the requirements of channel impedance matching and driver output swing, the optimization of circuit parameters has the following limitations: ① The output impedance of the low common-mode noise driver needs to match the channel impedance R 0 : R L2 =R 0 in, R 0 is the channel impedance, R L2 is the load resistor for the second stage current mode logic driver.

[0052] ②The output swing of the low common-mode noise driver needs to reach the target output swing required by the design V swing : R L2 I SS2 =V swing in, V swing is the target output swing, R L2 is the load resistance of the second-stage current mode logic driver, I SS2 is the tail current of the second stage current mode logic driver.

[0053] ③The output swing of the first-stage current mode logic driver must enable the second-stage current mode logic driver to reach full swing: R L1 I SS1 =V c in,V C is the critical swing of the second-stage current mode logic driver, R L1 is the load resistance of the first stage current mode logic driver, I SS1 is the tail current of the first stage current mode logic driver.

[0054] Figure 4 Demonstrates the output swing of a current mode logic driver V osw About input swing V isw When the input swing of the second-stage current mode logic driver (i.e., the output swing of the first-stage current mode logic driver) is greater than or equal to the critical swing V C When , the output swing can reach the full swing. At this time, the current of one field effect transistor of the current mode logic driver is zero, and the tail current is all provided by the other field effect transistor, and the driver works normally.

[0055] According to the above circuit parameter optimization and limitation analysis, the load resistance of the second-stage current mode logic driver is R L2 and tail current I SS2 is limited to a fixed value and needs to ensure that the load resistance of the first-stage current mode logic driver is multiplied by the tail current R L1 I SS1 Greater than or equal to the critical swing of the second-stage current mode logic driver V C .

[0056] In addition to the circuit parameters, the size of the field effect tube itself also has a great influence on the output common mode noise. On the one hand, the larger the size of the field effect tube, the larger the area of ​​the gate metal layer in its physical structure, and the larger the equivalent parasitic capacitance from the gate to the source and drain. In order to achieve the effect of suppressing the output common mode noise, it is necessary to reduce the size of the field effect tube itself to reduce the influence of the parasitic capacitance on the output common mode noise. On the other hand, the current that the field effect tube can pass is closely related to the width-to-length ratio of the field effect tube. Increasing the width-to-length ratio of the field effect tube can enable the field effect tube to pass more current at the same DC operating point. When the driver is working normally, it is necessary to allow a single field effect tube to pass the same current as the tail current, which places certain restrictions on the width-to-length ratio of the field effect tube. In order to achieve a larger width-to-length ratio at the smallest field effect tube size, it is necessary to minimize the length of the field effect tube. Under a certain process, the minimum length of the field effect tube is fixed, so the size of the field effect tube itself is also determined. That is, the length is the minimum length that can be achieved by the process used, and the width is the minimum length that can pass the required tail current under this length. The above analysis of the field effect tube size is based on a single-stage current mode logic driver structure. For the driver composed of the cascaded current mode logic driver proposed in the present invention, the field effect tube size selection of its second-stage current mode logic driver is consistent with the single-stage current mode logic driver. For the first-stage current mode logic driver, in order to achieve a balanced response to the rising and falling edges of the field effect tube of the second-stage current mode logic driver, a field effect tube of the same size as the second-stage current mode logic driver should also be used. Therefore, the low common mode noise driver proposed in the present invention is consistent with the single-stage current mode logic driver in the selection of the field effect tube size.

[0057] Figure 3 The accurate equivalent circuit model including parasitic capacitance established for the low common-mode noise driver proposed in the present invention is demonstrated. The extraction of these parasitic capacitance models is based on the physical structure and characteristics of the real device. Figure 3 middle, V DD is the power supply voltage, R L1 and R L2 are the load resistors of the first and second current mode logic drivers, respectively. In the first current mode logic driver, V op1 , V on1 is the drain voltage of the two field effect transistors and is also the differential output signal of the first-stage current mode logic driver. V s1 is the voltage of the common source of the two field effect transistors, Ip1 and I n1 is the source-drain current of the two field effect transistors, V ip and V in is the gate voltage of the two field effect transistors and is also the differential input signal of the first-stage current mode logic driver / low common mode noise driver. I ss1 is the tail current source. Similarly, in the second-stage current mode logic driver, V op2 , V on2 is the drain voltage of the two field effect transistors, and is the differential signal finally output by the low common mode noise driver. V s2 is the voltage of the common source of the two field effect transistors, I p2 and I n2 is the source-drain current of the two field effect transistors. The gates of the two field effect transistors are connected to the drain of the first-stage current mode logic driver, and the voltages are V op1 , V on1 , I ss1 is the tail current source. In this equivalent circuit model, each field effect tube uses a voltage-controlled current source and four parasitic capacitors to be equivalent. Among them, the controlled current source I p1 , I n1 , I p2 , I n2 Used for the source-drain current of the equivalent field effect transistor, which is affected by the gate-source voltage of the corresponding field effect transistor V GS and source-drain voltage V DS Joint control, the field effect tube voltage control current function extracted above is I DS ( V GS , V DS ). In addition, the parasitic capacitance of the extracted field effect tube is divided into gate-source capacitance, gate-drain capacitance, source junction capacitance, and drain junction capacitance according to the type, and the first two digits of their subscripts are gs , gd , js , jdThe third digit p or n of the parasitic capacitor subscript indicates that the differential signal branch it is in is the p branch or the n branch, respectively, and the fourth digit 1 or 2 indicates that it is in the first or second level current mode logic driver, respectively. The above naming rules for parasitic capacitors apply to Figure 3 All capacitors listed, e.g. C gsp1 represents the gate-source parasitic capacitance of the field effect transistor under the p-branch of the first-level current mode logic driver. In addition, Figure 3 In the figure, all currents are divided into different parts according to the associated nodes. The blue part of the current is associated with the common source of each level of current mode logic driver; the orange part of the current is associated with the drain output of each level of current mode logic driver; the green part of the current connects the output and input of the previous and next levels of current mode logic drivers.

[0058] In the field effect tube equivalent circuit model used in the present invention, the parasitic capacitance caused by the physical structure exists between any two ends of the field effect tube. Because the gate metal layer and the oxide layer of the field effect tube form a parallel plate capacitor structure with a larger area, the gate and source, gate and drain of the field effect tube all have larger parasitic capacitance values, and the size of this type of parasitic capacitance will change with the change of the working state of the field effect tube. Taking the N-type field effect tube as an example, a negative voltage is applied between its gate metal layer and the substrate, the field effect tube is in the cut-off region, the metal layer is negatively charged, and the substrate induces a positive charge. At this time, the main contribution of the parasitic capacitance of the field effect tube is the oxide layer capacitance. When a smaller positive voltage is applied between the gate metal layer and the substrate, the direction of the electric field in the oxide layer is directed from the gate to the substrate, and the carrier holes of a part of the substrate under the oxide layer are repelled due to positive charge, and this part of the substrate forms a space charge region. At this time, the parasitic capacitance of the field effect tube is mainly composed of the oxide layer capacitance and the space charge region capacitance in series, and the overall capacitance value is reduced. When the positive voltage between the gate metal layer and the substrate increases, on the one hand, the space charge region gradually increases, resulting in a decrease in capacitance, and on the other hand, the inversion layer charge begins to gradually appear and increases the overall capacitance, so the overall capacitance value first decreases and then increases. Figure 3In the equivalent circuit model shown, the parasitic capacitances affected by the physical structure of the parallel plate capacitor are the gate-source capacitance and the gate-drain capacitance. When the field effect tube is in the cut-off region, its gate-source capacitance and gate-drain capacitance are both contributed by the oxide layer capacitance of the field effect tube. When the gate voltage of the field effect tube begins to increase, the field effect tube begins to change from the cut-off region to the saturation region. In this process, a conductive channel begins to form in the substrate of the field effect tube. Although the source and drain of the field effect tube are symmetrical relative to the gate in terms of physical structure, in the process of forming the conductive channel, the gate-drain voltage is often less than the gate-source voltage, so the charge of the conductive channel tends to gradually accumulate from the source to the drain. The increase in channel charge capacitance causes the capacitance value between the gate and the source to continue to increase as the gate voltage increases. As for the gate-drain capacitance of the field effect tube, due to the influence of the channel modulation effect, the pinch-off point of the conductive channel of the field effect tube in the saturation region will move toward the source, so the channel will not be directly connected to the drain, and the gate-drain capacitance value is less affected by the channel charge, showing a relatively stable trend when the working area of ​​the field effect tube changes. In addition, different doping types at different locations of the field effect transistor will also cause a PN junction to form on the contact surface of the material (such as the N-doped source and P-doped substrate in an N-type field effect transistor), resulting in junction capacitance. In the N-type field effect transistor used in the current mode logic driver, the substrate is directly grounded, so the two PN junctions at the source and drain are in a reverse biased state. As the source and drain voltages increase, the carriers will be pulled away from the junction area. The reduction in the amount of charge in the junction area will reduce the PN junction capacitance at that location.

[0059] The specific embodiments of the present invention are as follows: First, the design requirements of the manufactured low common-mode noise driver are determined. The design requirements of this embodiment are: (1) the channel impedance is 50 ohms, and the output impedance must match the channel impedance; (2) the output swing reaches 0.4 volts. Therefore, under this design requirement, the load resistance used by the second-level current mode logic driver is determined to be 50 ohms, and the tail current is determined to be 8 mA.

[0060] Secondly, the integrated circuit manufacturing process used to manufacture the low common mode noise driver is selected. The manufacturing process used in this embodiment is TSMC's 65 nanometer process. The parameters of the field effect transistor device under the selected process are extracted to obtain the five parameter models of gate-source capacitance, gate-drain capacitance, source junction capacitance, drain junction capacitance and source-drain current mentioned in the specification.

[0061] Based on the extracted field effect tube parameter model and the low common mode noise driver equivalent model mentioned in the previous part of the manual, the circuit equations mentioned in the previous part of the manual are established to solve multiple groups of circuit parameters to be optimized ( R L1 , I SS1) to predict the output common mode noise. The result is as follows Figure 5 As shown, it can be seen that the common mode noise of the low common mode noise driver proposed by the present invention is related to the circuit parameters to be optimized: the load resistance of the first-stage current mode logic driver R L1 , the tail current of the first-stage current mode logic driver I SS1 Both are positively correlated. Figure 5 A set of circuit parameters corresponding to the minimum point of common mode noise ( R L1_min , I SS1_min ) as the optimization result of the driver circuit parameters. Figure 5 The functional relationship between the output common mode noise and the circuit parameters obtained in this embodiment shows that when the load resistance R of the first-stage current mode logic driver is L1 Take 178 ohms, tail current I ss1 When the output common mode noise of the driver is 4.04 mA, it reaches the minimum. Combined with the above-mentioned determined circuit parameters, the overall circuit parameters of the manufactured low common mode noise driver are: the first-stage current mode logic driver load resistance is 178 ohms, the tail current is 4.04 mA; the second-stage current mode logic driver load circuit is 50 ohms, and the tail current is 8 mA.

[0062] Figure 6 and Figure 7 The time domain waveform and spectrum comparison of the common mode part of the differential signal output by the manufactured low common mode noise driver and the single-stage current mode logic driver (load resistance is 50 ohms, tail current is 8 mA, and the field effect tube size and process are the same as those of the manufactured low common mode noise driver) are shown. The input signal of the comparison diagram is a 20 Gbps pseudo-random binary sequence (PRBS) signal. In the comparison of the time domain common mode waveform of the output differential signal, the fluctuation of the time domain common mode waveform of the low common mode noise driver proposed in the present invention when the input signal is flipped (0-10 picoseconds) is much smaller than that of the traditional current mode logic driver. In the comparison of the common mode spectrum diagram of the output differential signal, the low common mode noise driver proposed in the present invention achieves about 16 dB of noise optimization at the main signal frequency and its harmonic frequency compared with the traditional current mode logic driver.

[0063] The above content is combined with the accompanying drawings in detail to comprehensively describe the preferred embodiments of the present invention. However, it should be emphasized that the present invention is not limited to the specific details in the above embodiments. Under the guidance of the technical concept and design concept of the present invention, the technical solution of the present invention has wide applicability and flexibility, and can be subjected to a variety of simple and reasonable variations. Although these variations may differ from the above embodiments in some aspects, they are all based on the basic technical concept of the present invention and therefore should all be regarded as within the protection scope of the present invention.

[0064] It is further explained that the various technical features mentioned in the above specific embodiments are important components of the present invention. Without violating the basic principles and functions of the present invention, these technical features can be combined in any suitable manner according to actual needs and specific application scenarios. In order to save space and avoid unnecessary repetition, the present invention does not describe each possible combination one by one. However, this does not mean that these combinations are not within the scope of protection of the present invention.

[0065] In addition, different embodiments of the present invention also show extremely high compatibility and complementarity. Based on various embodiments, any combination and innovation can be made, as long as these combinations and innovations do not violate the core ideas and objectives of the present invention. Such combinations and innovations not only enrich the technical connotation of the present invention, but also expand its application field and improve its practical value. Therefore, these different embodiments and their combinations should also be regarded as the technical contents disclosed by the present invention.

[0066] In the design and application process of the present invention, we encourage technicians to flexibly apply and adjust the technical solutions of the present invention according to actual needs to achieve the best technical effects. At the same time, we also hope that technicians in related fields can continue to explore and research on the basis of the present invention, continuously promote technological progress, and meet the needs of social development. The protection scope of the present invention is not limited to the above-mentioned implementation methods, but also includes all variations, combinations and innovations within the scope of the technical concept of the present invention, which are the categories that the present invention expects to cover and protect.

Claims

1. A low common mode noise driver, characterized in that: The low common mode noise driver comprises two cascaded current mode logic drivers; The input end of the first-level current mode logic driver serves as the input end of the low common-mode noise driver, the output end of the first-level current mode logic driver is electrically connected to the input end of the second-level current mode logic driver, and the output end of the second-level current mode logic driver serves as the output end of the low common-mode noise driver.

2. The low common mode noise driver according to claim 1, characterized in that: The current mode logic driver includes two N-type field effect transistors with a common source, the common source is grounded through a constant current source, the drains of the two field effect transistors are respectively connected to a power supply through two load resistors with the same resistance, the gates of the two field effect transistors serve as input terminals of the current mode logic driver, and the drains of the two field effect transistors serve as output terminals of the current mode logic driver.

3. The low common mode noise driver according to claim 2, characterized in that: The drains of the two field effect transistors of the first-stage current mode logic driver are electrically connected to the gates of the two field effect transistors of the second-stage current mode logic driver respectively.

4. A method for manufacturing a low common mode noise driver as claimed in any one of claims 1 to 3, characterized in that: The following steps are involved: S1. Establish a parasitic capacitance model of the field effect tube according to the performance parameters of the field effect tube, and establish an equivalent circuit model of the low common mode noise driver according to the parasitic capacitance model; S2. Performing circuit analysis on an equivalent circuit model of the low common-mode noise driver to obtain a time domain waveform of the common-mode noise of the output signal under a plurality of different sets of circuit parameters to be optimized; S3. Predict the output common-mode noise according to the time domain waveform of the output signal common-mode noise under each group of circuit parameters to be optimized, obtain the relationship function between the circuit parameters to be optimized and the output signal common-mode noise, obtain the circuit parameters to be optimized corresponding to the minimum value of the output signal common-mode noise from the relationship function, use them as the optimal circuit parameters, and manufacture a low common-mode noise driver according to the optimal circuit parameters.

5. The method for manufacturing a low common mode noise driver according to claim 4, characterized in that: In the step S1, the parasitic capacitance model of the field effect transistor includes the gate-drain parasitic capacitance, the gate-source parasitic capacitance, the drain junction capacitance and the source junction capacitance of the field effect transistor at each DC operating point.

6. The method for manufacturing a low common mode noise driver according to claim 4, characterized in that: In step S1, the circuit equation of the equivalent circuit model is specifically: V op1 =V DD -R L1 I p1 V on1 =V DD -R L1 I n1 I p1 =I ds (V ip -V s1 ,V op1 -V s1 ) I n1 =I ds (V in -V s1 ,V on1 -V s1 ) I ss1 =I p1 + I n1 V op2 =V DD -R L2 I p2 V on2 =V DD -R L2 I n2 I p2 =I ds (V op1 -V s2 ,V op2 -V s2 ) I p2 =I ds (V on1 -V s2 ,V op2 -V s2 ) I ss2 =I p2 + I n2 Where V DD is the power supply voltage, R L1 , R L2 are the load resistances of the first-stage current mode logic driver and the second-stage current mode logic driver, V op1 、V on1 are the drain voltages of the two field effect transistors in the first-stage current mode logic driver, V s1 is the voltage of the common source of the two field effect transistors in the first-stage current mode logic driver, I p1 ,I n1 are the source and drain currents of the two field effect transistors in the first-stage current mode logic driver, V ip 、V in are the gate voltages of the two field effect transistors in the first-stage current mode logic driver, I ss1 is the tail current source of the first-stage current mode logic driver; V op2 、V on2 are the drain voltages of the two field effect transistors in the second-stage current mode logic driver, V s2 is the voltage of the common source of the two field effect transistors in the second-stage current mode logic driver, I p2 and I n2 are the source and drain currents of the two field effect transistors in the second-stage current mode logic driver, I ss2 is the tail current source for the second-stage current mode logic driver, I ds (V gs ,V ds ) is the source-drain current of the field effect transistor with respect to the gate-source voltage V gs and source-drain voltage V ds The functional relationship of .

7. The method for manufacturing a low common mode noise driver according to claim 4, characterized in that: In the step S2, the circuit analysis is specifically a dynamic response analysis of the driver during the input signal flipping process and a critical swing analysis of the current mode logic driver.

8. The method for manufacturing a low common mode noise driver according to claim 4, characterized in that: In step S3, the process of output common-mode noise prediction is specifically as follows: Fourier transform is performed on the time domain waveform of the output signal common-mode noise under each set of circuit parameters to be optimized to obtain the frequency spectrum of the output signal common-mode noise, and the maximum value of the AC component in the common-mode part frequency spectrum of the output signal common-mode noise is used as the output signal common-mode noise corresponding to the circuit parameters to be optimized, so as to obtain the functional relationship between the circuit parameters to be optimized and the output signal common-mode noise.

9. The method for manufacturing a low common mode noise driver according to claim 4, characterized in that: In step S2, each group of circuit parameters to be optimized is mainly composed of the load resistance and tail current of the first-level current mode logic driver.

10. The method for manufacturing a low common mode noise driver according to claim 9, characterized in that: In the step S2, before performing circuit analysis, the range of the product of the load resistance and tail current of the second-level current mode logic driver and the load resistance and tail current of the first-level current mode logic driver is set; The load resistance of the second-stage current mode logic driver is matched to the channel impedance; The product of the load resistance and tail current of the second-stage current mode logic driver matches the target output swing of the low common-mode noise driver; The product of the load resistance and the tail current of the first-stage current mode logic driver is greater than or equal to the critical swing of the second-stage current mode logic driver.

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