Heterogeneous electronic synapse device and preparation method and application thereof

Abstract

The invention discloses a heterogeneous electronic synapse device and a preparation method and application thereof, and belongs to the technical field of semiconductor devices. The heterogeneous electronic synapse device comprises a substrate, a connecting layer, a functional layer, a channel layer, a drain electrode, a source electrode, a first grid electrode and a second grid electrode, the connecting layer is arranged on part of the surface of the substrate; the functional layer is stacked on the surface of the connecting layer and covers the residual surface of the substrate; the functional layer comprises a first region serving as a dielectric layer and a second region serving as a ferroelectric layer which are connected, the first region is connected with the first grid electrode, and the second region is connected with the second grid electrode; the channel layer is arranged on the surface of the functional layer and located between the source electrode and the drain electrode. The heterogeneous electronic synaptic device transversely integrates the synergistic interaction of the first grid electrode and the second grid electrode, has a complete electric modulation capability, successfully simulates the heterosynaptic plasticity in a biological nervous system, and effectively meets the requirements of advanced neuromorphic calculation. The preparation method is simple and easy to operate.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a heterogeneous electronic synapse device and a preparation method and application thereof. Background Art

[0002] The research scope of artificial intelligence is extremely broad, covering multiple dimensions from robotics to speech recognition, image recognition, natural language processing, and complex expert systems. With the rapid advancement of science and technology, artificial intelligence has quietly integrated into every corner of our daily lives, such as the intelligent management of smart home systems, the increasing maturity of autonomous driving technology, and assisting doctors in making accurate diagnoses in the medical field. However, the development of artificial intelligence is also accompanied by an urgent need for higher-performance processors. The currently widely used data processing model is storage and computing separation. Although it gives the processor powerful computing power, its energy efficiency ratio is generally low, which has become a bottleneck restricting the further development of artificial intelligence.

[0003] In this context, neuromorphic computing has emerged as an innovative computing paradigm. Neuromorphic computing simulates the structure and functional principles of biological nervous systems, and attempts to reproduce the complex physiological structure and information processing mechanism of the nervous system by building a very large-scale integrated circuit system containing electronic analog circuits. The core goal of neuromorphic computing is to learn from the brain's efficient and energy-saving computing mode to optimize the existing computing system architecture and achieve improvements in computing efficiency and energy utilization.

[0004] Heterosynapse is a biological structure formed by presynaptic neurons, postsynaptic neurons and astrocytes, and is a crucial way of information transmission in biological systems. As an important research aspect of neuromorphic computing, heterosynapse simulation has unique advantages in learning methods such as adaptive learning, and has become an important research aspect of neuromorphic computing.

[0005] There are many non-volatile memories that have been used to simulate synaptic functions. However, these are usually designed to simulate the plasticity of two-terminal homosynapses and are insufficient in simulating the adjustability of heterosynapses.

[0006] In view of this, the present invention is proposed. Summary of the invention

[0007] The object of the present invention is to provide a heterogeneous electronic synapse device and a preparation method and application thereof, so as to solve or improve the above-mentioned technical problems.

[0008] The present invention can be implemented like this:

[0009] In a first aspect, the present invention provides a heterogeneous electronic synapse device, the heterogeneous electronic synapse device comprising a substrate, a connection layer, a functional layer, a channel layer, a drain, a source, a first gate and a second gate;

[0010] A connection layer is arranged on a part of the surface of the substrate; a functional layer is stacked on the surface of the connection layer and covers the remaining surface of the substrate; the functional layer includes a first region as a dielectric layer and a second region as a ferroelectric layer which are connected, wherein the first region is connected to a first gate and the second region is connected to a second gate; a channel layer is arranged on the surface of the functional layer and is located between a source electrode and a drain electrode.

[0011] In an optional embodiment, the first gate and the second gate are symmetrically arranged on the same horizontal plane.

[0012] In an optional embodiment, the connection layer is made of a material including titanium nitride;

[0013] And / or, the preparation material of the functional layer includes HfZrO x ;

[0014] And / or, the channel layer is made of materials including indium gallium zinc oxide;

[0015] And / or, the drain electrode, the source electrode, the first gate electrode and the second gate electrode are made of materials independently including titanium.

[0016] In an optional embodiment, the thickness of the connecting layer is 15 nm to 25 nm;

[0017] and / or, the thickness of the functional layer is 10 nm to 20 nm;

[0018] And / or, the thickness of the channel layer is 10 nm to 20 nm, the distance between the source and the drain corresponding to the channel layer is 5 μm to 15 μm, and the extension distance of the channel layer from the first gate to the second gate is 35 μm to 45 μm.

[0019] In a second aspect, the present invention provides a method for preparing a heterogeneous electronic synapse device according to any one of the aforementioned embodiments, comprising the following steps:

[0020] Preparing a connection layer on one side of the substrate according to a preset position;

[0021] Preparing a functional layer on the surface of the connecting layer according to a preset position;

[0022] Preparing a channel layer on the surface of the functional layer according to a preset position;

[0023] The drain, source, first gate and second gate are prepared according to the preset positions.

[0024] In an optional embodiment, the connecting layer is prepared by radio frequency sputtering;

[0025] and / or, the functional layer is prepared by atomic deposition;

[0026] and / or, the channel layer is prepared by sputtering;

[0027] And / or, the first gate, the second gate, the drain and the source are prepared by lift-off method.

[0028] In an optional embodiment, after the first gate, the second gate, the drain and the source are prepared, an annealing process is further included.

[0029] In an optional embodiment, the annealing is carried out under a protective atmosphere at 380° C. to 420° C. for 25 seconds to 35 seconds.

[0030] In a third aspect, the present invention provides a heterogeneous electronic synapse device array, which is integrated in the form of an array after connecting the heterogeneous electronic synapse device according to any of the aforementioned embodiments with a gating device.

[0031] In a fourth aspect, the present invention provides a use of a heterogeneous electronic synapse device according to any one of the aforementioned embodiments or a heterogeneous electronic synapse device array according to the aforementioned embodiments in simulating the function of astrocytes in biological synapses.

[0032] The beneficial effects of the present invention include:

[0033] The heterogeneous electronic synaptic device provided by the present invention can adjust the synaptic activity simulated by the ferroelectric field effect transistor by adjusting the voltage of the second gate, allowing the increase or change of the simulated information transmission. The principle is that the polarization of the ferroelectric capacitor where the second gate is located produces positive regulation, thereby enhancing the conductance regulation of the field effect transistor where the first gate is located. Through the synergistic effect of the first gate and the second gate, the regulation of the presynaptic nerve on the postsynaptic neuron can be simulated to accelerate or inhibit. The synergistic effect of multiple gates will change the potential of the floating gate, thereby adjusting the concentration of channel carriers. Different modulation rates can be achieved by changing the bias of the second gate.

[0034] The heterogeneous electronic synaptic device has full electrical modulation capability through the synergistic interaction of the first gate and the second gate, successfully simulates the heterosynaptic plasticity in the biological nervous system, and effectively meets the needs of advanced neuromorphic computing. Its preparation method is simple and easy to operate. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 A top view of the heterogeneous electronic synapse device provided by the present invention;

[0037] Figure 2 A cross-sectional view of the heterogeneous electronic synapse device provided by the present invention;

[0038] Figure 3 is the ferroelectric capacitance polarization voltage curve of the heterogeneous electronic synapse device in the experimental example;

[0039] Figure 4 is the transfer curve of the multi-gate in the experimental example;

[0040] Figure 5 This is a graph showing the synaptic characteristics of the gate voltage modulation in the experimental example.

[0041] Icon: 10 - substrate; 20 - connection layer; 30 - functional layer; 40 - channel layer; 51 - drain; 52 - source; 61 - first gate; 62 - second gate. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the technical scheme in the embodiments of the present invention will be described clearly and completely below. If the specific conditions are not specified in the embodiments, they are carried out according to conventional conditions or conditions recommended by the manufacturer. If the manufacturer of the reagents or instruments used is not specified, they are all conventional products that can be purchased commercially.

[0043] The heterogeneous electronic synapse device provided by the present invention and its preparation method and application are described in detail below.

[0044] The present invention provides a heterogeneous electronic synaptic device, combining Figure 1 and Figure 2 , the heterogeneous electronic synapse device includes a substrate 10, a connection layer 20, a functional layer 30, a channel layer 40, a drain 51, a source 52, a first gate 61 (represented by Gate-1) and a second gate 62 (represented by Gate-2);

[0045] The connecting layer 20 is arranged on a partial surface of the substrate 10; the functional layer 30 is stacked on the surface of the connecting layer 20 and covers the remaining surface of the substrate 10; the functional layer 30 includes a first region as a dielectric layer and a second region as a ferroelectric layer, wherein the first region is connected to the first gate 61 and the second region is connected to the second gate 62; the channel layer 40 is arranged on the surface of the functional layer 30 and is located between the source 52 and the drain 51.

[0046] The second gate 62, the functional layer 30 and the connection layer 20 form a ferroelectric capacitor together, and the first gate 61, the channel layer 40, the source 52 and the drain 51 form a thin film transistor together. The first region of the functional layer 30 serves as a dielectric layer of the thin film transistor, and the second region of the functional layer 30 serves as a ferroelectric layer of the ferroelectric capacitor.

[0047] In the present invention, the first gate 61 and the second gate 62 are symmetrically arranged on the same horizontal plane. In some typical embodiments, the first gate 61 and the second gate 62 are symmetrically arranged at both ends of the channel of the channel layer 40, which can also be understood as follows: the channel of the channel layer 40 has a first end and a second end opposite to each other along its length direction, the first gate 61 is spaced apart from the first end of the channel, the second gate 62 is spaced apart from the second end of the channel, and the distance between the first gate 61 and the first end of the channel is equal to the distance between the second gate 62 and the second end of the channel.

[0048] In some optional embodiments, the material for preparing the above-mentioned connection layer 20 may exemplarily include titanium nitride, and other metal materials may also be used, and the metal includes at least one of Ti, Au, Pt and W.

[0049] For example, the thickness of the connecting layer 20 can be 15 nm to 25 nm, such as 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm or 25 nm, etc., or other values ​​within the range of 15 nm to 25 nm. In some typical embodiments, the thickness of the connecting layer 20 is 20 nm.

[0050] In some optional embodiments, the material for preparing the functional layer 30 may exemplarily include HfZrO x Other ferroelectric materials may also be used, including HfO2 (which may be further doped with at least one of Zr, Al, Si, Y and La, etc.), lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), polyvinylidene fluoride (PVDF) and its copolymers, etc.

[0051] For example, the thickness of the functional layer 30 may be 10 nm to 20 nm, such as 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm or 20 nm, or other values ​​within the range of 10 nm to 20 nm. In some typical embodiments, the thickness of the functional layer 30 is 15 nm.

[0052] In some optional embodiments, the material used to prepare the channel layer 40 may illustratively include indium gallium zinc oxide, and other oxide semiconductors including ZnO and In2O3 may also be used.

[0053] For example, the thickness of the channel layer 40 may be 10 nm to 20 nm, such as 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm or 20 nm, or other values ​​within the range of 10 nm to 20 nm. In some typical embodiments, the thickness of the channel layer 40 is 15 nm.

[0054] The distance between the source 52 and the drain 51 corresponding to the channel layer 40 can be 5 μm to 15 μm, such as 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm or 15 μm, etc., or other values ​​within the range of 5 μm to 15 μm. In some typical embodiments, the distance between the source 52 and the drain 51 corresponding to the channel layer 40 is 10 μm.

[0055] The extension distance of the channel layer 40 from the first gate 61 to the second gate 62 may be 35 μm to 45 μm, such as 35 μm, 36 μm, 37 μm, 38 μm, 39 μm, 40 μm, 41 μm, 42 μm, 43 μm, 44 μm or 45 μm, etc., or other values ​​within the range of 35 μm to 45 μm. In some typical embodiments, the extension distance of the channel layer 40 from the first gate 61 to the second gate 62 is 40 μm.

[0056] In some optional embodiments, the drain electrode 51 , the source electrode 52 , the first gate electrode 61 , and the second gate electrode 62 are made of materials independently including titanium.

[0057] As mentioned above, the synaptic activity simulated by the ferroelectric field effect transistor can be adjusted by adjusting the voltage of the second gate 62, allowing the increase or change of the simulated information transmission. The principle is that the polarization of the ferroelectric capacitor where the second gate 62 is located produces positive regulation, thereby enhancing the conductance regulation of the field effect transistor where the first gate 61 is located. Through the synergistic effect of the first gate 61 and the second gate 62, the regulation of the presynaptic nerve on the postsynaptic neuron can be simulated to accelerate or inhibit. The synergistic effect of multiple gates will change the potential of the floating gate, thereby adjusting the concentration of channel carriers. Different modulation rates can be achieved by changing the bias of the second gate 62.

[0058] In some preferred embodiments, the modulation range of conductance can be purposefully adjusted by more than 10 times. Coupled with the low energy consumption of 150fJ per spike, the above-mentioned heterogeneous electronic synaptic device can provide a new way for advanced synaptic devices to improve the efficiency of neuromorphic computing systems by virtue of its high-order synaptic plasticity simulation.

[0059] Accordingly, the present invention also provides a method for preparing the above-mentioned heterogeneous electronic synapse device, comprising the following steps:

[0060] A connection layer 20 is formed on one side of the substrate 10 according to a preset position;

[0061] A functional layer 30 is formed on the surface of the connecting layer 20 according to a preset position;

[0062] A channel layer 40 is formed on the surface of the functional layer 30 according to a preset position;

[0063] The drain electrode 51 , the source electrode 52 , the first gate electrode 61 and the second gate electrode 62 are prepared according to the preset positions.

[0064] The connection layer 20 may be prepared by radio frequency sputtering. The functional layer 30 may be prepared by atomic deposition. The channel layer 40 may be prepared by sputtering, which may also include a patterning process. The first gate 61, the second gate 62, the drain 51 and the source 52 may be prepared by lift-off, and the first gate 61, the second gate 62, the drain 51 and the source 52 may be formed by a single patterning process.

[0065] Furthermore, after the first gate 61 , the second gate 62 , the drain 51 and the source 52 are prepared, an annealing process is also included.

[0066] Annealing may be performed under a protective atmosphere, wherein the protective atmosphere may be, for example, a nitrogen atmosphere, an argon atmosphere, or the like.

[0067] The annealing temperature may be 380°C to 420°C, such as 380°C, 385°C, 390°C, 395°C, 400°C, 405°C, 410°C, 415°C or 420°C, or other values ​​within the range of 380°C to 420°C.

[0068] The annealing holding time may be 25s to 35s, such as 25s, 28s, 30s, 32s or 35s, or may be other values ​​within the range of 25s to 35s.

[0069] In some specific embodiments, a multi-gate ferroelectric thin film transistor can be fabricated on a SiO2 / Si substrate 10. The floating gate is formed by depositing a 20 nm TiN layer using radio frequency (RF) sputtering to connect the ferroelectric capacitor and the thin film transistor. A pattern is formed by wet etching. Then, a 15 nm HfZrO layer is deposited by atomic layer deposition at 280°C. x The film is used as the ferroelectric layer of the capacitor and the dielectric layer of the thin film transistor. 22H5)CH3]4 and H2O are used as hafnium source, zirconium source and oxygen source, respectively. Then a 15nm indium gallium zinc oxide (IGZO) channel layer 40 is manufactured by sputtering and patterned by wet etching. A 5nm / 45nm Ti / Au source 52 / drain 51 and gate electrode are formed by lift-off. Then the whole is annealed at 400°C for 30s under nitrogen to induce the ferroelectric properties of the ferroelectric capacitor. The first gate 61 and the second gate 62 are two symmetrical gates integrated laterally.

[0070] It should be noted that the preparation process and conditions not described in detail in the present invention can refer to the relevant existing technologies for semiconductor preparation, and will not be elaborated or limited in detail here.

[0071] In addition, the present invention also provides a heterogeneous electronic synapse device array, which can be integrated in the form of an array by connecting the above-mentioned heterogeneous electronic synapse device with a gating device.

[0072] In addition, the present invention also provides a use of the above-mentioned heterogeneous electronic synapse device or the above-mentioned heterogeneous electronic synapse device array in simulating the function of astrocytes in biological synapses.

[0073] Through this application, heterosynaptic plasticity in biological nervous systems can be successfully simulated, effectively meeting the needs of advanced neuromorphic computing.

[0074] The features and performance of the present invention are further described in detail below in conjunction with the embodiments.

[0075] Example 1

[0076] This embodiment provides a heterogeneous electronic synapse device, which includes a substrate 10, a connection layer 20, a functional layer 30, a channel layer 40, a drain 51, a source 52, a first gate 61 and a second gate 62;

[0077] The connecting layer 20 is arranged on a partial surface of the substrate 10; the functional layer 30 is stacked on the surface of the connecting layer 20 and covers the remaining surface of the substrate 10; the functional layer 30 includes a first region as a dielectric layer and a second region as a ferroelectric layer, wherein the first region is connected to the first gate 61 and the second region is connected to the second gate 62; the channel layer 40 is arranged on the surface of the functional layer 30 and is located between the source 52 and the drain 51.

[0078] The second gate 62, the functional layer 30 and the connection layer 20 form a ferroelectric capacitor together, and the first gate 61, the channel layer 40, the source 52 and the drain 51 form a thin film transistor together. The first region of the functional layer 30 serves as a dielectric layer of the thin film transistor, and the second region of the functional layer 30 serves as a ferroelectric layer of the ferroelectric capacitor.

[0079] The channel of the channel layer 40 has a first end and a second end opposite to each other along its length direction, and the first gate 61 and the second gate 62 are symmetrically arranged at both ends of the channel of the channel layer 40 on the same horizontal plane, that is, the first gate 61 is spaced apart from the first end of the channel, the second gate 62 is spaced apart from the second end of the channel, and the distance between the first gate 61 and the first end of the channel is equal to the distance between the second gate 62 and the second end of the channel.

[0080] The thickness of the connecting layer 20 is 20 nm, the thickness of the functional layer 30 is 15 nm, the thickness of the channel layer 40 is 15 nm, the distance between the source 52 and the drain 51 of the channel layer 40 is 10 μm, and the extension distance of the channel layer 40 from the first gate 61 to the second gate 62 is 40 μm.

[0081] Example 2

[0082] The difference between this embodiment and embodiment 1 is that the thickness of the connecting layer 20 is 15 nm, the thickness of the functional layer 30 is 10 nm, the thickness of the channel layer 40 is 10 nm, the distance between the source 52 and the drain 51 corresponding to the channel layer 40 is 5 μm, and the extension distance of the channel layer 40 from the first gate 61 to the second gate 62 is 35 μm.

[0083] Example 3

[0084] The difference between this embodiment and embodiment 1 is that the thickness of the connecting layer 20 is 25 nm, the thickness of the functional layer 30 is 20 nm, the thickness of the channel layer 40 is 20 nm, the distance between the source 52 and the drain 51 of the channel layer 40 is 15 μm, and the extension distance of the channel layer 40 from the first gate 61 to the second gate 62 is 45 μm.

[0085] Example 4

[0086] This embodiment provides a method for preparing the heterogeneous electronic synapse device of embodiment 1, comprising:

[0087] A TiN layer of a preset thickness is deposited on the SiO2 substrate 10 by radio frequency (RF) sputtering to connect the ferroelectric capacitor and the thin film transistor, and a pattern is formed by wet etching. Then, a HfZrO layer of a preset thickness is deposited by atomic deposition at 280°C. x The film is used as the ferroelectric layer of the capacitor and the dielectric layer of the thin film transistor. 22H5)CH3]4 and H2O are used as hafnium source, zirconium source and oxygen source, respectively. Then, an indium gallium zinc oxide (IGZO) channel layer 40 of a preset thickness is fabricated by sputtering and patterned by wet etching. A 5nm / 45nm Ti / Au source 52 / drain 51 and gate electrode are formed by lift-off. Then, the whole is annealed at 400°C for 30s under nitrogen to induce the ferroelectric properties of the ferroelectric capacitor.

[0088] Example 5

[0089] The difference between this embodiment and embodiment 4 is that the annealing temperature is 380° C. and the holding time is 35 s.

[0090] Example 6

[0091] The difference between this embodiment and embodiment 4 is that the annealing temperature is 420° C. and the holding time is 25 seconds.

[0092] Test example

[0093] The performance of the heterogeneous electronic synapse device prepared in Example 1 was tested.

[0094] Among them, the ferroelectric capacitor polarization voltage curve of the heterogeneous electronic synaptic device is as follows Figure 3 As shown. Figure 3 It can be seen that the polarization increases with the increase of the scanning voltage with a frequency of 10 kHz and a range of 2 V to 3 V. The ferroelectric capacitor having the symmetric first gate 61 and the second gate 62 has good electrical performance consistency.

[0095] The transfer curve of multi-gate is as follows Figure 4 Due to the symmetry of the device structure, the two transmission curves of the ferroelectric capacitance of the first gate 61 and the second gate 62 are substantially overlapped, and the bidirectional scanning results are substantially consistent, which indicates that the device has excellent stability.

[0096] The synaptic characteristics of the gate voltage modulation are as follows Figure 5 Activated astrocytes can enhance or inhibit the release of neurotransmitters, thereby increasing or decreasing changes in synaptic weight to adapt to a variety of complex situations. Figure 5It is shown that applying a negative modulating gate voltage significantly enhances the change in conductance (ΔG / Gmin), while applying a positive modulating gate voltage inhibits the change in conductance. This process is similar to the enhancement and inhibition of synaptic activity by astrocytes. Under the conditions of a pulse amplitude of 2V to 5V and a pulse width of 100μs, 30 pulses were applied continuously with an increment of 0.1V. Without applying the second gate 62 voltage, the synaptic weight increased by 10.7%, while when the second gate 62 voltage was -1V (1V), the synaptic weight increased by 22.7% (1.6%), and the dynamic modulation range exceeded 10 times. This phenomenon is attributed to the modulation of the second gate 62 on the IGZO channel.

[0097] In summary, the present invention successfully demonstrated an all-electrically modulated lateral multi-gate heterosynaptic FeTFT with the advantages of simple process and multi-gate scalability. The additional modulation gate significantly regulates synaptic plasticity with a modulation range of more than 10 times, consuming a low energy of 150fJ per spike, accurately simulating the activity of astrocytes. Compared with traditional homologous synaptic devices that only include presynaptic and postsynaptic neurons, the proposed multi-gate FeTFT device simulates more complex biological synaptic functions, greatly improves the operating range of synaptic weights, and brings huge energy-saving benefits. This research provides an innovative way to realize energy-saving neuromorphic computing hardware systems.

[0098] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A heterogeneous electronic synaptic device, characterized in that: The heterogeneous electronic synapse device includes a substrate, a connection layer, a functional layer, a channel layer, a drain, a source, a first gate and a second gate; The connecting layer is arranged on a part of the surface of the substrate; the functional layer is stacked on the surface of the connecting layer and covers the remaining surface of the substrate; the functional layer includes a first region as a dielectric layer and a second region as a ferroelectric layer which are connected, wherein the first region is connected to the first gate and the second region is connected to the second gate; the channel layer is arranged on the surface of the functional layer and is located between the source and the drain.

2. The heterogeneous electronic synapse device according to claim 1, characterized in that: The first grid and the second grid are symmetrically arranged on the same horizontal plane.

3. The heterogeneous electronic synapse device according to claim 1 or 2, characterized in that: The connection layer is made of titanium nitride. And / or, the preparation material of the functional layer includes HfZrO x ; And / or, the channel layer is made of a material including indium gallium zinc oxide; And / or, the drain electrode, the source electrode, the first gate electrode and the second gate electrode are independently made of titanium.

4. The heterogeneous electronic synapse device according to claim 1 or 2, characterized in that: The thickness of the connecting layer is 15nm to 25nm; And / or, the thickness of the functional layer is 10nm to 20nm; And / or, the thickness of the channel layer is 10 nm to 20 nm, the distance between the source and the drain corresponding to the channel layer is 5 μm to 15 μm, and the extension distance of the channel layer from the first gate to the second gate is 35 μm to 45 μm.

5. A method for preparing a heterogeneous electronic synapse device according to any one of claims 1 to 4, characterized in that: The following steps are involved: Preparing the connection layer on one side surface of the substrate according to a preset position; Preparing the functional layer on the surface of the connecting layer according to a preset position; Preparing the channel layer on the surface of the functional layer at a preset position; The drain, the source, the first gate and the second gate are prepared according to preset positions.

6. The preparation method according to claim 5, characterized in that: The connecting layer is prepared by radio frequency sputtering; And / or, the functional layer is prepared by atomic deposition; And / or, the channel layer is prepared by sputtering; And / or, the first gate, the second gate, the drain and the source are prepared by lift-off method.

7. The preparation method according to claim 5 or 6, characterized in that: After the first gate, the second gate, the drain and the source are prepared, an annealing process is also included.

8. The preparation method according to claim 7, characterized in that: Annealing is carried out under a protective atmosphere at 380°C to 420°C for 25s to 35s.

9. A heterogeneous electronic synaptic device array, characterized in that: The heterogeneous electronic synapse device as claimed in any one of claims 1 to 3 is connected with a gating device and integrated in the form of an array.

10. Use of the heterogeneous electronic synaptic device according to any one of claims 1 to 3 or the heterogeneous electronic synaptic device array according to claim 9 in simulating the function of astrocytes in biological synapses.

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