Semiconductor structure and forming method thereof
In the semiconductor structure formation method, an etching process is performed to ensure that the thickness of the gate structure gap oxide layer in the input and output device region and the core device region is consistent, and the problem of residual gap oxide layer in the gate structure gap of the input and output device region is solved, and avoiding the problem of the gate structure gap oxide layer in the input and output device region. The risk of defects in subsequent processes is achieved.
Patent Information
- Application Number
- CN202411683069.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-22
- Publication Date
- 2025-02-21
AI Technical Summary
The oxide layer remaining in the gate structure gap of the input and output device region cannot be covered by the side wall protective layer, and in subsequent processes, it is easy to cause defects in the gate-level structure due to chemical attacks.
By providing a method of forming a semiconductor structure, including forming a gate oxide layer of the core device region and the input and output device region on the substrate, and performing a first etching process to form a first trench, followed by performing a second etching The process ensures the thickness of the oxide layer of the second gate structure gap of the input and output device region and the first of the core device region by simultaneously etching the hard mask layer, the polysilicon layer, the first gate oxide layer and the second gate oxide layer. The thickness of the oxide layer in the gate structure gap is the same.
The oxide layer of the gate-level structure gap of the input and output device area is removed, avoiding the defect problem caused by the oxide layer being attacked by chemicals in the subsequent process because it cannot be covered by the side wall protective layer.
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Figure CN119497419A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] With the rapid development of integrated circuit manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions, integrated circuit chips are developing towards higher device density and higher integration. Usually, a complete set of semiconductor devices includes at least one core device (Core device) and at least one input-output device (IO device) integrated on the same semiconductor substrate. The core device is formed in the core device area and is used to realize the main functions of the integrated circuit, including core PMOS devices and core NMOS devices. The IO device is formed in the input-output device area and is used to provide corresponding input signals for the core device or output the corresponding signals of the core device. The operating voltage of the IO device is higher than the operating voltage of the core device. Therefore, the thickness of the gate oxide layer in the IO device area is greater than the thickness of the gate oxide layer in the core device area. Before gate etching, the gate oxide layer thickness of the two areas is significantly different. The final over-etching step of the gate etching process is to use a high selectivity method so that it does not damage the underlying oxide layer. For this reason, the residual oxide layer in the gate structure gap of the IO device area cannot be eliminated. Therefore, the gate oxide layer in the gate structure gap of the IO device area cannot be completely etched, resulting in the gate oxide layer in the IO device area being unable to be covered by the sidewall protection layer, which is prone to cause gate structure defects due to chemical attacks in subsequent processes. Summary of the invention
[0003] The purpose of the present invention is to provide a semiconductor structure and a method for forming the same, so as to solve the problem that the oxide layer remaining in the gap of the gate structure of the input and output device cannot be covered by the sidewall protection layer, and is easily attacked by chemicals in subsequent processes, thereby causing defects in the gate structure.
[0004] In order to solve the above technical problems, the present invention provides a method for forming a semiconductor structure, comprising:
[0005] A substrate is provided, the substrate comprising a core device region and an input-output device region, a first gate oxide layer located in the core device region and a second gate oxide layer located in the input-output device region are formed on the substrate, and a polysilicon layer and a hard mask layer covering the first gate oxide layer and the second gate oxide layer are formed, and the thickness of the second gate oxide layer in the input-output device region is greater than the thickness of the first gate oxide layer in the core device region;
[0006] Performing a first etching process to etch the hard mask layer and the polysilicon layer in the input / output device region to form a first trench, wherein the first trench penetrates the hard mask layer and extends into the polysilicon layer;
[0007] A second etching process is performed to simultaneously etch the hard mask layer, the polysilicon layer, the first gate oxide layer and the second gate oxide layer of the core device area and the input-output device area to form a first gate structure of the core device area and a second gate structure of the input-output device area, and the thickness of the second gate oxide layer in the gap between the second gate structure of the input-output device area is the same as the thickness of the first gate oxide layer in the gap between the first gate structure of the core device area.
[0008] Optionally, the second etching process includes:
[0009] Performing a first sub-etching process to simultaneously etch the hard mask layer and the polysilicon layer of the core device region and the input / output device region, and stopping the etching on the second gate oxide layer of the input / output device region;
[0010] Performing a second sub-etching process to etch the polysilicon layer in the core device area and simultaneously etch the second gate oxide layer on the input / output device area;
[0011] Performing a third sub-etching process to continue etching the polysilicon layer in the core device area;
[0012] A fourth sub-etching process is performed to simultaneously etch the first gate oxide layer of the core device area and the second gate oxide layer of the input-output device area, so that the thickness of the second gate oxide layer of the second gate structure gap of the input-output device area is the same as the thickness of the first gate oxide layer of the first gate structure gap of the core device area.
[0013] Optionally, etching gases of the first sub-etching process and the third sub-etching process are hydrogen bromide and helium.
[0014] Optionally, the etching gas of the second sub-etching process is a fluorine-containing gas.
[0015] Optionally, the etching solution of the fourth sub-etching process is hydrofluoric acid.
[0016] Optionally, the depth of the first trench is 50 angstroms to 100 angstroms.
[0017] Optionally, before performing the first etching process, the process includes:
[0018] forming a first photoresist layer, wherein the first photoresist layer covers the hard mask layer;
[0019] A first photolithography process is performed to form a first opening in the first photoresist layer in the input-output device region to define a second gate structure region in the input-output device region.
[0020] Optionally, before performing the second etching process, the method includes:
[0021] forming a second photoresist layer, wherein the second photoresist layer covers the hard mask layer;
[0022] A second photolithography process is performed to form a second opening in the second photoresist layer in the core device area to define a first gate structure region in the core device area and expose the first opening in the input-output device area.
[0023] Optionally, after forming the first gate structure in the core device area and the second gate structure in the input / output device area, a sidewall is formed, the sidewall covering the sidewall of the first gate structure, the sidewall of the first gate oxide layer, the sidewall of the second gate structure and the sidewall of the second gate oxide layer.
[0024] Based on the same inventive concept, the present invention further provides a semiconductor structure, which is manufactured using any of the above-mentioned methods for forming a semiconductor structure.
[0025] In the method for forming a semiconductor structure provided by the present invention, a first etching process is first performed to etch the hard mask layer and polysilicon layer of the input-output device area to form a first groove, the first groove penetrates the hard mask layer and extends into the polysilicon layer; then a second etching process is performed to simultaneously etch the hard mask layer, polysilicon layer, first gate oxide layer and second gate oxide layer of the core device area and the input-output device area to form a first gate structure of the core device area and a second gate structure of the input-output device area, and the thickness of the second gate oxide layer of the second gate structure gap of the input-output device area is made the same as the thickness of the first gate oxide layer of the first gate structure gap of the core device area. The present invention etches and thins the thickness of the polysilicon layer of the input-output device area in advance, and can remove the second oxide layer of the gate structure gap of the input-output device area, solving the problem that the second oxide layer remaining in the gate structure gap of the input-output device area cannot be covered by the sidewall protection layer, and is easily attacked by chemicals in subsequent processes, thereby causing defects in the gate structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.
[0027] Figure 1 It is a flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention.
[0028] Figure 2 It is a schematic structural diagram of forming a first patterned photoresist layer according to an embodiment of the present invention.
[0029] Figure 3 It is a schematic structural diagram of forming a first opening according to an embodiment of the present invention.
[0030] Figure 4 It is a schematic structural diagram of forming a second patterned photoresist layer according to an embodiment of the present invention.
[0031] Figure 5 It is a schematic diagram of the structure after the first sub-etching process is performed in an embodiment of the present invention.
[0032] Figure 6 It is a schematic diagram of the structure after executing the second sub-etching process and the third sub-etching process according to an embodiment of the present invention.
[0033] Figure 7 It is a schematic diagram of the structure after executing the fourth sub-etching process according to an embodiment of the present invention.
[0034] Figure 8 It is a schematic diagram of the structure after the side wall is formed according to an embodiment of the present invention.
[0035] In the attached figure:
[0036] 10-substrate; 10a-core device area; 10b-input and output device area; 10c-cutting road; 11-shallow trench isolation structure; 12a-first gate oxide layer; 12b-second gate oxide layer; 13-polysilicon layer; 13a-first gate structure; 13b-second gate structure; 14-hard mask layer; 15-patterned first photoresist layer; 15a-first opening; 16-first trench; 17-patterned second photoresist layer; 17a-second opening; 18-side wall. DETAILED DESCRIPTION
[0037] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.
[0038] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second" and "third" can explicitly or implicitly include one or at least two of the features. In addition, as used in the present invention, an element is arranged on another element, which usually only indicates that there is a connection, coupling, matching or transmission relationship between the two elements, and the connection, coupling, matching or transmission between the two elements can be direct or indirect through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, an element can be in any orientation such as inside, outside, above, below or on one side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0039] Figure 1 FIG. 1 is a flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention. Figure 1 As shown, this embodiment provides a method for forming a semiconductor structure, comprising:
[0040] Step S10, providing a substrate, the substrate comprising a core device region and an input-output device region, a first gate oxide layer located in the core device region and a second gate oxide layer located in the input-output device region, and a polysilicon layer and a hard mask layer covering the first gate oxide layer and the second gate oxide layer are formed on the substrate, and the thickness of the second gate oxide layer in the input-output device region is greater than the thickness of the first gate oxide layer in the core device region;
[0041] Step S20, performing a first etching process to etch the hard mask layer and the polysilicon layer in the input / output device region to form a first trench, wherein the first trench penetrates the hard mask layer and extends into the polysilicon layer;
[0042] Step S30, performing a second etching process, simultaneously etching the hard mask layer, the polysilicon layer, the first gate oxide layer and the second gate oxide layer of the core device area and the input-output device area, forming a first gate structure of the core device area and a second gate structure of the input-output device area, and making the thickness of the second gate oxide layer in the gap between the second gate structure of the input-output device area the same as the thickness of the first gate oxide layer in the gap between the first gate structure of the core device area.
[0043] Figure 2 It is a schematic structural diagram of forming a first patterned photoresist layer according to an embodiment of the present invention. Figure 3 It is a schematic structural diagram of forming a first opening according to an embodiment of the present invention. Figure 4 It is a schematic structural diagram of forming a second patterned photoresist layer according to an embodiment of the present invention. Figure 5 It is a schematic diagram of the structure after the first sub-etching process is performed in an embodiment of the present invention. Figure 6 It is a schematic diagram of the structure after executing the second sub-etching process and the third sub-etching process according to an embodiment of the present invention. Figure 7 It is a schematic diagram of the structure after executing the fourth sub-etching process according to an embodiment of the present invention. Figure 8 1 is a schematic diagram of the structure of the embodiment of the present invention after the side wall is formed. In order to make the above-mentioned purpose, features and beneficial effects of the present invention more obvious and easy to understand, the following is a schematic diagram of the structure of the embodiment of the present invention after the side wall is formed. Figures 2 to 8 The specific embodiments of the present invention are described in detail.
[0044] like Figure 2 As shown, a substrate 10 is provided, and the substrate 10 may be a single crystal silicon or polycrystalline silicon substrate, or may be made of semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, etc., or may be a composite structure such as a silicon-on-insulator substrate. Those skilled in the art may select a suitable type of semiconductor substrate according to the requirements of the semiconductor device, and the type of the semiconductor substrate shall not limit the protection scope of the present invention.
[0045] Please continue to refer to Figure 2 The substrate 10 includes a core device area 10a, an input-output device area 10b and a cutting path 10c. The core device area 10a (Core device) is used to form core devices, which are used to realize the main functions of the integrated circuit, including core PMOS devices and core NMOS devices. The input-output device area 10b (Input Output device, IOdevice) is used to form input-output devices, which are used to provide corresponding input signals for core components or output corresponding signals of core devices. The cutting path 10c is used to cut chips. A shallow trench isolation structure 11 is formed in the substrate 10, and the shallow trench isolation structure 11 is used to isolate the core device area 10a and the input-output device area 10b. The substrate 10 includes a gate oxide layer, a polysilicon layer 13 and a hard mask layer 14, and the gate oxide layer includes a first gate oxide layer 12a located in the core device area 10a and a second gate oxide layer 12b located in the input-output device area 10b. Since the input-output device region 10b needs to withstand higher voltage and current, the thickness of the second gate oxide layer 12b of the input-output device region is greater than the thickness of the first gate oxide layer 12a of the core device region.
[0046] Please continue to refer to Figure 2 Before performing the first etching process, a first photoresist layer is formed, and the first photoresist layer covers the hard mask layer 14; a first photolithography process is performed to form a patterned first photoresist layer 15 having a first groove 16 on the first photoresist layer of the input-output device area 10b to define the second gate structure area of the input-output device area 10b. Since the second gate structure of the input-output device area 10b is relatively large, it is also called a large-block gate structure area, a non-dense pattern area, or an open area.
[0047] like Figure 3 As shown, a first etching process is performed, using the patterned first photoresist layer 15 as a mask to etch the hard mask layer 15 and the polysilicon layer 14 of the input / output device region 10b to form a first trench, wherein the first trench penetrates the hard mask layer 14 and extends into the polysilicon layer 13. The depth of the first trench is, for example, 50 angstroms to 100 angstroms. The first etching process is, for example, a dry etching process.
[0048] like Figures 4 to 7 As shown, a second photolithography process is performed to simultaneously etch the hard mask layer 14, the polysilicon layer 13 and the gate oxide layer of the core device area 10a and the input-output device area 10b, so that the thickness of the second gate oxide layer of the second gate structure gap of the input-output device area 10b is the same as the thickness of the first gate oxide layer of the first gate structure gap of the core device area 10a, and the first gate structure 13a of the core device area and the second gate structure 13b of the input-output device area are formed. The second etching process includes a first sub-etching process, a second sub-etching process, a third sub-etching process and a fourth sub-etching process.
[0049] Specifically, Figure 4 As shown, before performing the second etching process, a second photoresist layer is formed, and the second photoresist layer covers the hard mask layer 14; a second photolithography process is performed to convert the second photoresist layer of the core device area 10a into a patterned second photoresist layer 17 having a second opening 17a to define the first gate structure area of the core device area 10a, and the patterned second photoresist layer 17 exposes the first opening 15a of the input / output device area 10b and the hard mask layer 14 on the cutting road 10c. Since the first gate structure area of the core device area 10a is relatively small, it is also called a small-block gate structure area or a dense pattern area.
[0050] like Figure 5As shown, a first sub-etching process is performed, using the patterned second photoresist layer 17 as a mask, and simultaneously etching the hard mask layer 14 and the polysilicon layer 13 on the core device area 10a, the input-output device area 10b, and the cutting path 10c, and the etching stops on the second gate oxide layer 12b of the input-output device area 10b. The etching gas of the first sub-etching process is, for example, hydrogen bromide and helium, and the ratio of hydrogen bromide to helium is, for example, 1:1. The etching selectivity of hydrogen bromide (HBr) to polysilicon and silicon dioxide is very high, which can reach 100:1. Therefore, the first sub-etching process can stop etching on the second gate oxide layer 12b of the input-output device area 10b.
[0051] like Figure 6 As shown, a second sub-etching process is performed, using the patterned second photoresist layer 17 as a mask, etching the polysilicon layer 13 in the core device area 10a and simultaneously etching the second gate oxide layer 12b on the input-output device area 10b, and etching the polysilicon layer 13 on the cutting path 10c. The second sub-etching process can substantially remove the remaining polysilicon layer 13 in the core device area 10a and the remaining polysilicon layer 13 on the cutting path 10c. The etching gas of the second sub-etching process is a fluorine-containing gas. For example, the fluorine-containing gas is one or more of CF4, SF6 or NF3. The etching rates of fluorine-containing gas for polysilicon and silicon dioxide are similar, so it is a low etching selectivity. A short-second etch-back process is performed on the second gate oxide layer 12b with an etching gas ratio with a low selectivity, and at this time, the remaining polysilicon layer is also substantially removed from the core device area 10a and the cutting path 10c.
[0052] Please continue to refer to Figure 6 , perform the third sub-etching process, use the patterned second photoresist layer 17 as a mask, and continue to etch the polysilicon layer 13 of the core device area 10a and the cutting path 10c to ensure that the polysilicon layer 13 of the core device area 10a and the cutting path 10c is completely removed, that is, to ensure that the polysilicon layer 13 of the core device area 10a and the cutting path 10c is completely removed. The etching gas of the third sub-etching process is, for example, hydrogen bromide and helium. The ratio of hydrogen bromide to helium is, for example, 1:1. The etching selectivity of hydrogen bromide (HBr) to polysilicon and silicon dioxide is very high, which can reach 100:1. The etching process is performed with an etching gas ratio with a high etching selectivity to ensure that the polysilicon layer in all areas is completely removed.
[0053] After the third sub-etching process is performed, if the patterned second photoresist layer 17 has not been completely consumed, a photoresist removal process is required, and an ashing process or a stripping method is usually used to remove the remaining patterned photoresist.
[0054] like Figure 7As shown, the fourth sub-etching process is performed to simultaneously etch the first gate oxide layer 12a of the core device area 10a and the second gate oxide layer 12b of the input-output device area 10b, and the first gate oxide layer 12a of the core device area 10a and the second gate oxide layer 12b of the input-output device area 10b are substantially removed, and the first gate oxide layer 12a of the core device area 10a and the second gate oxide layer 12b of the input-output device area 10b may remain, and the thickness of the remaining second gate oxide layer 12b in the second gate structure gap of the input-output device area 10b is the same as or similar to the thickness of the remaining first gate oxide layer 12a in the first gate structure gap of the core device area 10a. The etching solution of the fourth sub-etching process is hydrofluoric acid.
[0055] In this embodiment, the non-dense graphic area is defined by the first photolithography process, and the dense graphic area is defined by the second photolithography process, and the hard mask layer at the gap of the non-dense graphic area (open graphic) is pre-etched by the first etching process, and then the second photolithography process and the second etching process flow for defining the first gate structure and the second gate structure are performed, thereby solving the problem of residual silicon oxide layer in the gap of the gate structure in the non-dense area. That is, a structure without residual oxide layer is formed in the gap of the gate structure in the non-dense area. The problem that the residual oxide layer in the gap of the gate structure in the input-output device area cannot be covered by the sidewall protection layer and is easily attacked by chemicals in the subsequent process, thereby causing defects in the gate.
[0056] like Figure 8 As shown, after forming the first gate structure 13a of the core device area and the second gate structure 13b of the input-output device area, the sidewalls 18 of the first gate structure 13a and the second gate structure 13b are formed, and the sidewalls 18 cover the sidewalls of the first gate structure 13a, the sidewalls of the first gate oxide layer 12a, the sidewalls of the second gate structure 13b, and the sidewalls of the second gate oxide layer 12b.
[0057] like Figure 8As shown, this embodiment also provides a semiconductor structure, which is made by any of the above-mentioned methods for forming a semiconductor structure, including a substrate 10, and the substrate 10 includes a core device area 10a, an input-output device area 10b and a cutting path 10c. The core device area 10a (Core device) is used to form core devices, which are used to realize the main functions of the integrated circuit, including core PMOS devices and core NMOS devices. The input-output device area 10b (Input Output device, IO device) is used to form input-output devices, which are used to provide corresponding input signals for core components or output corresponding signals of core devices. The cutting path 10c is used to cut chips. A shallow trench isolation structure 11 is formed in the substrate 10, and the shallow trench isolation structure 11 is used to isolate the core device area 10a and the input-output device area 10b. The substrate 10 includes a first gate oxide layer 12a and a first gate structure 13a located in the core device area 10a, and a second gate oxide layer 12b and a second gate structure 13b located in the input-output device area 10b. There is no residual second gate oxide layer 12b in the second gate structure 13b of the input / output device region 10b.
[0058] In summary, in the method for forming a semiconductor structure provided by an embodiment of the present invention, a first etching process is first performed to etch the hard mask layer and the polysilicon layer of the input-output device area to form a first groove, the first groove penetrates the hard mask layer and extends into the polysilicon layer; then a second etching process is performed to simultaneously etch the hard mask layer, the polysilicon layer, the first gate oxide layer and the second gate oxide layer of the core device area and the input-output device area to form a first gate structure of the core device area and a second gate structure of the input-output device area, and the thickness of the second gate oxide layer of the second gate structure gap of the input-output device area is made the same as the thickness of the first gate oxide layer of the first gate structure gap of the core device area. The present invention etches and thins the thickness of the polysilicon layer of the input-output device area in advance, and can remove the oxide layer of the gate structure gap of the input-output device area, solving the problem that the oxide layer remaining in the gate structure gap of the input-output device area cannot be covered by the sidewall protection layer, and is easily attacked by chemicals in subsequent processes, thereby causing defects in the gate structure.
[0059] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: A substrate is provided, the substrate comprising a core device region and an input-output device region, a first gate oxide layer located in the core device region and a second gate oxide layer located in the input-output device region are formed on the substrate, and a polysilicon layer and a hard mask layer covering the first gate oxide layer and the second gate oxide layer are formed, and the thickness of the second gate oxide layer in the input-output device region is greater than the thickness of the first gate oxide layer in the core device region; Performing a first etching process to etch the hard mask layer and the polysilicon layer in the input / output device region to form a first trench, wherein the first trench penetrates the hard mask layer and extends into the polysilicon layer; A second etching process is performed to simultaneously etch the hard mask layer, the polysilicon layer, the first gate oxide layer and the second gate oxide layer of the core device area and the input-output device area to form a first gate structure of the core device area and a second gate structure of the input-output device area, and the thickness of the second gate oxide layer in the gap between the second gate structure of the input-output device area is the same as the thickness of the first gate oxide layer in the gap between the first gate structure of the core device area.
2. The method for forming a semiconductor structure according to claim 1, wherein: The second etching process comprises: Performing a first sub-etching process to simultaneously etch the hard mask layer and the polysilicon layer of the core device region and the input / output device region, and stopping the etching on the second gate oxide layer of the input / output device region; Performing a second sub-etching process to etch the polysilicon layer in the core device area and simultaneously etch the second gate oxide layer on the input / output device area; Performing a third sub-etching process to continue etching the polysilicon layer in the core device area; A fourth sub-etching process is performed to simultaneously etch the first gate oxide layer of the core device area and the second gate oxide layer of the input-output device area, so that the thickness of the second gate oxide layer of the second gate structure gap of the input-output device area is the same as the thickness of the first gate oxide layer of the first gate structure gap of the core device area.
3. The method for forming a semiconductor structure according to claim 2, wherein: The etching gases of the first sub-etching process and the third sub-etching process are hydrogen bromide and helium.
4. The method for forming a semiconductor structure according to claim 2, wherein: The etching gas of the second sub-etching process is a fluorine-containing gas.
5. The method for forming a semiconductor structure according to claim 2, wherein: The etching solution of the fourth sub-etching process is hydrofluoric acid.
6. The method for forming a semiconductor structure according to claim 1, wherein: The first trench has a depth of 50 angstroms to 100 angstroms.
7. The method for forming a semiconductor structure according to claim 1, wherein: Before performing the first etching process, the method includes: forming a first photoresist layer, wherein the first photoresist layer covers the hard mask layer; A first photolithography process is performed to form a first opening in the first photoresist layer in the input-output device region to define a second gate structure region in the input-output device region.
8. The method for forming a semiconductor structure according to claim 1, wherein: Before performing the second etching process, the method comprises: forming a second photoresist layer, wherein the second photoresist layer covers the hard mask layer; A second photolithography process is performed to form a second opening in the second photoresist layer in the core device area to define a first gate structure region in the core device area and expose the first opening in the input-output device area.
9. The method for forming a semiconductor structure according to claim 1, wherein: After forming the first gate structure of the core device area and the second gate structure of the input / output device area, a sidewall is formed, which covers the sidewalls of the first gate structure, the first gate oxide layer, the second gate structure and the second gate oxide layer.
10. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by the method for forming a semiconductor structure as claimed in any one of claims 1 to 9.