Gate drive circuit for a power inverter branch in a power inverter, power inverter and method of operating the same

Abstract

A gate drive circuit for a power inverter branch in a power inverter includes a first power switch having a first reverse conducting channel and a second power switch having a second reverse conducting channel. The gate drive circuit comprises a first gate drive sub-circuit used for controlling switching of a first power switch; and the second gate driving sub-circuit is used for controlling the switching of the second power switch. The gate drive circuit controls switching of the first power switch and the second power switch in a complementary manner based on gate drive input signals to the first gate drive sub-circuit and the second gate drive sub-circuit. The gate drive input signal is indicative of a conduction condition of the first reverse conduction channel and the second reverse conduction channel and a slope of a load current in the inductive-resistive load.

Description

Technical Field

[0001] The present invention generally relates to the field of power electronics. One aspect of the present invention relates to a gate drive circuit for a power inverter branch in a power inverter. Another aspect of the present invention relates to a power inverter including a gate drive circuit. Another aspect of the present invention relates to a method of operating a gate drive circuit of a power inverter branch in a power inverter.

[0002] One aspect of the invention is particularly (but not exclusively) applicable to soft switching of power inverters operating at frequencies up to tens of megahertz.The invention may be used in wireless power transfer applications.

[0003] One aspect of the present invention is particularly applicable to reducing power losses in a power inverter. For example, improved soft switching of power switches in a power inverter can be achieved using the techniques disclosed herein. Using the techniques disclosed herein can allow improved zero voltage switching (ZVS) to be achieved in one or more power switches of a power inverter. Background Art

[0004] The advent of wide bandgap devices, wireless power transfer (WPT) technology, and high-performance magnetic materials have prompted researchers and engineers to explore power converters operating at frequencies exceeding tens of megahertz. High-frequency operation can not only reduce the size of magnetic components in general power conversion applications, but also improve the quality factor of magnetic coils commonly used in WPT applications. Power conversion generally involves dc-dc, dc-ac, ac-ac, and ac-dc power conversion. A dc-ac power converter is also known as a power inverter. In this document, power converter is used as a general term to cover the family of power converters.

[0005] Conventional power converters for switch-mode power supplies operate at frequencies in the typical range of 100kHz to 500kHz. For example, for dc-ac power converters used in WPT, the use of power inverter switching at several industrial, scientific and medical (ISM) frequencies (such as 6.78MHz, 13.56MHz, 26.96MHz and 40.66MHz) is increasingly explored. Therefore, it is expected that the operating frequency of some emerging power conversion applications will be above several hundred kilohertz to 100MHz, as reported in a review paper [reference: DJ Perreault, J. Hu, JM Rivas, Y. Han, O. Leitermann, RCN Pilawa-Podgurski, A. Sagneri and CRSullivan, "Opportunities and challenges in very high frequency power conversion," IEEE Applied Power Electronics Conference and Exposition Washington, DC, 2009]. Regardless of the topology, all switch-mode power converters use basic circuit elements that chop the dc waveform into an ac waveform. Soft switching technology is essential in this frequency range. Among them, the two most common soft switching technologies in practical applications are: single-switch type Class E or φ2 class, and half-bridge (push-pull) based D / DE class [Reference: NOSokal and AD Sokal, "Class E - a new class of high-efficiency tuned single-ended switching power amplifiers," IEEE Journal of Solid-State Circuits, vol.10, No.3, pp.168-176, 1975].

[0006] During the transition between turning on and off the switch, the conduction channel exhibits a linear transition within a finite period of time, such as Figure 1 This also results in a linear resistance transition for both voltage and current and is ultimately the factor that leads to the overlap interval that eliminates switching power losses, as shown in Figure 2As shown. This switching power loss is proportional to the switching frequency of the power switch and may become a limiting factor in the switching frequency of the power switch. Soft switching can be achieved by zero voltage switching (ZVS) or zero current switching (ZCS). By keeping the voltage across the power switch or the current in the power switch zero, the instantaneous power loss also becomes zero. In one example, if a capacitor is connected in parallel to the switching device, quasi-ZVS automatically occurs during the turn-off transition, as shown in Figure 3 As shown. The voltage across the switch rises more slowly and the IV integral (which is the energy lost during the transition) is significantly reduced. It is called a turn-off snubber. However, using only this parallel capacitor will increase the switching power losses during the turn-on transition, because the energy stored in the capacitor will be completely dissipated in the switch. Therefore, additional arrangements must be adopted to mitigate the turn-on transition.

[0007] It should be noted that parasitic capacitance exists in power electronic switches. Figure 4 A typical electrical equivalent circuit of a power MOSFET having three terminals (i.e., gate, drain, and source) is shown. The equivalent output capacitance Coss of a power MOSFET is equal to the sum of the drain-source capacitance (Cds) and the gate-drain capacitance (Cgd). The charging and discharging of the output capacitance Coss of the switch will be a factor that causes the switching power loss of the power switch.

[0008] For WBG devices, the turn-off time is short enough and since Coss forms a natural turn-off buffer, it can be considered as ZVS turn-off almost by default.

[0009] For very high frequency applications such as WPT systems, an inverter circuit is required on the transmitter side, which is usually composed of a push-pull circuit (half-bridge or full-bridge power inverter) (this is also pointed out in the following reference: W.D. Braun and D.J. Perreault, "A High-Frequency Inverter for Variable-Load Operation," IEEE Journal of Emerging and Selected Topics in Power Electronics, vol.7, No.2, pp.706-721, 2019). There are power switches whose sources are connected to a floating network in such a circuit, so signal isolators and floating power supplies are traditionally required to drive these switches. In their work, they have used a microcontroller to generate PWM signals for the top switch and the bottom switch, and drive them through a pair of identical gate drive circuits with the same delay time.

[0010] Regardless of the topology, all switch-mode power converters use basic circuit elements that convert a dc voltage or current waveform to an ac voltage or current waveform. In this frequency range, soft switching techniques are essential, of which the two most common soft switching techniques in practical applications are: single-switch type Class E or φ2 class, and half-bridge (push-pull) based Class D / DE ( Figure 5 ). For a half-bridge based converter, the gate drive circuit for the top switch requires a floating voltage rail referenced to the midpoint of the inverter leg, also known as the switching node. Figures 6a to 6c Some existing examples of gate drive techniques for top and bottom switches in a power inverter leg are shown. Figure 6a shows the bootstrapped floating gate drive of the top switch by charging the capacitor when the bottom switch is turned on. Or in other words, Figure 6a The bootstrapped gate drive of the top switch in the inverter leg is shown. The dc supply for the top switch gate drive is provided by a capacitor, which is charged by a fast recovery diode when the bottom switch is turned on. The floating capability is achieved by the fast recovery diode and no isolation is required in this circuit. Figure 6b In FIG. 1 , the use of an isolation transformer to provide a floating gate drive circuit for the top power switch is shown. Or in other words, Figure 6b An isolation transformer is shown being used to provide two floating supplies for the gate drivers. Figure 6c The use of a transformer isolation transformer with coupled secondary windings to provide isolated and floating gate drive for the switch is shown. Or in other words, Figure 6c The use of a transformer with coupled secondary windings to provide gate drive for the two switches is shown.

[0011] By connecting an inductive load to a half-bridge based inverter, the residual current in the inductor can be used to force the anti-parallel body diode of the switch to conduct and achieve ZVS during the turn-on transition [Reference: DC Hamill, “Class DE inverters and rectifiers for DC-DC conversion,” in PESC Record. 27th Annual IEEE Power Electronics Specialists Conference, Baveno, Italy, 1996]. However, operating the converter in a ZVS state requires additional calculation and control of the gate signal according to the load impedance. The switching frequency and duty cycle require careful and continuous tracking of the resonant tank parameters and load changes [Reference: DC Hamill, “Class DE inverters and rectifiers for DC-DC conversion,” in PESC Record. 27th Annual IEEE Power Electronics Specialists Conference, Baveno, Italy, 1996]. This usually requires complex control design or a narrow operating region range. [Reference: H.Sekiya, M.Matsuo, H.Koizumi, T.Suetsugu, S.Mori and I.Sasase, "New control method of Class DE inverter-Class DEthinning-out inverter," in INTELEC - Twentieth InternationalTelecommunications Energy Conference, San Francisco, CA, USA, 1998] [Reference: W.Braun and D.J.Perreault, "A High-Frequency Inverter for Variable-Load Operation," IEEE Journal of Emerging and Selected Topics in Power Electronics, vol.7, No.2, pp.706-721, 2019] A special type of ZVS operation is to detect the voltage and current phases in the circuit and automatically trigger the gate signal, including the Mazzilli converter [Reference: D.A.Hapidin, I.Saleh, M.M.Munir and Khairurrijal, “Design and Development of a Series-ConfigurationMazzilli Zero Voltage Switching Flyback Converter as a High-Voltage PowerSupply for Needleless Electrospinning,” in Engineering Physics International Conference, Bandung, Indonesia, 2016], TSOS technology [Reference: A. Namadmalan and JS Moghani, “Tunable Self-Oscillating Switching Technique for Current SourceInduction Heating Systems," IEEE Transactions on Industrial Electronics, vol.61, No.5, pp.2556-2563, 2014], double modulation technology [Reference: H.Belloumi and F.Kourda, "Double Modulation Technique for a ZVS Self-Oscillating Half-BridgeInverter," IEEE Transactions on Power Electronics, vol.30, No.4, pp.1907-1913, 2015], and low-latency frequency tracking technology [Reference: S.-H.Park, Y.-H.Sohn and G.-H.Cho, "SiC-Based 4 MHz 10 kW ZVS Inverter With Fast Resonance Frequency Tracking Controlfor High-Density Plasma Generators," IEEE Transactions on Power Electronics, vol.35, No.3, pp.3266-3275, 2020]. All of these methods use magnetic coupling components to sense the current signal and generate the gate signal of the switch. In the direct drive type, the gate drive power comes directly from the current transformer, and some energy will be wasted due to gate voltage protection, or undervoltage will not be able to fully turn on the switch. In the indirect type method, the gate signal is generated with ground as the reference, and paired isolated gate drivers are required for the top and bottom switches in the half-bridge. This results in additional delay time, which is typically about tens of nanoseconds assuming the use of state-of-the-art isolators [Reference: Texas Instruments datasheet: "UCC21520 4-A, 6-A, 5.7-kVRMS Isolated Dual-Channel Gate Driver," 2020]. Since the circuit is self-triggered, the additional delay limits the minimum cycle period and therefore the maximum operating frequency. For small-sized isolator components, common-mode transient immunity limits the rail voltage and switching frequency, which is also a problem. [Reference: V.Semiconductors, “Optocoupler Common Mode Transient Immunity (CMTI) - Theory and Practical Solutions,” 2013]. Since the turn-on and turn-off signals will be determined by the state of the circuit using the quasi-resonant method, the propagation delays of the control and drive circuit strings become critical. At a frequency of 10MHz, the period is 100ns, while the current best signal isolators have propagation delays of tens of ns. In a half-bridge or full-bridge power inverter with externally controlled ZVS operation, this is not a serious problem because the top switch and the bottom switch will be delayed by the same amount of time. However, in quasi-resonant operation, these delays will add additional time and limit the maximum operating frequency as well as the power level. .

[0012] Another self-triggering technique commonly seen in boost converters [reference: C. Zhang and D. J. Perreault, “An optimization approach for high-efficiency high-power-density boost converters,” in IEEE 19th Workshop on Control and Modeling for Power Electronics (COMPEL), Padua, Italy, 2018] or flyback converters [reference: T.-Y. Yang, R.-H. Lu, C.-C. Li, F.-C. Tsao, and P.-S. Tsu, “Switching Control Circuit Having A Valley Voltage Detector To Achieve Soft Switching For A Resonant Power Converter,” U.S. Patent 7,426,120 B2, September 16, 2008] uses a comparator to detect the voltage signal across the switch. It has the advantage of low latency (the most advanced comparators have a propagation delay of less than 5 ns) and is suitable for operating frequencies above 10 MHz. So far, this technique has only been applied to single-switch converters. Summary of the invention

[0013] Aspects of the invention are set out in the independent claims. Some optional features of the invention are defined in the dependent claims.

[0014] Implementation of the technology disclosed herein can provide significant technical advantages. For example, the technology disclosed herein can be considered to be related to a self-triggering gate drive system (the input signal of the gate drive (sub) circuit can be derived from the operating parameters (voltage and current) in the power inverter branch components), which includes two gate drive (sub) circuits for driving two power switches in the power inverter branch in a complementary manner under soft switching conditions, which can be used to generate a high-frequency AC output voltage from an input DC voltage source. In at least one implementation, the technology involves gate drive (sub) circuits and controls, and involves incorporating them into a power inverter with the ability to switch at up to tens of megahertz. The control of the gate drive circuit can be based on the detection of the conduction of the reverse conduction channel (e.g., the anti-parallel diode of the power switch) and / or the slope of the current of the load (e.g., the polarity of the slope). The proposed technology can be applied to power switches in the power inverter branch in a half-bridge power inverter (e.g., when in a totem pole arrangement), and can be extended to a full-bridge power inverter. The technique has the following advantages: no need for: (i) electrical isolation and level converters for the high-side gate drive signals for the power inverter legs, and (ii) active and continuous calculation of the drive frequency and duty cycle of the gate drive signal to maintain ZVS under load changes. This enables the gate drive system to operate at frequencies ranging from hundreds of kilohertz to at least tens of megahertz in applications where the gate signal transmission delay is very small. The technique can facilitate an inherently operational safe startup process from the moment the power inverter is powered on. Potential applications of the circuit include at least wireless charging systems, excitation windings in vacuum deposition processes, and high energy density and high efficiency DC-AC and DC-DC converters. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present invention will now be described by way of example only and with reference to the accompanying drawings, in which:

[0016] Figure 1 is a schematic block diagram showing the conduction channel state (lateral structure) of a MOSFET from fully on to fully off;

[0017] Figure 2 is a series of curves of voltage, current and power changing with time, which shows Figure 1 The switching losses of MOSFET devices due to resistance changes during the turn-on and turn-off intervals;

[0018] Figure 3 is a series of figures showing equivalent circuit diagrams and voltage, current and power curves when power loss is reduced;

[0019] Figure 4 is a schematic circuit diagram showing an electrical equivalent circuit of a known power MOSFET;

[0020] Figure 5 is a schematic circuit diagram of a D / DE class half-bridge power inverter (having a typical inverter branch including a top switch and a bottom switch);

[0021] FIG6 is a series of electrical diagrams showing some prior examples of gate drive techniques for top and bottom switches in a power inverter leg;

[0022] Figure 7 is an electrical schematic diagram showing a first exemplary gate drive circuit of a power inverter branch in a power inverter according to the technology disclosed herein;

[0023] Figure 8 is shown for implementing Figure 7 The electrical schematic diagram of the circuit of the condition 1 logic block in the circuit;

[0024] Fig. 9 It shows Figure 8 An electrical schematic diagram of a first variant of the circuit;

[0025] Fig.10 It shows Figure 8 An electrical schematic diagram of a second variation of the circuit;

[0026] Fig.11 is shown for implementing Figure 7 The electrical schematic diagram of the circuit of the condition 2 logic block in the circuit;

[0027] Fig.12 It shows Fig.11 An electrical schematic diagram of a first variant of the circuit;

[0028] Fig.13 It shows Fig.11 An electrical schematic diagram of a second variation of the circuit;

[0029] Fig.14 is shown for implementing Figure 7 The electrical schematic diagram of the circuit of the condition 3 logic blocks in the circuit;

[0030] Fig.15 It shows Fig.14 An electrical schematic diagram of a first variant of the circuit;

[0031] Fig.16 It shows Fig.14 An electrical schematic diagram of a second variation of the circuit;

[0032] Fig.17 is shown for implementing Figure 7 The electrical schematic diagram of the circuit of the condition 4 logic blocks in the circuit;

[0033] Fig.18 It shows Fig.17 Electrical schematic diagrams of variations of the circuit;

[0034] Fig.19 is an electrical schematic diagram showing an exemplary bootstrap circuit;

[0035] Fig. 20 is an electrical schematic diagram showing a circuit that provides a practical example of the technology disclosed herein;

[0036] Fig.21 It shows Fig. 20 Electrical schematic diagrams of variations of the circuit;

[0037] Fig. 22 is an electrical schematic diagram showing a technical expansion for a full-bridge power inverter;

[0038] Fig.23 is a series of schematic diagrams illustrating operating states of a half-bridge power inverter implementing the techniques described herein;

[0039] Fig.24 It is a series of curves showing the voltage and current changes over time during the working cycle of the power inverter branch;

[0040] Fig.25 is the electrical schematic diagram of the full-bridge power inverter driven by the proposed gate drive system for simulation study;

[0041] Fig.26 yes Fig.25 A series of simulated waveforms of the inductor current and midpoint voltage of the two power inverter branches of the circuit;

[0042] Fig. 27 It is for Fig.25 A voltage-current relationship diagram of an atypical switching trajectory of a power switch in a power inverter;

[0043] Fig.28 is a series of circuit diagrams showing examples of half-bridge power inverters using realistic component models;

[0044] Fig.29 yes Fig.28 A series of simulated waveforms of the inductor current and midpoint voltage of the power inverter branch; and

[0045] FIG. 30 shows Fig.11 and Fig.17 A series of circuit diagrams for further variations of . DETAILED DESCRIPTION

[0046] Unless otherwise stated, terms such as "first" and "second" are used to distinguish between the elements these terms describe. Therefore, these terms are not necessarily intended to indicate temporal or other prioritization of these elements.

[0047] Reference now Figure 7 , Figure 7 A power inverter / power inverter branch 700 is shown driving a load 702 from an output 703. Figure 7 In the example of , the power inverter 700 includes a single power inverter branch, i.e., a half-bridge power inverter. However, the techniques described in detail below extend to a full-bridge power inverter. After the preliminary discussion of the first exemplary gate drive circuit 704, the power inverter / power inverter branch 700 and the load 702 will be further discussed.

[0048] The gate driving circuit 704 includes a first gate driving sub-circuit 706 and a second gate driving sub-circuit 708 .

[0049] The first gate drive subcircuit 706 includes a first AND gate 710 having a first input 712 and a second input 714. The first AND gate 710 also has a first AND gate output 716.

[0050] The first AND gate 710 receives an input on a first input 712 from a condition 1 logic block 718 that implements logic condition 1, as described in more detail below. The condition 1 logic block 718 has a condition 1 logic block output 724 on which a condition 1 logic block control signal 726 is generated, which in turn is a first gate drive control signal, a first AND gate first input signal on the first AND gate first input 712.

[0051] The first AND gate 710 receives an input on a second input 714 from a condition 2 logic block 728, which implements logic condition 2, as described in more detail below. The condition 2 logic block 728 has a condition 2 logic block output 734, on which a condition 2 logic block control signal 736 is generated, which in turn is a second gate drive control signal, the first AND gate second input signal on the first AND gate second input 714.

[0052] The second gate drive subcircuit 708 includes a second AND gate 738 having a first input 740 and a second input 742. The second AND gate 738 also has a second AND gate output 744.

[0053] The second AND gate 738 receives an input on a first input 740 from a condition 3 logic block 746 that implements logic condition 3, as described in more detail below. The condition 3 logic block 746 has a condition 3 logic block output 752 on which a condition 3 logic block control signal 754 is generated, which in turn is a third gate drive control signal, a second AND gate first input signal on the second AND gate first input 740.

[0054] The second AND gate 738 receives an input on a second input 742 from a condition 4 logic block 756 that implements logic condition 4, as described in more detail below. The condition 4 logic block 756 has a condition 4 logic block output 762 on which a condition 4 logic block control signal 763 is generated, which in turn is a fourth gate drive control signal, a second AND gate second input signal on the second AND gate second input 742.

[0055] Figure 7 The power inverter branch 700 includes a first power switch 764 (a MOSFET in this example) having a first drain terminal D1 connected to the power rail Vs, a first gate terminal G1 for receiving (controlled by) an output signal on the first AND gate output 716, and a first source terminal S1 connected to a midpoint 774 between the switches. The first power switch 764 also has an associated first reverse conducting path (a first anti-parallel diode 766 in this example) connected in parallel (anti-parallel) across the first power switch 764 between terminals D1 and S1. The first power switch 764 also includes a first power switch parasitic capacitor 768, across which a voltage V s1 . The power inverter branch 700 also includes a second power switch 770 (a MOSFET in this example) having a second drain terminal D2 connected to a midpoint 774 between the switches, a second gate terminal G2 for receiving (controlled by) an output signal on the second AND gate output 744, and a second source terminal S2 connected to ground. The second power switch 770 also has an associated second reverse conducting channel (a second anti-parallel diode 772 in this example) connected in parallel across the second power switch 770 between terminals D2 and S2. The second power switch 770 also includes a second power switch parasitic capacitor 773, across which a voltage V s2 .

[0056] exist Figure 7In the example of FIG. 7 , the power inverter branches 700 are connected in a totem pole arrangement, wherein the midpoint 774 between the switches is connected to the output 703. In this example, the source terminal S1 of the first power switch 766 is connected to the drain terminal D2 of the second power switch 770 through the midpoint 774.

[0057] The electrical load 702 includes at least an inductor or an inductor component Lx (a voltage V is formed at both ends of the inductor). l ) and a resistor or resistive element Rx. Figure 7 In the example of , the electrical load 702 also has a capacitor or capacitive component Cx. Such a load circuit branch is typical in an equivalent circuit for wireless power transmission (where an inductor and a capacitor form a resonator). It is used as an example to illustrate the operation of the proposed gate drive circuit and control. In general, the technology disclosed herein is also applicable to pure inductive-resistive loads (loads that actually only include inductive and resistive components).

[0058] It is worth noting that the positions of the inductor Lx, resistor or resistive load Rx, and capacitor or capacitive load Cx in the circuit can be changed without affecting the operation of the techniques disclosed herein. That is, if the relative positions of the impedance components are changed, these techniques are still effective.

[0059] The gate drive system 704 of the power inverter branch 700 includes two gate drive circuits 706 , 708 , one gate drive circuit for controlling the switching state of a first (top) power switch 764 ( S1 ) and another gate drive circuit for controlling the switching state of a second (bottom) power switch 770 ( S2 ), respectively.

[0060] As mentioned above, Figure 7 The two switches 764 (S1) and 770 (S2) in the power inverter branch 700 are configured in a totem pole arrangement. In this example, the switches 764, 770 are switched in a complementary manner with a short dead time between their conduction cycles to avoid short circuit conditions. The parasitic output capacitances 768, 773 (i.e., C OSS ) is zero. The parasitic capacitance 768, 773 inherently provides zero voltage turn-on for turning off the power switches 764, 770 under ZVS conditions. The technical challenge is how to determine the conditions for turning on the power switches under ZVS.

[0061] For zero voltage turn-on of the first (top) power switch 764 ( S1 ) in the inverter leg 700 , two conditions need to be met, as described below.

[0062] Condition 1: For ZVS, Conductivity Top switch:

[0063] When the equivalent reverse conducting channel (in this example, the anti-parallel body diode 766) of the first power switch 764 (e.g., the top switch) is forced to conduct by the reverse current from the midpoint 774 to the supply voltage rail, the condition 1 logic block 718 outputs a high logic level signal 726 at the condition 1 logic block output 724, and vice versa. In other words, it is caused by Trigger, such as Figure 7 The truth table for condition 1 is provided in Table I.

[0064]

[0065] Table I Truth table of condition 1

[0066] Therefore, it will be understood that the gate drive circuit 704 is configured to cause the first gate drive control signal 726 to indicate the first reverse conduction channel voltage When is less than or equal to zero. In this regard, it is worth noting that, given the components of the reverse conducting channel (in Figure 7 The fact that there is always some voltage drop across the two ends of the anti-parallel diode 766 in the example above is that the voltage It may not be exactly zero. For GaN HEMTs, the typical voltage drop is usually anywhere between 0.3V and 1.4V. The important factors are: Voltage Close to zero, indeed zero (as it is significantly less than the dc rail voltage), is enough to provide the advantage of zero voltage switching.

[0067] (The comparison level can be adjusted by resistors 900a2 and 900b2 (see Fig. 9 ), and is affected by the power supply Vb, but it is worth noting that it is a positive voltage and therefore has nothing to do with the maximum negative voltage across the switch. By applying a voltage at the first non-inverting input 802 ( Figures 8 to 10 , as discussed below), the switch will turn on when the voltage across D1-S1 drops to nearly zero (e.g., if Vs=100V, this turn-on voltage may be about 1V to 2V). This is also related to Fig.16 The capacitor 1600 in FIG. 1 is related to the capacitor 1600 (discussed below), where, during the startup phase, the startup capacitor sets the initial voltage at 1304 to be larger to help establish ZVS operation.

[0068] The minimum voltage set at the first non-inverting input 802 of the first comparator will be zero, which is closely related to the midpoint 774 between the first power switch and the second power switch, where any negative voltage will be able to trigger the switch to turn on, so there is no limit on the maximum negative voltage in this case. When the voltage D1-S1 becomes negative, the switch will be actively turned on.)

[0069] refer to Figure 8 , the condition 1 logic block 718 can be implemented by a first comparator circuit having a first comparator 800 having a first non-inverting input 802 connected to the midpoint 774 between the two switches 764, 770 in the same inverter branch 700 and a first inverting input 804 connected to the supply voltage rail Vs. Therefore, the comparator 800 is measuring the voltage V developed across the first power switch 764, the first anti-parallel diode 766 and the first power switch parasitic capacitance 768. s1 That is, the first gate drive control signal is a first output signal of a first comparator 800 having a first non-inverting input 802 connected to the supply voltage rail Vs and a first inverting input 804 connected to the midpoint 774 between the first power switch and the second power switch.

[0070] It will be appreciated that the first gate drive control signal 726 indicates the first reverse conduction channel voltage V s1 When less than or equal to zero.

[0071] like Fig. 9 As shown, a first voltage divider circuit 900 (eg, a high-speed voltage divider) including top resistors 900a1, 900a2 and bottom resistors 900b1, 900b2 can be used to scale the input signal from the source voltage Vs and the midpoint 774 to within an acceptable range for the first comparator 800. Fig. 9 In the example of FIG. 1 , a first top resistor 900a1 is connected on a first side to the supply voltage rail Vs and the first drain terminal D1 of the first power switch and on a second side to a first bottom resistor 900b1 and to the first inverting input 804 of the first comparator 800. A second top resistor 900a2 is connected on a first side to the bootstrap supply rail Vb (see FIG. 1 ). Fig.19 ), and connected at its second side to the first non-inverting input 802 of the first comparator 800 and to the first side of the second bottom resistor 900b2. Each of the first bottom resistor 900b1 and the second bottom resistor 900b2 is connected at its respective second side to the midpoint 774 between the switches.

[0072] Therefore, the gate driving circuit may further include a first comparator 800 , and the gate driving circuit 704 is configured to scale the amplitude of the first voltage signal input to the first inverting input 804 and the first non-inverting input 802 using a first voltage divider circuit 900 .

[0073] As a further option, additional voltage margin may be added to the first non-inverting input 802 of the first comparator 800 to increase the resilience of the zero-crossing comparison, such as Fig. 9As shown. Note that in this case, the first comparator 800 is referenced to the same source Vs as the top switch 710, which eliminates the need for a level shifter. In one example, the two halves of the voltage divider circuit 900 can be identical, with the top resistors 900a1, 900a2 being 100 kilo-ohms, and the two bottom resistors 900b1, 900b2 being 1 kilo-ohm. In this case, the switch 764 is not turned on at exactly zero voltage, but is turned on at a voltage approximately equal to the supply voltage of the comparator and gate driver (typically about 5V).

[0074] Furthermore, an additional ramp capacitor 1000 may be connected in parallel to one of the top resistors 900a1, 900a2 (in this example the second top resistor 900a2 in the voltage divider 900 of the first non-inverting input 802 of the first comparator 800), as shown in FIG. Fig.10 As shown. When the circuit is initially started and the AC current in the resonant tank (load 702 when capacitor Cx is included) is building, this will force the circuit to operate in non-ZVS conduction. The circuit will take some time to enter ZVS conduction. In addition, when operating at high frequencies, the voltage divider circuit 900 will require additional compensation capacitors.

[0075] Therefore, the gate drive circuit 704 may further include a first ramping capacitor 1000 connected in parallel to the second upper resistor 900 a 2 in the first voltage divider circuit 900 of the first non-inverting input 802 .

[0076] Condition 2: For ZVS, Shutdown Top switch:

[0077] The condition 2 logic block 728 outputs a high logic level at the condition 2 logic block output 734 when the current flowing in the direction from the midpoint 774 between the first power switch 764 and the second power switch 770 to the DC sink (ground or supply voltage rail Vs) has a positive time derivative, and vice versa. In other words, it is determined by Trigger, such as Figure 7 The truth table of condition 2 logic block 728 is shown in Table II.

[0078]

[0079] Table II Truth table of condition 2

[0080] To obtain the time derivative of the current in the inductor Lx, one can simply sense the voltage across the inductor element or apply a differentiator to the current signal.

[0081] Example implementation:

[0082] The condition 2 logic block 728 may be implemented by a comparator circuit having a second comparator 1100 and outputting a condition 2 logic block output signal 736 at a condition 2 logic block output 734. The second comparator 1100 has a second comparator second inverting input 1102, a second comparator second non-inverting input 1104. The second comparator second non-inverting input 1104 is connected to one side of the dot of the inductor Lx, and the second comparator second inverting input 1102 is connected to the other end of the inductor Lx, as shown in FIG. Fig.11 As shown. One end of the inductor with a dot is usually connected to the midpoint (switching node) between the two switches 744 in the half-bridge power inverter branch 700, but there may be additional components in between. The other end is usually connected to a dc rail (such as a supply voltage rail) or ground through a capacitor (dc side). It will also work with a relatively small resistor (resistive load) in series with the inductor (or if the load is inductively coupled to the inductor).

[0083] Therefore, the gate drive circuit 704 is configured to cause the second gate drive control signal 736 to become a second output signal of a second comparator 1100, which has a second inverting input 1102 connected to the DC output side of the inductor Lx of the inductive-resistive load 702 and a second non-inverting input 1104 connected to the midpoint 774 between the first power switch and the second power switch, and is configured to cause the second gate drive control signal 736 to indicate when the slope of the load current in the inductive-resistive load 702 is positive.

[0084] In practice, an additional voltage divider circuit should be used with reference to the source of the top switch to reduce the input signal to within the acceptable range of the comparator, e.g. Fig.12 The second voltage divider circuit 1100 including top resistors 1106a1, 1106a2 and bottom resistors 1106b1, 1106b2 can be used to scale the input signal from the midpoint 744 between the switches and the DC side of the load inductor Lx to within an acceptable range for the second comparator 1100. Fig.12 In the example of , the first top resistor 1106a1 is connected at its first side to the dotted side of the inductor and to the midpoint 774 between the switches, and at its second side, is connected at the first side of the first bottom resistor 1106b1 to the first bottom resistor 1106b1 and to the second comparator second non-inverting input 1104. The second top resistor 1106a2 is connected at its first side to the DC side node, and at its second side to the second comparator second inverting input 1102 and the first side of the second bottom resistor 1106b2. Each of the first bottom resistor 1106b1 and the second bottom resistor 1106b2 is connected at its respective second side to the midpoint 774 between the switches. In Figure 7In the example connection in , the non-inverting input of the comparator can be connected directly to the lead side of the inductor, as shown in Fig.13 shown.

[0085] The second comparator 1100 and associated components may be part of a gate drive circuit, in which case the gate drive circuit 704 is configured to scale the amplitude of the voltage signal input to the second inverting input 1102 and optionally the second non-inverting input 1104 using a second voltage divider circuit 1106 .

[0086] It will also be appreciated that the gate drive circuit and the second comparator may be part of a power inverter.

[0087] When both condition 1 and condition 2 are satisfied, the first AND gate 710 outputs a logic high output signal 716, which is then fed into the first gate terminal G1 of the first power switch, and the half-bridge power inverter ( Figure 7 ) is turned on under zero voltage condition. That is, the gate drive circuit 704 is configured to: generate a first gate drive control signal 726 indicating the on state of the first reverse conduction channel 766; generate a second gate drive control signal 736 indicating the slope of the load current in the inductive-resistive load 702; and, when the first reverse conduction channel 766 is in the on state and when the slope of the load current in the inductive-resistive load 702 is positive, switch the first power switch 764 to the on state.

[0088] For zero voltage turn-on of the second (bottom) power switch 770 ( S2 ) in the inverter leg 700 , two conditions need to be met, as described below.

[0089] Condition 3: For ZVS, Conductivity Bottom switch:

[0090] When the equivalent reverse conducting channel of the second power switch 770 (in this example, the antiparallel body diode 772) is forced to conduct by the reverse current from ground to the midpoint 774, the condition 3 logic block 746 outputs a high logic level at the condition 1 logic block output 752, and vice versa. In other words, it is caused by Trigger, such as Figure 7 The truth table of condition 3 is given in Table III.

[0091]

[0092] Table III Truth table of condition 3

[0093] Therefore, it will be understood that the gate drive circuit 704 is configured to cause the third gate drive control signal 754 to indicate the second reverse conduction channel voltage V s2 When less than or equal to zero.

[0094] Example implementation:

[0095] refer to Fig.14 , the condition 3 logic block 714 can be implemented by a third comparator circuit having a third comparator 1300 having a third inverting input 1302 connected to the midpoint 774 between the two switches 764, 770 in the same inverter branch 700 and a third non-inverting input 1304 connected to ground. Therefore, the comparator 1300 is measuring the voltage V developed across the second power switch 770, the second anti-parallel diode 772, and the second power switch parasitic capacitance 773. s2。

[0096] That is, the third gate drive control signal 754 is a third output signal of a third comparator 1300 having a third inverting input 1302 connected to the midpoint 774 between the first power switch and the second power switch and a third non-inverting input 1304 connected to ground.

[0097] A variation of the implementation similar to that of the condition 1 logic block 718 described above may also be applied to the condition 3 logic block 746. For example, a third voltage divider 1306 may be used, such as Fig.15 The third voltage divider circuit 1306 includes top resistors 1306a1, 1306a2 and bottom resistors 1306b1, 1306b2, which can be used to scale the input signals from the midpoint 774 and from the ground to within an acceptable range for the third comparator 1300. Fig.15 In the example of FIG. 1 , the first top resistor 1306a1 is connected on its first side to the midpoint 774 between the switches and the second power switch second drain terminal D2, and on its second side, is connected on its first side to the first bottom resistor 1306b1 and to the third inverting input 1302 of the third comparator 1300. The second top resistor 1306a2 is connected on its first side to the DC supply voltage rail V of the control electronics (such as logic circuits, comparators and operational amplifier circuits). cc , and connected at a second side thereof to the third non-inverting input 1304 of the third comparator 1300 and to a first side of a second bottom resistor 1306b2. Each of the first bottom resistor 1306b1 and the second bottom resistor 1306b2 is connected at its respective second side to ground.

[0098] The gate drive circuit may further include a third comparator 1300 and is configured to scale the amplitude of the third voltage signal input to the third inverting input 1302 and the third non-inverting input 1304 using a third voltage divider circuit 1306. In addition, a third ramp capacitor 1600 may be connected in parallel to the second upper resistor 1306a2 in the third voltage divider 1306 of the third non-inverting input 1304.

[0099] In this example, the two upper resistors may be 100 kilo-Ohms and the two lower resistors may be 1 kilo-Ohm. Fig.10 As shown, a ramp capacitor (here, the third ramp capacitor 1600) may be connected in parallel with the second top resistor 1306a2, such as Fig.16 An exemplary third ramp capacitor 1600 has a capacitance of 100 pF.

[0100] Condition 4: For ZVS, Shutdown Bottom switch:

[0101] The conditional 4 logic block 756 outputs a high logic level at the conditional 4 logic block output 762 when the current flowing in the direction from the midpoint 774 between the first power switch 764 and the second power switch 770 to the DC sink (ground or supply voltage rail) has a negative time derivative, and vice versa. In other words, it is determined by Trigger, such as Figure 7 The truth table of condition 4 logic block 756 is given in Table IV.

[0102]

[0103] Table IV Truth table of condition 4

[0104] To obtain the time derivative of the current in the inductor Lx, the voltage across the inductor element can be simply detected or a differentiator can be applied to the current signal. Note that this can simply reuse the second gate drive signal 736, or a fourth gate drive signal 763 can be generated that replicates the state of the second gate drive signal.

[0105] Therefore, the gate drive circuit 704 is configured to make the fourth gate drive control signal 763 a fourth output signal of the fourth comparator 1700, which has a fourth inverting input 1702 connected to the midpoint 774 between the first power switch and the second power switch and a fourth non-inverting input 1704 connected to the DC output side of the inductor Lx of the inductive-resistive load 702, and is configured to make the fourth gate drive control signal 763 indicate when the slope of the load current is negative. In addition, the gate drive circuit may include the fourth comparator 1700 and is configured to scale the amplitude of the voltage signal input to the fourth inverting input 1702 and optionally to the fourth non-inverting input 1704 using a fourth voltage divider circuit 1706.

[0106] Example implementation:

[0107] The condition 4 logic block 756 may be implemented by a comparator circuit having a fourth comparator 1700 having a fourth inverting input 1702 connected to one side of the inductor with a dot, the side of the dot connected to the midpoint 774 between the first power switch 764 and the second power switch 770, but other components may also be present in between. The fourth comparator fourth non-inverting input 1704 is connected to the other end of the inductor, such as Fig.17 A variation of the implementation similar to that of the condition 2 logic block 728 described above may also be applied to the condition 4 logic block 756 .

[0108] For example, and if Fig.18 As shown, a fourth voltage divider circuit 1706 including top resistors 1706a1, 1706a2 and bottom resistors 1706b1, 1706b2 can be used to scale the input signal from the midpoint 744 between the switches and the DC side of the load inductor Lx to within an acceptable range for the fourth comparator 1700. Fig.18 In the example of FIG. 1 , the first top resistor 1706a1 is connected at its first side to the side of the dot of the inductor and to the midpoint 774 between the switches, and at its second side, is connected at the first side of the first bottom resistor 1706b1 to the first bottom resistor 1706b1 and to the fourth inverting input 1702 of the fourth comparator. The second top resistor 1706a2 is connected at its first side to the DC side node and at its second side to the fourth non-inverting input 1704 of the fourth comparator and to the first side of the second bottom resistor 1706b2. Each of the first bottom resistor 1706b1 and the second bottom resistor 1706b2 is connected to ground at its respective second side.

[0109] In one example, the two upper resistors may be 100 kilo-ohms and the two lower resistors may be 1 kilo-ohm.

[0110] When both conditions 3 and 4 are satisfied, the second AND gate 738 outputs a logic high output signal 744, which is in turn fed into the second gate terminal G2 of the second power switch, and the second power switch 770 (bottom power switch S2) in the inverter branch 700 of the half-bridge power inverter is turned on under zero voltage conditions. That is, the gate drive circuit 704 is configured to: generate a third gate drive control signal 754 indicating the conduction state of the second reverse conduction channel 772; generate a second gate drive input signal 736 or a fourth gate drive input signal 763 indicating the slope of the load current in the inductive-resistive load 702; and switch the second power switch 770 to the conduction state when the second reverse conduction channel 772 is in the conduction state and when the slope of the load current in the inductive-resistive load 702 is negative.

[0111] Fig.19 An example of a bootstrap circuit is provided that generates the supply rail Vs for the upper gate drive circuit. When the first (top) switch 764 and the first (bottom) switch 770 operate in a complementary manner, the bootstrap supply rail Vb will maintain a voltage close to the value of Vs, referenced to the floating switching node.

[0112] Therefore, it will be understood that Figure 7 The gate drive circuit 704 of the power inverter branch 700 in the power inverter is shown. The power inverter branch 700 includes a first power switch 764 having a first reverse conduction channel 766 and a second power switch 770 having a second reverse conduction channel 772. The power inverter branch 700 is configured to drive an inductive-resistive load 702. The gate drive circuit 704 includes: a first gate drive subcircuit 706 for controlling the switching of the first power switch 764; a second gate drive subcircuit 708 for controlling the switching of the second power switch 764; Switching of the switch 770; wherein the gate drive circuit 704 is configured to control the switching of the first power switch 764 and the second power switch 770 in a complementary manner and based on the gate drive input signals 722, 732, 750, 760 of the first gate drive sub-circuit 706 and the second gate drive sub-circuit 708, and the gate drive input signals 722, 732, 750, 760 indicate the conduction conditions of the first reverse conduction channel 766 and the second reverse conduction channel 772 and the slope of the load current in the inductive-resistive load 702.

[0113] Also disclosed is a power inverter including the gate drive circuit 704 .

[0114] Corresponding operating methods have also been described. Thus, a method of operating a gate drive circuit 704 for a power inverter branch 700 in a power inverter is disclosed, the power inverter branch 700 comprising a first power switch 764 having a first reverse conduction channel 766 and a second power switch 770 having a second reverse conduction channel 772, the power inverter branch 700 driving an inductive-resistive load 702, the gate drive circuit 704 comprising: a first gate drive subcircuit 706 for controlling the switching of the first power switch 764; a second gate drive subcircuit 708 for controlling the switching of the second Switching of the power switch 770; the method includes: operating the gate drive circuit 704 to control the switching of the first power switch 764 and the second power switch 770 in a complementary manner and based on the gate drive input signals 722, 732, 750, 760 to the first gate drive subcircuit 706 and the second gate drive subcircuit 708, the gate drive input signals 722, 732, 750, 760 indicating the conduction conditions of the first reverse conduction channel 766 and the second reverse conduction channel 772 and the slope of the load current in the inductive-resistive load 702.

[0115] Now refer to Fig. 20 Let’s discuss a real-world example.

[0116] In V sw is the midpoint between the first power switch and the second power switch ( Figure 7 In the case of the voltage at point 774), when V sw V S When , condition 1 is satisfied (based on the detection of the reverse voltage of the power switch or the voltage across the anti-parallel diode of the power switch);

[0117] When V sw V n When , condition 2 (based on the detection of the voltage across the inductor in the load branch) is met.

[0118] When gnd V sw When , condition 3 is met (based on the detection of the reverse voltage of the bottom power switch);

[0119] When V sw V n When , condition 4 (based on the voltage measurement across the inductor in the load branch) is met.

[0120] In actual implementation, four comparators are used to detect these four conditions. Fig. 20 In, V sw and V Sare fed to the positive and negative inputs of comparator U1 respectively. S1 When the load current is turned on, V sw >V S When condition 1 is met, the output of U1 is high. Signal V sw and V n is fed to the positive and negative inputs of the second comparator U2. The difference between their voltages represents the voltage across the inductor, which in turn represents the slope of the load current. sw >V n , condition 2 is met, and the output of comparator U2 becomes high. The outputs of U1 and U2 are fed to the input terminals of AND logic gate A1. When both input signals are high, the output of A1 becomes high, indicating that S1 is turned on.

[0121] Similar arguments apply to the gate drive of the bottom switch S2. Here, the voltages gnd and V sw are fed to the positive input terminal and negative input terminal of the third comparator U3 respectively. sw , which indicates that the body diode D of S2 S2 is conducting. Condition 3 is met, and the output of U3 becomes high. The voltage V n and V sw are fed to the positive input terminal and the negative input terminal of the fourth comparator U4 respectively to detect the slope of the load current. sw <V n When the load current has a negative slope, and condition 4 is met, the output of U4 becomes high. The outputs of U3 and U4 are fed to the input terminal of AND gate A2. When both condition 3 and condition 4 are met, the output of A2 becomes high, indicating that S2 is turned on.

[0122] The proposed high-frequency gate drive system can be applied to half-bridge power inverters, such as Fig.21 It should be noted that from a circuit theory point of view, Fig.21 The power circuit in is equivalent to Fig. 20 The power circuit in which C x It is C x1 With C x2 sum.

[0123] The techniques disclosed above with respect to a single power inverter branch (half-bridge power inverter) can also be extended to cover operation in a full-bridge power inverter, as shown in reference Fig. 22As discussed. In a full-bridge power inverter, S1 and S4 form a diagonal pair of power switches. They are turned on and off at the same time. Therefore, their gate drive circuits are the same. Similarly, S2 and S3 form another diagonal pair of power switches. They should have the same switching signals and therefore the same gate drive circuits and controls. Therefore, the logic control of the top switch (S3) and the bottom switch (S4) in the second inverter branch (right-hand side) of the full-bridge power inverter is opposite to the logic control of the top switch (S1) and the bottom switch (S4) in the first inverter branch on the left-hand side of the full-bridge power inverter.

[0124] Fig.23 The operation state diagram and Fig.24 The circuit waveforms in are used to illustrate the operation of the half-bridge power inverter. These operations are described in a stage-by-stage manner in Table V. Since the switches are guaranteed to have ZVS, the total power loss on the switches is negligible.

[0125]

[0126] Table V Description of gate drive control at different time intervals

[0127] As mentioned above, the gate signal is triggered entirely by the circuit itself. Figure 7 In the example, the operating frequency is determined by the loaded resonant frequency of the inductor-capacitor-resistor (LCR) circuit branch. If the capacitor Cx is small and is proportional to the output capacitance C of the switch OSS With the same order of magnitude, C OSS will affect the loading resonant frequency. However, there are several ways to control the output power.

[0128] The first method for controlling the output power is by varying the dc link voltage of the power inverter. This can be achieved by having a front-end power converter that changes its dc output voltage to a dc link voltage Vs of the power inverter using the proposed self-triggered gate drive system.

[0129] The second method for controlling the output power is to use an equivalent load with self-regulation of power consumption. The equivalent load Rx in the previous description of the simplified circuit operation can represent a power converter with closed-loop power / voltage regulation for powering an electrical load. The power converter for powering an electrical load is referred to here as a load power converter. The resistance Rx is equivalent to the input resistance of the load power converter, which can be controlled by the duty cycle control of the load power converter operation. In this way, the equivalent Rx in the equivalent circuit branch will change dynamically according to the power consumption.

[0130] A third method for controlling output power is to use a switchable inductor so that the equivalent impedance can be changed. The value of .

[0131] A fourth method for controlling output power is to add hysteresis control to the comparators used for conditions 2 and 4 so that the turn-off time can be delayed. This will change the phase shift between the voltage and current at the load and affect the actual power output. Fig.30a , shows a first implementation of this fourth method. It will be noted that Fig.30a Shows Fig.11 Another variation of the circuit. In this variation, the first control resistor R f1 At a first end, it is connected to the midpoint 744 between switches 764, 770 (and also to the inductor L x The second control resistor R f2 Connected at a first terminal to the condition 2 logic block output 734 and at a second terminal to the second comparator second non-inverting input 1104 .

[0132] Then refer to Fig.30b , shows a second implementation of this fourth method. It will be noted that Fig.30b Shows Fig.17 Another variation of the circuit. In this variation, the third control resistor R f3 Connected to the inductor L at the first end x The dc side of the fourth control resistor R f4 Connected at a first terminal to the condition 4 logic block output 762 and at a second terminal to the fourth comparator fourth non-inverting input 1704 .

[0133] By adding these control resistors, a delay in the toggle action on the condition 2 logic block output 734 and the condition 4 logic block output 762 can be achieved. This allows the off time of the switch to be adjusted and allows for continuous current flow for an additional period of time. Thus, these resistors modify the phase shift between the load (output) voltage and current.

[0134] A fifth method for controlling output power is to replace the condition 2 block and condition 4 block with a timer circuit and explicitly control the on-time of the two switches. The timer can be implemented using any known method. The timer can be started by the corresponding condition block output: for the condition 2 timer, it is started by the condition 1 output, and for the condition 4 timer, it is started by the condition 3 output. Like the gate drive circuit, the timer circuit for the upper switch also needs to be referenced to the floating ground of the switching node. The timer can be set with a fixed value or controlled externally.

[0135] Verification of the Invention

[0136] The proposed gate drive system is demonstrated in a full-bridge power inverter simulation. Fig.25 The circuit diagram is shown in . The dc link voltage of the power inverter is set to 24V. The load parameters are Lx=0.5μH, Cx=200pF, and Rx=2Ohm. The output capacitance of the power switch is 10pF. The circuit operates at a frequency of 17.83MHz.

[0137] Fig.26 The simulated time domain waveforms of the inductor current and midpoint voltage of the inverter branch are shown. Fig. 27 The switching trajectory of the power switch (i.e., the trajectory of the instantaneous voltage and current operating points) is shown in Fig. 27 In Figure 5, the vertical axis is the switching voltage, and the horizontal axis is the switching current. The switching trajectory approaches and moves along the zero voltage and zero current lines. This confirms that soft switching can be achieved by using the proposed gate drive system.

[0138] In this design, the gate signal of the top switch (first power switch) is completely generated from a floating circuit referenced to the switching node, so no isolated gate drive is required and the overall propagation delay has been minimized. With current state-of-the-art components, operation at 13.56MHz or even higher frequencies can be achieved with excellent performance.

[0139] Another example shows a circuit simulation using realistic component models. The load consists of a 0.5uH inductor, a 1.8 Ohm load resistor, and a total compensation capacitance of 200pF. The switch model used is the GS61004B, and an additional 20pF capacitor is added to the switch node to simulate the parasitic stray capacitance of the PCB trace. The placement of the bootstrap circuit and comparator can be found in Fig.28 . Note that there is an additional bootstrap circuit in the Condition 1 implementation to generate a stable reference voltage signal, thereby minimizing the voltage ripple due to power consumption of the top-side comparator and AND gate. The circuit operates at 15.57MHz and outputs 313.9W into the resistive load. Fig.29The simulated waveforms of the inductor current and midpoint voltage of the power inverter branch are shown in Figure 1. The power loss on the top switch and the bottom switch are 1.76W and 1.44W respectively. The whole circuit achieves an overall efficiency of more than 97%.

[0140] In practice, an ultrafast AND gate driver with high current capability, such as the 74LVC1G series, should be selected for the proposed gate drive system. The average propagation delay of such an AND gate is less than 3ns. The AND gate driver is capable of driving a 50pF load (such as the gate capacitance of a power switch) within 2.5ns. For future high-power power switches with relatively large gate-source capacitance, a buffer driver can be added between the AND gate output and the gate of the power switch as needed.

[0141] In view of the discussion herein, it will be appreciated that the current application discloses the following concepts.

[0142] 1. A self-triggered gate drive system comprising two gate drive circuits for driving a top power switch and a bottom power switch of a power inverter leg in a complementary manner under soft switching conditions to generate a high frequency ac output voltage from an input dc voltage source, wherein the input of the gate drive system is derived from the conduction condition of the anti-parallel diode (or other reverse conducting channel) of the power switch and the slope of the load current.

[0143] 2. The gate drive system of concept 1, wherein inputs to the gate drive system include reverse voltages of power switches in the inverter branches and polarities of slopes of load currents.

[0144] 3. The gate drive system according to Concept 2, wherein the slope of the load current is directly obtained by a current sensor having a differentiator, or indirectly obtained by measuring the voltage across an inductor in a load branch of the power inverter.

[0145] 4. The gate drive system according to concept 1, wherein the input of the gate drive system comprises: (1) a DC link voltage (V S ), (2) The voltage between two power switches in the same inverter branch (v sw ), (3) a reference voltage (gnd), and (4) a voltage on the inductor side of the load branch of the power inverter (v n ).

[0146] 5. The gate drive system of Concept 1 comprises two gate drive circuits, one for the top power switch of the inverter leg arranged in a totem pole, and another for the bottom power switch.

[0147] 6. Each of the two gate driving circuits in the gate driving system according to Concept 1 comprises at least two comparators and an AND logic gate, wherein the output of the logic gate determines the switching state of the power switch.

[0148] 7. The AND gate according to Concept 6 is preferably of ultrafast type and has a large current driving capability.

[0149] 8. For high-power power switches with relatively large gate capacitance, a buffer driver can be added between the output of the AND gate of Concept 6 and the gate of the power switch (if this arrangement can speed up the turn-on and turn-off process of the power switch).

[0150] 9. A gating signal is fed into the gate of a power switch of the system according to Concept 1, comprising a voltage divider circuit including one or more of a resistor, a capacitor, an inductor and a diode for linearly reducing the voltage under high frequency ac conditions in high voltage applications.

[0151] 10. The voltage between two power switches in an inverter branch according to Concept 1 (v sw ) are used as inputs to all four comparators of two gate drive circuits in the same inverter leg.

[0152] 11. The gate drive system according to Concept 1 can be extended to a full-bridge power inverter, which includes two inverter legs sharing the same dc link voltage and ground, wherein the gate drive logic control and circuit of the top power switch and the bottom power switch in the first inverter leg are the same as the gate drive logic control and circuit of the bottom power switch and the top power switch in the second inverter leg, respectively.

[0153] 12. The self-oscillating operating frequency of the power inverter using the gate drive system in Concept 1 is determined by the loading resonant frequency of the inductor-capacitor-resistor load branch.

[0154] 13. A control method for a gate drive system of a power inverter in Concept 1, wherein the switching action of the top power switch is determined by two conditions (i.e., condition 1 and condition 2), and the switching action of the bottom switch is determined by two conditions (i.e., condition 3 and condition 4); wherein the four conditions are defined as:

[0155] Condition 1: When the voltage across the top switch (v s1 )≤0, the logic output is high. s1 )>0, the logic output is low.

[0156] Condition 2: Assuming that the current entering the load from the midpoint of the inverter leg (i.e., the connection point between the top switch and the bottom switch) is defined as positive, when the rate of change of the load current (d iL / dt)>0, the logic output is high level; when d iL / dt>0, the output logic is low level.

[0157] Condition 3: When the voltage across the bottom switch (v s2 )≤0, the logic output is high. s2 )>0, the logic output is low.

[0158] Condition 4: Assuming that the current entering the load from the midpoint of the inverter leg (i.e., the connection point between the top switch and the bottom switch) is defined as positive, when the rate of change of the load current (d iL / dt) < 0, the logic output is high; when d iL / dt≥0, the output logic is low level.

[0159] 14. A control method for a gate drive system of a power inverter branch in Concept 13, wherein when both Condition 1 and Condition 2 have a logic output high level, the top power switch is turned on, and when both Condition 3 and Condition 4 have a logic output high level, the bottom switch is turned on.

[0160] 15. A control method for controlling the output power of a power inverter driven by the self-triggered gate drive system for a half-bridge power inverter or a full-bridge power inverter of Concept 1 by controlling a dc link voltage of the power inverter.

[0161] 16. A control method for controlling the output power of a power inverter driven by the self-triggered gate drive system for a half-bridge power inverter or a full-bridge power inverter of Concept 1 by using a power converter with voltage or power regulation capability to power an energy-consuming electrical load in a load branch of the power inverter.

[0162] 17. A control method for controlling the output power of a power inverter driven by the self-triggered gate drive system for a half-bridge power inverter or a full-bridge power inverter of Concept 1 by using a switchable inductor or a switchable capacitor or a combination of both so as to change the impedance of a load branch and thus change the current and power of the load.

[0163] 18. A control method for controlling the output power of a power inverter driven by the self-triggered gate drive system of Concept 13 by adding hysteresis control to the comparators of Condition 2 and Condition 4 so that the turn-off time can be delayed in order to change the phase shift between the voltage and current on the load and control the actual power output.

[0164] 19. A control method for controlling the output power of a power inverter driven by the self-triggered gate drive system of Concept 13 by replacing the condition 2 gate drive block and the condition 4 gate drive block with a timer circuit and explicitly controlling the on-time of the two switches, wherein the output of the condition 1 control block starts the timer circuit for the on-time of the top switch, the output of the condition 2 control block starts the timer circuit for the on-time of the bottom power switch, and the output power is determined by the on-cycle of the controllable timer circuit.

[0165] It will be understood that the present invention has been described by way of example only. Various modifications may be made to the techniques described herein without departing from the spirit and scope of the appended claims. The disclosed techniques include techniques that can be provided in an independent manner or in combination with each other. Therefore, features described for one technique may also be presented in combination with another technique.

Claims

1. A gate drive circuit for a power inverter branch in a power inverter, the power inverter branch comprising a first power switch having a first reverse conduction path and a second power switch having a second reverse conduction path, the power inverter branch being configured to drive an inductive-resistive load, the gate drive circuit comprising: a first gate driving sub-circuit, configured to control switching of the first power switch; The second gate drive sub-circuit is used to control the switching of the second power switch; wherein, The gate drive circuit is configured to control switching of the first power switch and the second power switch in a complementary manner and based on gate drive control signals of the first gate drive subcircuit and the second gate drive subcircuit, wherein the gate drive control signals indicate conduction conditions of the first reverse conduction channel and the second reverse conduction channel and a slope of a load current in the inductive-resistive load.

2. The gate driving circuit according to claim 1, configured as follows: generating a first gate drive control signal, wherein the first gate drive control signal indicates a conduction status of the first reverse conduction channel; generating a second gate drive control signal, the second gate drive control signal indicating a slope of a load current in the inductive-resistive load; and When the first reverse conduction channel is in a conducting state and the slope of the load current in the inductive-resistive load is positive, the first power switch is switched to a conducting state. 3 . The gate drive circuit according to claim 2 , configured so that the first gate drive control signal indicates when the first reverse conduction channel voltage is less than or equal to zero.

4. The gate drive circuit according to claim 2 or 3, wherein: The first gate drive control signal is a first output signal of a first comparator having a first non-inverting input connected to a supply voltage rail and a first inverting input connected to a midpoint between the first power switch and the second power switch. 5 . The gate driving circuit of claim 4 , further comprising the first comparator, the gate driving circuit being configured to scale the amplitude of the first voltage signal input to the first inverting input and the first non-inverting input using a first voltage divider circuit. 6 . The gate drive circuit of claim 5 , further comprising a first ramp capacitor connected in parallel with the second upper resistor in the first voltage divider circuit of the first non-inverting input.

7. The gate drive circuit according to any one of claims 2 to 6, wherein: The second gate drive control signal is a second output signal of a second comparator having a second inverting input connected to a DC output side of an inductor of the inductive-resistive load and a second non-inverting input connected to a midpoint between the first power switch and the second power switch, and is configured such that the second gate drive control signal indicates when a slope of a load current in the inductive-resistive load is positive.

8. The gate drive circuit of claim 7, further comprising the second comparator, the gate drive circuit being configured to scale the amplitude of the voltage signal input to the second inverting input and optionally to the second non-inverting input using a second voltage divider circuit.

9. The gate drive circuit according to any one of claims 2 to 8, configured as: generating a third gate drive control signal, wherein the third gate drive control signal indicates a conduction status of the second reverse conduction channel; generating a second gate drive input signal or a fourth gate drive input signal, the second gate drive input signal or the fourth gate drive input signal indicating a slope of a load current in the inductive-resistive load; and When the second reverse conduction channel is in a conducting state and the slope of the load current in the inductive-resistive load is negative, the second power switch is switched to a conducting state. 10 . The gate drive circuit according to claim 9 , configured so that the third gate drive control signal indicates when the second reverse conducting channel voltage is less than or equal to zero.

11. The gate drive circuit according to claim 9 or 10, wherein: The third gate driving control signal is a third output signal of a third comparator having a third inverting input connected to a midpoint between the first power switch and the second power switch and having a third non-inverting input connected to ground. 12 . The gate driving circuit of claim 11 , further comprising the third comparator, and configured to scale the amplitude of the third voltage signal input to the third inverting input and the third non-inverting input using a third voltage divider circuit.

13. The gate drive circuit of claim 11 or claim 12, further comprising a third ramping capacitor connected in parallel with a third upper resistor in a third voltage divider of the third non-inverting input.

14. The gate drive circuit according to any one of claims 9 to 13, wherein: The fourth gate drive control signal is a fourth output signal of a fourth comparator having a fourth inverting input connected to a midpoint between the first power switch and the second power switch and a fourth non-inverting input connected to a DC output side of an inductor of the inductive-resistive load, and is configured such that the fourth gate drive control signal indicates when a slope of the load current is negative.

15. The gate drive circuit of claim 14, further comprising the fourth comparator and configured to scale the amplitude of the voltage signal input to the fourth inverting input and optionally to the fourth non-inverting input using a fourth voltage divider circuit.

16. A power inverter comprising a gate drive circuit according to any preceding claim.

17. A method of operating a gate drive circuit, the gate drive circuit being used in a power inverter branch in a power inverter, the power inverter branch comprising a first power switch having a first reverse conduction path and a second power switch having a second reverse conduction path, the power inverter branch driving an inductive-resistive load, the gate drive circuit comprising: a first gate driving sub-circuit, configured to control switching of the first power switch; A second gate driving subcircuit is used to control the switching of the second power switch; the method comprises: The gate drive circuit is operated to control switching of the first power switch and the second power switch in a complementary manner and based on gate drive input signals of the first gate drive sub-circuit and the second gate drive sub-circuit, the gate drive input signals indicating conduction conditions of the first reverse conduction channel and the second reverse conduction channel and a slope of a load current in the inductive-resistive load.

Images