Manufacturing method of diode wafer and wafer to be processed

Abstract

The invention provides a manufacturing method of a diode wafer and a wafer to be processed, belongs to the field of wafer manufacturing, and is used for processing a plurality of original wafers obtained by cutting a crystal bar. First, it is determined whether a plurality of original wafers conform to a fabrication specification. And when the original wafer accords with the manufacturing specification, the original wafer is used as a high-order original wafer. And when the original wafer does not conform to the manufacturing specification, taking the original wafer as a low-order original wafer. Thirdly, calculating the proportion of the number of the low-order original wafers with the lattice orientation pit related problems to the number of all the low-order original wafers, and judging whether the proportion is greater than a preset value or not; and when the proportion is not greater than the preset value, removing part of the structure of each low-order original wafer, and smoothing the surface of each low-order original wafer. And finally, forming a diode structure in the smoothed low-order original wafer to obtain a diode wafer. According to the invention, the diode wafer and the wafer to be processed with better quality can be manufactured with lower cost.

Description

Technical Field

[0001] The invention relates to the field of wafer manufacturing, and in particular to a method for manufacturing a diode wafer and a wafer to be processed. Background Art

[0002] In the semiconductor manufacturing process, wafers are made from ingots. First, the appropriate material is selected to make the ingot. Common materials include silicon, gallium arsenide, etc. The selected material is placed in a high-temperature furnace for melting. The temperature and gas conditions in the furnace need to be properly controlled to ensure that the material can be melted evenly and reach the required purity. In the molten material, a crystal called a "seed crystal" (usually single crystal silicon) is gently placed and slowly lifted. During the lifting process, the crystal grabs the seed crystal from the molten material to form a growing ingot. The ingot gradually cools during the ingot pulling process to form a single crystal structure. The cooling rate and temperature control during the process are crucial to the quality of the ingot to ensure the purity and integrity of the ingot. After the ingot is cooled, it is cut to form wafers of the required diameter. Diamond blades or other cutting tools are usually used for cutting. The cut wafers are chemically or mechanically treated to remove surface residues, contamination and defects to make their surfaces flat and clean. The wafers are then polished to further improve surface flatness and optical quality. The finished wafers are then cleaned to remove any residue and contaminants. The wafers are then inspected and tested to ensure they meet specific quality standards.

[0003] In the semiconductor manufacturing industry, A-grade wafers and B-grade wafers are definitions of wafer quality and specifications. These definitions are usually reached through negotiations between semiconductor manufacturers, international standards organizations, and customers. Generally speaking, A-grade wafers usually have higher quality standards, such as surface flatness, wafer thickness uniformity, lattice structure integrity, etc. B-grade wafers have relatively lower quality standards and are usually used for general applications that do not require very high performance and reliability. A-grade wafers have a lower defect density, that is, fewer defects on the surface or within the volume of the wafer. B-grade wafers may have a higher defect density, which means that there may be more defects on the surface or within the volume of the wafer. A-grade wafers have strict specification controls in terms of size, wafer thickness, wafer flatness, lattice orientation, etc. to ensure process consistency and repeatability. The size, flatness, lattice orientation, etc. of B-grade wafers are relatively loose and not as strict as A-grade wafers. Generally, the wafers to be processed include low-order wafers, mid-order wafers, and high-order wafers. However, the price of higher-order wafers often cannot be reduced in the market. For example, diode wafers include low-order diode wafers, mid-order diode wafers, and high-order diode wafers. Due to the selling price of wafers, many low-order diode wafers use inferior A-gauge wafers, resulting in poor quality. In addition, many mid-order diode wafers use better A-gauge wafers, but due to the difference in substrate costs, they cannot compete with mid- and low-order diode wafers.

[0004] Therefore, in view of the above-mentioned difficulties, the present invention proposes a method for manufacturing a diode wafer and a wafer to be processed to solve the problems in the prior art. Summary of the invention

[0005] The invention provides a method for manufacturing a diode wafer and a wafer to be processed, which can manufacture a diode wafer and a wafer to be processed with better quality at a lower cost.

[0006] In one embodiment of the present invention, a method for manufacturing a diode wafer is provided, which is used to process multiple original wafers obtained by slicing from an ingot. The method for manufacturing a diode wafer includes the following steps: determining whether the multiple original wafers meet a manufacturing specification: if so, using the original wafer as a high-order original wafer; and if not, using the original wafer as a low-order original wafer, wherein the number of low-order original wafers is multiple; calculating the ratio of the number of low-order original wafers with crystal oriented pits (COP) related problems to the number of all low-order original wafers, and determining whether the ratio is greater than a preset value: if so, end; and if not, removing a portion of the structure of each low-order original wafer, wherein the portion of the structure has a fixed thickness; smoothing the surface of each low-order original wafer from which the structure is removed; and forming multiple diode structures in each smoothed low-order original wafer to obtain a diode wafer.

[0007] In one embodiment of the present invention, the items of production specifications include resistance, defects, black film, color film, wafer thickness, wafer growth method, wafer size, wafer surface, residual metal particle concentration, total thickness deviation, total indication reading, wafer warpage, local total indication reading and dust count.

[0008] In one embodiment of the present invention, the defects include chipping, crack, redundant laser engraving, scratch, stain and lattice crack.

[0009] In one embodiment of the present invention, in the step of removing a portion of the structure of each low-order original wafer, a low-order original wafer having a thickness greater than a preset value is selected, and a portion of the structure of each selected low-order original wafer is removed.

[0010] In one embodiment of the present invention, an etching process and a polishing process are sequentially performed on the surface of each low-level original wafer from which the structure is removed, so as to smooth the surface of each low-level original wafer from which the structure is removed.

[0011] In one embodiment of the present invention, a grinding process and a polishing process are sequentially performed on the surface of each low-level original wafer from which the structure is removed, so as to smooth the surface of each low-level original wafer from which the structure is removed.

[0012] In one embodiment of the present invention, the method for manufacturing a diode wafer further includes: a step of roughening the surface of each smoothed low-order original wafer. In the step of forming a plurality of diode structures in each smoothed low-order original wafer to obtain a diode wafer, a plurality of diode structures are formed in each roughened low-order original wafer to obtain a diode wafer.

[0013] In one embodiment of the present invention, the surface of each smoothed low-level original wafer is roughened by bench etching or spin etching.

[0014] In one embodiment of the present invention, the method for manufacturing a diode wafer further includes: a step of forming a metal conductive layer on a surface of the diode wafer.

[0015] In one embodiment of the present invention, the diode structure includes: a doped well region, a first heavily doped region, and a second heavily doped region. The doped well region and the first heavily doped region have a first conductivity type, wherein the doped well region is located in the smoothed low-level original wafer. The first heavily doped region is located in the doped well region. The second heavily doped region has a second conductivity type opposite to the first conductivity type, wherein the second heavily doped region is located in the doped well region.

[0016] In one embodiment of the present invention, a method for manufacturing a wafer to be processed is used to process multiple original wafers obtained by slicing from an ingot. The method for manufacturing the wafer to be processed includes the following steps: determining whether the multiple original wafers meet a manufacturing specification: if so, treating the original wafer as a high-order original wafer; and if not, treating the original wafer as a low-order original wafer, wherein the number of low-order original wafers is multiple; calculating the ratio of the number of low-order original wafers with problems related to crystal oriented pits (COP) to the number of all low-order original wafers, and determining whether the ratio is greater than a preset value: if so, end; and if not, removing a portion of the structure of each low-order original wafer, wherein the portion of the structure has a fixed thickness; and smoothing the surface of each low-order original wafer from which the structure is removed to obtain a wafer to be processed.

[0017] In one embodiment of the present invention, the items of production specifications include resistance, defects, black film, color film, wafer thickness, wafer growth method, wafer size, wafer surface, residual metal particle concentration, total thickness deviation, total indication reading, wafer warpage, local total indication reading and dust count.

[0018] In one embodiment of the present invention, the defects include chipping, crack, redundant laser engraving, scratch, stain and lattice crack.

[0019] In one embodiment of the present invention, in the step of removing a portion of the structure of each low-order original wafer, a low-order original wafer having a thickness greater than a preset value is selected, and a portion of the structure of each selected low-order original wafer is removed.

[0020] In one embodiment of the present invention, an etching process and a polishing process are sequentially performed on the surface of each low-level original wafer from which the structure is removed, so as to smooth the surface of each low-level original wafer from which the structure is removed.

[0021] In one embodiment of the present invention, a grinding process and a polishing process are sequentially performed on the surface of each low-level original wafer from which the structure is removed, so as to smooth the surface of each low-level original wafer from which the structure is removed.

[0022] In one embodiment of the present invention, the method for manufacturing a wafer to be processed further comprises a step of roughening the surface of each smoothed low-level original wafer.

[0023] In one embodiment of the present invention, the surface of each smoothed low-level original wafer is roughened by bench etching or spin etching.

[0024] Based on the above, the method for manufacturing diode wafers and wafers to be processed selects low-order original wafers with better quality according to the presence of crystal oriented pits (COP), thereby manufacturing diode wafers and wafers to be processed with better quality at a lower cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0026] Figure 1 The present invention is a flow chart of an embodiment of a method for manufacturing a diode wafer.

[0027] Figure 2 A structural cross-sectional view of a diode wafer according to an embodiment of the present invention.

[0028] Figure 3 The present invention is a flow chart of an embodiment of a method for manufacturing a wafer to be processed provided by the present invention.

[0029] Explanation of symbols:

[0030] 1: diode wafer;

[0031] 10: diode structure;

[0032] 100: doping well region;

[0033] 102: first heavily doped region;

[0034] 104: second heavily doped region;

[0035] 11: Low-order raw wafers;

[0036] 12: Metal conductive layer;

[0037] S10, S12, S14, S18, S20, S22, S24, S26, S28, S30, S32, S34, S36, S40, S42: steps. DETAILED DESCRIPTION

[0038] The embodiments of the present invention will be further explained below with reference to the accompanying drawings. As much as possible, the same reference numerals represent the same or similar components in the drawings and the specification. In the drawings, shapes and thicknesses may be exaggerated for simplicity and convenience. It is understood that the components not specifically shown in the drawings or described in the specification are known to those skilled in the art. Those skilled in the art may make various changes and modifications based on the contents of the present invention.

[0039] Unless otherwise specified, some conditional sentences or words, such as "can", "could", "might", or "may", are generally intended to express that the embodiments of the present invention have, but can also be interpreted as features, components, or steps that may not be required. In other embodiments, these features, components, or steps may not be required.

[0040] The description of "one embodiment" or "an embodiment" in the following text refers to a specific element, structure or feature associated with at least one embodiment. Therefore, multiple descriptions of "one embodiment" or "an embodiment" appearing in multiple places in the following text do not refer to the same embodiment. Furthermore, specific components, structures and features in one or more embodiments may be combined in an appropriate manner.

[0041] Certain words are used in the specification and claims to refer to specific components. However, those skilled in the art should understand that the same component may be referred to by different terms. The specification and claims do not distinguish components by differences in name, but by differences in the functions of the components. The term "include" as mentioned in the specification and claims is an open-ended term and should be interpreted as "include but not limited to". In addition, "coupling" includes any direct and indirect connection means. Therefore, if the text describes a first component coupled to a second component, it means that the first component can be directly connected to the second component through electrical connection or signal connection methods such as wireless transmission, optical transmission, etc., or can be indirectly electrically or signal connected to the second component through other components or connection means.

[0042] The following examples are particularly described, and these examples are only used for illustration, because for those skilled in the art, various changes and modifications can be made without departing from the spirit and scope of the disclosure of the present invention, so the protection scope of the disclosure of the present invention shall be determined by the scope of the appended claims. Throughout the specification and the claims, unless the content clearly specifies, the meaning of "one" and "the" includes this type of description including "one or at least one" of the elements or components. In addition, as used in the present invention, unless it is obvious from the specific context that more is excluded, the singular article also includes the description of multiple elements or components. Moreover, when applied in this description and the following claims, unless the content clearly specifies, the meaning of "in which" may include "in which" and "on which". The terms used in the specification and the claims, unless otherwise specified, usually have the ordinary meaning of each term used in this field, in the content of this invention and in the special content. Certain terms used to describe the present invention will be discussed below or elsewhere in this specification to provide practitioners with additional guidance in describing the present invention. Examples anywhere throughout the specification, including the use of examples of any term discussed herein, are provided for illustrative purposes only and certainly do not limit the scope and meaning of the present invention or any exemplified term. Likewise, the present invention is not limited to the various embodiments set forth in this specification.

[0043] In the specification and claims, if a first element is described as being located on, above, connected, joined, coupled to, or in contact with a second element, it means that the first element may be directly located on, directly connected, directly joined, or directly coupled to the second element, or it may mean that there are other elements between the first element and the second element. Conversely, if a first element is described as being directly located on, directly connected, directly joined, directly coupled, or directly in contact with a second element, it means that there are no other elements between the first element and the second element.

[0044] In the following description, a method for manufacturing a diode wafer and a wafer to be processed is provided, which selects a low-order original wafer with better quality according to the crystal oriented pits (COP) related issues, thereby manufacturing a diode wafer and a wafer to be processed with better quality at a lower cost.

[0045] Figure 1 This is a flow chart of an embodiment of the method for manufacturing a diode wafer provided by the present invention. Figure 1The following is a method for manufacturing a diode wafer, which is used to process a plurality of original wafers obtained by slicing from an ingot. These wafers have been subjected to grinding, etching and polishing processes to smoothen their surfaces. The original wafer is taken as an example of a silicon wafer, but the present invention is not limited thereto.

[0046] First, as shown in step S10, it is determined whether a plurality of raw wafers meet a manufacturing specification. When the raw wafers meet the manufacturing specification, as shown in step S12, the raw wafers are used as high-order raw wafers. When the raw wafers do not meet the manufacturing specification, as shown in step S14, the raw wafers are used as low-order raw wafers.

[0047] For example, the items of manufacturing specifications may include, but are not limited to, resistance, defects, black film, color film, wafer thickness, wafer growth method, wafer size, wafer surface, metal particle residual concentration, total thickness deviation, total indication reading, wafer warpage, local total indication reading and dust count. Defects may include chipping, crack, redundant laser engraving, scratch, stain and lattice crack, but the present invention is not limited thereto.

[0048] The total thickness deviation is defined as the difference between the maximum and minimum thickness of the wafer from the reference plane when the wafer is clamped tightly; it is generally expressed in microns (μm), and the general expression is such as: ≤15μm. The total indication reading is defined as the difference between the maximum distance and the minimum distance between the wafer surface and the reference plane when the wafer is clamped tightly, with the smallest surface formed by the sum of the intercepts of all points in the qualified quality area of ​​the wafer surface as the reference plane. The wafer warpage is defined as the difference between the minimum and maximum values ​​of the wafer surface from the reference plane when the wafer is not tightly attached, usually with the back of the wafer as the reference plane. The wafer warpage includes concave and convex conditions, with concave curvature being negative and convex curvature being positive; it is generally expressed in microns, and the general expression is such as: ≤30μm. The local total indication reading is defined as the difference between the maximum distance and the minimum distance between the wafer surface and the reference plane when the wafer is clamped tightly, with the smallest surface formed by the sum of the intercepts of all points in the local area specified on the wafer surface as the reference plane.

[0049] Table 1 provides a manufacturing specification. When the raw wafer does not meet one of the conditions in the manufacturing specification, it is considered a low-order raw wafer. When the raw wafer meets all the conditions in the manufacturing specification, it is considered a high-order raw wafer. In addition, when defects, black films or color films are observed on the raw wafer, it is also considered a low-order raw wafer. When defects, black films and color films are not observed on the raw wafer, it is considered a high-order raw wafer.

[0050] Table 1 Production specifications

[0051]

[0052]

[0053] Generally speaking, there are multiple low-order original wafers cut from the crystal rod. After step S14, step S18 is performed. In step S18, the ratio of the number of low-order original wafers with lattice oriented pits (crystal oriented pits, COP) related problems to the total number of low-order original wafers is calculated, and it is determined whether this ratio is greater than a preset value. Lattice oriented pits are not easily removed by etching, grinding or polishing processes, and tools such as optical microscopes or electron microscopes can be used to observe lattice oriented pits. The problem related to lattice oriented pits is defined as the corresponding low-order original wafer failing to pass the COP specification test set by the detection machine. For example, when the number of lattice oriented pits in a low-order original wafer is greater than a set value, this low-order original wafer cannot pass the COP specification test set by the detection machine. If the number of selected low-order original wafers with lattice oriented pits related problems is 64, and the total number of selected low-order original wafers is 100, it means that the ratio is 0.64. The appearance of lattice-oriented pits means that when the diode is manufactured and the wafer is etched, holes that should not exist will appear. Because when the diode is made, it is necessary to process the silicon wafer. During the processing, the silicon wafer will be needed as a substrate for ion implantation or diffusion and other processes. Where there are holes, there is no silicon wafer. Therefore, it cannot carry the required process, which will cause the electrical characteristics of the diode itself to drift, resulting in undesirable phenomena, which will lead to a decrease in yield. In addition, when manufacturing diodes, it is sometimes necessary to dig holes and fill them with the required materials. If the COP is poor, it is very likely that after digging the holes, there will be too much dust, causing subsequent process problems, and then the electrical characteristics of the diode itself will drift, causing undesirable phenomena, which will lead to a decrease in yield. Therefore, a good silicon wafer substrate can help the diode not to lower the overall process yield due to material problems. In other words, when the number of selected low-order original wafers with lattice-oriented pit-related problems accounts for a ratio greater than a preset value to the number of all selected low-order original wafers, it means that the yield of diode wafers made with this batch of low-order original wafers will drop significantly, so step S20 is entered to end the entire process. When the number of selected low-order original wafers with lattice-oriented pit-related problems accounts for a ratio greater than a preset value to the number of all selected low-order original wafers, it means that the yield of diode wafers made with this batch of low-order original wafers will increase significantly, and the price of low-order original wafers is low and very valuable in the market. That is to say, when the judgment result of step S18 is no, step S22 is entered. In step S22, a low-order original wafer having a thickness greater than a preset value is selected, and a partial structure of each selected low-order original wafer is removed, wherein the partial structure has a fixed thickness, thereby removing the observed lattice-oriented pits. This fixed thickness depends on how deep the observed lattice-oriented pits are located.For example, if the observed lattice-oriented pits are located at a depth of 7 microns from the surface, it means that the fixed thickness can be 7 microns.

[0054] After step S22, step S24 is performed. In step S24, the surface of each low-level original wafer from which the structure is removed is smoothed to remove surface stains, chemical films or scratches, so that the surface flatness and the amount of dust of the low-level original wafer reach the desired level. In certain embodiments of the present invention, the surface of each low-level original wafer from which the structure is removed is sequentially subjected to an etching process and a polishing process to smooth the surface of each low-level original wafer from which the structure is removed. Alternatively, the surface of each low-level original wafer from which the structure is removed is sequentially subjected to a grinding process and a polishing process to smooth the surface of each low-level original wafer from which the structure is removed.

[0055] After step S24, proceed to step S26. In step S26, the surface of each smoothed low-order original wafer is roughened to facilitate the stability of the bonding metal layer. The surface of each smoothed low-order original wafer can be roughened by bench etching or spin etching. Then, in step S28, multiple diode structures are formed in each roughened low-order original wafer to obtain a diode wafer. Finally, as shown in step S30, a metal conductive layer is formed on the surface of the diode wafer, and the metal conductive layer is used as the electrode of the diode. After step S30, proceed to step S20. If substantially the same results can be obtained, these steps do not have to be followed. Figure 1 Execute in the order shown.

[0056] Figure 2 FIG. 1 is a cross-sectional view of a structure of a diode wafer 1 according to an embodiment of the present invention. Figure 2 As shown, each diode structure 10 may include a doped well region 100, a first heavily doped region 102, and a second heavily doped region 104. The doped well region 100 and the first heavily doped region 102 have a first conductivity type, and the second heavily doped region 104 has a second conductivity type opposite to the first conductivity type. For example, when the first conductivity type is N-type, the second conductivity type is P-type. When the first conductivity type is P-type, the second conductivity type is N-type. The doped well region 100 is located in the roughened low-level original wafer 11. The first heavily doped region 102 is located in the doped well region 100, and the second heavily doped region 104 is located in the doped well region 100. The metal conductive layer 12 is located on the surface of the roughened low-level original wafer 11.

[0057] exist Figure 1In the process, the step of selecting a low-order original wafer with a thickness greater than a preset value can be omitted, so that step S22 is to remove a portion of the structure of each low-order original wafer. In addition, step S26 can also be omitted. When step S26 is omitted, step S28 is to form a plurality of diode structures in each smoothed low-order original wafer to obtain a diode wafer. Step S30 can also be executed or omitted as required. When step S30 is omitted, after step S28 is completed, step S20 will be directly performed.

[0058] Figure 3 This is a flow chart of an embodiment of a method for manufacturing a wafer to be processed provided by the present invention. Figure 3 The following describes a method for manufacturing a wafer to be processed, which is used to process a plurality of original wafers obtained by slicing from an ingot. These wafers have been subjected to grinding, etching and polishing processes to smoothen their surfaces. The original wafer is taken as an example of a silicon wafer, but the present invention is not limited thereto. Figure 3 Steps S32, S34, S36, S40, S42 and S44 are respectively Figure 1 Steps S10, S12, S14, S18, S20 and S22 are the same and will not be described here. After step S44 is completed, step S46 is performed. In step S46, the surface of each low-order original wafer from which the structure is removed is smoothed to obtain a wafer to be processed. Any semiconductor element, such as a diode or a micro-electromechanical (MEMS) element, can be formed on the wafer to be processed. In step S46, the surface of each low-order original wafer from which the structure is removed is sequentially subjected to an etching process and a polishing process to smooth the surface of each low-order original wafer from which the structure is removed. Alternatively, the surface of each low-order original wafer from which the structure is removed is sequentially subjected to a grinding process and a polishing process to smooth the surface of each low-order original wafer from which the structure is removed. Then, step S48 is performed to roughen the surface of each smoothed low-order original wafer to facilitate the stability of the bonding metal layer. The surface of each smoothed low-order original wafer can be roughened by a bench etching method or a spin etching method. After step S48 is completed, step S42 is performed.

[0059] exist Figure 3 In the process, the step of selecting the low-order original wafer with a thickness greater than the preset value can be omitted, so that step S44 is to remove the partial structure of each low-order original wafer. In addition, step S48 can also be executed or omitted according to needs. When step S48 is omitted, after step S46 is completed, step S42 will be directly performed.

[0060] According to the above embodiments, the method for manufacturing diode wafers and wafers to be processed selects low-order original wafers with better quality based on the issues related to lattice oriented pits, thereby manufacturing diode wafers and wafers to be processed with better quality at a lower cost.

[0061] The above is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Therefore, all equivalent changes and modifications to the shape, structure, characteristics and spirit described in the scope of the claims of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A method for manufacturing a diode wafer, which is used to process a plurality of raw wafers cut from a crystal rod, characterized in that: The method for manufacturing the diode wafer comprises the following steps: Determine whether the plurality of original wafers meet a manufacturing specification: if so, treat the original wafer as a high-order original wafer; if not, treat the original wafer as a low-order original wafer, wherein the number of the low-order original wafers is multiple; Calculate the ratio of the number of low-order original wafers with lattice-oriented pit-related problems to the number of all low-order original wafers, and determine whether the ratio is greater than a preset value: if so, end; if not, remove a partial structure of each low-order original wafer, wherein the partial structure has a fixed thickness; smoothing the surface of each low-level original wafer from which the structure is removed; as well as A plurality of diode structures are formed in each of the smoothed low-level original wafers to obtain a diode wafer.

2. The method for manufacturing a diode wafer according to claim 1, characterized in that: The production specifications include resistance, defects, black film, color film, wafer thickness, wafer growth method, wafer size, wafer surface, residual metal particle concentration, total thickness deviation, total indication reading, wafer warpage, local total indication reading and dust count.

3. The method for manufacturing a diode wafer according to claim 2, characterized in that: The defects include chipped corners, broken pieces, extra laser engravings, scratches, stains and lattice cracks.

4. The method for manufacturing a diode wafer according to claim 1, characterized in that: In the step of removing a portion of the structure of each low-order original wafer, a low-order original wafer having a thickness greater than a preset value is selected, and a portion of the structure of each selected low-order original wafer is removed.

5. The method for manufacturing a diode wafer according to claim 1, characterized in that: In the step of smoothing the surface of each low-level original wafer from which the structure is removed, an etching process and a polishing process are sequentially performed on the surface of each low-level original wafer from which the structure is removed to smooth the surface of each low-level original wafer from which the structure is removed.

6. The method for manufacturing a diode wafer according to claim 1, characterized in that: In the step of smoothing the surface of each low-level original wafer from which the structure is removed, a grinding process and a polishing process are sequentially performed on the surface of each low-level original wafer from which the structure is removed to smooth the surface of each low-level original wafer from which the structure is removed.

7. The method for manufacturing a diode wafer according to claim 1, characterized in that: The method for manufacturing the diode wafer also includes: a step of roughening the surface of each smoothed low-order original wafer; in the step of forming multiple diode structures in each smoothed low-order original wafer to obtain a diode wafer, multiple diode structures are formed in each roughened low-order original wafer to obtain a diode wafer.

8. The method for manufacturing a diode wafer according to claim 7, characterized in that: The surface of each low-level original wafer that has been smoothed is roughened by a groove etching method or a spin etching method.

9. The method for manufacturing a diode wafer according to claim 7, characterized in that: The method for manufacturing the diode wafer also includes: a step of forming a metal conductive layer on the surface of the diode wafer.

10. The method for manufacturing a diode wafer according to claim 1, characterized in that: The diode structure comprises: a doped well region having a first conductivity type, wherein the doped well region is located in the smoothed low-level original wafer; a first heavily doped region having the first conductivity type, wherein the first heavily doped region is located in the doped well region; and A second heavily doped region has a second conductivity type opposite to the first conductivity type, wherein the second heavily doped region is located in the doped well region.

11. A method for manufacturing a wafer to be processed, which is used to process a plurality of original wafers cut from a crystal rod, characterized in that: The method for manufacturing the wafer to be processed comprises the following steps: Determine whether the plurality of original wafers meet a manufacturing specification: if so, treat the original wafer as a high-order original wafer; if not, treat the original wafer as a low-order original wafer, wherein the number of the low-order original wafers is multiple; Calculate the ratio of the number of low-order original wafers with lattice-oriented pit-related problems to the number of all low-order original wafers, and determine whether the ratio is greater than a preset value: if so, end; if not, remove a partial structure of each low-order original wafer, wherein the partial structure has a fixed thickness; and The surface of each low-level original wafer from which the structure is removed is smoothed to obtain a wafer to be processed.

12. The method for manufacturing a wafer to be processed according to claim 11, characterized in that: The production specifications include resistance, defects, black film, color film, wafer thickness, wafer growth method, wafer size, wafer surface, residual metal particle concentration, total thickness deviation, total indication reading, wafer warpage, local total indication reading and dust count.

13. The method for manufacturing a wafer to be processed according to claim 12, characterized in that: The defects include chipped corners, broken pieces, extra laser engravings, scratches, stains and lattice cracks.

14. The method for manufacturing a wafer to be processed according to claim 11, characterized in that: In the step of removing a portion of the structure of each low-order original wafer, a low-order original wafer having a thickness greater than a preset value is selected, and a portion of the structure of each selected low-order original wafer is removed.

15. The method for manufacturing a wafer to be processed according to claim 11, characterized in that: In the step of smoothing the surface of each low-level original wafer from which the structure is removed, an etching process and a polishing process are sequentially performed on the surface of each low-level original wafer from which the structure is removed to smooth the surface of each low-level original wafer from which the structure is removed.

16. The method for manufacturing a wafer to be processed according to claim 11, characterized in that: In the step of smoothing the surface of each low-level original wafer from which the structure is removed, a grinding process and a polishing process are sequentially performed on the surface of each low-level original wafer from which the structure is removed to smooth the surface of each low-level original wafer from which the structure is removed.

17. The method for manufacturing a wafer to be processed according to claim 11, characterized in that: The method for manufacturing the wafer to be processed further includes: a step of roughening the surface of each smoothed low-order original wafer.

18. The method for manufacturing a wafer to be processed according to claim 17, characterized in that: The surface of each low-level original wafer that has been smoothed is roughened by a groove etching method or a spin etching method.

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