Angle sensor chip

Abstract

The invention belongs to the field of electronic chips, and discloses an angle sensor chip, the main structure of the chip sequentially comprises a silicon layer, a silicon oxide layer with the layer thickness of 500 nm-2 [mu] m, a magnetic sensitive film layer with the thickness of 20-200 nm, a silicon nitride layer with the thickness of 0.5-2 [mu] m, and an aluminum layer with the thickness of 1-2 [mu] m, the structure of the magnetic sensitive film layer is formed by arranging two groups of Wheatstone bridges with the angle difference of 40-50 degrees, each group of Wheatstone bridges comprises four single bridges, lines of each group of bridges are connected through NiFe, the sensitivity and reliability of the angle sensing chip are improved by optimizing the structural design, and the usable area of the chip is reduced, so that the production cost is reduced.

Description

Technical Field

[0001] The invention belongs to the field of electronic chips, in particular to an angle sensor chip. Background Art

[0002] There are many angle sensor chips based on the AMR effect on the market. The temperature of the chips is unstable during use, which has a great impact on their service life. Therefore, some subsequent operations using these chips will be affected, especially affecting the sensitivity and reliability of use, which also leads to defects in the use of corresponding electronic products. Summary of the invention

[0003] In order to solve the above problems, the present invention provides an angle sensor chip, and the specific technical solution is as follows:

[0004] An angle sensor chip, the main structure of the chip comprises in sequence a silicon layer, a silicon oxide layer, the layer thickness is 500nm-2um, a magnetically sensitive thin film layer, the thickness is 20-200nm, a silicon nitride layer, the thickness is 0.5-2um, and an aluminum layer, the thickness is 1-2um. The first layer is made of silicon, the main purpose of which is to meet the processing requirements of semiconductor wafers. The second layer of silicon oxide plays a passivation role to prevent leakage of Si substrate. The structure of the magnetically sensitive thin film layer is: it is formed by arranging two groups of Wheatstone bridges with an angle difference of 40-50°, preferably 45°, the symmetry centers of the two groups of Wheatstone bridges coincide, each group of Wheatstone bridges includes four single bridges, and the lines of each group of bridges are connected by NiFe, so that a buffer area can be provided for the internal magnetic moment of the thin film layer, and the interference caused by the same easy magnetization axis of parallel lines can be eliminated, and the bridge resistance deviation can be better controlled to be controlled within a lower range. Each group of Wheatstone bridges is placed independently to prevent the bridges from interfering with each other.

[0005] A further improvement is that the symmetry centers of the two groups of Wheatstone bridges completely coincide.

[0006] A further improvement is that the NiFe is in an arc shape.

[0007] A further improvement is that the line width of the bridge is 4um-40um, and the line spacing is 1-5um.

[0008] Further improvements are: the length of the lines of each group of bridges is consistent to ensure the minimum offset of the Wheatstone bridge, and the chip utilization rate is maximized through optimized design.

[0009] A further improvement is that each interface of the bridge on the magnetically sensitive film layer is connected to the aluminum layer through an aluminum wire.

[0010] At the joints of the Wheatstone bridge, the silicon nitride in the area that needs to be connected has been etched away through the previous process, exposing the NiFe film at the bottom. Through a certain Al line pattern, the various resistor bridges are connected and gathered at the PAD position. The design width of the A1 line remains consistent. The purpose is to ensure that the aspect ratio of the line is consistent even after the process error of the processing platform is introduced.

[0011] Further improvements are: an outer silicon oxide layer with a thickness of 1-2um is grown on the outer surface of the aluminum layer. The first is to protect the A1 line from oxidation and increase the working stability and reliability of the chip. The second is to cover the A1 line, enhance the adhesion of the pad position, enhance the tensile strength after wire bonding, and thus enhance the chip reliability.

[0012] Beneficial effects of the present invention: The angle sensor chip provided by the present invention has a double Wheatstone bridge structure so that its output is a sine-cosine curve, thereby improving the temperature stability of the chip output, so that the temperature will not fluctuate too much during use, and the life of the chip can be guaranteed. Moreover, through the centering structure, the angle sensing error of the chip is also relatively small, and its sensitivity is more reliable. The size of the chip can be controlled by the number of lines of the bridge, generally distributed in 500um*500um-3000um*3000um, thereby reducing the chip usage area and thus reducing production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 The layer structure of the chip in the embodiment;

[0014] Figure 2 is a schematic diagram of the structure of the thin film material layer in the embodiment;

[0015] Figure 3 This is a diagram of the aluminum layer and aluminum electrode structure in the embodiment;

[0016] Figure 4 It is a PAD position structure diagram in the embodiment. DETAILED DESCRIPTION

[0017] In order to deepen the understanding of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. The embodiments are only used to explain the present invention and do not limit the scope of protection.

[0018] This embodiment provides an angle sensor chip, and its chip structure is as follows: Figure 1As shown: the materials of the chip are: 1. Si; 2. SiO2; 3. Magnetic sensitive film; 4. Si3N4 / SiO2; 5. A1; 6. SiO2. The first layer of material is Si, which is mainly used as a substrate to meet the needs of semiconductor wafer processing. The second layer of material is silicon oxide, with a thickness of 500nm~2um, which is used for passivation to prevent leakage of Si substrate. The third layer of material is magnetic sensitive film material, with a thickness of 20nm~200nm, which is used to sense the magnetic field signal in the environment and convert it into a voltage signal. The fourth layer of material is Si3N4, with a thickness of 0.5um~2um, which protects the third layer of material from oxidation and plays a role in voltage isolation. The fifth layer of material is A1, with a thickness of 1um~2um. Through a certain structural design, the third layer of material is led out to the PAD position to facilitate wire bonding packaging. The sixth layer of material is SiO2, with a thickness of 1um~2um. While protecting the A1 electrode from oxidation, it can also improve the adhesion of the A1 electrode at the PAD position and improve the reliability of the chip.

[0019] Among them, the structural design of the film layer refers to Figure 2 , two groups of Wheatstone bridges with an angle difference of 45° are arranged through a certain structure. The chip size can be controlled by increasing or decreasing the number of lines, and the size distribution is between 500um*500um and 3000um*3000um. The main structural features are as follows: 1. Each group of Wheatstone bridges is composed of 4 single bridges, evenly distributed around the chip; 2. The two groups of Wheatstone bridges are specially arranged at a 45° angle to ensure that the phase difference of the output curves of the two groups of bridges is 45°, and the symmetry centers of the two groups of Wheatstone bridges coincide; 3. The lines are directly connected by arc-shaped NiFe, which can provide a buffer area for the internal magnetic moment of the film, eliminate the interference caused by the same easy magnetization axis of parallel lines, and better control the bridge resistance deviation to keep it within a lower range; 4. According to different parameters, the line width is 4um-40um, and the line spacing is 1um-5um. 5. Each group of bridges of the Wheatstone bridge is placed independently to prevent the bridges from interfering with each other. The length of each bridge group is consistent, ensuring the minimum offset of the Wheatstone bridge, and maximizing chip utilization through optimized design.

[0020] Then, the connection design of the aluminum layer and the film layer is as follows: Figure 3 As shown in the figure, it is an aluminum electrode structure. At the joint of the Wheatstone bridge, the silicon nitride in the area that needs to be connected has been etched away through the previous process, exposing the NiFe film at the bottom. Through a certain A1 line pattern, the various resistor bridges are connected and gathered at the PAD position. The design width of the A1 line remains consistent. The purpose is to ensure that the aspect ratio of the line is consistent even after the process error of the processing platform is introduced.

[0021] Finally, the PAD position structure, such as Figure 4 As shown in the figure, after the A1 electrode structure is grown, a SiO2 passivation layer will be grown on the surface. The main purpose is twofold. The first is to protect the A1 line from oxidation and increase the working stability and reliability of the chip. The second is to cover the A1 line, enhance the adhesion of the pad position, and enhance the tensile strength after wire bonding, thereby enhancing chip reliability.

[0022] The angle sensor chip provided in this embodiment uses a double Wheatstone bridge structure to make its output a sine-cosine curve, thereby improving the temperature stability of the chip output. In this way, the temperature will not fluctuate too much during use, thereby ensuring the life of the chip. In addition, through the centering structure, the angle sensing error of the chip is relatively small, and its sensitivity is more reliable. The size of the chip can be controlled by the number of lines of the bridge, generally distributed in the range of 500um*500um-3000um*3000um, thereby reducing the chip usage area and thus reducing production costs.

Claims

1. An angle sensor chip, characterized in that: The main structure of the chip includes a silicon layer, a silicon oxide layer with a thickness of 500nm-2um, a magnetically sensitive thin film layer with a thickness of 20-200nm, a silicon nitride layer with a thickness of 0.5-2um, and an aluminum layer with a thickness of 1-2um. The structure of the magnetically sensitive thin film layer is: it is composed of two groups of Wheatstone bridges with an angle difference of 40-50°, each group of Wheatstone bridges includes four single bridges, and the lines of each group of bridges are connected by NiFe.

2. The angle sensor chip according to claim 1, characterized in that: The NiFe is in an arc shape.

3. The angle sensor chip according to claim 1, characterized in that: The angle between the two sets of Wheatstone bridges is 45°.

4. The angle sensor chip according to claim 1, characterized in that: The symmetry centers of the two sets of Wheatstone bridges coincide.

5. The angle sensor chip according to claim 1, characterized in that: The line width of the bridge is 4um-40um, and the line spacing is 1-5um.

6. The angle sensor chip according to claim 1, characterized in that: The length of the lines in each set of bridges is the same.

7. The angle sensor chip according to claim 1, characterized in that: Each interface of the bridge on the magnetically sensitive film layer is connected to the aluminum layer through an aluminum wire.

8. The angle sensor chip according to claim 1, characterized in that: An outer silicon oxide layer with a thickness of 1-2 um is grown on the outer surface of the aluminum layer.

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