Photon number distinguishable detection system and method

Abstract

The invention relates to a photon number distinguishable detection system and a photon number distinguishable detection method. A BOOST booster circuit module provides a direct-current voltage meeting the requirement that a multi-pixel photon counter works in a Geiger mode under the control of an FPGA (Field Programmable Gate Array); the temperature control circuit module collects the internal temperature of the multi-pixel photon counter and controls the temperature, so that the multi-pixel photon counter works at a constant temperature; the signal amplification circuit module amplifies an avalanche signal output by the multi-pixel photon counter and sends the amplified avalanche signal to the signal processing module, the signal processing module carries out extraction, photon number distribution analysis, error analysis and optimization and real-time photon number judgment and output on the signal output by the multi-pixel photon counter, and the FPGA receives an error analysis and optimization result of the signal processing module. And the adjusting signal is sent to the BOOST circuit module. The system is high in integration level and stable in temperature control, comprises an error detection and optimization unit, can output the photon number in real time, is simple to operate, can communicate with a PC upper computer through a USB interface, is flexible to use, and can realize low-error photon number distinguishable detection.

Description

Technical Field

[0001] The present invention relates to the field of multi-pixel photon counters, and in particular to a photon number resolvable detection system and method. Background Art

[0002] In recent years, multi-pixel photon counters have attracted extensive attention as highly sensitive photoelectric detection devices in the fields of quantum communication, nuclear medical imaging, photon imaging, and lidar. This type of device has the advantages of high temporal resolution, low noise level, and high efficiency, and can achieve accurate counting and measurement of single photon events. In many applications, especially in the field of quantum communication, the detection efficiency, time response, and anti-interference ability of multi-pixel photon counters directly affect the transmission quality and information security of the system. In order to effectively capture fast optical signals, the detection performance of multi-pixel photon counters and the design of subsequent signal processing circuits are crucial. Therefore, research on the resolvable detection of photon numbers has become an important technical direction in photon detection technology and its applications.

[0003] An existing conventional photon number resolvable detection system includes N waveguide beam splitters, N first single-photon detectors, an adjustable beam splitter, a second single-photon detector, a cyclic waveguide, and a control module. The N waveguide beam splitters are connected in sequence, and the light pulse to be measured is input into the first waveguide beam splitter and then input into each waveguide beam splitter in sequence. At the same time, the first single-photon detector connected to each waveguide beam splitter detects and counts the received light pulse and feeds the result back to the control module. The control module counts the total count of each first single-photon detector in each cycle process, and the control module controls whether the cycle ends according to whether the total count in each cycle is zero. When the cycle ends, the control module accumulates the total count of the first single-photon detector in each cycle process and the count of the second single-photon detector to complete the photon number resolution of the light pulse to be measured.

[0004] However, the photon number resolvable detection system has a complex structure and requires multiple waveguide beam splitters, single photon detectors and adjustable beam splitters to work together. The results are affected by the accuracy of each device, and it does not have the error analysis and real-time resolution functions of the photon number distribution state. It cannot guarantee the accuracy of the final detection results, thus limiting the application scope of the photon number resolvable detection system. Summary of the invention

[0005] In view of the above problems, a photon number resolvable detection system and method are proposed.

[0006] The technical scheme of the present invention is: a photon number distinguishable detection system, comprising FPGA, a host computer, a BOOST boost circuit module, a temperature control circuit module, a signal amplification circuit module, and a signal processing module; the BOOST boost circuit module provides a DC voltage that satisfies the multi-pixel photon counter working in a Geiger mode under the control of the FPGA; an external laser signal sequentially outputs light pulses to the multi-pixel photon counter through an adjustable optical attenuator, a laser collimating lens, and an aspheric condensing lens; the temperature control circuit module collects the internal temperature of the multi-pixel photon counter and controls the working temperature of the multi-pixel photon counter so that the multi-pixel photon counter works at a constant temperature; the signal amplification circuit module is used to amplify the avalanche signal output by the multi-pixel photon counter; the output signal of the signal amplification circuit module is sent to a data acquisition card through a low-pass filter, the data acquisition card communicates with the signal processing module through a PC terminal of the host computer, the signal processing module extracts the signal output by the multi-pixel photon counter, performs photon number distribution analysis, error analysis and optimization, and real-time photon number judgment and output, the FPGA receives the error analysis and optimization results of the signal processing module, and adjusts the signal to the BOOST boost circuit module.

[0007] Preferably, the temperature control circuit module includes an error amplifier and an LED indicator light; the error amplifier amplifies the acquired error signal and sends it to a semiconductor refrigerator built into the multi-pixel photon counter, the semiconductor refrigerator performs cooling to change the device temperature, the local monitoring temperature is collected in real time to generate a new error signal again, forming a closed loop, and at the same time the error amplifier outputs a signal as a driving signal to the LED indicator light, and the cooling condition is displayed in real time through the light emission of the LED light.

[0008] Preferably, the BOOST boost circuit module includes a voltage reference chip, a digital-to-analog converter, a voltage follower and a professional power management chip which are electrically connected in sequence, the voltage reference chip provides a 2.5V reference DC voltage with an accuracy of ±0.5% to the digital-to-analog converter; the digital-to-analog converter is connected to the FPGA via SPI, the SCLK port of the chip in the digital-to-analog converter receives the synchronous clock signal sent by the FPGA to ensure the correct transmission and processing of data, and the DIN port of the digital-to-analog converter changes the value of the output DC voltage by receiving the digital signal sent by the FPGA; the voltage follower receives the DC voltage output by the digital-to-analog converter, and performs signal buffering and voltage stabilization on the received signal, providing a stable voltage value signal for the subsequent boost circuit; the professional power management chip is used to form a basic BOOST boost topology circuit with peripheral inductors, capacitors, and MOS tubes, providing the MOS tube with a PWM wave with stable duty cycle and period, and realizing the amplification of the DC voltage by changing the value of the input voltage, so as to provide a stable bias voltage for the normal operation of the multi-pixel photon counter.

[0009] Preferably, the signal amplification circuit module is electrically connected to the multi-pixel photon counter to perform gain amplification on the weak avalanche signal output by the multi-pixel photon counter, and is simultaneously matched with a filter module to filter and screen the signal, thereby facilitating subsequent collection and analysis of the avalanche signal output by the multi-pixel photon counter.

[0010] Preferably, the signal processing module collects avalanche signals of a multi-pixel photon counter, and uses the collected signals to perform fitting analysis of the photon number distribution state, error analysis and optimization of the photon number distribution state, and real-time photon number distribution state judgment and output.

[0011] A photon number resolvable detection method, using the photon number resolvable detection system to collect photon numbers, the detection includes fitting analysis of photon number distribution state, error analysis and optimization of photon number distribution state, and real-time photon number distribution state judgment;

[0012] The fitting of the photon number distribution state: the photon number distribution state of the multi-pixel photon counter is calculated by collecting and fitting data with a storage depth of 1M and a cycle number of 500 cycles;

[0013] Error analysis and optimization of photon number distribution state: The error threshold is set to 1% by calculating the proportion of the overlapping area of ​​adjacent photon state waveforms to the area of ​​their respective waveforms. When the actual error is higher than 1%, if the error is caused by too many incident photons, resulting in an increase in the detection error, the error is reduced by reducing the bias voltage. If the error is caused by too low a bias voltage, resulting in too much dark noise and the signal being submerged in the dark noise, the error is reduced by increasing the bias voltage. The error optimization system communicates with the FPGA through timely feedback to change the digital signal input into the digital-to-analog converter in the BOOST boost circuit module, thereby changing the output voltage value to achieve correction of the output bias voltage so that the photon number distribution error can meet the error threshold.

[0014] After calculating the number of photons N that meet the error condition, N is input into the real-time photon number distribution state judgment; the real-time photon number distribution state judgment is based on the number of photons below the error threshold determined in the error analysis, and the signal passing through the data acquisition card is input into the photon number judgment and output program. First, the peak information of the pulse signal is extracted, and then input into the N-way comparison circuit. The comparison circuit consists of a comparator and an XOR gate. The reference voltage of the first comparator is the voltage value at the intersection of the 0 photon peak and the 1 photon peak, and the reference voltage of the second comparator is the voltage value at the intersection of the 1 photon peak and the 2 photon peak. voltage value, and so on, the reference voltage of the Nth comparator is the voltage value at the intersection of the N-1 photon peak and the N photon peak; after the signal passes through the comparator, if the amplitude is higher than or equal to the reference voltage, it will output "1", and if it is lower than the reference voltage, it will output "0". Finally, the output state of the comparator of each channel is sent to the XOR gate circuit of the next stage, and the "XOR" operation is performed through the connection with the next level channel. Only when one channel outputs "1" and the other outputs "0", the XOR gate circuit will have an output. Different channel outputs correspond to different photon numbers, thereby realizing the judgment and output of different photon state information.

[0015] The beneficial effects of the present invention are as follows: compared with the existing photon number resolvable detection system, the photon number resolvable detection system and method of the present invention have high integration, stable temperature control, include error detection and optimization units, can output the number of photons in real time, are simple to operate, can communicate with a PC host computer through a USB interface, are flexible to use, and can achieve low-error photon number resolvable detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the system structure of the present invention;

[0017] Figure 2 It is a circuit connection schematic diagram of the present invention;

[0018] Figure 3 It is a schematic diagram of the signal processing module program of the present invention;

[0019] Figure 4 A schematic diagram of selecting a reference voltage value for a comparator program of the present invention. DETAILED DESCRIPTION

[0020] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. This embodiment is implemented based on the technical solution of the present invention, and provides a detailed implementation method and specific operation process, but the protection scope of the present invention is not limited to the following embodiments.

[0021] The present invention provides a low-error photon number resolvable detection system. Figure 1As shown, it includes: FPGA, EEPROM of the host computer, BOOST boost circuit module, temperature control circuit module, signal amplification circuit module, and signal processing module; the FPGA is electrically connected to the EEPROM, BOOST boost circuit module, and temperature control circuit module respectively; the BOOST boost circuit module, temperature control circuit module, and signal amplification circuit module are electrically connected to the multi-pixel photon counter respectively; the BOOST boost circuit module provides a DC voltage that satisfies the multi-pixel photon counter working in the Geiger mode under the control of the FPGA; the external laser signal outputs light pulses to the multi-pixel photon counter in turn through the adjustable optical attenuator, the laser collimating lens, and the aspheric focusing lens The temperature control circuit module collects the internal temperature of the multi-pixel photon counter and controls the working temperature of the multi-pixel photon counter so that the multi-pixel photon counter works at a constant temperature. The signal amplification circuit module is used to amplify the avalanche signal output by the multi-pixel photon counter. The output signal of the signal amplification circuit module is sent to the data acquisition card through a low-pass filter. The data acquisition card communicates with the signal processing module through the PC end of the host computer. The signal processing module extracts the signal output by the multi-pixel photon counter, performs photon number distribution analysis, error analysis and optimization, and real-time photon number judgment and output. The FPGA receives the error analysis and optimization results of the signal processing module and adjusts the signal to the BOOST boost circuit module.

[0022] See also Figure 1 and Figure 2 , the present invention requires the following guarantees to achieve photon number resolution:

[0023] 1) Temperature control: The temperature control circuit module controls the temperature of the multi-pixel photon counter so that the multi-pixel photon counter works at a constant temperature, ensuring that its dark count rate is at a low level and remains stable;

[0024] 2) Providing high-voltage bias: The BOOST boost circuit module includes a voltage reference chip, a digital-to-analog converter, a voltage follower and a professional power management chip that are electrically connected in sequence. The voltage reference chip is used to generate a high-precision reference voltage that acts on the subsequent digital-to-analog converter; the digital-to-analog converter is electrically connected to the FPGA via SPI, and the FPGA generates a signal and sends it to the digital signal receiving end of the digital-to-analog converter chip, and changes the value of the output analog voltage by changing the value of the digital signal input by the FPGA; the voltage follower is used for signal buffering and voltage stabilization, and provides a stable output voltage for the subsequent boost circuit; the professional power management chip is used to amplify the input DC voltage and provide a stable bias voltage for the normal operation of the multi-pixel photon counter;

[0025] 3) Signal amplification: The signal amplification circuit module is electrically connected to the multi-pixel photon counter to stably amplify the weak avalanche signal amplitude output by the multi-pixel photon counter with a fixed gain, and can be used with a filter module to filter and screen the signal, so as to facilitate the subsequent collection and analysis of the avalanche signal output by the multi-pixel photon counter;

[0026] 4) Signal processing: The signal amplified in step 3) communicates with the PC through the data acquisition card, extracts the signal output by the multi-pixel photon counter, analyzes the photon number distribution, analyzes and optimizes the error, and determines the real-time photon number. The error and optimization signals are returned to the FPGA, and the input voltage signal of the BOOST boost circuit module is adjusted to achieve stable photon number output and real-time photon number detection.

[0027] The BOOST boost circuit module is as follows: Figure 2 As shown, it includes a voltage reference chip, a digital-to-analog converter, a voltage follower and a professional power management chip which are electrically connected in sequence. The voltage reference chip provides a 2.5V reference DC voltage with an accuracy of ±0.5% to the digital-to-analog converter; the digital-to-analog converter is a high-precision digital-to-analog converter with a resolution of up to 16 bits, which is connected to the FPGA through SPI. The SCLK port of the digital-to-analog converter chip receives the synchronous clock signal sent by the FPGA to ensure the correct transmission and processing of data. The DIN port of the digital-to-analog converter changes the value of the output DC voltage by receiving the digital signal sent by the FPGA; the voltage follower receives the DC voltage output by the digital-to-analog converter, and performs signal buffering and voltage stabilization on the received signal, so as to provide a stable voltage value signal for the subsequent boost circuit; the professional power management chip is used to form a basic BOOST boost topology circuit with peripheral inductors, capacitors and MOS tubes, and provide a PWM wave with stable duty cycle and period for the MOS tube, and realizes the amplification of the DC voltage by changing the value of the input voltage. The output voltage range is 40-68V, and the output voltage adjustment of 0.01V can be realized, so as to provide a stable bias voltage for the normal operation of the multi-pixel photon counter.

[0028] The temperature control circuit module is as follows Figure 2As shown, it includes a voltage reference chip, an error amplifier, a digital-to-analog converter, and an LED indicator. The temperature control module includes two modes: manual setting and digital control setting. In the manual setting mode, the voltage reference chip generates a 4.096V reference voltage to act on the manually set resistor and the built-in thermistor of the multi-pixel photon counter. The two resistors are respectively divided by resistors with the same resistance value. The voltage value of the manually set resistor is used as the reference voltage value. The resistance value of the manually set resistor is selected to refer to the temperature-resistance characteristic curve of the multi-pixel photon counter. The manually set resistor and the built-in thermistor of the multi-pixel photon counter are respectively connected to the IN+ pin and IN- pin of the error amplifier to generate an error signal. The error signal is amplified by the error amplifier and sent to the TEC (semiconductor cooler) built into the multi-pixel photon counter. The TEC then performs cooling to change the device temperature. The local monitoring temperature changes accordingly to complete the cycle, and the cooling situation is observed in real time through the lighting of the LED light. The lighting of the LED light indicates that the cooling process is in progress, and the LED light is off to indicate that the cooling process is completed. In the digital control setting mode, the digital-to-analog converter chip is electrically connected to the FPGA and is electrically connected to the FPGA through SPI. The FPGA generates a signal and sends it to the digital signal receiving end of the digital-to-analog converter chip. The value of the output analog voltage is changed by changing the value of the digital signal input to the FPGA, and is connected to the IN- pin of the error amplifier. The working principle is the same as that of the manual setting mode. The TEC temperature is adjusted by controlling the closed loop to make the multi-pixel photon counter work at a constant temperature.

[0029] The signal amplification circuit module is as follows: Figure 2 As shown, it is electrically connected to a multi-pixel photon counter to stably amplify the weak avalanche signal output by the multi-pixel photon counter with a gain of 40 dB. At the same time, the filter module can be used to filter and screen the signal, so as to facilitate the subsequent collection and analysis of the avalanche signal output by the multi-pixel photon counter.

[0030] The signal processing module is as follows Figure 3As shown, it includes the acquisition of avalanche signals of multi-pixel photon counters, fitting analysis of signal photon number distribution state, error analysis and optimization of photon number distribution state, and real-time photon number distribution state judgment and output. Generally, the fitting of the photon number distribution state is performed by collecting and fitting data with a storage depth of 1M and a cycle number of 500 cycles for the multi-pixel photon counter, and calculating the photon number distribution state of the multi-pixel photon counter; the error analysis of the photon number distribution state is judged by calculating the proportion of the overlapping area of ​​adjacent photon state waveforms to the area of ​​each waveform. Usually the error threshold is set to 1%. When the actual error is higher than 1%, it may be because the number of incident photons is too large, resulting in an increase in the detection error. The error can be reduced by reducing the bias voltage. It may also be that the bias voltage is too low, resulting in too much dark noise, and the signal is submerged in the dark noise. The error can be reduced by increasing the bias voltage. The error optimization system communicates with the FPGA through timely feedback to change the digital signal input into the digital-to-analog converter in the BOOST boost circuit module, thereby changing the output voltage value to achieve correction of the output bias voltage of the professional power management chip so that the photon number distribution error can meet the error threshold. After calculating the number of photons N that meet the error condition, N is input into the real-time photon number distribution state judgment; the real-time photon number distribution state judgment is based on the number of photons below the error threshold determined in the error analysis, and the signal passing through the data acquisition card is input into the photon number judgment and output program, and the peak information of the pulse signal is first extracted, and then input into the N-way comparison circuit, which is composed of a comparator and an XOR gate. The reference voltage value of the comparator is selected as follows Figure 4 As shown, the reference voltage of the first comparator is the voltage value at the intersection of the 0 photon peak and the 1 photon peak, the reference voltage of the second comparator is the voltage value at the intersection of the 1 photon peak and the 2 photon peak, and so on, the reference voltage of the Nth comparator is the voltage value at the intersection of the N-1 photon peak and the N photon peak; after the signal passes through the comparator, if the amplitude is higher than or equal to the reference voltage, it will output "1", and if it is lower than the reference voltage, it will output "0". Finally, the output state of the comparator of each channel will be sent to the XOR gate circuit of the next stage, and the "XOR" operation will be performed by connecting with the next level channel. Only when one channel outputs "1" and the other outputs "0", the XOR gate circuit will have an output. Different channel outputs correspond to different numbers of photons, thereby realizing the judgment and output of different photon state information.

[0031] In addition, the system also includes a host computer, which is connected to the FPGA, and the operating voltage and operating temperature of the circuit can be set in the host computer. The host computer communicates with the FPGA through the serial port RS232 to control the BOOST boost circuit module and the temperature control circuit module of the multi-pixel photon counter.

[0032] The photon number resolvable detection system of the present invention has the ability to quickly judge and optimize errors, has real-time photon number resolution capability, a stable BOOST boost circuit output voltage, and a stable operation of the temperature control circuit module. It can enable the multi-pixel photon counter to operate in a stable temperature environment, is simple to operate, flexible to use, and can achieve low-error photon number resolvable detection.

[0033] The above-mentioned embodiments only express the specific implementation of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the invention patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be based on the attached claims.

Claims

1. A photon number resolvable detection system, characterized in that: The invention comprises an FPGA, a host computer, a BOOST boost circuit module, a temperature control circuit module, a signal amplifying circuit module and a signal processing module; the BOOST boost circuit module provides a DC voltage to satisfy the multi-pixel photon counter working in a Geiger mode under the control of the FPGA; an external laser signal sequentially outputs light pulses to the multi-pixel photon counter through an adjustable optical attenuator, a laser collimating lens and an aspheric focusing lens; the temperature control circuit module collects the internal temperature of the multi-pixel photon counter and controls the working temperature of the multi-pixel photon counter so that the multi-pixel photon counter works at a constant temperature; the signal amplifying circuit module is used to amplify the avalanche signal output by the multi-pixel photon counter; the output signal of the signal amplifying circuit module is sent to a data acquisition card through a low-pass filter, the data acquisition card communicates with the signal processing module through the PC terminal of the host computer, the signal processing module extracts the signal output by the multi-pixel photon counter, performs photon number distribution analysis, error analysis and optimization, and real-time photon number judgment and output, the FPGA receives the error analysis and optimization results of the signal processing module, and adjusts the signal to the BOOST boost circuit module.

2. The photon number resolvable detection system according to claim 1, characterized in that: The temperature control circuit module includes an error amplifier and an LED indicator light; the error amplifier amplifies the acquired error signal and sends it to a semiconductor refrigerator built into a multi-pixel photon counter, the semiconductor refrigerator performs cooling to change the device temperature, the local monitoring temperature is collected in real time to generate a new error signal again, forming a closed loop, and at the same time the error amplifier outputs a signal as a driving signal to the LED indicator light, and the cooling condition is displayed in real time through the light emission of the LED light.

3. The photon number resolvable detection system according to claim 1, characterized in that: The BOOST boost circuit module includes a voltage reference chip, a digital-to-analog converter, a voltage follower and a professional power management chip which are electrically connected in sequence. The voltage reference chip provides a 2.5V reference DC voltage with an accuracy of ±0.5% to the digital-to-analog converter; the digital-to-analog converter is connected to the FPGA via SPI, the SCLK port of the chip in the digital-to-analog converter receives the synchronous clock signal sent by the FPGA to ensure the correct transmission and processing of data, and the DIN port of the digital-to-analog converter changes the value of the output DC voltage by receiving the digital signal sent by the FPGA; the voltage follower receives the DC voltage output by the digital-to-analog converter, and performs signal buffering and voltage stabilization on the received signal, providing a stable voltage value signal for the subsequent boost circuit; the professional power management chip is used to form a basic BOOST boost topology circuit with peripheral inductors, capacitors, and MOS tubes, providing the MOS tube with a PWM wave with a stable duty cycle and period, and realizing the amplification of the DC voltage by changing the value of the input voltage, and providing a stable bias voltage for the normal operation of the multi-pixel photon counter.

4. The photon number resolvable detection system according to claim 1, characterized in that: The signal amplification circuit module is electrically connected to the multi-pixel photon counter to perform gain amplification on the weak avalanche signal output by the multi-pixel photon counter, and is used in conjunction with the filter module to filter and screen the signal, thereby facilitating the subsequent collection and analysis of the avalanche signal output by the multi-pixel photon counter.

5. The photon number resolvable detection system according to any one of claims 1 to 4, characterized in that: The signal processing module collects avalanche signals of a multi-pixel photon counter, and uses the collected signals to perform fitting analysis of the photon number distribution state, error analysis and optimization of the photon number distribution state, and real-time photon number distribution state judgment and output.

6. A photon number resolvable detection method, characterized in that: The photon number is collected by using the photon number resolvable detection system described in claim 5, and the detection includes fitting analysis of the photon number distribution state, error analysis and optimization of the photon number distribution state, and real-time photon number distribution state judgment; The fitting of the photon number distribution state: the photon number distribution state of the multi-pixel photon counter is calculated by collecting and fitting data with a storage depth of 1M and a cycle number of 500 cycles; Error analysis and optimization of photon number distribution state: The error threshold is set to 1% by calculating the proportion of the overlapping area of ​​adjacent photon state waveforms to the area of ​​their respective waveforms. When the actual error is higher than 1%, if the error is caused by too many incident photons, resulting in an increase in the detection error, the error is reduced by reducing the bias voltage. If the error is caused by too low a bias voltage, resulting in too much dark noise and the signal being submerged in the dark noise, the error is reduced by increasing the bias voltage. The error optimization system communicates with the FPGA through timely feedback to change the digital signal input into the digital-to-analog converter in the BOOST boost circuit module, thereby changing the output voltage value to achieve correction of the output bias voltage so that the photon number distribution error can meet the error threshold. After calculating the number of photons N that meet the error condition, N is input into the real-time photon number distribution state judgment; the real-time photon number distribution state judgment is based on the number of photons below the error threshold determined in the error analysis, and the signal passing through the data acquisition card is input into the photon number judgment and output program. First, the peak information of the pulse signal is extracted, and then input into the N-way comparison circuit. The comparison circuit consists of a comparator and an XOR gate. The reference voltage of the first comparator is the voltage value at the intersection of the 0 photon peak and the 1 photon peak, and the reference voltage of the second comparator is the voltage value at the intersection of the 1 photon peak and the 2 photon peak. voltage value, and so on, the reference voltage of the Nth comparator is the voltage value at the intersection of the N-1 photon peak and the N photon peak; after the signal passes through the comparator, if the amplitude is higher than or equal to the reference voltage, it will output "1", and if it is lower than the reference voltage, it will output "0". Finally, the output state of the comparator of each channel is sent to the XOR gate circuit of the next stage, and the "XOR" operation is performed through the connection with the next level channel. Only when one channel outputs "1" and the other outputs "0", the XOR gate circuit will have an output. Different channel outputs correspond to different numbers of photons, thereby realizing the judgment and output of different photon state information.

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