Chip testing and sorting method and system combined with application scene

Abstract

The invention provides a chip testing and sorting method and system in combination with an application scene, and relates to the technical field of chip testing and sorting, and the method comprises the steps: executing the correlation feature tracing of a simulation test index set, and determining a plurality of correlation feature sets; performing feature extraction and feature clustering on the plurality of sample chip information sets based on the plurality of associated feature sets, and constructing a plurality of feature matrix libraries; and performing actual detection on the target chip according to the actual test index set, performing simulation detection on the target chip through the plurality of feature matrix libraries, and outputting an actual detection result and a simulation detection result. According to the chip testing and sorting method and device, the technical problems that in an existing chip testing and sorting method, due to the fact that matched testing indexes cannot be set according to application scenes, and meanwhile in the chip testing process, due to the limitation of testing conditions, certain indexes cannot be directly tested, and the accuracy and reliability of chip testing results are poor can be solved; and the comprehensiveness, the accuracy and the reliability of a chip test result can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of chip testing and sorting, and in particular to a chip testing and sorting method and system combined with application scenarios. Background Art

[0002] With the continuous development of science and technology, the performance and reliability of chips as the core components of electronic devices are crucial to the entire electronic device. Therefore, accurate testing and sorting of chips has become a key link in ensuring product quality.

[0003] At present, the existing chip testing and sorting methods are unable to set matching test indicators according to the chip application scenarios. At the same time, during the chip testing process, due to the limitations of the test conditions, certain indicators cannot be directly tested, resulting in poor accuracy and reliability of the chip testing results, causing technical problems such as poor precision and accuracy of chip sorting. Summary of the invention

[0004] The purpose of this application is to provide a chip testing and sorting method and system combined with application scenarios, so as to solve the technical problems of the existing chip testing and sorting methods, which are unable to set matching test indicators according to the chip application scenarios, and at the same time, during the chip testing process, due to the limitations of the test conditions, certain indicators cannot be directly tested, resulting in poor accuracy and reliability of the chip testing results, and causing poor precision and accuracy of chip sorting.

[0005] In view of the above problems, the present application provides a chip testing and sorting method and system combined with application scenarios.

[0006] In a first aspect, the present application provides a chip test sorting method combined with an application scenario, which is implemented by a chip test sorting system combined with an application scenario, including: obtaining application scenario information of a target chip, based on chip attribute information, taking the application scenario information as a conditional constraint, taking expected screening indicators as quality constraints, performing homologous information retrieval through the industrial Internet, and determining a chip test indicator set; identifying the chip test indicator set, determining an actual test indicator set and a simulation test indicator set, wherein the simulation test indicator is an indicator type that the current test conditions cannot meet the test requirements; performing associated feature tracing of the simulation test indicator set, and determining multiple associated feature sets, wherein the associated feature identifier has a correlation degree; taking chip attribute information and satisfying simulation test indicators as constraints, retrieving and obtaining multiple sample chip information sets, performing feature extraction and feature clustering on the multiple sample chip information sets based on the multiple associated feature sets, and constructing multiple feature matrix libraries in combination with the correlation degree; performing actual detection on the target chip according to the actual test indicator set, performing simulation detection on the target chip through the multiple feature matrix libraries, and outputting actual detection results and simulation detection results; sorting the target chip based on the actual detection results and the simulation detection results.

[0007] In the second aspect, the present application also provides a chip test sorting system combined with application scenarios, which is used to execute a chip test sorting method combined with application scenarios as described in the first aspect, including: a chip test indicator set determination module, which is used to obtain application scenario information of the target chip, based on chip attribute information, with the application scenario information as a conditional constraint, and with the expected screening index as a quality constraint, and to perform homologous information retrieval through the industrial Internet to determine the chip test indicator set; a chip test indicator identification module, which is used to identify the chip test indicator set, determine the actual test indicator set and the simulation test indicator set, wherein the simulation test indicator is an indicator type that the current test conditions cannot meet the test requirements; an associated feature tracing module, which is used to execute the simulation The associated features of the test indicator set are traced to determine multiple associated feature sets, wherein the associated feature identifiers have a correlation degree; a feature matrix library construction module is used to retrieve and obtain multiple sample chip information sets based on chip attribute information and meeting simulation test indicators as constraints, perform feature extraction and feature clustering on the multiple sample chip information sets based on the multiple associated feature sets, and construct multiple feature matrix libraries based on the correlation degree; a chip detection module is used to perform actual detection on the target chip according to the actual test indicator set, simulate detection on the target chip through the multiple feature matrix libraries, and output actual detection results and simulated detection results; a chip sorting module is used to sort the target chip based on the actual detection results and the simulated detection results.

[0008] One or more technical solutions provided in this application have at least the following technical effects or advantages: By using chip attribute information as component constraints, application scenario information as condition constraints, and expected screening indicators as quality constraints, and searching for homologous information through the industrial Internet to determine the chip test indicator set, it is possible to improve the adaptability of chip test indicators to chip application scenarios and improve the accuracy of test indicator settings; then identify the chip test indicator set, determine the actual test indicator set and the simulation test indicator set, where the simulation test indicator is an indicator type that the current test conditions cannot meet the test requirements; then trace the associated features of the simulation test indicator set to determine multiple associated feature sets, where the associated feature identifier has a correlation degree, and the correlation degree represents the degree of correlation between the associated feature and the simulation test indicator; further use the chip attribute information and the satisfaction of the simulation test indicators as constraints to retrieve and obtain multiple A sample chip information set is prepared, and then feature extraction and feature clustering are performed on the multiple sample chip information sets based on multiple associated feature sets, and multiple feature matrix libraries are constructed in combination with the correlation degree; next, the target chip is actually tested according to the actual test indicator set to obtain the actual test result; the target chip is simulated tested through multiple feature matrix libraries to obtain the simulated test result; finally, the target chip is sorted based on the actual test result and the simulated test result; the adaptability of the test indicator to the chip application scenario is improved, and the accuracy of the test indicator setting is improved. Through intelligent analysis means, the goal of simulating the test of indicators with limitations can be achieved, and the comprehensiveness, accuracy and reliability of the chip test results can be improved, thereby achieving the technical effect of improving the chip sorting precision and accuracy.

[0009] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented according to the contents of the specification, and in order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are specifically cited below. It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easy to understand through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the present application or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only exemplary, and for ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0011] Figure 1 A schematic diagram of a chip testing and sorting method combined with an application scenario for this application; Figure 2 A schematic diagram of a process for determining a chip test index set in a chip test sorting method combined with an application scenario of the present application; Figure 3 This is a structural schematic diagram of a chip testing and sorting system combined with an application scenario in the present application.

[0012] Description of reference numerals: Chip test indicator set determination module 11, chip test indicator identification module 12, associated feature tracing module 13, feature matrix library construction module 14, chip detection module 15, chip sorting module 16. DETAILED DESCRIPTION

[0013] This application provides a chip test sorting method and system combined with application scenarios, which solves the existing chip test sorting method. Since it is impossible to set matching test indicators according to chip application scenarios, and during the chip testing process, due to the limitations of test conditions, some indicators cannot be directly tested, resulting in poor accuracy and reliability of chip test results, resulting in poor precision and accuracy of chip sorting. The adaptability of test indicators to chip application scenarios can be improved, and the accuracy of test indicator settings can be improved. Through intelligent analysis methods, the goal of simulating and detecting indicators with limitations can be achieved, and the comprehensiveness, accuracy and reliability of chip test results can be improved, thereby achieving the technical effect of improving chip sorting precision and accuracy.

[0014] Below, the technical solutions in the present application will be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments of the present application. It should be understood that the present application is not limited to the example embodiments described herein. Based on the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application. It should also be noted that, for the convenience of description, only the parts related to the present application are shown in the accompanying drawings, rather than all of them.

[0015] For example, please refer to the attached Figure 1 The present application provides a chip testing and sorting method combined with an application scenario, which is applied to a chip testing and sorting system combined with an application scenario, and specifically includes the following steps: Step 1: Obtain the application scenario information of the target chip, based on the chip attribute information, use the application scenario information as a conditional constraint, use the expected screening indicators as quality constraints, perform homologous information retrieval through the Industrial Internet, and determine the chip test indicator set.

[0016] Specifically, the application scenario information of the target chip is obtained, where the application scenario information includes data such as application equipment, workload, and environmental parameters, which can be set according to actual conditions. The application equipment includes parameters such as device type and device field, such as electronic products, industrial fields, medical fields, etc. Electronic product types include smart phones, tablets, etc.; workloads include data processing, signal processing, control logic, etc.; environmental parameters refer to the working environment faced by the chip, including temperature, humidity, vibration, electromagnetic interference, etc.

[0017] Obtain chip attribute information and expected screening indicators, where chip attribute information includes chip type, chip specifications, performance parameters, electrical characteristics and other data, and expected screening indicators include service life, data processing capabilities and performance stability and other indicators; then use chip attribute information as component constraints, the application scenario information as conditional constraints, and meet the expected screening indicators as quality constraints, and perform homologous information retrieval through the Industrial Internet, that is, use the database and algorithm of the Industrial Internet to screen out sample chip test indicator data sets that meet chip attribute information, application scenario information and expected screening indicators, and determine the chip test indicator set based on the sample chip test indicator data set analysis. By setting constraints, performing homologous information retrieval based on the Industrial Internet, and determining the chip test indicator set, the adaptability of chip test indicators to chip application scenarios can be improved, thereby improving the accuracy of test indicator settings.

[0018] Step 2: Identify the chip test index set, determine the actual test index set and the simulation test index set, wherein the simulation test index is an index type that the current test conditions cannot meet the test requirements.

[0019] Specifically, the chip test indicator set is then identified, and the chip test indicators are divided into actual test indicators and simulated test indicators. The actual test indicator set is an indicator that can be directly measured based on the current test conditions, while the simulated test indicator set refers to those indicators that cannot be directly measured under the current test conditions. For example, the actual test indicators include electrical indicators, performance indicators, etc.; the simulated test indicators include vibration tests, temperature cycle tests, humidity tests, corrosive gas tests, impact tests, etc.; determine the actual test indicator set and the simulated test indicator set.

[0020] Step three: perform correlation feature tracing of the simulation test indicator set to determine a plurality of correlation feature sets, wherein the correlation feature identifiers have correlation degrees.

[0021] Specifically, first, a chip feature library is constructed, and the chip feature library contains multiple chip features, such as semiconductor materials, conductive materials, insulating materials, packaging materials, circuit layouts, circuit channels, packaging features, etc., which can be set according to actual conditions; then, based on the chip feature library, the simulation test indicator set is traced for correlation features, that is, the correlation between the chip features and the simulation test indicators is evaluated, and it is determined which features have the greatest impact on the simulation test indicators. The evaluation can be performed through methods such as correlation coefficient, regression coefficient, cluster analysis, etc., and chip features with a larger degree of correlation are selected as the correlation features of the simulation test indicators, and multiple correlation feature sets are determined, wherein the correlation feature identifier has a degree of correlation, and the degree of correlation represents the degree of correlation between the correlation feature and the simulation test indicator. The larger the degree of correlation, the higher the degree of correlation.

[0022] Step 4: Taking chip attribute information and satisfying simulation test indicators as constraints, retrieve and obtain multiple sample chip information sets, perform feature extraction and feature clustering on the multiple sample chip information sets based on the multiple associated feature sets, and construct multiple feature matrix libraries based on the association degrees.

[0023] Specifically, with chip attribute information and meeting simulation test indicators as retrieval constraints, homologous information retrieval is performed through the industrial Internet to obtain multiple sample chip information sets; then, feature extraction is performed on the multiple sample chip information sets according to the multiple associated feature sets to obtain multiple associated data sets; further, feature clustering is performed on the multiple associated data sets, that is, representative features in the associated data are selected to obtain multiple associated representative feature sets; then, multiple feature matrix sets are constructed based on the multiple associated representative feature sets, where each associated representative feature corresponds to a feature matrix; on the other hand, weights are configured according to the degree of association, where the greater the degree of association, the greater the corresponding weight, and the feature matrix sets are weighted according to the weights to generate multiple feature matrix libraries. By constructing multiple feature matrix libraries, a basis is provided for subsequent simulation detection of target chips, and at the same time, the technical goal of simulation detection of indicators with limitations can be achieved.

[0024] Step 5: Perform actual detection on the target chip according to the actual test index set, perform simulated detection on the target chip through the multiple feature matrix libraries, and output actual detection results and simulated detection results.

[0025] Specifically, the target chip is actually tested according to the actual test indicator set, and the actual test results are output. For example, first, suitable test equipment is prepared, such as automatic test equipment (ATE), probe tester, etc., to ensure that the test equipment is compatible with the target chip and can measure the required performance parameters; then the target chip is loaded onto the test equipment, the test program is executed, and the target chip is actually tested; then test data is collected, including performance parameters, electrical characteristics, etc., and the collected data is processed and analyzed using data analysis tools; finally, the actual test results are output based on the test data.

[0026] On the other hand, the target chip is simulated and tested through the multiple feature matrix libraries. First, data is collected for the target chip according to the multiple associated feature sets to obtain multiple real-time feature sets; then, the multiple real-time feature sets are input into the multiple feature matrix libraries for similarity traversal comparison, and multiple comprehensive similarities are output, wherein the comprehensive similarities correspond to the simulation test indicators one by one; if the comprehensive similarity is greater than or equal to a predetermined similarity threshold, indicating that the feature similarity between the simulation test result and the qualified chip product is high, then the simulation test result is passed; otherwise, if the comprehensive similarity is less than the predetermined similarity threshold, indicating that the feature similarity between the simulation test result and the qualified chip product is low, then the simulation test result is failed; and the simulation test result is output.

[0027] Through the above steps, the technical goal of simulating the detection of indicators with limitations can be achieved. At the same time, this method is easy to operate and can improve the convenience and practicality of simulation detection. By obtaining the final chip detection results based on actual detection results and simulation detection results, the comprehensiveness, accuracy and reliability of the chip test results can be improved.

[0028] Step six: sorting the target chips based on the actual detection results and the simulated detection results.

[0029] Specifically, the performance of the target chip is evaluated based on the actual test results and the simulated test results, including functions, performance, reliability, stability and other aspects; finally, according to the performance evaluation results and based on the established sorting criteria, the target chip is sorted.

[0030] The chip test sorting method combined with application scenarios is applied to a chip test sorting system combined with application scenarios, which can solve the existing chip test sorting method. Since it is impossible to set matching test indicators according to chip application scenarios, and during the chip testing process, due to the limitations of test conditions, some indicators cannot be directly tested, resulting in poor accuracy and reliability of chip test results, resulting in poor precision and accuracy of chip sorting. Technical problems. By using chip attribute information as component constraints, application scenario information as conditional constraints, and expected screening indicators as quality constraints, homologous information retrieval is performed through the industrial Internet to determine the chip test indicator set, which can improve the adaptability of chip test indicators to chip application scenarios and improve the accuracy of test indicator settings; then identify the chip test indicator set, determine the actual test indicator set and the simulation test indicator set, wherein the simulation test indicator is an indicator type that the current test conditions cannot meet the test requirements; then trace the associated features of the simulation test indicator set to determine multiple associated feature sets, wherein the associated feature identifier has a correlation degree, and the correlation degree represents the degree of correlation between the associated feature and the simulation test indicator; further, using chip attribute information and meeting simulation test indicators as constraints, retrieve and obtain multiple A sample chip information set is prepared, and then feature extraction and feature clustering are performed on the multiple sample chip information sets based on multiple associated feature sets, and multiple feature matrix libraries are constructed in combination with the correlation degree; next, the target chip is actually tested according to the actual test indicator set to obtain the actual test result; the target chip is simulated tested through multiple feature matrix libraries to obtain the simulated test result; finally, the target chip is sorted based on the actual test result and the simulated test result; the adaptability of the test indicator to the chip application scenario is improved, and the accuracy of the test indicator setting is improved. Through intelligent analysis means, the goal of simulating the test of indicators with limitations can be achieved, and the comprehensiveness, accuracy and reliability of the chip test results can be improved, thereby achieving the technical effect of improving the chip sorting precision and accuracy.

[0031] Further, determine the chip test indicator set, as shown in the attached Figure 2 As shown, step one of this application includes: The application scenario information includes at least application equipment, workload and environmental parameters, and the expected screening indicators include at least service life, data processing capability and performance stability; taking chip attribute information as component constraints, and application equipment, workload and environmental parameters as conditional constraints, and satisfying service life, data processing capability and performance stability as quality constraints, homologous information retrieval is performed through the industrial Internet to obtain multiple sample chip test indicator sets; randomly selecting a first sample chip test indicator set, calculating the mean of the first sample indicators, extracting indicators greater than the mean of the first sample indicators to construct a first standard test indicator set, and selecting the mode of the first standard test indicator set as the first chip test indicator, and adding it to the chip test indicator set.

[0032] Specifically, the application scenario information includes at least application equipment, workload and environmental parameters. Application equipment includes parameters such as equipment type and equipment field, such as electronic products, industrial fields, medical fields, etc. Electronic product types include smart phones, tablet computers, etc. Workload includes data processing, signal processing, control logic, etc. Environmental parameters refer to the working environment faced by the chip, including temperature, humidity, vibration, electromagnetic interference, etc. The expected screening indicators include at least service life, data processing capability and performance stability, and the expected screening indicators can also be added according to actual conditions.

[0033] Then, using chip attribute information as component constraints, application equipment, workload and environmental parameters as conditional constraints, and meeting service life, data processing capability and performance stability as quality constraints, homologous information retrieval is performed through the Industrial Internet. That is, the database and algorithm of the Industrial Internet are used to screen out sample chip test indicator data sets that meet the constraints, and multiple sample chip test indicator sets are obtained.

[0034] Then, a first sample chip test indicator set is randomly selected from the multiple sample chip test indicator sets, wherein the first sample chip test indicator set is any one of the multiple sample chip test indicator sets; then, the first sample chip test indicator set is mean calculated to obtain the first sample indicator mean; further indicators greater than the first sample indicator mean are extracted to construct a first standard test indicator set, and the mode of the first standard test indicator set is selected and set as the first chip test indicator. The above steps can improve the accuracy and reliability of the first chip test indicator setting; finally, the same method is used to obtain multiple chip test indicators in turn to construct a chip test indicator set.

[0035] Further, multiple associated feature sets are determined, and step three of this application includes: Construct a chip feature library, wherein the chip features include at least semiconductor materials, conductive materials, insulating materials, packaging materials, circuit layouts, circuit channels, packaging features, welding features, lead frames, physical structures, layer stacking features, and heat dissipation configurations; randomly select a first simulation test indicator from the simulation test indicator set, and perform correlation analysis on the first simulation test indicator and multiple chip features in the chip feature library to determine multiple correlation degrees; select a chip feature with a correlation degree greater than a predetermined correlation threshold value as a first correlation feature, construct a first correlation feature set, and add it to the multiple correlation feature sets.

[0036] Specifically, first, a chip feature library is constructed, which contains multiple chip features, wherein the chip features include at least semiconductor materials, conductive materials, insulating materials, packaging materials, circuit layouts, circuit channels, packaging features, welding features, lead frames, physical structures, layer stacking features and heat dissipation configurations.

[0037] Then, any simulation test indicator is randomly selected from the simulation test indicator set and set as the first simulation test indicator. Then, the first simulation test indicator and multiple chip features in the chip feature library are respectively subjected to correlation analysis. Appropriate correlation analysis methods can be selected according to actual conditions, such as Pearson correlation coefficient, Spearman rank correlation coefficient, mutual information, etc. These methods can help quantify the degree of correlation between features and simulation test indicators. Then, the selected correlation analysis method is used to calculate the first simulation test indicator and each chip feature, and the correlation between each feature and the simulation test indicator is calculated. Among them, features with higher correlation have a significant impact on the simulation test indicator, and multiple correlations are obtained.

[0038] First, according to actual needs and application scenarios, a predetermined correlation threshold is set; then, chip features with a correlation degree greater than the predetermined correlation threshold are selected as first correlation features, and multiple first correlation features are obtained to construct a first correlation feature set; finally, the same method is used to obtain multiple correlation feature sets corresponding to the simulation test indicator set.

[0039] Further, multiple feature matrix libraries are constructed in combination with the correlation degree. Step 4 of this application includes: A first associated feature set is randomly selected from the multiple associated feature sets, and a first sample chip information set is obtained, wherein the first associated feature set and the first sample chip information set have a corresponding relationship; feature extraction is performed on the first sample chip information set according to the first associated feature set to obtain multiple sample chip feature sets; feature clustering is performed on the multiple sample chip feature sets to obtain multiple standard chip feature sets; a first feature space is constructed according to the multiple standard chip feature sets, and multiple feature spaces of multiple associated feature sets are obtained in turn, and multiple feature matrix libraries are generated according to the multiple feature spaces and the correlation degree.

[0040] Specifically, any one of the multiple associated feature sets is randomly selected as the first associated feature set, and a first sample chip information set is obtained, wherein the first associated feature set and the first sample chip information set have a corresponding relationship; then, feature extraction is performed on the first sample chip information set according to the first associated feature set to obtain multiple sample chip feature sets; further, feature clustering is performed on the multiple sample chip feature sets, that is, representative associated features are selected as standard chip features to obtain multiple standard chip feature sets; finally, a first feature space is constructed according to the multiple standard chip feature sets; then, the same method as that for constructing the first feature space is used to sequentially obtain multiple feature spaces of multiple associated feature sets, and multiple feature matrix libraries are generated according to the multiple feature spaces and the correlation degree.

[0041] Further, to obtain multiple standard chip feature sets, the present application also includes the following steps: A first sample chip feature set is selected from the multiple sample chip feature sets; similar features are clustered for the first sample chip feature set, and the frequency of similar features is counted, and similar features with a feature frequency greater than a predetermined frequency threshold are selected as first standard chip features, and a first standard chip feature set is constructed and added to the multiple standard chip feature sets.

[0042] Specifically, a first sample chip feature set is randomly selected from the plurality of sample chip feature sets, and then the first sample chip feature set is clustered with similar features, that is, the features of the same data are clustered into one category, and the frequency of similar features in each clustering result is counted, wherein the frequency of similar features is positively correlated with the number of features in the clustering result, and the more the number of features, the greater the feature frequency. Then, similar features with a feature frequency greater than a predetermined frequency threshold are selected and set as first standard chip features, wherein the first standard chip features are representative feature data, and multiple first standard chip features are obtained to construct a first standard chip feature set; finally, multiple standard chip feature sets are obtained using the same method.

[0043] Further, multiple feature matrix libraries are generated according to the multiple feature spaces and the correlation degrees, and the present application further includes the following steps: Select the first feature space of the first associated feature set, and obtain multiple first standard chip feature sets of the first feature space, and construct multiple first standard feature matrix sets based on the multiple first standard chip feature sets; obtain multiple correlation degrees of multiple associated features in the first feature set, set weight ratios according to the multiple correlation degrees, assign values ​​to the multiple first standard feature matrix sets based on the weight ratios, generate a first feature matrix library, and add it to the multiple feature matrix libraries.

[0044] Specifically, firstly, the first feature space of the first associated feature set is selected, and multiple first standard chip feature sets of the first feature space are obtained; then, multiple first standard feature matrix sets are constructed based on the multiple first standard chip feature sets, wherein each feature matrix corresponds to a first standard chip feature set, and contains the features in the feature set and the corresponding sample data. Further, multiple correlations of multiple associated features in the first feature set are obtained, and weight ratios are set according to the multiple correlations, wherein the greater the correlation of the indicator, the greater the corresponding weight, and the weight configuration can be performed based on the existing coefficient of variation method. Finally, multiple first standard feature matrix sets are assigned values ​​based on the weight ratio to generate a first feature matrix library; multiple feature matrix libraries are constructed using the same method as that of constructing the first feature matrix library.

[0045] Further, the target chip is simulated and tested by using the plurality of feature matrix libraries, and step six of the present application includes: Based on the multiple associated feature sets, data is collected on the target chip to obtain multiple real-time feature sets; a first real-time feature set is randomly selected, and the first real-time feature set is input into the first feature matrix library for similarity traversal comparison, and a first comprehensive similarity is calculated based on a similarity comparison function, wherein the first real-time feature set and the first feature matrix library have a corresponding relationship; the first comprehensive similarity is judged based on a predetermined similarity threshold, and a first simulation detection result is output, and the first simulation detection result is added to the simulation detection result, wherein if the first comprehensive similarity is greater than or equal to the predetermined similarity threshold, the first simulation detection result is passed, otherwise it is not passed; the expression of the similarity comparison function is: ;in, is the comprehensive similarity, is the number of standard feature matrix sets in the feature matrix library, is the weight of the nth standard feature matrix set, It is the mean similarity of the comparison of multiple standard feature matrices in the nth standard feature matrix set.

[0046] Specifically, first, data is collected on the target chip based on the multiple associated feature sets to obtain multiple real-time feature sets; then, a first real-time feature set is randomly selected from the multiple real-time feature sets, and then the first real-time feature set is input into a first feature matrix library for similarity traversal comparison, wherein the first real-time feature set and the first feature matrix library have a corresponding relationship, and commonly used similarity comparison algorithms include cosine similarity comparison, Euclidean distance, Manhattan distance, etc., and an adapted similarity comparison algorithm can be selected according to actual conditions; then, the similarity comparison result is calculated based on the similarity comparison function to obtain a first comprehensive similarity.

[0047] Then, the first comprehensive similarity is judged based on a predetermined similarity threshold. If the first comprehensive similarity is greater than or equal to the predetermined similarity threshold, it indicates that the feature similarity between the simulation test result and the qualified chip product is high, and the simulation test result is passed; otherwise, if the comprehensive similarity is less than the predetermined similarity threshold, it indicates that the feature similarity between the simulation test result and the qualified chip product is low, and the simulation test result is failed; the first simulation test result is obtained, and finally multiple simulation test results of multiple real-time feature sets are obtained to obtain the simulation test result.

[0048] In the similarity comparison function, is the comprehensive similarity, is the number of standard feature matrix sets in the feature matrix library, is the weight of the nth standard feature matrix set, It is the mean similarity of the comparison of multiple standard feature matrices in the nth standard feature matrix set.

[0049] In summary, the chip testing and sorting method combined with the application scenario provided by the present application has the following technical effects: By using chip attribute information as component constraints, application scenario information as condition constraints, and expected screening indicators as quality constraints, and searching for homologous information through the industrial Internet to determine the chip test indicator set, it is possible to improve the adaptability of chip test indicators to chip application scenarios and improve the accuracy of test indicator settings; then identify the chip test indicator set, determine the actual test indicator set and the simulation test indicator set, where the simulation test indicator is an indicator type that the current test conditions cannot meet the test requirements; then trace the associated features of the simulation test indicator set to determine multiple associated feature sets, where the associated feature identifier has a correlation degree, and the correlation degree represents the degree of correlation between the associated feature and the simulation test indicator; further use the chip attribute information and the satisfaction of the simulation test indicators as constraints to retrieve and obtain multiple A sample chip information set is prepared, and then feature extraction and feature clustering are performed on the multiple sample chip information sets based on multiple associated feature sets, and multiple feature matrix libraries are constructed in combination with the correlation degree; next, the target chip is actually tested according to the actual test indicator set to obtain the actual test result; the target chip is simulated tested through multiple feature matrix libraries to obtain the simulated test result; finally, the target chip is sorted based on the actual test result and the simulated test result; the adaptability of the test indicator to the chip application scenario is improved, and the accuracy of the test indicator setting is improved. Through intelligent analysis means, the goal of simulating the test of indicators with limitations can be achieved, and the comprehensiveness, accuracy and reliability of the chip test results can be improved, thereby achieving the technical effect of improving the chip sorting precision and accuracy.

[0050] Embodiment 2: Based on the chip test sorting method combined with the application scenario in the above embodiment, the present application also provides a chip test sorting system combined with the application scenario, please refer to the attached Figure 3 ,include: The chip test indicator set determination module 11 is used to obtain the application scenario information of the target chip, based on the chip attribute information, with the application scenario information as a conditional constraint, and with the expected screening index as a quality constraint, to perform homologous information retrieval through the industrial Internet to determine the chip test indicator set.

[0051] The chip test index identification module 12 is used to identify the chip test index set, determine the actual test index set and the simulation test index set, wherein the simulation test index is an index type that the current test condition cannot meet the test requirements.

[0052] The associated feature tracing module 13 is used to perform associated feature tracing of the simulation test indicator set and determine multiple associated feature sets, wherein the associated feature identifiers have a degree of association.

[0053] The feature matrix library construction module 14 is used to retrieve and obtain multiple sample chip information sets based on chip attribute information and meeting simulation test indicators, perform feature extraction and feature clustering on the multiple sample chip information sets based on the multiple associated feature sets, and construct multiple feature matrix libraries based on the association degree.

[0054] The chip detection module 15 is used to perform actual detection on the target chip according to the actual test index set, perform simulated detection on the target chip through the multiple feature matrix libraries, and output actual detection results and simulated detection results.

[0055] The chip sorting module 16 is used to sort the target chips based on the actual detection result and the simulated detection result.

[0056] Furthermore, the chip testing and sorting system combined with the application scenario is also used for: The application scenario information includes at least application equipment, workload and environmental parameters, and the expected screening indicators include at least service life, data processing capability and performance stability; taking chip attribute information as component constraints, and application equipment, workload and environmental parameters as conditional constraints, and satisfying service life, data processing capability and performance stability as quality constraints, homologous information retrieval is performed through the industrial Internet to obtain multiple sample chip test indicator sets; randomly selecting a first sample chip test indicator set, calculating the mean of the first sample indicators, extracting indicators greater than the mean of the first sample indicators to construct a first standard test indicator set, and selecting the mode of the first standard test indicator set as the first chip test indicator, and adding it to the chip test indicator set.

[0057] Furthermore, the chip testing and sorting system combined with the application scenario is also used for: Construct a chip feature library, wherein the chip features include at least semiconductor materials, conductive materials, insulating materials, packaging materials, circuit layouts, circuit channels, packaging features, welding features, lead frames, physical structures, layer stacking features, and heat dissipation configurations; randomly select a first simulation test indicator from the simulation test indicator set, and perform correlation analysis on the first simulation test indicator and multiple chip features in the chip feature library to determine multiple correlation degrees; select a chip feature with a correlation degree greater than a predetermined correlation threshold value as a first correlation feature, construct a first correlation feature set, and add it to the multiple correlation feature sets.

[0058] Furthermore, the chip testing and sorting system combined with the application scenario is also used for: A first associated feature set is randomly selected from the multiple associated feature sets, and a first sample chip information set is obtained, wherein the first associated feature set and the first sample chip information set have a corresponding relationship; feature extraction is performed on the first sample chip information set according to the first associated feature set to obtain multiple sample chip feature sets; feature clustering is performed on the multiple sample chip feature sets to obtain multiple standard chip feature sets; a first feature space is constructed according to the multiple standard chip feature sets, and multiple feature spaces of multiple associated feature sets are obtained in turn, and multiple feature matrix libraries are generated according to the multiple feature spaces and the correlation degree.

[0059] Furthermore, the chip testing and sorting system combined with the application scenario is also used for: A first sample chip feature set is selected from the multiple sample chip feature sets; similar features are clustered for the first sample chip feature set, and the frequency of similar features is counted, and similar features with a feature frequency greater than a predetermined frequency threshold are selected as first standard chip features, and a first standard chip feature set is constructed and added to the multiple standard chip feature sets.

[0060] Furthermore, the chip testing and sorting system combined with the application scenario is also used for: Select the first feature space of the first associated feature set, and obtain multiple first standard chip feature sets of the first feature space, and construct multiple first standard feature matrix sets based on the multiple first standard chip feature sets; obtain multiple correlation degrees of multiple associated features in the first feature set, set weight ratios according to the multiple correlation degrees, assign values ​​to the multiple first standard feature matrix sets based on the weight ratios, generate a first feature matrix library, and add it to the multiple feature matrix libraries.

[0061] Furthermore, the chip testing and sorting system combined with the application scenario is also used for: Based on the multiple associated feature sets, data is collected on the target chip to obtain multiple real-time feature sets; a first real-time feature set is randomly selected, and the first real-time feature set is input into the first feature matrix library for similarity traversal comparison, and a first comprehensive similarity is calculated based on a similarity comparison function, wherein the first real-time feature set and the first feature matrix library have a corresponding relationship; the first comprehensive similarity is judged based on a predetermined similarity threshold, and a first simulation detection result is output, and the first simulation detection result is added to the simulation detection result, wherein if the first comprehensive similarity is greater than or equal to the predetermined similarity threshold, the first simulation detection result is passed, otherwise it is not passed; the expression of the similarity comparison function is: ;in, is the comprehensive similarity, is the number of standard feature matrix sets in the feature matrix library, is the weight of the nth standard feature matrix set, It is the mean similarity of the comparison of multiple standard feature matrices in the nth standard feature matrix set.

[0062] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The chip test sorting method combined with an application scenario and the specific examples in the aforementioned embodiment 1 are also applicable to a chip test sorting system combined with an application scenario in this embodiment. Through the aforementioned detailed description of a chip test sorting method combined with an application scenario, those skilled in the art can clearly know a chip test sorting system combined with an application scenario in this embodiment, so for the sake of brevity of the specification, it will not be described in detail here. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method section description.

[0063] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

[0064] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application belong to the scope of the present application and its equivalent technology, the present application is also intended to include these modifications and variations.

Claims

1. A chip testing and sorting method combined with application scenarios, characterized in that: include: Obtain application scenario information of the target chip, and based on the chip attribute information, use the application scenario information as a conditional constraint, use the expected screening index as a quality constraint, perform homologous information retrieval through the industrial Internet, and determine the chip test index set; Identify the chip test index set, determine the actual test index set and the simulation test index set, wherein the simulation test index is an index type that the current test conditions cannot meet the test requirements; Execute the correlation feature tracing of the simulation test indicator set to determine a plurality of correlation feature sets, wherein the correlation feature identifiers have correlation degrees; Taking chip attribute information and meeting simulation test indicators as constraints, multiple sample chip information sets are retrieved and obtained, and feature extraction and feature clustering are performed on the multiple sample chip information sets based on the multiple associated feature sets, and multiple feature matrix libraries are constructed in combination with the association degrees; Performing actual testing on the target chip according to the actual test index set, performing simulated testing on the target chip through the multiple feature matrix libraries, and outputting actual testing results and simulated testing results; The target chips are sorted based on the actual detection results and the simulated detection results.

2. The chip testing and sorting method combined with the application scenario according to claim 1 is characterized in that: Determine the chip test indicator set, including: The application scenario information includes at least application equipment, workload and environmental parameters, and the expected screening indicators include at least service life, data processing capability and performance stability; Taking chip attribute information as component constraints, application equipment, workload and environmental parameters as conditional constraints, and satisfying service life, data processing capacity and performance stability as quality constraints, homologous information retrieval is performed through the industrial Internet to obtain multiple sample chip test indicator sets; A first sample chip test indicator set is randomly selected, the first sample indicator mean is calculated, indicators greater than the first sample indicator mean are extracted to construct a first standard test indicator set, and the mode of the first standard test indicator set is selected as the first chip test indicator, which is added to the chip test indicator set.

3. The chip testing and sorting method combined with the application scenario according to claim 1 is characterized in that: Identify multiple sets of associated features, including: Constructing a chip feature library, wherein the chip features at least include semiconductor materials, conductive materials, insulating materials, packaging materials, circuit layouts, circuit channels, packaging features, welding features, lead frames, physical structures, layer stacking features, and heat dissipation configurations; Randomly selecting a first simulation test indicator from the simulation test indicator set, performing correlation analysis on the first simulation test indicator and a plurality of chip features in the chip feature library, and determining a plurality of correlation degrees; A chip feature with a correlation degree greater than a predetermined correlation threshold is selected and set as a first correlation feature, a first correlation feature set is constructed, and the first correlation feature set is added to the plurality of correlation feature sets.

4. The chip testing and sorting method combined with the application scenario according to claim 1 is characterized in that: Combined with the correlation degree, multiple feature matrix libraries are constructed, including: Randomly selecting a first associated feature set from the multiple associated feature sets, and obtaining a first sample chip information set, wherein the first associated feature set and the first sample chip information set have a corresponding relationship; Extracting features from the first sample chip information set according to the first associated feature set to obtain multiple sample chip feature sets; Performing feature clustering on the plurality of sample chip feature sets to obtain a plurality of standard chip feature sets; A first feature space is constructed according to the plurality of standard chip feature sets, a plurality of feature spaces of a plurality of associated feature sets are obtained in sequence, and a plurality of feature matrix libraries are generated according to the plurality of feature spaces and the association degrees.

5. The chip testing and sorting method combined with the application scenario according to claim 4 is characterized in that: Get multiple standard chip feature sets, including: Selecting a first sample chip feature set from the plurality of sample chip feature sets; The first sample chip feature set is clustered with similar features, and the frequency of similar features is counted, and similar features with feature frequencies greater than a predetermined frequency threshold are selected as first standard chip features, and a first standard chip feature set is constructed and added to the multiple standard chip feature sets.

6. The chip testing and sorting method combined with the application scenario according to claim 4 is characterized in that: Generating a plurality of feature matrix libraries according to the plurality of feature spaces and the association degrees includes: Selecting a first feature space of a first associated feature set, and obtaining a plurality of first standard chip feature sets of the first feature space, and constructing a plurality of first standard feature matrix sets based on the plurality of first standard chip feature sets; Acquire multiple correlation degrees of multiple associated features in the first feature set, set weight ratios according to the multiple correlation degrees, assign values ​​to multiple first standard feature matrix sets based on the weight ratios, generate a first feature matrix library, and add it to the multiple feature matrix libraries.

7. The chip testing and sorting method combined with the application scenario according to claim 1 is characterized in that: Performing simulation detection on the target chip through the multiple feature matrix libraries includes: Based on the multiple associated feature sets, data is collected on the target chip to obtain multiple real-time feature sets; Randomly selecting a first real-time feature set, inputting the first real-time feature set into a first feature matrix library for similarity traversal comparison, and calculating a first comprehensive similarity based on a similarity comparison function, wherein the first real-time feature set and the first feature matrix library have a corresponding relationship; The first comprehensive similarity is judged based on a predetermined similarity threshold, a first simulation detection result is output, and the first simulation detection result is added to the simulation detection result, wherein if the first comprehensive similarity is greater than or equal to the predetermined similarity threshold, the first simulation detection result is passed, otherwise it is failed; The expression of the similarity comparison function is: ； in, is the comprehensive similarity, is the number of standard feature matrix sets in the feature matrix library, is the weight of the nth standard feature matrix set, It is the mean similarity of the comparison of multiple standard feature matrices in the nth standard feature matrix set.

8. A chip testing and sorting system combined with application scenarios, characterized in that: The steps for implementing the chip testing and sorting method combined with the application scenario as described in any one of claims 1 to 7 include: A chip test index set determination module is used to obtain application scenario information of a target chip, and based on chip attribute information, use the application scenario information as a conditional constraint, use expected screening indicators as quality constraints, perform homologous information retrieval through the industrial Internet, and determine a chip test index set; A chip test index identification module is used to identify the chip test index set, determine the actual test index set and the simulation test index set, wherein the simulation test index is an index type that the current test conditions cannot meet the test requirements; A correlation feature tracing module is used to perform correlation feature tracing of the simulation test indicator set and determine a plurality of correlation feature sets, wherein the correlation feature identifier has a correlation degree; A feature matrix library construction module is used to retrieve and obtain multiple sample chip information sets based on chip attribute information and meeting simulation test indicators as constraints, perform feature extraction and feature clustering on the multiple sample chip information sets based on the multiple associated feature sets, and construct multiple feature matrix libraries in combination with the association degree; A chip detection module, used to perform actual detection on the target chip according to the actual test index set, perform simulated detection on the target chip through the multiple feature matrix libraries, and output actual detection results and simulated detection results; The chip sorting module is used to sort the target chips based on the actual detection result and the simulated detection result.

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