Nonvolatile memory device, corresponding method and system

Abstract

The disclosure relates to non-volatile memory devices, corresponding methods and systems. A memory device includes a memory array having memory cells in a set of memory portions and addressable via pairs of row and column values; a set of sense amplifiers coupled to and interposed between adjacent memory portions; a control logic circuit configured to provide at least one address signal indicative of a pair of row and column values to locate at least one addressed memory cell and issue a read or write access request towards the at least one addressed memory cell; a first set of access devices configured to couple addressed memory cells in respective memory portions to respective sense amplifier circuits in response to a read access request; and a second set of access devices configured to couple the addressed memory cells in the respective memory portions to the main program bit line in response to a write access request.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Patent Application No. 102023000017553, filed on August 24, 2023, which is hereby incorporated herein by reference. Technical Field

[0003] The present specification relates to non-volatile memory (NVM) systems and methods.

[0004] One or more embodiments may be applied to various NVM technologies, such as phase change memory (PCM), magnetoresistive random access memory (MRAM), or resistive random access memory (RRAM), for example. Background Art

[0005] The term "nonvolatile memory" currently refers to semiconductor technology that is capable of retaining data or program code stored in a computing device in the absence of continuous power.

[0006] There are many types of NVM systems. For example, in a subset of NVM, the state of a memory cell can be changed via a change in the current flowing through the cell. For example, US10 515 697 B1 discloses a method of controlling operations performed on a resistive memory cell. US 2006 / 181932A1 discloses a method for pulse width control in a phase change memory device.

[0007] WO 2005 / 117021 A1 discloses an example of a non-volatile memory device. US 2015 / 243355 A1 discloses a method for reducing peak current in a variable resistance memory device.

[0008] Conventional NVM systems include:

[0009] a program driver configured to write (e.g., a single bit) to the memory, and

[0010] A sense amplifier is configured to read (eg, determine a logic level assigned to a sensed current level).

[0011] Conventionally, sense amplifiers and program drivers are located on top of the array of bit cells of the NVM.A common master bit line is used to perform both read operations from the memory and write operations to the memory.

[0012] For example, if the length of the main bit line is about 800 μm (1 μm=10 -6 m = 1 micron), the access time to the memory cell can be introduced in the operation to be about 1.5 ns (1 ns = 10-9 s = 1 nanosecond), which may be considered inconvenient, depending on the application. Summary of the invention

[0013] It is an object of one or more embodiments to help overcome the above-mentioned disadvantages.

[0014] According to one or more embodiments, this object can be achieved via a (eg non-volatile memory) device having the features set out in the claims.

[0015] One or more embodiments may be directed to a corresponding method.

[0016] One or more embodiments may be directed to a corresponding (eg, flash memory) system.

[0017] The claims are an integral part of the technical teaching provided herein with reference to the embodiments.

[0018] One or more embodiments may facilitate providing sufficient access time for read / write (R / W) operations performed on a NVM system.

[0019] One or more embodiments may facilitate reducing silicon footprint. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0021] Figure 1 is an example diagram of a non-volatile memory device;

[0022] Figure 2 is an example diagram of a device according to the present disclosure;

[0023] Figure 3 is an example diagram of a read operation in a method according to the present disclosure;

[0024] Figure 4 is an example diagram of a write operation in a method according to the present disclosure;

[0025] Figure 5 is an example diagram of a non-volatile memory device according to the present disclosure; and

[0026] Figure 6 is a diagram of an example of a system equipped with a non-volatile memory device according to the present disclosure.

[0027] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.

[0028] The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

[0029] The edges of a feature drawn in a figure do not necessarily indicate the end of the extent of the feature. DETAILED DESCRIPTION

[0030] In the subsequent description, one or more specific details are described to provide a deeper understanding of the embodiments of the present specification. These embodiments can be obtained without one or more specific details, or using other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail so as not to obscure certain aspects of the embodiments.

[0031] References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or feature associated with the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more points of this specification do not necessarily refer to the same embodiment.

[0032] Furthermore, particular conformations, structures or characteristics may be combined in any suitable manner in one or more embodiments.

[0033] The references used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0034] For simplicity, in the following detailed description, the same reference numerals may be used to represent nodes / lines in a circuit, and signals that may appear on the nodes or lines.

[0035] Figure 1 A conventional non-volatile memory (NVM) device 10 is illustrated, comprising:

[0036] An array 18 of memory cells known per se; the memory cells of the array 18 are arranged in rows or word lines, and columns or bit lines BL; merely as a non-limiting example, Figure 1 exemplified in FIG. 1 , a word line represented by WL and two bit lines represented by BL are coupled to a master bit line represented by MBL;

[0037] a set of column decoders 11 and a set of row decoders 12, which comprise access devices configured to select memory cells of the array (indicated as a whole by AS) based on address signals received at input terminals,

[0038] The R / W interface 14 includes a sense amplifier 140 and a program driver 142 . The program driver 142 is used to read and write data to the memory.

[0039] For example, the memory cells in array 18 include phase change memory (PCM for short) cells, which include a material that can be switched between a disordered / amorphous phase and an ordered (crystalline or polycrystalline) phase, where the different phases are characterized by different resistivity values ​​and are therefore associated with different values ​​of data stored in the memory cell.

[0040] like Figure 1 As illustrated, the address signal AS can be generated by control logic CL configured to drive the column decoders and row decoders of the array 18 to enable reading and writing (also referred to as programming) of the memory cells addressed by the address signal AS.

[0041] For example, the control logic CL also supplies control signals to the R / W interface 14 in order to govern read / write operations.

[0042] As can be appreciated by those skilled in the art, the set of column decoder 11 and row decoder 12 is configured to bias and thereby select word line WL and bit line BL each time a selection is made so as to select a memory cell of array 18 coupled thereto; in this manner, reading and writing of the memory cells of array 18 is enabled.

[0043] Specifically, the row decoder 12 is designed to select the corresponding word line WL based on the address signal AS, while other word lines are deselected. To this end, the row decoder 12 includes a decoding stage 124 and a plurality of driving circuits 126.

[0044] like Figure 1 As illustrated, the decoding stage 124 receives the address signal AS from the control logic CL and operates the driver circuit 126 according to the address signal AS. Each of the plurality of driver circuits 126 has an input terminal coupled to the decoding stage 124.

[0045] Regarding the set of column decoders 11 , these column decoders 11 include access elements / devices (eg, transistors) configured to select one or more bit lines BL based on an address signal AS.

[0046] like Figure 1 As illustrated, the access devices in column decoder 11 cooperate with the access devices in row decoder 12 in such a way that during a read or write step of any memory cell selected in array 18, a read current or a write current, respectively, flows through the storage elements of the memory cells of array 18.

[0047] For example, the access devices in the set of column decoders 11 are configured to implement two different paths towards the bit line BL of the memory array 18 at each selection:

[0048] a read path that electrically connects each bit line BL selected during a read step to a sense amplifier 140, and

[0049] A write path that electrically connects each bit line BL selected during the programming step to a program driver circuit (in Figure 1 (not visible in the image).

[0050] As illustrated herein, for each read path and write path, the column decoder 11 includes appropriate access or selection elements / devices (eg, transistors, see e.g., Figure 5 ) in order to implement hierarchical decoding of the address signal AS, thereby selecting the memory cells of the memory array 18.

[0051] like Figure 1 As illustrated, the memory array 18 may be organized into a plurality of sectors S, each sector S including a plurality of memory cells.

[0052] For example, each region S includes a plurality of corresponding word lines WL and a plurality of corresponding local bit lines, which are again represented by BL and are different from the local bit lines of other regions.

[0053] like Figure 1 As illustrated, in each zone S, the local bit lines BL are connected to the memory cells of the same zone S. Figure 1 In the example considered in , for each set formed by an integer number k (eg 32) of local bit lines BL, a corresponding master bit line MBL is provided.

[0054] For example, the main bit line MBL, when selected at a higher level, enables subsequent selection of one or more of the corresponding local bit lines BL, and corresponding memory cells, at a lower level. In addition, different regions S are crossed by different word lines WL.

[0055] like Figure 1 As illustrated, the master bit lines MBL pass through a certain number of zones S and can be selected in groups at a hierarchical decoding level that is even higher than the hierarchical decoding level associated with the selection of the master bit lines MBL.

[0056] For example, at least one corresponding first-stage decoding circuit (composed of Figure 1 11 in FIG. 1, also referred to as a “local column decoder”) enables the local bit line BL to be connected to the corresponding main bit line MBL both during a write operation and during a read operation; for each group of regions S (in Figure 2 In the example of FIG. 1 including two regions), the corresponding second-stage decoding circuit enables selection of the main bit line MBL both during a write operation and during a read operation.

[0057] For example, the control logic CL sends a column decoding signal sYN to the decoding circuit 11. A subset of the address signal AS, based on the column decoding signal sYN The decoding circuit activates the selected master bit line (e.g., MBL) via activation of the corresponding master select switch (not visible). ) and the electrical path between the sense amplifier 140.

[0058] Furthermore, given a zone S, the corresponding first-level decoding circuit 11 is able to address each memory cell coupled to the local bit line BL of the zone S due to the presence of local selection switches, which are driven by corresponding local column decoding control signals YO (for corresponding access devices), which are generated by the control logic CL and also form part of the above-mentioned address signal AS.

[0059] The inventors have observed that distributing the components of the R / W interface 14 can speed up access to the various memory areas.

[0060] like Figure 2 As illustrated, the memory device 20 according to the present disclosure includes:

[0061] A memory array 28, which is organized into a plurality of memory portions (also referred to as sub-arrays) 280, 282, each memory portion including at least one region S of the memory array 28, wherein each region S includes a corresponding plurality of memory cells of the array 28, and a plurality of corresponding word lines WL; furthermore, each region S is coupled to a main bit line MBL_P to receive data from the main bit line MBL_P to be written to a corresponding memory cell of the array 28;

[0062] a program driver circuit block 242 coupled to the control logic CL to receive the address signal AS from the control logic CL and coupled to the memory portions 280, 282 via the main programming bit line MBL_P; and

[0063] A collection of sense amplifier circuit blocks 240 located among different memory portions 280 , 282 of the memory array 28 .

[0064] For example, the sense amplifier circuit block 240 is coupled to memory cells of a region S of a corresponding memory portion (eg, 280 ) adjacent to each sense amplifier circuit block in the set of sense amplifier circuit blocks 240 via a local bit line LBL.

[0065] For simplicity, one or more embodiments will be discussed below with respect to the case where the memory array 28 includes a first memory portion 280 and a second memory portion 282 and a sense amplifier circuit block 240 located between the two portions 280, 282, except that it should be understood that this case is purely exemplary and in no way limiting. One or more embodiments may include a theoretically arbitrary number of memory portions and a corresponding number of sense amplifier circuit blocks interleaved relative to the respective memory portions.

[0066] Figure 3 and Figure 4 is an operation of reading data from memory cells in region S of memory portion 280 of memory array 28 using a solution according to the present disclosure ( Figure 3 ) and the operation of writing data to the memory cell ( Figure 4 )

[0067] As will be appreciated by those skilled in the art, in the case of a phase change memory (PCM for short), an access (or selection) device such as a bipolar transistor or a MOS transistor may be coupled to a heater and selectively enable a programming current (also referred to as a write current) to pass through the heater; this current generates the heat required for the phase change by the Joule effect and in particular switches from a high resistivity state (called the reset (RESET) state) to a low resistivity state (the so-called set (SET) state) and vice versa in a manner known per se. During a read operation, the state of the phase change material can be detected by applying a voltage low enough so as not to cause significant heating thereof, and then reading the value of the current flowing in the memory cell by means of a sense amplifier circuit block 240. Since the current is proportional to the conductivity of the phase change material, it is possible to determine in which state the material is in and therefore the data stored in the memory cells of the array 28.

[0068] like Figure 3 As illustrated, the operation of reading data from at least one memory cell in the memory array portion 280 includes:

[0069] receiving an address signal AS of a memory cell storing data to be read from among the memory cells of the memory array 28 from the control logic;

[0070] selectively rendering a first bit line portion BL1 coupling a master bit line MBL_P to a memory array portion 280 non-conductive 11;

[0071] The local bit line LBL is coupled to the second bit line portion BL2 via an enable signal YN,

[0072] making the second bit line portion BL2 and the local bit line portion LBL selectively conductive YO, coupling the array region S of the memory portion 280 to the adjacent sense amplifier 240 as a result;

[0073] The current I flowing through the second bit line portion BL2 and the local bit line LBL is sensed via the sense amplifier 240. R , as a result of accessing a memory cell having an address corresponding to the address signal AS.

[0074] like Figure 4 As illustrated, the operation of writing data to at least one memory cell in region S of memory portion 180 of memory array 18 includes:

[0075] receiving, from the control logic, an address signal AS of a memory cell storing data to be read among the memory cells of the memory array 18;

[0076] The first bit line portion BL1 that couples the main bit line MBL_P to the memory array portion 280 is selectively conductive 11, and data is provided via the main programming bit line MBL_P to write I W ;

[0077] The program driver 242 is coupled to the second bit line portion BL2 of the memory array portion 280 via another local bit line portion LBLP via an enable signal YNP driven, for example, by the decoder 243.

[0078] making the second bit line portion BL2 selectively conductive YO, coupling the region S of the memory array to the program driver 242 via another local bit line portion LBLP;

[0079] The current I flowing through the second bit line portion BL2 and another local bit line portion LBLP is sensed via the program driver 242. FB , to check that the data has been written correctly and end the write operation.

[0080] because Figure 2 In the device 20 illustrated in FIG. 1 , the current (eg, about 20 μA, where 1 μA=10 -6 A=1 microampere) can be much lower than the current flowing on the main bit line MBL_P during a write operation (eg, about 800 μA). As a result, the latency to perform a read operation can be significantly reduced, particularly relative to the latency to perform a write operation.

[0081] like Figure 5 As illustrated, each memory portion 280, 282 includes a memory region S surrounded by:

[0082] a first set of access devices 110, 112, 114, 116 (eg, MOSFETs or BJT transistors) configured to selectively render conductive a first portion BL1 of a bit line coupling a main bit line MBL_P to the array region S, and

[0083] A second set of access devices YO1 , YO2 , YO4 , YO6 (eg, MOSFETs or BJT transistors) configured to selectively render conductive a second portion BL2 of a bit line coupling the array region S with the sense amplifier circuit block 240 .

[0084] like Figure 5 As illustrated, the sense amplifier circuit block 240 includes:

[0085] The sense amplifier 2400 is configured to sense the current I flowing at its input terminal. R , and based on the sensed current I R And generate logic level as output;

[0086] At least one first access device YN configured to provide a current flow path therethrough (corresponding to the local bit line LBL) to selectively couple a second portion of the bit line BL2 to the sense amplifier 2400, thereby providing a read current I to the sense amplifier 2400. R ,as well as

[0087] at least one second access device YNP configured to provide a current flow path therethrough (corresponding to another local bit line LBLP) to selectively couple a second portion of the bit line BL2 with the main bit line MBL_P to provide a current to the program driver circuit block (at Figure 5 (not visible in the figure) provides feedback current I FB .

[0088] As illustrated herein, the apparatus 20 comprises:

[0089] A memory array 28 includes memory cells arranged as a set of memory portions 280, 282 and addressable via pairs of row and column values, wherein each memory portion in the set of memory portions (280, 282) includes at least one region (S) of memory cells arranged as rows and columns.

[0090] For example, the device 20 further includes:

[0091] a set of sense amplifier circuits 240, 2400 including sense amplifier circuits coupled to and interposed between adjacent memory portions of the set of memory portions 280, 282 of the memory array;

[0092] a control circuit CL coupled to the memory array and configured to provide at least one address signal AS indicating a pair of row value and column value to locate at least one addressed memory cell in the memory array, the control circuit being further configured to issue a read access request or a write access request toward the at least one addressed memory cell in the memory array;

[0093] a first set of access devices YO, YN coupled to the control circuit, the memory cells in the memory array, and the set of sense amplifiers 240, the access devices in the first set of access devices being configured to conduct in response to a read access request issued by the control circuit to couple addressed memory cells in respective memory portions of the set of memory portions of the memory array BL2, LBL to respective sense amplifier circuits in the set of sense amplifier circuits;

[0094] A second set of access devices 11, YNP is coupled to the control circuit, the memory cells in the memory array, and the programming bit lines WL, MBL_P, and the access device YNP in the second set of access devices 11, YNP is configured to conduct in response to a write access request issued by the control circuit to couple the addressed memory cells BL1, BL2, LBLP in the corresponding memory parts in the set of memory parts of the memory array to the programming bit lines.

[0095] As illustrated herein, a first set of access devices includes:

[0096] a first subset of access devices YO; YO1, YO2, YO4, YO6 coupled to memory portions of the set of memory portions of the addressed memory cells and to local bit line portion BL2, and

[0097] A second subset of access devices YN is coupled to local bit line portion BL2 and sense amplifier circuit 2400 in the set of sense amplifier circuits.

[0098] For example, in response to a read signal issued by the control logic:

[0099] The access devices in the first subset of access devices are conductive, coupling the addressed memory cells to the local bit line portions as a result, and

[0100] The access devices in the second subset of access devices are conductive to provide a current flow path LBL from the local bit line portion to the sense amplifier, wherein the current I R Flows from the addressed memory cell to the sense amplifier as a result.

[0101] As illustrated herein, the second set of access devices includes:

[0102] A third subset of access devices 11; 110, 112, 114, 116 coupled to memory portions of the set of memory portions 280, 282 of the addressed memory cells and the master programming bit lines WL, MBL_P, and

[0103] A fourth subset of access devices YNP is coupled to the main programming bit lines WL, MBL_P.

[0104] For example, in response to a write signal issued by the control logic (CL):

[0105] The access devices in the third subset of access devices are conductive, coupling the addressed memory cells to the master programming (bit) line to receive the programming current (I W ) as a result, and

[0106] The access devices in the fourth subset of access devices are conductive to provide a current flow path (LBLP) wherein the feedback current I FB As a result, 240 Ω flows from the addressed memory cells to the main programming bit lines WL, MBL_P.

[0107] As illustrated herein, the apparatus includes a program driver circuit 242 coupled to:

[0108] control logic to receive an address signal from the control logic,

[0109] programming bit lines, and

[0110] Access devices in the second set of access devices.

[0111] For example, the program driver circuit is configured to receive feedback current from addressed memory cells in the set of memory portions of the memory array in response to access devices in a fourth subset of access devices in the second set of access devices conducting.

[0112] As illustrated herein, the memory cells in the memory array are phase change memories, PCM.

[0113] As illustrated herein, a method includes providing a memory array 28 including memory cells arranged as a set of memory portions 280, 282 and addressable via pairs of row and column values. For example, each memory portion in the set of memory portions includes at least one region S of memory cells arranged as rows and columns.

[0114] As exemplified herein, the method further comprises:

[0115] coupling sense amplifier circuits of the set of sense amplifier circuits 240; 2400 to adjacent memory portions of the set of memory portions of the memory array and inserting sense amplifier circuits of the set of sense amplifier circuits 240; 2400 between adjacent memory portions of the set of memory portions of the memory array;

[0116] coupling a control circuit CL to the memory array, the control circuit being configured to provide at least one address signal AS indicating a pair of row value and column value to locate at least one addressed memory cell in the memory array, the control circuit being further configured to issue a read access request or a write access request toward the at least one addressed memory cell in the memory array;

[0117] coupling a first set of access devices YO, YN to control circuitry, memory cells in a memory array, and a set of sense amplifiers, the access devices in the first set of access devices being configured to conduct in response to a read access request issued by the control circuitry to couple addressed memory cells BL2, LBL in respective memory portions of a set of memory portions of the memory array to respective sense amplifier circuits in the set of sense amplifier circuits;

[0118] A second set of access devices is coupled to the control circuitry, the memory cells in the memory array, and the programming bit lines, the access devices in the second set of access devices being configured to conduct in response to a write access request issued by the control circuitry to couple addressed memory cells in corresponding memory portions of the set of memory portions of the memory array to the programming bit lines.

[0119] As illustrated herein, a first set of coupled access devices includes:

[0120] coupling a first subset of access devices to memory portions of the set of memory portions of the addressed memory cells and to local bit line portions, and

[0121] A second subset of access devices is coupled to the local bit line portions and to a sense amplifier circuit in the set of sense amplifier circuits.

[0122] For example, in response to a read signal being issued by the control logic:

[0123] The access devices in the first subset of access devices are conductive, coupling the addressed memory cells to the local bit line portions as a result, and

[0124] The access devices in the second subset of access devices are conductive to provide a current flow path from the local bit line portion to the sense amplifier, wherein the current I R Flows from the addressed memory cell to the sense amplifier as a result.

[0125] As illustrated herein, the second set of coupled access devices includes:

[0126] coupling a third subset of access devices to memory portions of the set of addressed memory cells and to the master programming bit lines, and

[0127] A fourth subset of access devices is coupled to the master programming bit lines.

[0128] For example, in response to a write signal issued by the control logic CL:

[0129] The access devices in the third subset of access devices conduct electricity, coupling the addressed memory cells to the primary programming (bit) line to receive the programming current as a result, and

[0130] The access devices in the fourth subset of access devices are conductive to provide a current flow path wherein feedback current flows from the addressed memory cell to the primary programming bit line as a result.

[0131] As illustrated herein, the method includes coupling a program driver circuit to:

[0132] control logic to receive an address signal from the control logic,

[0133] programming bit lines, and

[0134] an access device from a second set of access devices,

[0135] Wherein the method includes receiving a feedback current from addressed memory cells in a set of memory portions of a memory array via a program driver circuit in response to an access device in a fourth subset of access devices in the second set of access devices conducting.

[0136] The system 500 equipped with the device 20 according to the present disclosure may further include a digital-to-analog converter circuit DAC configured to generate a current I W , preferably provided to the main programming (bit) lines WL, MBL_P via a program driver circuit (242) coupled to the main programming (bit) lines WL, MBL_P.

[0137] like Figure 6 As illustrated, the system of the present disclosure includes:

[0138] like Figure 2 The memory device 20 illustrated in FIG.

[0139] control logic CL, which includes a plurality of interfaces for operating on the memory device 20;

[0140] A plurality of service circuits, such as a bandgap circuit BGAP, a local oscillator circuit OSC, a digital-to-analog converter circuit DACT, a bus, etc., are configured to be coupled to various components of the device to drive the operation thereof, as can be appreciated by those skilled in the art.

[0141] like Figure 6 Example:

[0142] The bandgap circuit BGAP provides a reference voltage for analog circuit devices in the memory 20;

[0143] The oscillator circuit block OSC is configured to generate a clock signal to run a read / write instruction operation on the control logic CL;

[0144] The digital-to-analog converter circuit block DAC is configured to generate a write current I during a write operation. W The current intensity value;

[0145] The decoder circuit block "Pre dec address" is configured to apply a decoding process to the address signal AS so as to drive the decoders 11, 14; and

[0146] A mask circuit block, msk_prall, is configured to store information related to bits of the array to be programmed during a write operation.

[0147] In addition, it should be understood that the individual implementation options illustrated in the drawings of this specification are not necessarily intended to be used in the same combination illustrated in the drawings. Therefore, one or more embodiments can adopt these (otherwise non-mandatory) options separately and / or in a different combination relative to the combination illustrated in the drawings.

[0148] The details and embodiments may vary, even significantly, with respect to what has been described merely by way of example, without prejudice to the essential principles and without departing from the scope of protection, which is defined by the appended claims.

Claims

1. A memory device, comprising: a memory array comprising memory cells arranged as a set of memory portions and addressable via pairs of row and column values, wherein each memory portion of the set of memory portions comprises at least one region of memory cells arranged as rows and columns; a set of sense amplifier circuits, the sense amplifier circuits comprising sense amplifier circuits coupled to and interposed between adjacent memory portions of the set of memory portions of the memory array; a control logic circuit coupled to the memory array and configured to: providing at least one address signal to locate at least one addressed memory cell in the memory array, the at least one address signal indicating a pair of row and column values; and issuing a read access request or a write access request toward the at least one addressed memory cell in the memory array; a first set of access devices, the first set of access devices being coupled to the control logic circuit, the memory cells in the memory array, and the set of sense amplifier circuits, wherein the first set of access devices is configured to conduct in response to a read access request issued by the control logic circuit to couple a respective first addressed memory cell in a respective one of the set of memory portions of the memory array to a respective one of the set of sense amplifier circuits; as well as a second set of access devices, the second set of access devices being coupled to the control logic circuit, the memory cells in the memory array, and a master programming bit line, wherein the second set of access devices is configured to conduct in response to a write access request issued by the control logic circuit to couple a corresponding second addressed memory cell in a corresponding one of the set of memory portions of the memory array to the master programming bit line.

2. The memory device of claim 1 , wherein the first set of access devices comprises: a first subset of access devices, said first subset of access devices being coupled to said memory portions of said set of memory portions of said addressed memory cells and to a local bit line portion; as well as a second subset of access devices coupled to the local bit line portion and a sense amplifier circuit in the set of sense amplifier circuits; Wherein, in response to the control logic circuit sending a read signal: a first access device of said first subset of said access devices being configured to be conductive to couple said addressed memory cell to said local bit line portion as a result; and A second access device in the second subset of the access devices is configured to conduct electricity to provide a current flow path from the local bit line portion to the sense amplifier circuit, wherein a read current flows from the addressed memory cell to the sense amplifier circuit as a result.

3. The memory device of claim 2, wherein the second set of access devices comprises: a third subset of access devices, said third subset of access devices being coupled to said memory portions of said set of memory portions of said addressed memory cells and to said master programming bit lines; as well as a fourth subset of access devices, the fourth subset of access devices coupled to the master programming bit lines; Wherein, in response to the control logic circuit sending a write signal: a third access device in the third subset of the access devices is configured to be conductive, coupling the addressed memory cell to the primary programming bit line to receive a programming current as a result; and A fourth access device in the fourth subset of the access devices is configured to conduct electricity to provide a second current flow path, wherein feedback current flows from the addressed memory cell to the primary programming bit line as a result.

4. The memory device of claim 3, further comprising a program driver circuit coupled to: the control logic circuit to receive an address signal from the control logic circuit; the primary programming bit line; and the second access device in the second set of access devices; Wherein the program driver circuit is configured to receive the feedback current from the addressed memory cells in the set of memory portions of the memory array in response to the fourth access device in the fourth subset of the access devices being conductive.

5. The memory device of claim 1 , wherein the second set of access devices comprises: a third subset of access devices, said third subset of access devices being coupled to said memory portions of said set of memory portions of said addressed memory cells and to said master programming bit lines; as well as a fourth subset of access devices, the fourth subset of access devices coupled to the master programming bit lines; Wherein, in response to the control logic circuit sending a write signal: a third access device in the third subset of the access devices is configured to be conductive, coupling the addressed memory cell to the primary programming bit line to receive a programming current as a result; and A fourth access device in the fourth subset of the access devices is configured to conduct electricity to provide a current flow path wherein feedback current flows from the addressed memory cell to the primary programming bit line as a result.

6. The memory device of claim 5, further comprising a program driver circuit coupled to: the control logic circuit to receive an address signal from the control logic circuit; the master programming bit line; as well as the fourth access device in the fourth subset of the access devices; Wherein the program driver circuit is configured to receive the feedback current from the addressed memory cells in the set of memory portions of the memory array in response to the fourth access device in the fourth subset of the access devices being conductive.

7. The memory device of claim 1, wherein the memory cells in the memory array are phase change memories.

8. A method comprising: providing a memory array comprising memory cells arranged as a set of memory portions and addressable via pairs of row and column values, each memory portion of the set of memory portions comprising at least one region of memory cells arranged as rows and columns; coupling sense amplifier circuits of a set of sense amplifier circuits to adjacent memory portions of the set of memory portions of the memory array and interposing the sense amplifier circuits of the set of sense amplifier circuits between adjacent memory portions of the set of memory portions of the memory array; coupling a control logic circuit to the memory array, the control logic circuit being configured to provide at least one address signal to locate at least one addressed memory cell in the memory array and to issue a read access request or a write access request toward the at least one addressed memory cell in the memory array, the at least one address signal indicating a pair of row value and column value; coupling a first set of access devices to the control logic circuit, the memory cells in the memory array, and the set of sense amplifier circuits, the access devices in the first set of access devices being configured to conduct in response to a read access request issued by the control logic circuit to couple a respective first addressed memory cell in a respective memory portion in the set of memory portions of the memory array to a respective sense amplifier circuit in the set of sense amplifier circuits; as well as A second set of access devices is coupled to the control logic circuit, the memory cells in the memory array, and a master programming bit line, the access devices in the second set of access devices being configured to conduct in response to a write access request issued by the control logic circuit to couple corresponding second addressed memory cells in corresponding ones of the set of memory portions of the memory array to the master programming bit line.

9. The method of claim 8, wherein coupling the first set of access devices comprises: coupling a first subset of access devices to said memory portions of said set of memory portions of said addressed memory cells and to local bit line portions; as well as coupling a second subset of access devices to the local bit line portions and to sense amplifier circuits in the set of sense amplifier circuits; Wherein, in response to a read signal issued by the control logic circuit: a first access device of said first subset of said access devices being conductive, coupling said addressed memory cell to said local bit line portion as a result; and A second access device in the second subset of the access devices conducts to provide a current flow path from the local bit line portion to the sense amplifier circuit, wherein a read current flows from the addressed memory cell to the sense amplifier circuit as a result.

10. The method of claim 9, wherein coupling the second set of access devices comprises: coupling a third subset of access devices to said memory portions of said set of memory portions of said addressed memory cells and to said master programming bit lines; as well as coupling a fourth subset of access devices to the master programming bit lines; Wherein, in response to a write signal issued by the control logic circuit: A third access device in the third subset of the access devices conducts electricity, coupling the addressed memory cell to the master programming bit line to receive a programming current as a result; and A fourth access device in the fourth subset of the access devices conducts electricity to provide a second current flow path, wherein feedback current flows from the addressed memory cell to the primary programming bit line as a result.

11. The method of claim 10, further comprising coupling the program driver circuit to: the control logic circuit to receive an address signal from the control logic circuit; the master programming bit line; as well as the second access device in the second set of access devices; Wherein the method includes receiving the feedback current from the addressed memory cells in the set of memory portions of the memory array via the program driver circuit in response to access devices in the fourth subset of the access devices conducting.

12. The method of claim 8, wherein coupling the second set of access devices comprises: coupling a third subset of access devices to said memory portions of said set of memory portions of said addressed memory cells and to said master programming bit lines; as well as coupling a fourth subset of access devices to the master programming bit lines; Wherein, in response to a write signal issued by the control logic circuit: A third access device in the third subset of the access devices conducts electricity, coupling the addressed memory cell to the master programming bit line to receive a programming current as a result; and A fourth access device in the fourth subset of the access devices conducts electricity to provide a current flow path wherein feedback current flows from the addressed memory cell to the primary programming bit line as a result.

13. The method of claim 12, further comprising coupling the program driver circuit to: the control logic circuit to receive an address signal from the control logic circuit; the master programming bit line; as well as the fourth access device in the fourth subset of the access devices; Wherein the method includes receiving the feedback current from the addressed memory cells in the set of memory portions of the memory array via the program driver circuit in response to access devices in the fourth subset of the access devices conducting.

14. A system comprising: A memory device, the memory device comprising: a memory array comprising memory cells arranged as a set of memory portions and addressable via pairs of row and column values, wherein each memory portion of the set of memory portions comprises at least one region of memory cells arranged as rows and columns; a set of sense amplifier circuits, the sense amplifier circuits comprising sense amplifier circuits coupled to and interposed between adjacent memory portions of the set of memory portions of the memory array; a control logic circuit coupled to the memory array and configured to: providing at least one address signal to locate at least one addressed memory cell in the memory array, the at least one address signal indicating a pair of row and column values; and issuing a read access request or a write access request toward the at least one addressed memory cell in the memory array; a first set of access devices, the first set of access devices being coupled to the control logic circuit, the memory cells in the memory array, and the set of sense amplifier circuits, wherein the first set of access devices is configured to conduct in response to a read access request issued by the control logic circuit to couple a respective first addressed memory cell in a respective one of the set of memory portions of the memory array to a respective one of the set of sense amplifier circuits; and a second set of access devices, the second set of access devices being coupled to the control logic circuit, the memory cells in the memory array, and a master programming bit line, wherein the second set of access devices is configured to conduct in response to a write access request issued by the control logic circuit to couple a corresponding second addressed memory cell in a corresponding one of the set of memory portions of the memory array to the master programming bit line; and A digital-to-analog converter circuit is configured to generate a programming current that is provided to the primary programming bit line.

15. The system of claim 14, wherein the digital-to-analog converter circuit is configured to generate the programming current provided to the primary programming bit line via a program driver circuit coupled between the digital-to-analog converter circuit and the primary programming bit line.

16. The system of claim 14, wherein the first set of access devices comprises: a first subset of access devices, said first subset of access devices being coupled to said memory portions of said set of memory portions of said addressed memory cells and to a local bit line portion; as well as a second subset of access devices coupled to the local bit line portion and a sense amplifier circuit in the set of sense amplifier circuits; Wherein, in response to the control logic circuit sending a read signal: a first access device of said first subset of said access devices being configured to be conductive to couple said addressed memory cell to said local bit line portion as a result; and A second access device in the second subset of the access devices is configured to conduct electricity to provide a current flow path from the local bit line portion to the sense amplifier circuit, wherein a read current flows from the addressed memory cell to the sense amplifier circuit as a result.

17. The system of claim 16, wherein the second set of access devices comprises: a third subset of access devices, said third subset of access devices being coupled to said memory portions of said set of memory portions of said addressed memory cells and to said master programming bit lines; as well as a fourth subset of access devices, the fourth subset of access devices coupled to the master programming bit lines; Wherein, in response to the control logic circuit sending a write signal: a third access device in the third subset of the access devices is configured to be conductive, coupling the addressed memory cell to the primary programming bit line to receive the programming current as a result; and A fourth access device in the fourth subset of the access devices is configured to conduct electricity to provide a second current flow path, wherein feedback current flows from the addressed memory cell to the primary programming bit line as a result.

18. The system of claim 17, further comprising a program driver circuit coupled to: the control logic circuit to receive an address signal from the control logic circuit; the primary programming bit line; and the second access device in the second set of access devices; Wherein the program driver circuit is configured to receive the feedback current from the addressed memory cells in the set of memory portions of the memory array in response to the fourth access device in the fourth subset of the access devices being conductive.

19. The system of claim 14, wherein the second set of access devices comprises: a third subset of access devices, said third subset of access devices being coupled to said memory portions of said set of memory portions of said addressed memory cells and to said master programming bit lines; as well as a fourth subset of access devices, the fourth subset of access devices coupled to the master programming bit lines; Wherein, in response to the control logic circuit sending a write signal: a third access device in the third subset of the access devices is configured to be conductive, coupling the addressed memory cell to the primary programming bit line to receive the programming current as a result; and A fourth access device in the fourth subset of the access devices is configured to conduct electricity to provide a current flow path wherein feedback current flows from the addressed memory cell to the primary programming bit line as a result.

20. The system of claim 19, further comprising a program driver circuit coupled to: the control logic circuit to receive an address signal from the control logic circuit; the master programming bit line; as well as the fourth access device in the fourth subset of the access devices; Wherein the program driver circuit is configured to receive the feedback current from the addressed memory cells in the set of memory portions of the memory array in response to the fourth access device in the fourth subset of the access devices being conductive.

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