Low-loss switching method and system of three-level ANPC inverter

Abstract

The invention relates to the technical field of power electronics, and particularly discloses a low-loss switching method and system for a three-level ANPC inverter, and the method comprises the steps: carrying out the time delay of drive signals of a power device S2 and a power device S6, so as to increase the adjustable range of drive time delay; if yes, the control signal is switched on in the delayed adjustable range, so that transition from switching on a leading power device S6 by a power device S2 to switching on the leading power device S2 by the power device S6 can be realized, and the overall loss of the inverter is measured under different working currents and different switching-on control signals, and the relationship among the three is obtained; therefore, in specific application, the optimal opening control signal corresponding to the minimum loss can be obtained according to the specific size of the working current, then the power devices S2 and S6 are opened according to the optimal opening control signal and the delayed driving signal, and it can be guaranteed that the opening loss and the conduction loss are balanced under the condition that the inverter works at low loss. And meanwhile, the two devices are almost switched on simultaneously, so that the peak of the devices during switching on is reduced.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and in particular to a low-loss switching method and system for a three-level ANPC inverter. Background Art

[0002] Compared with the two-level inverter, the three-level inverter has the advantages of low device voltage stress, small dv / dt and high output waveform quality. Figure 1 As shown, the ANPC three-level topology is composed of six controllable power devices (SiC MOSFET), including controllable power devices S1, S5, S6 and S4 connected sequentially between the positive terminal (point P) and the negative terminal (point Q) of the power supply, and capacitors C1 and C2 connected sequentially between the positive terminal (point P) and the negative terminal (point Q) of the power supply, and also including controllable power devices S2 and S3 connected sequentially between the controllable power devices S1 and S4 and connected in parallel with the series-connected S5 and S6, the common end of S5 and S6 is connected to the common end of capacitors C1 and C2, the common end of S2 and S3 serves as the output end of the inverter, and point a serves as the neutral point.

[0003] When the three-level inverter operates in neutral point commutation, Figure 2 The working states of the four quadrants shown (from the upper right, upper left, lower left, and lower right are the first to fourth quadrants respectively) are that when working in the first and third quadrants, the commutation is performed through the anti-parallel diode of the MOSFET. The diode is an uncontrollable device and cannot be controlled. When working in the second quadrant, S2 and S6 are controlled. When working in the fourth quadrant, S3 and S5 are controlled. Since the topology is symmetrical, the control conditions of the second and fourth quadrants are similar. By reasonably controlling the opening and closing of S2, S6 and S3, S5, the loss distribution of each power device can be made more uniform, and the reliability of the inverter operation can be improved.

[0004] Taking the second quadrant as an example, before S2 and S6 are turned on, S1 is turned off, S5 is turned on but does not carry current, S3 is turned on and carries current, and S4 is turned off and the anti-parallel diode carries current. When the inverter works in the second quadrant, two parallel current paths are used for freewheeling during neutral point commutation to reduce conduction losses, such as Figure 3 As shown, the two parallel current paths include a long loop and a short loop. Figure 3 (a) is a short commutation loop, passing through devices S6 and S4, and including the parasitic inductance of the two devices (red), a line parasitic inductance (purple), and the neutral point freewheeling devices are S6 and S3. Figure 3(b) is a long commutation loop, passing through devices S5, S2, S3, and S4, and including the parasitic inductance of four devices (red) and three line parasitic inductances (purple). The neutral point freewheeling devices are S5 and S2. Since SiC MOSFET has an extremely fast turn-on speed, and since the threshold voltage of the power device and the delay of the drive circuit are not completely consistent, the power devices cannot be guaranteed to be turned on at the same time. The working conditions of the devices will also be different under different currents, and the turn-on conditions of the power devices will be affected, causing more serious losses.

[0005] Based on the characteristic of low turn-on loss of long circuit, some scholars proposed that the long circuit should bear all the conduction loss. After the turn-on is completed, the short circuit device will be turned on by ZVS to reduce the turn-on loss. However, since the long circuit device is turned on alone, the discharge of the junction capacitance causes a huge current spike, which greatly affects the normal operation of the inverter; the existence of tail current, circulating current and the aggravation of uneven current also increase the conduction loss.

[0006] When the three-level active clamp inverter is working, when the short-loop device is turned on first, the short-loop device bears the main turn-on loss, and the turn-on loss is large when the short loop is turned on, which will cause the overall loss to increase. When the long loop is turned on first, the tail current and the loop current formed in the loop when the junction capacitance is released and the uneven current phenomenon will cause additional losses. Summary of the invention

[0007] The present invention provides a low-loss switching method and system for a three-level ANPC inverter, and solves the technical problem of how to reduce the overall loss of the three-level ANPC inverter when it switches to the second and fourth quadrants.

[0008] In order to solve the above technical problems, the present invention provides a low-loss switching method for a three-level ANPC inverter. The three-level ANPC inverter includes power devices S1, S5, S6 and S4 connected sequentially between the positive terminal and the negative terminal of a power supply, and capacitors C1 and C2 connected sequentially between the positive terminal and the negative terminal of the power supply. It also includes power devices S2 and S3 connected sequentially between S1 and S4 and connected in parallel with S5 and S6 connected in series. The common end of S5 and S6 is connected to the common end of capacitors C1 and C2, and the common end of S2 and S3 is used as the output end of the inverter. It is characterized in that the low-loss switching method is applied when the three-level ANPC inverter is switched to the second and fourth quadrants, and specifically includes the steps of:

[0009] S1, respectively delay the driving signals of power devices S2 and S6;

[0010] S2. Under different working currents, the inverter is made to transition from power device S2 turning on ahead of power device S6 to power device S6 turning on ahead of power device S2 by turning on the control signal, and the overall loss of the inverter under different working currents is calculated, and the relationship between the working current, the turning on control signal and the overall loss is obtained;

[0011] S3, real-time detection of the working current of the inverter, and obtaining the optimal opening control signal when the working current corresponds to the minimum overall loss according to the relationship among the working current, the opening control signal and the overall loss;

[0012] S4, using the delayed driving signal and the optimal opening control signal to act on the power devices S2 and S6.

[0013] Further, in step S2, an opening control signal is generated to enable the inverter to transition from power device S2 opening ahead of power device S6 to power device S6 opening ahead of power device S2, and the operations taken are:

[0014] S21, generate two voltages of +2.5V and -2.5V;

[0015] S22, generate a reference voltage V adjusted in 0-5V based on the two voltages of +2.5V and -2.5V ref That is, turn on the control signal;

[0016] S23, reference voltage V ref Performing pressurization and decompression respectively to obtain a pressurization signal and a decompression signal;

[0017] S24, input the pressure-increasing signal and the delayed driving signal of the power device S6 to the inverting input terminal and the non-inverting input terminal of the first high-speed comparator respectively, and the output terminal of the first high-speed comparator is connected to the driving circuit of the power device S6; input the pressure-reducing signal and the delayed driving signal of the power device S2 to the inverting input terminal and the non-inverting input terminal of the second high-speed comparator respectively, and the output terminal of the second high-speed comparator is connected to the driving circuit of the power device S2;

[0018] The outputs of S25, the driving circuit of the power device S6 and the driving circuit of the power device S2 act on the power device S6 and the power device S2 to turn them on.

[0019] Furthermore, in the step S1, a delay circuit is added between the driving signals of the power devices S2 and S6 and the ground to delay the driving signals of the power devices S2 and S6.

[0020] Furthermore, in step S21, two voltages of +2.5V and -2.5V are generated by passing the auxiliary power supply through a positive DC-DC circuit and a negative DC-DC circuit respectively.

[0021] Furthermore, in step S22, by connecting the +2.5V and -2.5V voltages to the two ends of the adjustable resistor, the adjustable resistor outputs a reference voltage V ref .

[0022] Furthermore, in step S23, the reference voltage V ref Through the adding circuit, the output is connected to the inverting input terminal of the first high-speed comparator; the reference voltage V ref The output is connected to the inverting input terminal of the second high-speed comparator through the subtraction circuit; the inputs of the inverting input terminals of the first high-speed comparator and the second high-speed comparator are freely variable between 0 and 5V.

[0023] Furthermore, during commutation, in step S2, the overall loss includes turn-on loss, conduction loss and turn-off loss; the voltage and current at both ends of the power devices S2 and S6 have overlapping areas, causing turn-on loss; when the power devices S2 and S6 are turned on, conduction loss will be caused in the power devices S2, S3, S5 and S6; when the power devices S2 and S6 are turned off, S6 bears all the turn-off loss.

[0024] Furthermore, by obtaining the drain current and drain-source voltage waveforms of the power devices S2 and S6, and then integrating the product of the current and voltage during the turn-on time, the turn-on loss is obtained; by integrating the power device current during the conduction time and multiplying the integral by twice the on-resistance, the conduction loss of the power device is obtained; for the turn-off loss, the calculation process is the same as the turn-on loss calculation process.

[0025] Furthermore, in step S2, the relationship among the working current, the opening control signal and the overall loss is obtained by function fitting.

[0026] The present invention also provides a low-loss switching system for a three-level ANPC inverter, which is applied to the low-loss switching system for the three-level ANPC inverter. The key is that: it includes a drive signal adjustment circuit, a loss calculation module, a relationship fitting module, and a current measurement module. The drive signal adjustment circuit includes a delay module and an opening control signal module. The delay module is used to execute step S1; the opening control signal module is used to realize the transition from power device S2 turning on the leading power device S6 to power device S6 turning on the leading power device S2 in step S2 under different working currents through the opening control signal; The loss calculation module is used to implement the calculation of the overall loss of the inverter under different working currents in step S2; the relationship fitting module is used to execute the relationship between the working current, the opening control signal, and the overall loss in step S2; the current measurement module is used to implement the real-time detection of the working current of the inverter in step S3, and the relationship fitting module is also used to implement the step S3 of obtaining the optimal opening control signal when the working current corresponds to the minimum overall loss according to the relationship between the working current, the opening control signal, and the overall loss to the opening control signal module; the opening control signal module is also used to implement step S4.

[0027] The present invention provides a low-loss switching method and system for a three-level ANPC inverter. By first delaying the drive signals of power devices S2 and S6 to increase the adjustable range of the drive delay, the control signal is turned on within the adjustable range of the delay to enable a relatively slow and smooth transition from power device S2 turning on ahead of power device S6 to power device S6 turning on ahead of power device S2. The overall loss of the inverter is measured under different working currents and turn-on control signals to obtain the relationship between the three. In a specific application, the optimal turn-on control signal corresponding to the minimum loss can be obtained according to the specific size of the working current. Then, the power devices S2 and S6 are turned on with the optimal turn-on control signal and the delayed drive signal, which can ensure that the inverter works under low loss conditions and achieves a balance between the turn-on loss and the conduction loss. At the same time, since the two devices are still turned on almost at the same time, the peak when the device is turned on is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a circuit diagram of a three-level ANPC inverter provided by the background technology of the present invention;

[0029] Figure 2 It is a circuit diagram of a three-level ANPC inverter working in four quadrants provided by the background technology of the present invention;

[0030] Figure 3 It is a current path diagram of a three-level ANPC inverter provided by the background technology of the present invention when it works in the second quadrant;

[0031] Figure 4 is a schematic diagram of a drive signal adjustment circuit provided by an embodiment of the present invention;

[0032] Figure 5 is a circuit diagram of a positive DC-DC circuit provided by an embodiment of the present invention;

[0033] Figure 6 is a circuit diagram of a negative DC-DC circuit provided by an embodiment of the present invention;

[0034] Figure 7 is a circuit diagram of an adjustable resistor provided by an embodiment of the present invention;

[0035] Figure 8 is a circuit diagram of an adding circuit provided by an embodiment of the present invention;

[0036] Fig. 9 is a circuit diagram of a subtraction circuit provided by an embodiment of the present invention;

[0037] Fig.10 is a waveform diagram of a delayed driving signal provided by an embodiment of the present invention;

[0038] Fig.11 is a waveform diagram for calculating the opening loss provided by an embodiment of the present invention;

[0039] Fig.12 is a diagram showing the loss of changing the reference voltage under different currents provided by an embodiment of the present invention;

[0040] Fig.13 It is a fitting surface graph provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The following specifically illustrates the implementation mode of the present invention in conjunction with the accompanying drawings. The embodiments are provided for illustrative purposes only and cannot be understood as limiting the present invention. The accompanying drawings are provided for reference and illustration only and do not constitute a limitation on the scope of patent protection of the present invention, because many changes can be made to the present invention without departing from the spirit and scope of the present invention.

[0042] Example 1

[0043] An embodiment of the present invention provides a low-loss switching method for a three-level ANPC inverter, which reduces the loss by adjusting the switching delay of controllable power devices S2 and S6 (hereinafter referred to as power devices) in two commutation paths of the neutral point when the three-level ANPC inverter works in the second quadrant, and specifically includes the following steps:

[0044] S1, respectively delay the driving signals of power devices S2 and S6;

[0045] S2. Under different working currents, the inverter is made to transition from power device S2 turning on ahead of power device S6 to power device S6 turning on ahead of power device S2 by turning on the control signal, and the overall loss of the inverter under different working currents is calculated, and the relationship between the working current, the turning on control signal and the overall loss is obtained;

[0046] S3, real-time detection of the working current of the inverter, and obtaining the optimal opening control signal when the working current corresponds to the minimum overall loss according to the relationship among the working current, the opening control signal and the overall loss;

[0047] S4, using the delayed driving signal and the optimal opening control signal to act on the power devices S2 and S6.

[0048] The method is to first delay the driving signals of the power devices S2 and S6 to increase the adjustable range of the driving delay, so that within the adjustable range of the delay, the opening control signal can make the transition from the power device S2 opening ahead of the power device S6 to the power device S6 opening ahead of the power device S2 relatively slowly and smoothly, and measure the overall loss of the inverter under different working currents and opening control signals, and obtain the relationship between the three, so that in specific applications, the optimal opening control signal corresponding to the minimum loss can be obtained according to the specific size of the working current, and then the power devices S2 and S6 are opened with the optimal opening control signal and the delayed driving signal, which can ensure that the inverter works under low loss conditions and balances the opening loss and conduction loss. At the same time, since the two devices are still opened almost at the same time, the peak when the device is turned on is reduced.

[0049] In step S1, if the driving signals of power devices S2 and S6 are not delayed, the rising edge of the driving signal itself is about 6ns. At this time, if step S2 is directly controlled by opening the control signal, the adjustable range of the driving delay is too small, and the driving delay adjustment range is small, and it may be impossible to find the lowest loss. For example, the lowest loss point is a delay of 5ns. If the delay adjustment range can only be adjusted to 4ns at most, the lowest loss point cannot be found. According to actual application requirements, this embodiment requires that when a circulating current occurs, the reference voltage is one-fourth of the adjustable voltage. In this embodiment, the reference voltage range is approximately -2V-+2V, and the reference voltage is 1V when a circulating current occurs.

[0050] In order to simply and reliably delay the driving signals of the power devices S2 and S6 , the method adopted in this embodiment is to add a delay circuit between the driving signals of the power devices S2 and S6 and the ground.

[0051] As a more preferred embodiment, the delay circuit uses a delay capacitor, that is, a first delay capacitor and a second delay capacitor are respectively connected between the driving signals of the power devices S2 and S6 and the ground to delay the driving signals of the power devices S2 and S6. The advantage of using capacitors for delay is that the adjustable range can be adjusted simply and conveniently. After adding the delay capacitor, the rising edge of the driving signals of the power devices S2 and S6 will be greatly increased.

[0052] In other implementations, the delay circuit may use a filter constructed with an operational amplifier as the core.

[0053] In step S2, because the commutation branch where the power device S2 is located is a long loop, the opening loss is small. As the power device S2 is turned on ahead of the power device S6, the opening loss is mainly borne by S2, and the overall opening loss will be reduced. However, due to the existence of tail current and circulating current, and the aggravation of the uneven current phenomenon, as the power device S6 is turned on ahead of the power device S2, the conduction loss will increase greatly. The selection of the capacitance of the two delay capacitors must ensure that when the power device S2 is ahead of S6 to the greatest extent, S2 bears the main opening loss, and when the power device S6 is ahead of S2 to the greatest extent, S6 bears the main opening loss, so that a smaller overall loss can be obtained.

[0054] In order to generate a turn-on control signal so that the inverter can transition from power device S2 turning on the leading power device S6 to power device S6 turning on the leading power device S2, the operations taken in this embodiment are:

[0055] S21, generate two voltages of +2.5V and -2.5V;

[0056] S22, generate a reference voltage V adjusted in 0-5V based on the two voltages of +2.5V and -2.5V ref ;

[0057] S23, reference voltage V ref Performing pressurization and decompression respectively to obtain a pressurization signal and a decompression signal;

[0058] S24, input the pressure-increasing signal and the delayed driving signal of the power device S6 to the inverting input terminal and the non-inverting input terminal of the first high-speed comparator respectively, and the output terminal of the first high-speed comparator is connected to the driving circuit of the power device S6; input the pressure-reducing signal and the delayed driving signal of the power device S2 to the inverting input terminal and the non-inverting input terminal of the second high-speed comparator respectively, and the output terminal of the second high-speed comparator is connected to the driving circuit of the power device S2;

[0059] The outputs of S25, the driving circuit of the power device S6 and the driving circuit of the power device S2 act on the power device S6 and the power device S2 to turn them on.

[0060] Here, the reference voltage V plays a decisive role in the switching state of the power device S6 and the power device S2. ref , which is the opening control signal described in step S2.

[0061] As an implementation mode, the embodiment of the present invention adopts Figure 4 The driving signal conditioning circuit shown implements steps S1 and S21 to S24.

[0062] like Figure 4 As shown, in step S21, the auxiliary power supply can be generated into two voltages of +2.5V and -2.5V through the positive DC-DC circuit and the negative DC-DC circuit respectively. As an example, the circuit of the positive DC-DC circuit is as follows Figure 5 As shown, the circuit of the negative DC-DC circuit is as follows Figure 6 As shown, the DC-DC chips all use LMR16006XDDC, which is used to generate a +2.5V voltage in the positive direction and a -2.5V voltage in the negative direction.

[0063] like Figure 4 As shown, in step S22, +2.5V and -2.5V voltages are connected to the two ends of the adjustable resistor, and the adjustable resistor outputs a reference voltage V ref As an example, the circuit of the adjustable resistor is as follows Figure 7 As shown, by adjusting the value of the voltage divider resistor, the reference voltage V can be adjusted ref , the reference voltage can be adjusted from 0-5V. In order to avoid the influence of the subsequent circuit on the voltage divider circuit, a voltage follower circuit is added to isolate the circuit.

[0064] like Figure 4 As shown, in step S23, the reference voltage V ref Through the adding circuit, the output is connected to the inverting input terminal of the first high-speed comparator. ref Through the subtraction circuit, the output is connected to the inverting input terminal of the second high-speed comparator. It is worth noting that both the addition circuit and the subtraction circuit perform addition and subtraction based on 2.5V. Therefore, when the operational amplifiers used in the addition circuit and the subtraction circuit are rail-to-rail operational amplifiers, the input of the inverting input terminal of the first high-speed comparator and the second high-speed comparator can freely change between 0-5V. As an example, the circuit diagrams of the addition circuit and the subtraction circuit are as follows: Figure 8 , Fig. 9 As shown, the chip ADA4817-1ARDZ is used to add and subtract based on 2.5V, and the corresponding signals are output from the V2REF terminal and the V1REF terminal to the first high-speed comparator and the second high-speed comparator respectively.

[0065] like Figure 4As shown in the figure, when the voltage at the non-inverting input of the high-speed comparator is less than the voltage at the inverting input, the output of the high-speed comparator is low level, and when the voltage at the non-inverting input is greater than the voltage at the inverting input, the output of the high-speed comparator immediately becomes high level. The output of the high-speed comparator is the driving signal of the power device.

[0066] After the drive signal adjustment circuit, the turn-on delay of power devices S2 and S6 can be freely adjusted. The delay capacitor value is selected as 490pF. After the delay capacitor, the rising edge of the drive signal is about 27ns, and the adjustable range is increased to 27ns. Fig.10 As shown, when close to 0V and 5V, the operational amplifier does not work well when generating the reference voltage, so an effective adjustment range of about 1V-4V is selected, and generally 0.5V-4.5V can be selected.

[0067] It should be noted that Figures 5 to 9 The specific circuit is only an example, and other circuit designs that can achieve the same function may be used in other implementations.

[0068] In step S2, by changing V ref The inverter switches from power device S2 turning on before power device S6 to power device S6 turning on before power device S2. As an example, the operating currents in this example are 30A, 45A, 60A, 75A and 90A for measurement, and the maximum operating current is 100A. Adjust V at different operating currents ref The value is used to adjust the working state of the inverter, and the working state is gradually adjusted from S2 bearing the main turn-on loss to S6 bearing the main turn-on loss, that is, circulating current appears.

[0069] Before the neutral point freewheeling, the current path is the S4 anti-parallel diode and the conducting device S3. During commutation, although there is a certain lead-lag relationship, S2 and S6 are turned on almost at the same time. Since both devices are hard-on, there is an overlapping area between the voltage and current at both ends of the device, causing turn-on loss. When the device is turned on, due to the existence of the on-resistance and a large current flowing through the device at the same time, conduction loss will be caused in S2, S3, S5 and S6. When the device is turned off, the long-loop device S2 is turned off first. At this time, the long-loop device S2 is turned off at zero voltage and does not cause loss. The short-loop device S6 is turned off later and bears all the turn-off losses.

[0070] When measuring the loss, this example uses the integration method to calculate the loss. For the turn-on loss, when measuring the loss, the power devices S2 and S6 are in parallel, but because there are parasitic parameters between the drain of S2 and the drain of S6, and there are also parasitic parameters between the source of S2 and the source of S6, so when measuring the voltage between the drain and source of the power device, the drain-source voltage of the power device S6 and the drain-source voltage of S2 should be measured separately, that is, by obtaining the current Id (drain current) and voltage (drain-source voltage) waveform Vds of the turn-on device, and then integrating the product of the current and voltage (instant power) during the turn-on time (between data1 and data2), the turn-on loss is obtained, such as Fig.11 As shown in Figure 2. For the turn-off loss, the calculation process is the same as the turn-on loss calculation process.

[0071] For conduction loss, there are two conducting power devices in each neutral point commutation path. The integral value is obtained by integrating the detected current, and then multiplied by twice the conduction resistance of a single power device (obtained through technical manual query) as the conduction loss. When measuring the conduction loss, it is necessary to determine the conduction time (integral time) corresponding to the specified working current. In this example, the conduction time under the specified current is obtained by the intersection of a triangle wave with an amplitude of 1 and a frequency of 50kHz and a sine wave with an amplitude of 1 and a frequency of 50Hz, as shown in Table 1.

[0072] Table 1

[0073]

[0074] In this embodiment, a multi-pulse test platform is built to measure the loss of power devices. The bus voltage is set to 550 V. When measuring the switching loss of the device, due to the measurement error, the method of repeating the measurement four times and taking the average value is used to reduce the measurement error of the loss.

[0075] After measuring the loss under different working conditions, first observe the loss under different currents, such as Fig.12 As shown, Fig.12 (a) to (e) correspond to the working current of 90A, 75A, 60A, 45A, and 30A respectively. ref Corresponding loss. By observing the reference voltage V under different currents ref The impact on the total loss shows that when the current is determined, there is a reference voltage V with the minimum loss. ref .

[0076] Select the curve fitter in MATLAB and use the polynomial fitting method to fit the curve to generate the working current and reference voltage V refThe binary function relationship is the independent variable and the total loss is the dependent variable, where the variable x is the reference voltage and the variable y is the working current. The binary function relationship is as follows:

[0077] f(x,y)=-0.2006+0.0058*x+0.0760*y+0.0665*x 2 +-0.0027*x*y+-0.0014*y 2

[0078] +-0.0328*x 3 +-0.0014*x 2 *y+0.0001*x*y 2 +0.0199*x 4 +0.0001*x 3 *y

[0079] The fitting surface corresponding to this function is as follows Fig.13 As shown, Loss represents loss and I represents operating current.

[0080] In step S3, after the loss curve is fitted, an open-loop method is used to calculate the working current or a closed-loop method is used to monitor the working current of the inverter in real time. The working current is substituted into the function, and the fitted binary function becomes a univariate function, so that the value of the reference voltage corresponding to the optimal loss can be easily obtained. The reference voltage value is directly provided by the DAC digital-to-analog conversion module of the DSP, so that the inverter can realize a low-loss switching method in a continuous working state.

[0081] Finally, when the neutral point commutation circuit devices are turned off, the long-loop devices are turned off first to achieve zero voltage shutdown. The short-loop devices are turned off later and bear all shutdown losses. Since some scholars have studied this shutdown method, I will not elaborate on it here.

[0082] The method is to first delay the driving signals of the power devices S2 and S6 to increase the adjustable range of the driving delay, so that within the adjustable range of the delay, the opening control signal can make the transition from the power device S2 opening ahead of the power device S6 to the power device S6 opening ahead of the power device S2 relatively slowly and smoothly, and measure the overall loss of the inverter under different working currents and opening control signals, and obtain the relationship between the three, so that in specific applications, the optimal opening control signal corresponding to the minimum loss can be obtained according to the specific size of the working current, and then the power devices S2 and S6 are opened with the optimal opening control signal and the delayed driving signal, which can ensure that the inverter works under low loss conditions and balances the opening loss and conduction loss. At the same time, since the two devices are still opened almost at the same time, the peak when the device is turned on is reduced.

[0083] It should also be noted that when the three-level ANPC inverter operates in the fourth quadrant, it is symmetrical with the second quadrant design, and the same low-loss switching can be achieved by swapping S2, S6 with S3, S5.

[0084] Example 2

[0085] The present invention also provides a low-loss switching system for a three-level ANPC inverter, which is applied to a low-loss switching method for a three-level ANPC inverter described in Example 1, including a drive signal adjustment circuit, a loss calculation module, a relationship fitting module, and a current measurement module. The drive signal adjustment circuit includes a delay module and an opening control signal module. The delay module is used to execute step S1; the opening control signal module is used to implement the step S2 in which, under different working currents, the inverter is turned on by the opening control signal to transition from power device S2 turning on the leading power device S6 to power device S6 turning on the leading power device S2; the loss The power consumption calculation module is used to implement the calculation of the overall loss of the inverter under different working currents in step S2; the relationship fitting module is used to execute the relationship between the working current, the opening control signal and the overall loss in step S2; the current measurement module is used to implement the real-time detection of the working current of the inverter in step S3, and the relationship fitting module is also used to implement the step S3 of obtaining the optimal opening control signal when the working current corresponds to the minimum overall loss according to the relationship between the working current, the opening control signal and the overall loss to the opening control signal module; the opening control signal module is also used to implement step S4.

[0086] Since the first embodiment has described in detail how to implement each function in the method, this embodiment will not repeat it. This embodiment should emphasize that each module set in the system is a functional module, and in the specific implementation, an electronic circuit that can implement the corresponding function is used.

[0087] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be equivalent replacement methods and are included in the protection scope of the present invention.

Claims

1. A low-loss switching method for a three-level ANPC inverter, wherein the three-level ANPC inverter comprises power devices S1, S5, S6 and S4 sequentially connected between the positive terminal and the negative terminal of a power supply, and capacitors C1 and C2 sequentially connected between the positive terminal and the negative terminal of the power supply, and further comprises power devices S2 and S3 sequentially connected between S1 and S4 and connected in parallel with S5 and S6 connected in series, wherein the common terminal of S5 and S6 is connected to the common terminal of capacitors C1 and C2, and the common terminal of S2 and S3 serves as the output terminal of the inverter, wherein: The low-loss switching method is applied when a three-level ANPC inverter switches to the second quadrant, and specifically includes the following steps: S1, respectively delay the driving signals of power devices S2 and S6; S2. Under different working currents, the inverter is made to transition from power device S2 turning on ahead of power device S6 to power device S6 turning on ahead of power device S2 by turning on the control signal, and the overall loss of the inverter under different working currents is calculated, and the relationship between the working current, the turning on control signal and the overall loss is obtained; S3, real-time detection of the working current of the inverter, and obtaining the optimal opening control signal when the working current corresponds to the minimum overall loss according to the relationship among the working current, the opening control signal and the overall loss; S4, using the delayed driving signal and the optimal opening control signal to act on the power devices S2 and S6.

2. A low-loss switching method for a three-level ANPC inverter according to claim 1, characterized in that: Generate an opening control signal to enable the inverter to transition from power device S2 opening ahead of power device S6 to power device S6 opening ahead of power device S2. The operations taken are: S21, generate two voltages of +2.5V and -2.5V; S22, generate a reference voltage V adjusted in 0-5V based on the two voltages of +2.5V and -2.5V ref That is, the control signal is turned on; S23, reference voltage V ref Performing pressurization and decompression respectively to obtain a pressurization signal and a decompression signal; S24, input the pressure-increasing signal and the delayed driving signal of the power device S6 to the inverting input terminal and the non-inverting input terminal of the first high-speed comparator respectively, and the output terminal of the first high-speed comparator is connected to the driving circuit of the power device S6; input the pressure-reducing signal and the delayed driving signal of the power device S2 to the inverting input terminal and the non-inverting input terminal of the second high-speed comparator respectively, and the output terminal of the second high-speed comparator is connected to the driving circuit of the power device S2; The outputs of S25, the driving circuit of the power device S6 and the driving circuit of the power device S2 act on the power device S6 and the power device S2 to turn them on.

3. The low-loss switching method of a three-level ANPC inverter according to claim 2, characterized in that: In the step S1 , a delay circuit is added between the driving signals of the power devices S2 and S6 and the ground to delay the driving signals of the power devices S2 and S6 .

4. The low-loss switching method of a three-level ANPC inverter according to claim 3, characterized in that: In step S21, two voltages of +2.5V and -2.5V are generated by passing the auxiliary power supply through a positive DC-DC circuit and a negative DC-DC circuit respectively.

5. The low-loss switching method of a three-level ANPC inverter according to claim 3, characterized in that: In step S22, by connecting +2.5V and -2.5V voltages to the two ends of the adjustable resistor, the adjustable resistor outputs a reference voltage V ref .

6. The low-loss switching method of a three-level ANPC inverter according to claim 3, characterized in that: In step S23, the reference voltage V ref Through the adding circuit, the output is connected to the inverting input terminal of the first high-speed comparator; the reference voltage V ref The output is connected to the inverting input terminal of the second high-speed comparator through the subtraction circuit; the inputs of the inverting input terminals of the first high-speed comparator and the second high-speed comparator are freely variable between 0 and 5V.

7. The low-loss switching method of a three-level ANPC inverter according to claim 3, characterized in that: During commutation, in step S2, the overall loss includes turn-on loss, conduction loss and turn-off loss; the voltage and current at both ends of power devices S2 and S6 have overlapping areas, causing turn-on loss; when power devices S2 and S6 are turned on, conduction loss will be caused in power devices S2, S3, S5 and S6; when power devices S2 and S6 are turned off, S6 bears all turn-off losses.

8. The low-loss switching method of a three-level ANPC inverter according to claim 7, characterized in that: The turn-on loss is obtained by obtaining the drain current and drain-source voltage waveforms of the power devices S2 and S6, and then integrating the product of the current and voltage during the turn-on time. The turn-on loss of the power device is obtained by integrating the power device current during the conduction time and multiplying the integral by twice the on-resistance. For the turn-off loss, the calculation process is the same as the turn-on loss calculation process.

9. The low-loss switching method of a three-level ANPC inverter according to claim 1, characterized in that: In step S2, the relationship among the working current, the opening control signal and the overall loss is obtained by function fitting.

10. A low-loss switching system for a three-level ANPC inverter, applied to a low-loss switching method for a three-level ANPC inverter according to any one of claims 1 to 9, characterized in that: The invention comprises a driving signal regulating circuit, a loss calculating module, a relationship fitting module and a current measuring module. The driving signal regulating circuit comprises a delay module and an opening control signal module. The delay module is used to execute step S1. The opening control signal module is used to realize that under different working currents, the inverter switches from power device S2 turning on ahead of power device S6 to power device S6 turning on ahead of power device S2 through an opening control signal. The loss calculating module is used to realize that the overall loss of the inverter under different working currents is calculated in step S2. The relationship fitting module is used to execute that the relationship among the working current, the opening control signal and the overall loss is obtained in step S2. The current measuring module is used to realize that the working current of the inverter is detected in real time in step S3. The relationship fitting module is also used to realize that according to the working current and the relationship among the working current, the opening control signal and the overall loss, the optimal opening control signal corresponding to the working current when the overall loss is the smallest is obtained and given to the opening control signal module in step S3. The opening control signal module is also used to realize that step S4.

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