Fully differential amplifier and electronic device

Abstract

The invention discloses a fully differential amplifier and electronic equipment, the fully differential amplifier comprises a first single-ended amplification link and a second single-ended amplification link, in the first single-ended amplification link, the grid electrode of a first MOS transistor is coupled with the input end of the first single-ended amplification link, and the drain electrode of the first MOS transistor is coupled with the source electrode of a second MOS transistor and the source electrode of a fifth MOS transistor; the drain electrode of the second MOS tube is coupled with the drain electrode of the third MOS tube, and a second bias voltage is input into the grid electrode of the second MOS tube; a source electrode of the third MOS transistor is coupled with a drain electrode of the fourth MOS transistor, a first bias voltage is input into a grid electrode of the third MOS transistor, and a drain electrode of the third MOS transistor is coupled with an output end of the first single-ended amplification link; the source electrode of the fourth MOS transistor inputs the power supply voltage, and the drain electrode of the fourth MOS transistor is coupled with the input end of the first single-ended amplification link; a second bias voltage is input into the grid electrode of the fifth MOS tube, and the drain electrode of the fifth MOS tube is coupled with the drain electrode of the sixth MOS tube and the input end of the first single-ended amplification link; and the grid electrode of the sixth MOS tube inputs the first bias voltage, and the source electrode of the sixth MOS tube is coupled with the drain electrode of the fourth MOS tube. According to the scheme, the noise generated by the first MOS transistor can be effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a fully differential amplifier and electronic equipment. Background Art

[0002] In wireless communication systems, low noise amplifiers (LNAs) are important components of receivers. Low noise amplifiers are usually located below the antenna of the receiver to amplify the weak electrical signals received by the antenna.

[0003] The characteristics of the low noise amplifier directly affect the quality of the received signal of the receiver. The low noise amplifier needs to have a low noise figure and low distortion. The existing fully differential low power noise amplifier has a large noise. Summary of the invention

[0004] An object of the present invention is at least to provide a fully differential amplifier with lower noise.

[0005] In a first aspect, the present invention provides a fully differential amplifier, comprising: a first single-ended amplification link and a second single-ended amplification link, wherein: the first single-ended amplification link comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube and a sixth MOS tube, wherein: the first MOS tube, its gate is coupled to the input end of the first single-ended amplification link, its source is grounded, and its drain is coupled to the source of the second MOS tube and the source of the fifth MOS tube; the second MOS tube, its drain is coupled to the drain of the third MOS tube, and its gate is connected to the input end of the first single-ended amplification link; The third MOS tube has a source coupled to the drain of the fourth MOS tube, a gate inputting the first bias voltage, and a drain coupled to the output end of the first single-ended amplification link; the fourth MOS tube has a source inputting the power supply voltage, and a drain coupled to the input end of the first single-ended amplification link; the fifth MOS tube has a gate inputting the second bias voltage, and a drain coupled to the drain of the sixth MOS tube and the input end of the first single-ended amplification link; the sixth MOS tube has a gate inputting the first bias voltage, and a source coupled to the drain of the fourth MOS tube.

[0006] By providing the fifth MOS tube, the noise of the first MOS tube can be fed back to the gate of the first MOS tube through the fifth MOS tube, and then amplified and reversed through the first MOS tube, so that the noise generated by the first MOS tube can be effectively offset, thereby reducing the noise of the fully differential amplifier and improving the performance of the fully differential amplifier.

[0007] Optionally, the fully differential amplifier further includes: a first feedback resistor; the first feedback resistor is coupled to the output end of the first single-ended amplification link.

[0008] Optionally, the fully differential amplifier further includes: a first feedback resistor; the first feedback resistor is coupled between the drain of the fifth MOS tube and the input end of the first single-ended amplification link.

[0009] The first feedback resistor is arranged between the drain of the fifth MOS tube and the input end of the first single-ended amplification link to achieve isolation between the first feedback resistor and the load of the first single-ended amplification link. When the load of the first single-ended amplification link changes, it will not affect the first feedback resistor, thereby achieving impedance matching.

[0010] Optionally, the fully differential amplifier further includes: a first capacitor coupled between the input end of the first single-ended amplification link and the gate of the fourth MOS tube.

[0011] Optionally, the second single-ended amplification link includes a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube and a twelfth MOS tube, wherein: the seventh MOS tube has a gate coupled to the input end of the first single-ended amplification link, a source connected to ground, and a drain coupled to the source of the eighth MOS tube and the source of the eleventh MOS tube; the eighth MOS tube has a drain coupled to the drain of the ninth MOS tube, and a gate inputs a second bias voltage; the ninth MOS tube has a source connected to the ground, and a drain coupled to the source of the eighth MOS tube and the source of the eleventh MOS tube; the eighth MOS tube has a drain coupled to the drain of the ninth MOS tube, and a gate inputs a second bias voltage; the ninth MOS tube has a source connected to the ground, and a drain coupled to the drain of the ninth MOS tube; The drain of the tenth MOS tube is coupled, the gate thereof inputs the first bias voltage, and the drain thereof is coupled to the output end of the first single-ended amplification link; the source of the tenth MOS tube inputs the power supply voltage, and the drain thereof is coupled to the input end of the first single-ended amplification link; the gate of the eleventh MOS tube inputs the second bias voltage, and the drain thereof is coupled to the drain of the twelfth MOS tube and the input end of the first single-ended amplification link; the gate of the twelfth MOS tube inputs the first bias voltage, and the source thereof is coupled to the drain of the tenth MOS tube.

[0012] By providing the eleventh MOS tube, the noise of the seventh MOS tube can be fed back to the gate of the seventh MOS tube through the eleventh MOS tube, and then amplified and reversed through the seventh MOS tube, so that the noise generated by the seventh MOS tube can be effectively offset, thereby reducing the noise of the fully differential amplifier and improving the performance of the fully differential amplifier.

[0013] Optionally, the fully differential amplifier further includes: a second feedback resistor; the second feedback resistor is coupled to the output end of the second single-ended amplification link.

[0014] Optionally, the fully differential amplifier further includes: a second feedback resistor; the second feedback resistor is coupled between the drain of the eleventh MOS tube and the input end of the second single-ended amplification link.

[0015] The second feedback resistor is arranged between the drain of the eleventh MOS tube and the input end of the second single-ended amplification link to achieve isolation between the second feedback resistor and the load of the second single-ended amplification link. When the load of the second single-ended amplification link changes, it will not affect the second feedback resistor, thereby achieving impedance matching.

[0016] Optionally, the fully differential amplifier further includes: a second capacitor coupled between the output end of the first single-ended amplification link and the gate of the tenth MOS tube.

[0017] Optionally, the fully differential amplifier also includes: a common-mode suppression circuit, whose first input end is coupled to the output end of the first single-ended amplification link and the output end of the second single-ended amplification link, whose second input end inputs a preset reference voltage, and whose output end is coupled to the input end of the first single-ended amplification link and the second single-ended amplification link.

[0018] In a second aspect, the present invention further provides an electronic device, comprising any one of the fully differential amplifiers described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a structural schematic diagram of a first single-ended amplification link in an embodiment of the present invention;

[0020] Figure 2 is a structural schematic diagram of another first single-ended amplification link in an embodiment of the present invention;

[0021] Figure 3 is a structural schematic diagram of a second single-ended amplification link in an embodiment of the present invention;

[0022] Figure 4 is a structural schematic diagram of another first single-ended amplification link in an embodiment of the present invention;

[0023] Figure 5 is a schematic structural diagram of a fully differential amplifier in an embodiment of the present invention;

[0024] Figure 6 It is a schematic diagram of the structure of another fully differential amplifier in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] As described in the above background technology, the existing fully differential low power noise amplifier has relatively large noise.

[0026] In the embodiment of the present invention, by providing the fifth MOS tube, the noise of the first MOS tube can be fed back to the gate of the first MOS tube through the fifth MOS tube, and then amplified and reversed through the first MOS tube, so that the noise generated by the first MOS tube can be effectively offset, thereby reducing the noise of the fully differential amplifier and improving the performance of the fully differential amplifier.

[0027] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0028] An embodiment of the present invention provides a fully differential amplifier, which may include: a first single-ended amplification link and a second single-ended amplification link.

[0029] In some embodiments, the first single-ended amplification link may be a forward amplification link, and the second single-ended amplification link may be a reverse amplification link.

[0030] In some other embodiments, the first single-ended amplification link is a reverse amplification link, and the second single-ended amplification link is a forward amplification link.

[0031] Reference Figure 1 , a schematic structural diagram of a first single-ended amplification link in an embodiment of the present invention is given.

[0032] In a specific implementation, the first single-ended amplification link may include a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5 and a sixth MOS transistor M6, wherein:

[0033] The first MOS tube M1, the second MOS tube M2, the third MOS tube M3 and the fourth MOS tube M4 are connected in series to form a first main channel; the fifth MOS tube M5 and the sixth MOS tube M6 are connected in series to form a first auxiliary channel.

[0034] In a specific implementation, the gate of the first MOS transistor M1 can be coupled to the input end of the first single-ended amplifier link, and the first differential input voltage V INP ; The source of the first MOS tube M1 is grounded; The drain of the first MOS tube M1 is coupled to the source of the second MOS tube M2 and the source of the fifth MOS tube M5;

[0035] The gate of the second MOS tube M2 inputs a preset second bias voltage V BP , the drain of the second MOS tube M2 is coupled to the drain of the third MOS tube M3 and the output end of the first single-ended amplification link;

[0036] The gate of the third MOS tube M3 inputs the first bias voltage V BN , the source of the third MOS tube M3 is coupled to the source of the fourth MOS tube M4 and the output end of the first single-ended amplification link;

[0037] A gate of the fourth MOS transistor M4 is coupled to the input end of the first single-ended amplification link, and a source of the fourth MOS transistor M4 is input with a power supply voltage VDD.

[0038] The output end of the first single-ended amplifier link outputs a first differential output voltage V OUTN .

[0039] It can be seen that one end of the first main channel is connected to the power supply voltage VDD, and the other end of the first main channel is grounded. The input of the first main channel is the input of the first single-ended amplifier link (that is, the first differential input voltage V INP ).

[0040] The gate of the fifth MOS tube M5 is input with the first bias voltage V BN , the drain of the fifth MOS tube M5 is coupled to the drain of the sixth MOS tube M6;

[0041] The gate of the sixth MOS tube M6 inputs the second bias voltage V BP , the source of the sixth MOS tube M6 is coupled to the source of the fourth MOS tube M4.

[0042] It can be seen that in the first auxiliary channel, the fifth MOS transistor M5 and the sixth MOS transistor M6 are connected in series, and their structures are symmetrical with those of the second MOS transistor M2 and the third MOS transistor M3 in the first main channel.

[0043] In some embodiments, the first MOS transistor M1 , the second MOS transistor M2 , and the fifth MOS transistor M5 are NMOS transistors, and the third MOS transistor M3 , the fourth MOS transistor M4 , and the sixth MOS transistor M6 are PMOS transistors.

[0044] In a specific implementation, the first bias voltage V BN may not be equal to the second bias voltage V BP The first bias voltage V BN With the second bias voltage V BP The specific value of can be preset.

[0045] In specific applications, it can be known that in a fully differential amplifier, the first MOS tube M1 contributes the most to the noise of the fully differential amplifier. By providing the fifth MOS tube M5, the noise of the first MOS tube M1 can be fed back to the gate of the first MOS tube M1 through the fifth MOS tube M5, and then amplified and reversed again through the first MOS tube M1, thereby effectively offsetting the noise generated by the first MOS tube M1, thereby reducing the noise of the fully differential amplifier and improving the performance of the fully differential amplifier.

[0046] In the embodiment of the present invention, the first single-ended amplification link may further include a first feedback resistor RF1.

[0047] In a specific implementation, the resistance value of the first feedback resistor RF1 is related to the antenna impedance of the electronic device. Usually, the antenna impedance of the electronic device is 50 ohms, so the resistance value of the first feedback resistor RF1 can be 50 ohms.

[0048] In some embodiments, the first feedback resistor RF1 may be coupled to the output end of the first single-ended amplification link. Figure 1 shown.

[0049] In a specific implementation, when the first feedback resistor RF1 is coupled to the output end of the first single-ended amplifier link, if the load of the first single-ended amplifier link changes, the impedance of the first main channel will change, which will in turn affect the first feedback resistor RF1, making it difficult to achieve impedance matching.

[0050] In order to avoid the first feedback resistor RF1 being affected, in an embodiment of the present invention, the first feedback resistor RF1 may be arranged between the drain of the fifth MOS tube M5 and the input end of the first single-ended amplification link. Thus, the first feedback resistor RF1 is isolated from the load of the first single-ended amplification link. When the load of the first single-ended amplification link changes, since the voltages of the fifth MOS tube M5 and the sixth MOS tube M6 do not change with the load of the first single-ended amplification link, the change in the load of the first single-ended amplification link will not affect the first feedback resistor RF1, thereby achieving impedance matching.

[0051] Reference Figure 2 , a schematic diagram of the structure of another fully differential amplifier in an embodiment of the present invention is given. Figure 2 In the embodiment, a first end of the first feedback resistor RF1 is coupled to the drain of the fifth MOS transistor M5 and the drain of the sixth MOS transistor M6, and a second end of the first feedback resistor RF1 is coupled to the input end of the first single-ended amplification link.

[0052] In a specific implementation, the first single-ended amplification link may further include a first capacitor C1 , and the first capacitor C1 may be coupled between the input end of the first single-ended amplification link and the gate of the fourth MOS transistor M4 .

[0053] In the embodiment of the present invention, for the second single-ended amplification link, its structure may be similar to Figure 1 The first single-ended amplifier link provided in Figure 3 , a schematic diagram of the structure of another fully differential amplifier in an embodiment of the present invention is given.

[0054] In a specific implementation, the second single-ended amplification link may include a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, and a twelfth MOS transistor M12, wherein:

[0055] The seventh MOS tube M7 , the eighth MOS tube M8 , the ninth MOS tube M9 and the tenth MOS tube M10 are connected in series to form a second main channel; the eleventh MOS tube M11 and the twelfth MOS tube M12 are connected in series to form a second auxiliary channel.

[0056] In a specific implementation, the gate of the seventh MOS transistor M7 can be coupled to the input end of the second single-ended amplification link, and the second differential input voltage V INN ; The source of the seventh MOS tube M7 is grounded; The drain of the seventh MOS tube M7 is coupled to the source of the eighth MOS tube M8 and the source of the eleventh MOS tube M11;

[0057] The gate of the eighth MOS tube M8 is input with a preset second bias voltage V BP , the drain of the eighth MOS tube M8 is coupled to the drain of the ninth MOS tube M9 and the output end of the second single-ended amplification link;

[0058] The gate of the ninth MOS tube M9 inputs the first bias voltage V BN , the source of the ninth MOS tube M9 is coupled to the source of the tenth MOS tube M10 and the output end of the second single-ended amplification link;

[0059] The gate of the tenth MOS transistor M10 is coupled to the input end of the second single-ended amplification link, and the source of the tenth MOS transistor M10 is input with the power supply voltage VDD.

[0060] It can be seen that one end of the second main channel is connected to the power supply voltage VDD, and the other end of the second main channel is grounded. The input of the second main channel is the input of the second single-ended amplifier link (that is, the second differential input voltage V INN ).

[0061] The gate of the eleventh MOS tube M11 is input with the first bias voltage V BN , the drain of the eleventh MOS tube M11 is coupled to the drain of the twelfth MOS tube M12;

[0062] The gate of the twelfth MOS tube M12 inputs the second bias voltage V BP , the source of the twelfth MOS tube M12 is coupled to the source of the tenth MOS tube M10.

[0063] It can be seen that in the second auxiliary channel, the eleventh MOS transistor M11 and the twelfth MOS transistor M12 are connected in series, and their structures are symmetrical with those of the eighth MOS transistor M8 and the ninth MOS transistor M9 in the second main channel.

[0064] In some embodiments, the seventh MOS transistor M7 , the eighth MOS transistor M8 , and the eleventh MOS transistor M11 are NMOS transistors, and the ninth MOS transistor M9 , the tenth MOS transistor M10 , and the twelfth MOS transistor M12 are PMOS transistors.

[0065] In specific applications, it can be known that in the fully differential amplifier, the seventh MOS tube M7 contributes the most to the noise of the fully differential amplifier. By providing the eleventh MOS tube M11, the noise of the seventh MOS tube M7 can be fed back to the gate of the seventh MOS tube M7 through the eleventh MOS tube M11, and then amplified and reversed again through the seventh MOS tube M7, so that the noise generated by the seventh MOS tube M7 can be effectively offset, thereby reducing the noise of the fully differential amplifier and improving the performance of the fully differential amplifier.

[0066] In the embodiment of the present invention, the second single-ended amplification link may further include a second feedback resistor RF2.

[0067] In a specific implementation, similar to the first feedback resistor RF1, the resistance of the second feedback resistor RF2 is also related to the antenna impedance of the electronic device. Usually, the antenna impedance of the electronic device is 50 ohms, so the resistance of the second feedback resistor RF2 can be 50 ohms.

[0068] In some embodiments, the second feedback resistor RF2 may be coupled to the output end of the second single-ended amplification link. Figure 3 shown.

[0069] In a specific implementation, when the second feedback resistor RF2 is coupled to the output end of the second single-ended amplification link, if the load of the second single-ended amplification link changes, the impedance of the second main channel will change, which will in turn affect the second feedback resistor RF2, making it difficult to achieve impedance matching.

[0070] In order to avoid the second feedback resistor RF2 being affected, in an embodiment of the present invention, the second feedback resistor RF2 may be arranged between the drain of the eleventh MOS tube M11 and the input end of the second single-ended amplification link. Thus, the second feedback resistor RF2 is isolated from the load of the second single-ended amplification link. When the load of the second single-ended amplification link changes, since the voltages of the eleventh MOS tube M11 and the twelfth MOS tube M12 do not change with the load of the second single-ended amplification link, the change in the load of the second single-ended amplification link will not affect the second feedback resistor RF2, thereby achieving impedance matching.

[0071] Reference Figure 4 , a schematic diagram of the structure of another fully differential amplifier in an embodiment of the present invention is given. Figure 4 In the embodiment, a first end of the second feedback resistor RF2 is coupled to the drain of the eleventh MOS transistor M11 and the drain of the twelfth MOS transistor M12, and a second end of the second feedback resistor RF2 is coupled to the input end of the second single-ended amplification link.

[0072] In a specific implementation, the second single-ended amplification link may further include a second capacitor C1 , and the second capacitor C1 may be coupled between the input end of the second single-ended amplification link and the gate of the tenth MOS transistor M10 .

[0073] like Figure 1 to Figure 4 As shown in , for a fully differential amplifier, a first auxiliary channel corresponding to the first main channel may be set only for the first single-ended amplification link to reduce the noise of the first single-ended amplification link, thereby reducing the noise of the fully differential amplifier to a certain extent. Alternatively, a second auxiliary channel corresponding to the second main channel may be set only for the second single-ended amplification link to reduce the noise of the second single-ended amplification link, thereby reducing the noise of the fully differential amplifier to a certain extent.

[0074] In the embodiment of the present invention, Figure 1 and Figure 2 The first single-ended amplification link provided in Figure 3-4 In the fully differential amplifier obtained after the combination, the first single-ended amplification link includes a first main channel and a first auxiliary channel, and the second single-ended amplification link includes a second main channel and a second auxiliary channel.

[0075] Reference Figure 5 , a schematic diagram of the structure of another fully differential amplifier circuit in an embodiment of the present invention is given. Figure 5 The structure of the first single-ended amplifier link can refer to Figure 1 The structure of the first single-ended amplification link provided in the embodiment of the present invention can refer to the structure of the second single-ended amplification link provided in the embodiment of the present invention. Figure 3 The structure of the second single-ended amplification link provided in.

[0076] Reference Figure 6 , a structural schematic diagram of another fully differential amplifier circuit in an embodiment of the present invention is given. Figure 6 The structure of the first single-ended amplifier link can refer to Figure 2 The structure of the first single-ended amplification link provided in the embodiment of the present invention can refer to the structure of the second single-ended amplification link provided in the embodiment of the present invention. Figure 4 The structure of the second single-ended amplification link provided in.

[0077] In a specific implementation, the fully differential amplifier may further include a common mode suppression circuit (CMFB). A first input terminal of the common mode suppression circuit is coupled to an output terminal of the first single-ended amplification link and an output terminal of the second single-ended amplification link, and a second input terminal of the common mode suppression circuit inputs a preset reference voltage V REF The output end of the common mode suppression circuit is coupled to the input end of the first single-ended amplification link and the input end of the second single-ended amplification link respectively.

[0078] like Figure 5As shown, the first input terminal of CMFB is coupled to the output terminal of the first single-ended amplification link through the first resistor R1, and is coupled to the output terminal of the second single-ended amplification link through the second resistor R2, and the second input terminal of CMFB inputs a preset reference voltage V REF The output end of CMFB is coupled to the second end of the first capacitor C1 through the third resistor R3 and to the second end of the second capacitor C2 through the fourth resistor R4.

[0079] Accordingly, in Figure 6 In the embodiment, the connection relationship between CMFB and the first single-ended amplification link and the second single-ended amplification link is Figure 5 The same, no further description is given here. Figure 1 to Figure 4 Although CMFB is not provided, you can directly refer to it when CMFB is set. Figure 5 The connection relationship of CMFB.

[0080] A first differential output voltage output by the first single-ended amplification link and a second differential output voltage output by the second single-ended amplification link are clamped by a common-mode suppression circuit.

[0081] An embodiment of the present invention further provides an electronic device, comprising the fully differential amplifier provided by any of the above embodiments.

[0082] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A fully differential amplifier, characterized in that: include: A first single-ended amplification link and a second single-ended amplification link, wherein: The first single-ended amplification link includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor and a sixth MOS transistor, wherein: The first MOS transistor has a gate coupled to the input end of the first single-ended amplification link, a source connected to the ground, and a drain coupled to the source of the second MOS transistor and the source of the fifth MOS transistor; The second MOS tube has a drain coupled to the drain of the third MOS tube, and a gate input with a second bias voltage; The third MOS transistor has a source coupled to the drain of the fourth MOS transistor, a gate inputting a first bias voltage, and a drain coupled to the output end of the first single-ended amplification link; The fourth MOS tube has a source terminal inputting a power supply voltage and a drain terminal coupled to an input terminal of the first single-ended amplification link; The fifth MOS transistor has a gate inputting the second bias voltage, and a drain coupled to the drain of the sixth MOS transistor and the input end of the first single-ended amplification link; The gate of the sixth MOS tube is input with the first bias voltage, and the source of the sixth MOS tube is coupled with the drain of the fourth MOS tube.

2. The fully differential amplifier according to claim 1, wherein: Also includes: A first feedback resistor; The first feedback resistor is coupled to an output end of the first single-ended amplification link.

3. The fully differential amplifier according to claim 1, wherein: Also includes: A first feedback resistor; The first feedback resistor is coupled between the drain of the fifth MOS tube and the input end of the first single-ended amplification link.

4. The fully differential amplifier according to claim 1, wherein: Also includes: The first capacitor is coupled between the input end of the first single-ended amplification link and the gate of the fourth MOS tube.

5. The fully differential amplifier according to any one of claims 1 to 4, characterized in that: The second single-ended amplification link includes a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor and a twelfth MOS transistor, wherein: The seventh MOS transistor has a gate coupled to the input end of the first single-ended amplification link, a source connected to the ground, and a drain coupled to the source of the eighth MOS transistor and the source of the eleventh MOS transistor; The eighth MOS tube has a drain coupled to the drain of the ninth MOS tube, and a gate input with a second bias voltage; The ninth MOS transistor has a source coupled to the drain of the tenth MOS transistor, a gate inputting a first bias voltage, and a drain coupled to the output end of the first single-ended amplification link; The tenth MOS transistor has a source electrode inputting a power supply voltage and a drain electrode coupled to the input end of the first single-ended amplification link; The eleventh MOS transistor has a gate inputting the second bias voltage, and a drain coupled to the drain of the twelfth MOS transistor and the input end of the first single-ended amplification link; The gate of the twelfth MOS tube is input with the first bias voltage, and the source of the twelfth MOS tube is coupled with the drain of the tenth MOS tube.

6. The fully differential amplifier according to claim 5, wherein: Also includes: A second feedback resistor; The second feedback resistor is coupled to an output end of the second single-ended amplification link.

7. The fully differential amplifier according to claim 5, wherein: Also includes: A second feedback resistor; The second feedback resistor is coupled between the drain of the eleventh MOS tube and the input end of the second single-ended amplification link.

8. The fully differential amplifier according to claim 5, wherein: Also includes: The second capacitor is coupled between the output end of the first single-ended amplification link and the gate of the tenth MOS transistor.

9. The fully differential amplifier according to claim 1, wherein: Also includes: A common-mode suppression circuit, wherein a first input terminal is coupled to the output terminal of the first single-ended amplification link and the output terminal of the second single-ended amplification link, a second input terminal inputs a preset reference voltage, and an output terminal is coupled to the input terminal of the first single-ended amplification link and the input terminal of the second single-ended amplification link.

10. An electronic device, characterized in that: A fully differential amplifier comprising the fully differential amplifier according to any one of claims 1 to 9.

Images