Orthogonal transformation method and system for high-speed parallel digital signals

Abstract

The invention discloses an orthogonal transformation method and system for high-speed parallel digital signals, and the method comprises the steps: obtaining a current signal, and calculating a frequency mixing local oscillation value corresponding to each path according to the number of parallel paths of the current signal; calculating an in-phase component and a quadrature component of the current signal, and multiplying each path of the in-phase component and the quadrature component by a corresponding frequency mixing local oscillation value for frequency mixing; filtering coefficients of the half-band filter are alternately extracted to serve as filtering coefficients of an in-phase component and a quadrature component, a multi-phase filtering optimization structure is derived according to the number of parallel paths of the quadrature component, the quadrature component is filtered through the multi-phase filtering optimization structure, each path of the in-phase component is multiplied by the corresponding filtering coefficient, time delay is carried out, and the in-phase component and the quadrature component are obtained. Therefore, filtering of in-phase components is completed, and filtering results of orthogonal components are synchronized. According to the invention, orthogonal transformation can be carried out on any high-speed digital signal, and consumption of chip resources is reduced through selection of filter coefficients and optimization of a multi-phase parallel filtering structure.

Description

Technical Field

[0001] The present invention relates to electronic information technology, and in particular to a method and system for orthogonal transformation of high-speed parallel digital signals. Background Art

[0002] Signal orthogonal transformation in electronic information technology (i.e., transforming RF signals into baseband in-phase and quadrature components) plays an extremely important role in signal processing. The in-phase and quadrature components are obtained by digital orthogonal transformation. This direct digital orthogonal transformation technology can realize functions below the intermediate frequency by software on the one hand, and solve the matching problem between channels on the other hand.

[0003] With the rapid development of digital signal processing technology and the improvement of receiver signal processing capabilities, the demand for high-speed signal processing is increasing. Similarly, for the orthogonal transformation of signals, the processing requirements have exceeded 1GHz. As a general hardware platform, the field programmable logic array (FPGA) cannot directly perform digital orthogonal transformation at a rate exceeding 1GHz, although its device has a maximum operating frequency of more than 500MHz. Therefore, in order to implement digital orthogonal transformation with high-speed operation in FPGA, only a parallel structure can be used, which consumes more resources to reduce the operating frequency of FPGA. Summary of the invention

[0004] The technical problem to be solved by the present invention is to reduce the consumption of chip resources.

[0005] In view of the above problems in the prior art, a method and system for orthogonal transformation of high-speed parallel digital signals are provided, which can perform orthogonal transformation on any high-speed digital signal and reduce the consumption of chip resources by selecting filter coefficients and optimizing the multi-phase parallel filtering structure.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A high-speed parallel digital signal orthogonal transformation method comprises the following steps:

[0008] Obtain the current signal, and calculate the mixing local oscillator value corresponding to each path according to the number of parallel paths of the current signal;

[0009] Calculate the in-phase component and the quadrature component of the current signal, multiply each in-phase component by the corresponding mixing local oscillator value, and multiply each quadrature component by the corresponding mixing local oscillator value;

[0010] The filter coefficients of the half-band filter are alternately extracted as the filter coefficients of the in-phase component and the orthogonal component respectively. The multi-phase filtering optimization structure is derived according to the parallel paths of the orthogonal component, and the multi-phase filtering optimization structure is used to filter the orthogonal component. Each path of the in-phase component is multiplied by the corresponding filter coefficient and delayed to complete the filtering of the in-phase component and synchronize the filtering results of the orthogonal component.

[0011] Furthermore, when calculating the mixing local oscillator value corresponding to each path according to the parallel paths of the current signal, it includes: serially converting and transforming the mixing local oscillator signal according to the parallel paths of the mixed current signal, so that the mixing local oscillator value corresponding to each path is a fixed value.

[0012] Furthermore, when calculating the in-phase component and the orthogonal component of the current signal, it includes: performing odd-even cross extraction on the current signal to obtain an even index sequence as the in-phase component, and at the same time obtain an odd index sequence as the orthogonal component, and staggering the in-phase component and the orthogonal component by one sampling delay.

[0013] Furthermore, when the multi-phase filter optimization structure is derived according to the number of parallel paths of the orthogonal components, it includes:

[0014] Calculate the z-domain expression of each parallel filtering result output of the orthogonal component;

[0015] The z-domain expression of each parallel filtering result output is decomposed into polynomials to reuse the same sub-filter results and obtain a multi-phase filtering optimization structure.

[0016] Furthermore, the z-domain expression of each parallel filtering result output is as follows:

[0017]

[0018] Among them, Y k represents the z-domain expression of the k-th parallel filtering result output, H i is the z-domain expression of the i-th filter, X i is the z-domain expression of the i-th signal, z -L is the L beats at the delayed intermediate frequency sampling rate, and L is the number of parallel filtering paths.

[0019] Furthermore, when the z-domain expression of each parallel filtering result output is subjected to polynomial decomposition, it includes:

[0020] Substitute the z-domain expression of each parallel filtering result output into the z-domain expression of the final filtered output signal after multi-channel combination and perform derivation and evolution. According to the derivation and evolution result, rewrite the z-domain expression of each parallel filtering result output corresponding to the z-domain expression of the parallel filtering result output.

[0021] Furthermore, the number of parallel paths of the orthogonal components is 8, and the polyphase filter optimization structure expression is as follows:

[0022] Y0=X0H0+z -8 (X 1357 H 1357 +X 26 H 26 )+z -8 (X1H1+X3H3+X4H4)#+z -8 (H5H5+X7H7-X 13 H 13 )+z -8 (-X 15 H 15 -X 37 H 37 )+z -8 (-X 57 H 57 -X2H2-X6H6)

[0023] Y1=(X 01 H 01 -X0H0-X1H1)+z -8 X3H3+z -8 (X 2367 h 2367 +X 45 H 45 +X2H2)+z -8 (X6H6+X7H7-X 23 H 23 -X 26 H 26 )+z -8 (-X 37 H 37 -X 67 H 67 -X4H4-X5H5)

[0024] Y2=(X 02 H 02 +X1H1-X0H0-X2H2)+z -8 (X 37 h 37 +X 46 H 46 +X5H5)+z -8 (-X3H3-X4H4-X5H6-X7H7)

[0025] Y3=(X 0123 H 0123 +X0H0+X1H1)+(X2H2+X3H3-X 01 H 01 )+(-X02 H 02 -X 13 H 13 -X 23 H 23 )+z -8 (X 4567 H 4567 +X4H4+X5H5)+z -8 (X6H6+X7H7-X 45 H 45 )+z -8 (-X 46 H 46 -X 57 H 57 -X 67 H 67 )

[0026] Y4=(X 04 H 04 +X 13 H 13 +X2H2)+(-X0H0-X1H1-X1H3-X4H4)+z -8 (X 57 H 57 +X6H6-X5H5-X7H7)

[0027] Y5=(X 0145 H 0145 +X 23 H 23 +X0H0+X1H1)+(X5H5-X 01 H 01 -X 04 H 04 -X 15 H 15 )+(X4H4-X 45 H 45 -X2H2-X3H3)+z -8 (X 67 H 67 -X6H6-X7H7)

[0028] Y6=(X 0246 H 0246 +X 15 H 15 +X0H0)+(X4H4+X6H6-X 02 H 02 -X 04 H 04 )+(-X 26 H 26 -X 46 H 46-X1H1-X5H5)+X3H3+X2H2+z -8 X7H7

[0029] Y7=(X 01234567 H 01234567 +X 01 H 01 +X 02 H 02 +X 04 H 04 +X 13 H 13 +X 15 H 15 )+(X 23 H 23 +X 26 H 26 +X 37 H 37 +X 45 H 45 +X 46 H 46 +x 567 H 57 +X 67 H 67 )+(-X 0123 H 0123 -x 0246 H 0246 -x 0145 H 0145 -x 1357 H 1357 -x 2367 H 2367 -x 4567 H 4567 )+(-X0H0-X1H1-X2H2-X3H3-X4H4-X5H5-X6H6-X7H7)#

[0030] Among them, X abcd The formal parameter is X a +X b +X c +X d The simplified expression of H abcd The formal parameter is H a +H b +H c +H d The simplified expression of X ab The formal parameter is X a +X b The simplified expression of H ab The formal parameter is H a +H bThe simplified expression of , Y0 to Y7 represent the z-domain expression of the output of the 0th to 7th parallel filtering results, H0 to H7 are the z-domain expressions of the 0th to 7th filters, X0 to X7 are the z-domain expressions of the 0th to 7th signals, z -8 is 8 beats at the delayed intermediate frequency sampling rate, and L is the number of parallel filtering paths.

[0031] Furthermore, when the filter coefficients of the half-band filter are alternately extracted as the filter coefficients of the in-phase component and the orthogonal component respectively, the filter coefficient h(2n+1) of the half-band filter is used as the filter coefficient of the channel corresponding to the in-phase component, and the filter coefficient h(2n) of the half-band filter is used as the filter coefficient of the channel corresponding to the orthogonal component, n=0,1,…,N, N is the order of the half-band filter.

[0032] Further, each channel of the in-phase component is multiplied by a corresponding filter coefficient and delayed. Specifically, each channel of the in-phase component is multiplied by 0.5 and then delayed by 1 beat at the intermediate frequency sampling rate.

[0033] The present invention also proposes an orthogonal transformation system for high-speed parallel digital signals, comprising a microprocessor and a computer-readable storage medium connected to each other, wherein the microprocessor is programmed or configured to execute any one of the orthogonal transformation methods for high-speed parallel digital signals.

[0034] Compared with the prior art, the advantages of the present invention are:

[0035] When setting the filter coefficients of the in-phase component and the orthogonal component, the present invention selects a half-band filter to alternately extract the coefficients. Since half of the half-band filter coefficients are 0 and the coefficients are symmetrical around the middle coefficient 0.5, the orthogonal component filtering only needs to be delayed and synchronized with the in-phase component processing time.

[0036] The present invention derives a multi-phase filtering optimization structure according to the number of parallel paths of orthogonal components. Specifically, the z-domain expressions of each parallel filtering result output in the multi-phase parallel filtering expression are respectively decomposed into polynomials, so that the same sub-filter results can be reused. Compared with traditional filtering processing, the use of sub-filters is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a general block diagram of the orthogonal transformation principle under single channel.

[0038] Figure 2 This is the principle block diagram of orthogonal transformation using a multi-phase filtering structure.

[0039] Figure 3 4 is a block diagram of the orthogonal transformation principle of a polyphase filtering structure using half-band filtering coefficients in an embodiment of the present invention.

[0040] Figure 4 The figure is a flow chart of a method according to an embodiment of the present invention.

[0041] Figure 5 This is the overall block diagram of the simulink digital orthogonal transformation of the 8-way parallel polyphase filter structure in the embodiment of the present invention.

[0042] Figure 6 This is a simulink block diagram of Q-path filtering processing in an embodiment of the present invention.

[0043] Figure 7 Schematic diagram of a sub-filter of a multi-phase filtering optimization structure in an embodiment of the present invention.

[0044] Figure 8 X in the embodiment of the present invention 01234567 H 01234567 Schematic diagram of the filter's internal processing.

[0045] Fig. 9 Schematic diagram of the output result of 8-way multi-phase parallel filtering in an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The present invention is further described below in conjunction with the accompanying drawings and specific preferred embodiments, but the protection scope of the present invention is not limited thereby.

[0047] Embodiment 1

[0048] For general digital orthogonalization under single channel, its principle block diagram is as follows Figure 1 As shown in the figure, after the signal is down-converted, it is filtered and extracted to complete the digital orthogonalization. After optimizing the multi-phase filter structure, its principle block diagram is as follows Figure 2 As shown in the figure, when the signal frequency changes by 3 / 4fs, the local oscillator is:

[0049]

[0050] In fact, the imaginary parts are "1, 0, -1, 0...", "0, 1, 0, -1..." respectively. Therefore, when filtering after mixing, half of the samples are invalid. On this basis, according to the characteristics of the signal extraction after filtering, half of the filter coefficients can also be saved. Therefore, the signal and the filter coefficients are cross-extracted first, which is simplified to Figure 2 Medium structure.

[0051] Using half-band filter coefficients, the structure is further optimized to Figure 3 The half-band filter has the characteristics of an even order, a non-zero first coefficient, and an alternating coefficient value of 0, with the middle coefficient being 0.5. Therefore, when the coefficients are extracted alternately, only 0.5 remains in the orthogonal component filter coefficient, and the rest are 0. Finally, the orthogonal component filtering only needs to be delayed and synchronized with the in-phase component processing time.

[0052] Based on the above ideas, this embodiment proposes a high-speed parallel digital signal orthogonal transformation method, such as Figure 4 As shown, the following steps are included:

[0053] S1) obtaining the current signal, and calculating the mixing local oscillator value (1 or -1) corresponding to each path according to the number of parallel paths of the current signal;

[0054] S2) calculating the in-phase component (i.e., I component) and the quadrature component (i.e., Q component) of the current signal, multiplying each of the I and Q components by the corresponding mixing local oscillator value (1 / -1), multiplying each of the in-phase components by the corresponding mixing local oscillator value, and multiplying each of the quadrature components by the corresponding mixing local oscillator value;

[0055] S3) alternately extracting the filter coefficients of the half-band filter as the filter coefficients of the in-phase component and the orthogonal component respectively, deriving a multi-phase filter optimization structure according to the number of parallel paths of the orthogonal component, and using the multi-phase filter optimization structure to filter the orthogonal component, multiplying each path of the in-phase component by the corresponding filter coefficient and delaying it to complete the filtering of the in-phase component and synchronize the filtering results of the orthogonal component.

[0056] In this embodiment, the logic circuit for orthogonal conversion of high-speed parallel digital signals is configured as follows:

[0057] The signal sampling rate is 2400MHz, 16 channels are processed in parallel at 150MHz, the digital frequency conversion intermediate frequency is 1800MHz (3 / 4fs), the half-band filter order N=30 (the number of coefficients is 31), and the stopband attenuation is 55dB. When processing 8 channels of I and Q parallel data of this embodiment, the overall block diagram of the simulink simulation is as follows: Figure 5 Each step is described in detail below in combination with the relevant configuration of this embodiment.

[0058] In step S1 of this embodiment, the multiplication value of each signal is calculated based on the multiplication-free mixing intermediate frequency value and the number of parallel paths of the current signal. Specifically, when the mixing local oscillator value corresponding to each path is calculated based on the number of parallel paths of the current signal, it includes: performing serial conversion and transformation on the mixing local oscillator signal based on the number of parallel paths of the mixing current signal, so that the mixing local oscillator value corresponding to each path is a fixed value. The following is a specific implementation process of serial conversion and transformation:

[0059] Assuming the number of parallel paths is L, the mixed local oscillator signal (-1) nThe samples are assigned to different paths according to index n. The specific assignment rule can be: if the result of taking the sample index n modulo L is k, then the sample will be assigned to the kth path. For example, if the number of parallel paths is 8, the mixing local oscillator value of each path after serial conversion and transformation is as follows:

[0060] Path 1: n=0,8,16,… The corresponding values ​​are 1,1,1,…

[0061] Path 2: n=1,9,17,… The corresponding values ​​are -1,-1,-1,…

[0062] Path 3: n=2,10,18,… The corresponding values ​​are 1,1,1,…

[0063] Path 4: n=3,11,19,… The corresponding values ​​are -1,-1,-1,…

[0064] Path 5: n=4,12,20,… The corresponding values ​​are 1,1,1,…

[0065] Path 6: n=5,13,21,… The corresponding values ​​are -1,-1,-1,…

[0066] Path 7: n=6,14,22,… The corresponding values ​​are 1,1,1,…

[0067] Path 8: n=7,15,23,… The corresponding values ​​are -1,-1,-1,…

[0068] It can be seen that the mixing local oscillator (-1) n After serial-to-parallel conversion, all parallel paths have fixed sample point values, thus eliminating the need for alternate reading of the mixing local oscillator 1 and -1, simplifying the circuit.

[0069] In step S2 of this embodiment, when calculating the in-phase component and the orthogonal component of the current signal, the current signal is extracted twice and divided into an in-phase component and an orthogonal component, and the two parts are staggered by one sampling delay, specifically including:

[0070] Perform odd-even cross extraction on the current signal to obtain the even index sequence x(2n) as the in-phase component, and the odd index sequence x(2n+1) as the orthogonal component, thereby corresponding to Figure 5 The simulation block diagram of Ch1\3..\15_in, Ch2\4..\16 in , stagger the in-phase component and the orthogonal component by one sampling delay.

[0071] Step S3 of this embodiment is intended to filter the in-phase component and the orthogonal component respectively, and when the filter coefficients of the half-band filter are alternately extracted as the filter coefficients of the in-phase component and the orthogonal component respectively, specifically, the filter coefficient j(2n+1) of the half-band filter is used as the filter coefficient of the channel corresponding to the in-phase component, and the filter coefficient h(2n) of the half-band filter is used as the filter coefficient of the channel corresponding to the orthogonal component, n=0,1,…,N, N is the order of the half-band filter.

[0072] For parallel data filtering of the in-phase component, due to the use of a half-band filter, such as Figure 3 As shown in the figure, the effective coefficient of the filter coefficient h(2n+1) of the in-phase component is only 0.5, so the parallel paths of the in-phase component only need to be shifted right by one bit to complete the filtering, and delay one intermediate frequency sampling period (1 / fs). Figure 6 As shown, each channel of the in-phase component is multiplied by the corresponding filter coefficient and delayed. Specifically, each channel of the in-phase component data is multiplied by 0.5 (right shifted by 1 bit), and then delayed by 1 beat at the intermediate frequency sampling rate to process the clock synchronization orthogonal component filtering result. The delay of one beat of the intermediate frequency sampling period (1 / fs) is achieved by staggering the order of the 8 inputs and outputs.

[0073] For parallel data filtering of orthogonal components, this embodiment uses a multi-phase filtering optimization structure derived according to the number of parallel paths and multiplexes sub-filters to complete filtering.

[0074] Specifically, in this embodiment, when filtering 8-channel parallel data of orthogonal components, the specific steps include:

[0075] S31) The expression of the general parallel filtering output in the Z domain is listed in a formula, which is as follows:

[0076]

[0077] Where Y is the z-domain expression of the final filtered output signal after multi-channel combination, Y k represents the z-domain expression of the k-th parallel filtering result output, H i is the z-domain expression of the i-th filter, X i is the z-domain expression of the i-th signal, z -L It can be understood as L beats at the delayed intermediate frequency sampling rate, where L is the number of parallel filtering paths.

[0078] S32) deriving a multi-phase filter optimization structure according to the number of parallel paths of the orthogonal components, including:

[0079] Calculate the z-domain expression of each parallel filtering result output of the orthogonal component. Take 2-way parallel filtering as an example to reflect the idea of ​​optimizing the 8-way parallel filtering structure. According to the z-domain general expression of each channel, the expression of 2-way multi-phase parallel filtering can be obtained as follows:

[0080] Y0=Z -2 H1X1+H0X0#

[0081] Y1=H0X1+H1X0#(2)

[0082] The z-domain expression of each parallel filtering result output is decomposed into polynomials to reuse the same sub-filter results and obtain a multi-phase filtering optimization structure. Specifically, the z-domain expression of each parallel filtering result output calculated by formula (2) is substituted into the z-domain expression Y of the final filtered output signal after multi-channel combination in formula (1) and then deduced and evolved:

[0083] Y=Y0+Z -1 Y1#

[0084] =X0H0+z -1 (X0H1+X1H0)+z -2 X1H1

[0085] =X0H0+z -1 ((H0+H1)(X0+X1)-H0X0-H1X1)+z -2 X1H1#(3)

[0086] According to the derivation results, rewrite the z-domain expression of the corresponding parallel filtering result output in the z-domain expression of each parallel filtering result output:

[0087] Y0=Z -2 H1X1+H0X0#

[0088] Y1=(H0+H1)(X0+X1)-H0X0-H1X1#(4)

[0089] From the above formula, we can find that the parallel 2-way output Y1 and Y0 have the same sub-filter results H0X0, H1X1, so the filtering results of this part can be reused, and the remaining filtering result is (H0+H1)(X0+X1). Compared with the traditional filtering process, it requires four groups of sub-filters H1X1, H0X0, H0X1, H1X0, which reduces the use of one group of sub-filters.

[0090] Similarly, the z-domain expression of each parallel filtering result output in the 8-way multi-phase parallel filtering expression can be decomposed into polynomials to obtain the polyphase filtering optimization structure expression when the number of parallel paths of the orthogonal component is 8:

[0091] Y0=X0H0+z -8 (X 1357 H 1357 +X 26 H 26 )+z-8 (X1H1+X3H3+X4H4)#+z -8 (X5H5+X7H7-X 13 H 13 )+z -8 (−X 15 H 15 -X 37 H 37 )+z -8 (−X 57 H 57 -X2H2-X6H6)

[0092] Y1=(X 01 H 01 -X0H0-X3H1)+z -8 X3H3+z -8 (X 2367 h 2367 +X 45 H 45 +X2H2)+z -8 (X6H6+X7H7-X 23 H 23 -X 26 H 26 )+z -8 (−X 37 H 37 -X 67 H 67 -X4H4-X5H5)

[0093] Y2=(X 02 H 02 +X1H1-X0H0-X2H2)+z -8 (X 37 h 37 +X 46 H 46 +X5H5)+z -8 (-X3H3-X4H4-X6H6-X7H7)

[0094] Y3=(X 0123 H 0123 +X0H0+X1H1)+(X2H2+X3H3-X 01 H 01 )+(−X 02 H 02 -X 13 H 13 -X 23 H 23 )+z -8 (X 4567 H 4567 +X4H4+X5H5)+z-8 (X6H6+X7H7-X 45 H 45 )+z -8 (-X 46 H 46 -X 57 H 57 -X 67 H 67 )

[0095] Y4=(X 04 H 04 +X 13 H 13 +X2H2)+(-X0H0-X1H1-X3H3-X4H4)+z -8 (X 57 H 57 +X6H6-X5H5-X7H7)

[0096] Y5=(X 0145 H 0145 +X 23 H 23 +X0H0+X1H1)+(X5H5-X 01 H 01 -X 04 H 04 -X 15 H 15 )+(X4H4-X 45 H 45 -X2H2-X3H3)+z -8 (X 67 H 67 -X6H6-X7H7)

[0097] Y6=(X 0246 H 0246 +X 15 H 15 +X0H0)+(X4H4+X6H6-X 02 H 02 -X 04 H 04 )+(-X 26 H 26 -X 46 H 46 -X1H1-X5H5)+X3H3+X2H2+z -8 X7H7

[0098] Y7=(X 01214567 H 01214567 +X 01 H 01 +X 02 H 02+X 04 H 04 +X 13 H 13 +X 15 H 15 )+(X 21 H 21 +X 26 H 26 +X 37 H 37 +X 45 H 45 +X 46 H 46 +X 57 H 57 +X 67 H 67 )+(-X 0123 H 0123 -X 0246 H 0246 -X 0145 H 0145 -X 1357 H 1357 -X 2367 H 2367 -X 4567 H 4567 )+(-X0H0-X1H1-X2H2-X3H3-X4H4-X5H5-X6H6-X7H7)#(5)

[0099] Among them, X abcd The formal parameter is X a +X b +X c +X d The simplified expression of H abcd The formal parameter is H a +H b +H c +H d The simplified expression of X ab The formal parameter is X a +X b The simplified expression of H ab The formal parameter is H a +H b The simplified expression of , Y0 to Y7 represent the z-domain expression of the output of the 0th to 7th parallel filtering results, H0 to H7 are the z-domain expressions of the 0th to 7th filters, X0 to X7 are the z-domain expressions of the 0th to 7th signals, z -8 is 8 beats at the delayed intermediate frequency sampling rate, and L is the number of parallel filtering paths.

[0100] The sub-filters used in formula (5) are summarized into four forms:

[0101] X a H a ,X mn H mn ,X ijkl H ijkl ,X opqrstuv #(6)#

[0102] In the above formula, the filter subscript combinations are as follows:

[0103] {a}={0},{1},{2},{3},{4},{5},{6|,{7}#

[0104] {m,n}={0,1},{0,2},{0,4},{1,3},{1,5},{2,3},{2,6},{3,7},{4,5},{4,6},{5,7},{6,7}

[0105] {j,k,l,m}={0,1,2,3},{0,1,4,5},{0,2,4,6},{1,3,5,7},{2,3,6,7},{4,5,6,7}

[0106] {o,p,q,r,s,t,u,v}={0,1,2,3,4,5,6,7}#(7)

[0107] From formula (7), we can see that the total number of sub-filters is 27. Compared with the general structure in formula (1), 8*8-27=37 sub-filters are saved, which greatly saves chip resources. The simulink simulation of each level of sub-filter is as follows: Figure 7 , expand X 01234567 H 01234567 The filter internal processing is as follows Figure 8 The filter coefficients in (num(z) / 1) have been pre-processed and split and added.

[0108] The final 8-way parallel filter output is output by adding 27 sub-filter combinations. The simulink simulation is as follows: Fig. 9 , z in the figure -1 represents the delay of one processing clock (fs / 16). For the parallel filtering of 8 orthogonal components, it is z in equation (5) -8 .

[0109] Embodiment 2

[0110] This embodiment proposes an orthogonal transformation system for high-speed parallel digital signals, including a microprocessor and a computer-readable storage medium connected to each other, wherein the microprocessor is programmed or configured to execute the orthogonal transformation method for high-speed parallel digital signals described in the first embodiment.

[0111] In summary, the present invention discloses a method and system for orthogonal transformation of high-speed parallel digital signals, which can address the problem of orthogonal transformation of high-speed digital signals and can adapt to the digital orthogonal transformation of any high-speed signal. At the same time, by selecting filter coefficients and optimizing the multi-phase parallel filtering structure, the consumption of chip resources is reduced.

[0112] The above is only a preferred embodiment of the present invention. The protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications without departing from the principle of the present invention, such as modifying the number of parallel paths, filter coefficients, processing clocks, etc. for different application scenarios, should also be regarded as the protection scope of the present invention.

Claims

1. A method for orthogonal transformation of high-speed parallel digital signals, characterized in that: The following steps are involved: Obtain the current signal, and calculate the mixing local oscillator value corresponding to each path according to the number of parallel paths of the current signal; Calculate the in-phase component and the quadrature component of the current signal, multiply each in-phase component by the corresponding mixing local oscillator value, and multiply each quadrature component by the corresponding mixing local oscillator value; The filter coefficients of the half-band filter are alternately extracted as the filter coefficients of the in-phase component and the orthogonal component respectively. The multi-phase filtering optimization structure is derived according to the parallel paths of the orthogonal component, and the multi-phase filtering optimization structure is used to filter the orthogonal component. Each path of the in-phase component is multiplied by the corresponding filter coefficient and delayed to complete the filtering of the in-phase component and synchronize the filtering results of the orthogonal component.

2. The orthogonal transformation method of high-speed parallel digital signals according to claim 1, characterized in that: When calculating the mixing local oscillator value corresponding to each path according to the parallel paths of the current signal, it includes: serially converting and transforming the mixing local oscillator signal according to the parallel paths of the mixed current signal, so that the mixing local oscillator value corresponding to each path is a fixed value.

3. The orthogonal transformation method of high-speed parallel digital signals according to claim 1, characterized in that: When calculating the in-phase component and the orthogonal component of the current signal, it includes: performing odd-even cross extraction on the current signal to obtain an even index sequence as the in-phase component, and at the same time obtain an odd index sequence as the orthogonal component, and staggering the in-phase component and the orthogonal component by one sampling delay.

4. The orthogonal transformation method of high-speed parallel digital signals according to claim 1, characterized in that: When deriving the optimized structure of polyphase filtering based on the number of parallel paths of orthogonal components, it includes: Calculate the z-domain expression of each parallel filtering result output of the orthogonal component; The z-domain expression of each parallel filtering result output is decomposed into polynomials to reuse the same sub-filter results and obtain a multi-phase filtering optimization structure.

5. The orthogonal transformation method of high-speed parallel digital signals according to claim 4, characterized in that: The z-domain expression of each parallel filtering result output is as follows: Among them, Y k represents the z-domain expression of the k-th parallel filtering result output, H i is the z-domain expression of the i-th filter, X i is the z-domain expression of the i-th signal, z -L is the L beats at the delayed intermediate frequency sampling rate, and L is the number of parallel filtering paths.

6. The orthogonal transformation method of high-speed parallel digital signals according to claim 4, characterized in that: When performing polynomial decomposition on the z-domain expression of each parallel filtering result output, it includes: Substitute the z-domain expression of each parallel filtering result output into the z-domain expression of the final filtered output signal after multi-channel combination and perform derivation and evolution. According to the derivation and evolution result, rewrite the z-domain expression of each parallel filtering result output corresponding to the z-domain expression of the parallel filtering result output.

7. The orthogonal transformation method of high-speed parallel digital signals according to claim 4, characterized in that: The number of parallel paths of the orthogonal components is 8, and the polyphase filter optimization structure expression is as follows: Y0=X0H0+z -8 (X 1357 H 1357 +X 26 H 26 )+z -8 (X1H1+X3H3+X4H4)#+z -8 (X5H5+X7H7-X 13 H 13 )+z -8 (-X 15 H 15 -X 37 H 37 )+z -8 (-X 57 H 57 -X2H2-X6H6) Y1=(X 01 H 01 -X0H0-X1H1)+z -8 X3H3+z -8 (X 2367 h 2367 +X 45 H 45 +X2H2)+z -8 (X6H6+X7H7-X 23 H 23 -X 26 H 26 )+z -8 (-X 37 H 37 -X 67 H 67 -X4H4-X5H5) Y2=(X 02 H 02 +X1H1-X0H0-X2H2)+z -8 (X 37 h 37 +x 46 H 46 +X5H5)+z -8 (-X3H3-X4H4-X6H6-X7H7) Y3=(X 0123 H 0123 +X0H0+X1H1)+(X2H2+X3H3-X 01 H 01 )+(-X 02 H 02 -X 13 H 13 -X 23 H 23 )+z -8 (X 4567 H 4567 +X4H4+X5H5)+z -8 (X6H6+X7H7-X 45 H 45 )+z -8 (-X 46 H 46 -X 57 H 57 -X 67 H 67 ) Y4=(X 04 H 04 +X 13 H 13 +X2H2)+(-X0H0-X1H1-X3H3-X4H4)+z -8 (X 57 H 57 +X6H6-X5H5-X7H7) Y5=(X 0145 H 0145 +X 23 H 23 +X0H0+X1H1)+(X5H5-X 01 H 01 -X 04 H 04 -X 15 H 15 )+(X4H4-X 45 H 45 -X2H2-X3H3)+z -8 (X 67 H 67 -X6H6-X7H7) Y6=(X 0246 H 0246 +X 15 H 15 +X0H0)+(X4H4+X6H6-X 02 H 02 -X 04 H 04 )+(-X 26 H 26 -X 46 H 46 -X1H1-X5H5)+X3H3+X2H2+z -8 X7H7 Y7=(X 01234567 H 01234567 +X 01 H 01 +X 02 H 02 +X 04 H 04 +X 13 H 13 +X 15 H 15 )+(X 23 H 23 +X 26 H 26 +X 37 H 37 +X 45 H 45 +X 46 H 46 +X 57 H 57 +X 67 H 67 )+(-X 0123 H 0123 -X 0246 H 0246 -X 0145 H 0145 -X 1357 H 1357 -X 2367 H 2367 -X 4567 H 4567 )+(-X0H0-X1H1-X2H2-X3H3-X4H4-X5H5-X6H6-X7H7)# Among them, X abcd The formal parameter is X a +X b +X c +X d The simplified expression of H abcd The formal parameter is H a +H b +H c +H d The simplified expression of X ab The formal parameter is X a +X b The simplified expression of H ab The formal parameter is H a +H b The simplified expression of , Y0 to Y7 represent the z-domain expression of the output of the 0th to 7th parallel filtering results, H0 to H7 are the z-domain expressions of the 0th to 7th filters, X0 to X7 are the z-domain expressions of the 0th to 7th signals, z -8 is 8 beats at the delayed intermediate frequency sampling rate, and L is the number of parallel filtering paths.

8. The orthogonal transformation method of high-speed parallel digital signals according to claim 1, characterized in that: When the filter coefficients of the half-band filter are alternately extracted as the filter coefficients of the in-phase component and the orthogonal component respectively, specifically, the filter coefficient h(2n+1) of the half-band filter is used as the filter coefficient of the channel corresponding to the in-phase component, and the filter coefficient h(2n) of the half-band filter is used as the filter coefficient of the channel corresponding to the orthogonal component, n=0,1,…,N, N is the order of the half-band filter.

9. The orthogonal transformation method of high-speed parallel digital signals according to claim 8, characterized in that: Each in-phase component is multiplied by the corresponding filter coefficient and delayed. Specifically, each in-phase component is multiplied by 0.5 and then delayed by 1 beat at the intermediate frequency sampling rate.

10. A high-speed parallel digital signal orthogonal transformation system, characterized in that: The invention comprises a microprocessor and a computer-readable storage medium connected to each other, wherein the microprocessor is programmed or configured to execute the orthogonal transformation method of high-speed parallel digital signals as claimed in any one of claims 1 to 9.

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