Ultra-low power consumption physical unclonable function device based on multi-time programmable nonvolatile memory and working method

Abstract

The invention discloses an ultra-low power consumption physical unclonable function device based on a multi-time programmable nonvolatile memory. The ultra-low power consumption physical unclonable function device comprises two same multi-time programmable memory arrays, a transmission gate array and a sensing amplifier array, response values are generated by utilizing random distribution of bit line read current after multiple programmable memory cell programming caused by manufacturing process deviation. The ultra-low power consumption physical unclonable function structure designed by the invention is suitable for resource-limited Internet of Things edge equipment containing a multi-time programmable memory, and is extremely low in power consumption and relatively high in security.

Description

Technical Field

[0001] The present invention relates to the field of hardware encryption technology for edge devices of the Internet of Things, and in particular to an ultra-low power consumption physical unclonable function device and a working method based on a multi-time programmable non-volatile memory. Background Art

[0002] Physically unclonable functions (PUFs) provide a new approach to address hardware security issues in the Internet of Things. Due to certain process mismatches in the manufacturing process of silicon-based chips, the physical differences of each component and unit are unclonable and unpredictable. After manufacturing is completed, these random physical differences are stored inside each chip. PUF extracts the random process differences between these different chips, amplifies and characterizes them, and thus obtains a "digital fingerprint" unique to each chip. As a hardware security primitive, PUF is often used in applications such as identity recognition, device key generation and authentication. Because its response has the unique property of "power on and power off", it solves the hardware security risks brought about by the traditional encryption scheme that must store keys in non-volatile memory (NVM).

[0003] At present, a variety of storage-based PUFs based on different memories have been proposed. For example, PUF technology based on static random-access memory (SRAM) is a typical hardware security solution that uses SRAM storage cells and architecture to generate PUF responses. This solution is to put the SRAM cell into a metastable state, and then use each cell to finally return to a steady state to represent "0" or "1" to obtain the PUF response. Due to process mismatch, the difference between cells in tending to eventually be 0 or 1 is random, but the tendency of each cell is determined. Therefore, an SRAM array can generate a random and unique binary sequence. However, SRAM PUF often requires a continuous power loop to generate a response, which is not suitable for all IoT devices. In addition, there are currently few PUF solutions designed based on NVM. PUF technology based on the emerging resistive random-access memory (RRAM) is a new PUF solution based on NVM technology. The entropy source of this solution mainly comes from the resistive configuration of RRAM. However, the energy-efficient technology of RRAM in standard CMOS process is not mature enough to widely replace multi-time programmable NVM in edge devices. Therefore, the PUF design of multi-time programmable NVM with high security and low power consumption is urgently needed for use in IoT edge devices with mature process but limited resources containing multi-time programmable memory. Summary of the invention

[0004] In view of the shortcomings of existing storage-type PUFs, the present invention proposes an ultra-low power consumption physical unclonable function device and a working method based on multi-time programmable non-volatile memory, which has good uniqueness and reliability and extremely low power consumption. In addition, as an intrinsic storage-type PUF design, the present invention does not change or add additional circuit structures, and performs security reinforcement design while greatly avoiding redundant hardware overhead of the system. The present invention is suitable for resource-constrained IoT edge devices containing multi-time programmable memories, with extremely low power consumption and high security.

[0005] In order to achieve the above technical objectives, the technical solution adopted by the present invention is:

[0006] An ultra-low power consumption physical unclonable function device based on multi-time programmable non-volatile memory, the ultra-low power consumption physical unclonable function device comprising two identical multi-time programmable storage arrays, a transmission gate array and a sense amplifier array;

[0007] Four transmission gates of the transmission gate array are arranged in pairs in two identical multi-time programmable memory arrays, and the other transmission gates are connected in pairs to two input terminals of one of the sense amplifiers in the sense amplifier array;

[0008] The multi-time programmable storage array includes a plurality of multi-time programmable basic differential storage cells, and all cells maintain consistent programming and erasing settings;

[0009] When executing the physical unclonable function, the multi-time programmable memory array is fully erased, and then fully programmed after the erasure is complete to complete the preprocessing process; thereafter, the excitation signal acts as an input signal on the row and column addresses of the two multi-time programmable memory arrays respectively, and the selected programming terminal BL has a post-programming read current output, which enters the corresponding sense amplifier through the corresponding transmission gate, and the sense amplifier senses, amplifies and compares the two post-programming BL read currents input.

[0010] Furthermore, each row of the multi-time programmable storage array has a total of m multi-time programmable basic differential storage cells, and the cells in each row share a floating gate terminal TUN, a read terminal RDL and a selection tube terminal SL; each column has a total of n multi-time programmable basic differential storage cells, and the cells in each column share a left control terminal CG0, a right control terminal CG1, a left bit line BL0 and a right bit line BL1; the shared floating gate terminal TUN, the read terminal RDL, the selection tube terminal SL, the left control terminal CG0 and the right control terminal CG1 are used to control the cells in the array to perform programming, erasing, reading and standby operations, and the shared left bit line BL0 and the right bit line BL1 are used to output a read current after programming or erasing; the programming terminal BL shared by each column is pulled out to the transmission gate array.

[0011] Furthermore, the multi-time programmable basic differential storage unit is composed of two left and right single-ended structures with complete mirror symmetry to form a differential storage structure, the MOS capacitors of two floating gates TUN are connected to a TUN terminal, and the two selection tubes PMOS tubes are connected to a SL terminal;

[0012] Each single-ended structure consists of a basic three-tube structure and a selection tube structure. The storage tubes of the basic three-tube structure include PMOS tube PM0, PMOS tube PM1 and PMOS tube PM2; PMOS tube PM0 is a control gate-floating gate MOS capacitor, and PMOS tube PM2 is a floating gate channel-TUN terminal MOS capacitor; the gates of PMOS tube PM0, PMOS tube PM1 and PMOS tube PM2 are connected as floating gates through polycrystalline.

[0013] Furthermore, the transmission gate array includes 4m+4 transmission gates; the 4m transmission gates are connected to the two input terminals of the sensing amplifier in pairs; the other 4 transmission gates are respectively on both sides of two identical multi-time programmable storage arrays. When the current reading function is executed, the 4 transmission gates are opened accordingly to complete the current detection.

[0014] Furthermore, the sense amplifier array includes 2m sense amplifiers, wherein two input terminals of each amplifier are respectively connected to a transmission gate.

[0015] Furthermore, the sense amplifier compares the magnitudes of the post-programming read currents at the two input terminals, and outputs a high level or a low level according to the comparison result.

[0016] In a second aspect, the present invention discloses a working method of an ultra-low power consumption physical unclonable function device based on a multi-time programmable non-volatile memory, wherein the ultra-low power consumption physical unclonable function device adopts the device as described above;

[0017] The working method comprises the following steps:

[0018] Step 1: Preprocessing stage:

[0019] Before the PUF function is implemented, all storage cells in the multi-time programmable memory array are fully erased according to the setting, and after confirming that the original storage state is fully erased, all storage cells in the multi-time programmable memory array are fully programmed according to the setting;

[0020] Step 2: Incentive configuration phase:

[0021] Input X+Y bit stimulus, apply X bit stimulus to the row decoder and enable the shared SL line and RDL line of the corresponding row unit, select the row path of the corresponding row, and the selection tube of the corresponding unit on the unselected row line is not turned on; then apply Y bit stimulus to the transmission gate array and enable the transmission gate connected to the corresponding two column units. If the stimulus is 1, the transmission gate at the corresponding position is turned on, and if the stimulus is 0, the transmission gate at the corresponding position remains closed.

[0022] Step 3: Response generation phase:

[0023] The sense amplifier connected to the corresponding conductive transmission gate is enabled, and the process deviation of the cells in the two selected multi-time programmable memory arrays is manifested as a random BL current value after programming, which enters the sense amplifier for comparison and amplification; a unique 1-bit response value is generated in each comparison cycle.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The ultra-low power consumption physical unclonable function device and working method based on multi-time programmable non-volatile memory of the present invention realizes the physical unclonable function by utilizing the different read current after programming of multi-time programmable non-volatile memory. Due to the manufacturing process differences of transistors, floating gates and other circuit structures of multi-time programmable basic differential storage units, the read current after programming changes randomly under the same conditions. The current value is compared by controlling the sense amplifier through the enable signal to realize the efficient generation of PUF response. The tape-out results show that the physical unclonable function structure based on multi-time programmable non-volatile memory of the present invention has good uniqueness and reliability, and its average single-bit energy consumption is only 0.04-0.09pJ / bit, and the redundant overhead of the hardware overhead under the storage function is 0. Therefore, the present invention can effectively reduce the energy consumption of PUF response generation based on non-volatile memory, simplify circuit design, and ensure security. The implementation method of the physical unclonable function can be extended to other application scenarios containing the same type of multi-time programmable non-volatile memory, realizing the low power consumption and low overhead design of its PUF security reinforcement. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a structural diagram of an ultra-low power consumption physical unclonable function device based on multi-time programmable non-volatile memory of the present invention;

[0027] Figure 2 This is a structural diagram of a multi-time programmable basic differential storage unit of the present invention;

[0028] Figure 3 It is a working block diagram of a physical unclonable function based on a multi-time programmable non-volatile memory of the present invention;

[0029] Figure 4 This is an example diagram of the excitation configuration of the present invention. DETAILED DESCRIPTION

[0030] The embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings.

[0031] The structure diagram of the ultra-low power consumption physical unclonable function device based on multi-time programmable non-triviality of the present invention is as follows Figure 1 As shown, Figure 1The invention includes two identical multi-time programmable memory arrays, a transmission gate array and a sense amplifier array, wherein the multi-time programmable memory array performs programming, erasing, reading and standby operations of the array through control signals and row and column decoding. Each row of the multi-time programmable memory array has a total of 8 multi-time programmable basic differential memory cells, and the cells in each row share a floating gate terminal TUN, a read terminal RDL and a select tube terminal SL. Each column has a total of 128 multi-time programmable basic differential memory cells, and the cells in each column share a left control terminal CG0, a right control terminal CG1, a left bit line BL0 and a right bit line BL1. The shared floating gate terminal TUN, the read terminal RDL, the select tube terminal SL, the left control terminal CG0 and the right control terminal CG1 are used to control the cells in the array to perform programming, erasing, reading and standby operations, and the shared left bit line BL0 and the right bit line BL1 are used to output the read current after programming or erasing. All cells in the array maintain consistent programming and erasing settings. When BL0 is set as the programming end bit line, the corresponding BL1 is the erasing end bit line; when BL0 is set as the erasing end bit line, the corresponding BL1 is the programming end bit line. The programming end BL shared by each column is pulled out to the transmission gate array. When the physical unclonable function is executed, the array is first fully erased, and then fully programmed after the erasure is complete to complete the preprocessing process. Afterwards, the excitation signal acts as an input signal on the row and column addresses of the storage array, and the selected programming end BL has a post-programming read current output.

[0032] The transmission gate array includes a total of 36 transmission gates, of which 32 transmission gates are connected to the two input terminals of the sense amplifier in pairs, and the other 4 transmission gates are on both sides of two identical multi-time programmable storage arrays. When the physical unclonable function is executed, the transmission gate corresponding to the selected programming terminal BL among the 32 transmission gates is opened, and the read current after programming passes through the transmission gate into the corresponding sense amplifier. When the current reading function is executed, the 4 transmission gates are opened accordingly to complete the current detection.

[0033] The sense amplifier array includes 16 sense amplifiers in total, wherein each amplifier has two input terminals connected to a transmission gate. When the physical unclonable function is executed, the sense amplifier senses, amplifies and compares the two input BL read currents after programming. The comparison result is set such that when the read current after programming at the left input terminal is greater than the read current after programming at the right input terminal, the sense amplifier output is a high level, i.e., "1"; when the read current after programming at the left input terminal is less than the read current after programming at the right input terminal, the sense amplifier output is a low level, i.e., "0". The set comparison result and "0" and "1" can be changed in relative relationship, but are not used to limit the scope of the implementation of the present invention. Without substantial changes in the technical content, it is also regarded as the scope of the implementation of the present invention. Specifically, when the physical unclonable function is executed, the transmission gate corresponding to the selected programming terminal BL is opened, and the read current after programming enters the corresponding sense amplifier through the transmission gate. The sense amplifier connected to the corresponding conductive transmission gate is enabled, and the process deviation of the two selected cells in the array is finally manifested as a random BL current value after programming, which enters the sense amplifier for comparison and amplification. A unique 1-bit response value is generated in each comparison cycle. This process is repeated until enough binary response sequences are obtained.

[0034] Figure 2 The figure shows the structure of a multi-time programmable basic differential storage unit. The differential storage structure is composed of two single-ended structures on the left and right that are completely mirror-symmetrical. The MOS capacitors of two floating gates TUN are connected to a TUN terminal, and two selection tubes PMOS tubes are connected to an SL terminal. Each single-ended structure consists of a basic three-tube structure and a selection tube structure. The storage tube of the basic three-tube structure uses three PMOS tubes. PM0 is a control gate-floating gate MOS capacitor, and PM2 is a floating gate channel-TUN terminal MOS capacitor. The gates of PM0, PM1, and PM2 are connected as floating gates through polycrystalline. When executing the preprocessing process of the physical unclonable function, in the first step, CG1, SL and TG apply high voltage, CG0 and RDL are grounded, the electrons in the left floating gate tunnel out from the TUN end through the floating gate tube, and the electrons in the right floating gate tunnel into the floating gate structure from the RDL, completing the defined "erase"; in the second step, CG0, SL and TG apply high voltage, CG1 and RDL are grounded, the electrons in the left floating gate tunnel into the floating gate structure from the RDL, and the electrons in the right floating gate tunnel out from the TUN end through the floating gate tube, completing the defined "programming"; in the third step, RDL applies high voltage, CG0, CG1, SL and TG are grounded, and the post-programming read current is output on the programming end BL0. The defined "programming" and "erasing" can be mirror-interchanged at the left and right ends, but are not used to limit the scope of the implementation of the present invention. Without substantially changing the technical content, the change in their relative relationship should also be regarded as the scope of the implementation of the present invention.

[0035] Figure 3The figure is a working block diagram of a physical unclonable function based on a multi-time programmable non-volatile memory, which includes a working method of the ultra-low power physical unclonable function structure based on the multi-time programmable non-volatile memory mentioned in the present invention, and the working method includes the following steps:

[0036] Step 1: Preprocessing stage:

[0037] Before the PUF function is implemented, all cells in the array are fully erased according to the settings. After confirming that the original storage state is fully erased, all cells in the array are fully programmed according to the settings.

[0038] Step 2: Incentive configuration phase:

[0039] Input X+Y bit stimulus, apply X bit stimulus to the row decoder and enable the shared SL line and RDL line of the corresponding row unit, select the row path of the corresponding row, and the select tube of the corresponding unit on the unselected row line is not turned on. Then apply Y bit stimulus to the transmission gate array and enable the transmission gate connected to the corresponding two column units. If the stimulus is "1", the transmission gate at this position is turned on, and if the stimulus is "0", the transmission gate at this position remains closed.

[0040] Step 3: Response generation phase:

[0041] The sense amplifier connected to the corresponding conduction transmission gate is enabled, and the process deviation of the two selected array cells is finally manifested as a random post-programming BL current value, which enters the sense amplifier for comparison and amplification. A unique 1-bit response value is generated in each comparison cycle.

[0042] Figure 4 The figure is an example of the stimulus configuration of the present invention. When the input stimulus is the example of "Challenge 1" or "0000000000000011", the first 8 bits indicate that the selected row address is the first row, and the two cells corresponding to "1" in the last 8 bits are the selected comparison cells. Therefore, this stimulus indicates that the BL current values ​​of the 7th and 8th adjacent memory cells are compared after programming under the address of the 1st row, as shown in FIG. Figure 4 As shown in the process marked in red and green. For another example, when the input stimulus is the example "Challenge 2" or "1111111100000101", the first 8 bits indicate that the row address selected at this time is the last row, and the two cells corresponding to "1" in the last 8 bits are the selected comparison cells. Therefore, this stimulus means that the BL current values ​​of the 6th and 8th memory cells separated by the 128th row address are compared after programming, as shown in Figure 4 The process is shown in orange and blue.

[0043] After tape-out verification, the ultra-low power physical unclonable function structure based on multi-time programmable non-volatile memory uses the randomness of the BL current after programming as the entropy source, and the method designed to obtain the response by comparing the current through the sense amplifier controlled by the excitation signal can be applied to resource-constrained scenarios containing the same type of multi-time programmable non-volatile memory. When no excitation signal is applied, the memory performs normal storage functions; when an excitation signal containing multiple specific enable signals is applied, the multi-time programmable memory array, transmission gate array and sense amplifier array form an intrinsic and low-power storage-type physical unclonable function.

[0044] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of complete hardware embodiments, complete software embodiments, or embodiments in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code. The scheme in the embodiments of the present application can be implemented in various computer languages, for example, object-oriented programming language Java and literal scripting language JavaScript, etc.

[0045] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0046] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0047] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0048] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0049] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. An ultra-low power consumption physical unclonable function device based on multi-time programmable non-volatile memory, characterized in that: The ultra-low power consumption physical unclonable function device comprises two identical multi-time programmable storage arrays, a transmission gate array and a sense amplifier array; Four transmission gates of the transmission gate array are arranged in pairs in two identical multi-time programmable memory arrays, and the other transmission gates are connected in pairs to two input terminals of one of the sense amplifiers in the sense amplifier array; The multi-time programmable storage array includes a plurality of multi-time programmable basic differential storage cells, and all cells maintain consistent programming and erasing settings; When executing the physical unclonable function, the multi-time programmable memory array is fully erased, and then fully programmed after the erasure is complete, completing the pre-processing process; Afterwards, the excitation signal acts as an input signal on the row and column addresses of the two multi-time programmable storage arrays respectively. The selected programming terminal BL has a programmed read current output, which enters the corresponding sense amplifier through the corresponding transmission gate. The sense amplifier senses, amplifies and compares the two programmed BL read currents input.

2. The ultra-low power consumption physical unclonable function device based on multi-time programmable non-volatile memory according to claim 1, characterized in that: Each row of the multi-time programmable storage array has a total of m multi-time programmable basic differential storage cells, and the cells in each row share a floating gate terminal TUN, a read terminal RDL and a selection tube terminal SL; each column has a total of n multi-time programmable basic differential storage cells, and the cells in each column share a left control terminal CG0, a right control terminal CG1, a left bit line BL0 and a right bit line BL1; the shared floating gate terminal TUN, the read terminal RDL, the selection tube terminal SL, the left control terminal CG0 and the right control terminal CG1 are used to control the cells in the array to perform programming, erasing, reading and standby operations, and the shared left bit line BL0 and the right bit line BL1 are used to output a read current after programming or erasing; the programming terminal BL shared by each column is pulled out to the transmission gate array.

3. The ultra-low power consumption physical unclonable function device based on multi-time programmable non-volatile memory according to claim 2, characterized in that: The multi-time programmable basic differential storage unit is composed of two left and right single-ended structures with complete mirror symmetry to form a differential storage structure, two MOS capacitors of floating gates TUN are connected to a TUN terminal, and two selection tubes PMOS tubes are connected to a SL terminal; Each single-ended structure consists of a basic three-tube structure and a selection tube structure. The storage tubes of the basic three-tube structure include PMOS tube PM0, PMOS tube PM1 and PMOS tube PM2; PMOS tube PM0 is a control gate-floating gate MOS capacitor, and PMOS tube PM2 is a floating gate channel-TUN terminal MOS capacitor; the gates of PMOS tube PM0, PMOS tube PM1 and PMOS tube PM2 are connected as floating gates through polycrystalline.

4. The ultra-low power consumption physical unclonable function device based on multi-time programmable non-volatile memory according to claim 1, characterized in that: The transmission gate array includes 4m+4 transmission gates; Among them, 4m transmission gates are connected to the two input terminals of the sense amplifier in pairs; the other 4 transmission gates are on both sides of two identical multi-time programmable storage arrays. When the current reading function is executed, the 4 transmission gates are opened accordingly to complete the current detection.

5. The ultra-low power consumption physical unclonable function device based on multi-time programmable non-volatile memory according to claim 1, characterized in that: The sense amplifier array includes 2m sense amplifiers, wherein two input terminals of each amplifier are respectively connected to a transmission gate.

6. The ultra-low power consumption physical unclonable function device based on multi-time programmable non-volatile memory according to claim 5, characterized in that: The sense amplifier compares the magnitudes of the post-programming read currents at the two input terminals and outputs a high level or a low level according to the comparison result.

7. A working method of an ultra-low power consumption physical unclonable function device based on multi-time programmable non-volatile memory, characterized in that: The ultra-low power consumption physical unclonable function device adopts the device as claimed in any one of claims 1 to 6; The working method comprises the following steps: Step 1: Preprocessing stage: Before the PUF function is implemented, all storage cells in the multi-time programmable memory array are fully erased according to the setting, and after confirming that the original storage state is fully erased, all storage cells in the multi-time programmable memory array are fully programmed according to the setting; Step 2: Incentive configuration phase: Input X+Y bit stimulus, apply X bit stimulus to the row decoder and enable the shared SL line and RDL line of the corresponding row unit, select the row path of the corresponding row, and the selection tube of the corresponding unit on the unselected row line is not turned on; then apply Y bit stimulus to the transmission gate array and enable the transmission gate connected to the corresponding two column units. If the stimulus is 1, the transmission gate at the corresponding position is turned on, and if the stimulus is 0, the transmission gate at the corresponding position remains closed. Step 3: Response generation phase: The sense amplifier connected to the corresponding conductive transmission gate is enabled, and the process deviation of the cells in the two selected multi-time programmable memory arrays is manifested as a random BL current value after programming, which enters the sense amplifier for comparison and amplification; a unique 1-bit response value is generated in each comparison cycle.

Images