Printed circuit board

Abstract

The present disclosure relates to a printed circuit board including: a first insulating layer; a first wiring layer disposed at one surface of the first insulating layer; a second wiring layer disposed on the other surface of the first insulating layer; the second insulating layer is arranged on the other surface of the first insulating layer; a third wiring layer disposed on the second insulating layer; a first cavity penetrating a portion of the first insulating layer; and a second cavity penetrating the second insulating layer and connected to the first cavity. The first cavity and the second cavity have different wall surface gradients, and a depth of the first cavity is less than a thickness of the first insulating layer and greater than a thickness of each of the first wiring layer and the second wiring layer.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0111014 filed on August 24, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] As the performance of smartphones improves, the thickness of components mounted on the package substrate continues to increase, but the thickness of the assembly substrate needs to be reduced or maintained. Therefore, it is necessary to form a cavity with a considerable depth in the package substrate. Summary of the invention

[0004] An aspect of the present disclosure is to provide a printed circuit board in which the depth of a cavity can be easily adjusted, such as allowing the cavity to be formed deeper.

[0005] One solution proposed by the present disclosure is to use a laser processing method and a metal etching method together to form a plurality of cavities connected to each other.

[0006] For example, according to one aspect of the present disclosure, there is provided a printed circuit board, the printed circuit board comprising: a first insulating layer having a first surface and a second surface opposite to each other in a first direction; a first wiring layer disposed at the first surface of the first insulating layer; a second wiring layer disposed at the second surface of the first insulating layer; a second insulating layer having a third surface and a fourth surface opposite to each other in the first direction and disposed on the first insulating layer so that the third surface is connected to the second surface; a third wiring layer disposed at the fourth surface of the second insulating layer; a first cavity penetrating a portion of the first insulating layer in the first direction; and a second cavity penetrating the second insulating layer in the first direction and connected to the first cavity. The first cavity and the second cavity may have different wall surface inclinations relative to the first direction, and based on the first direction, the depth of the first cavity may be less than the thickness of the first insulating layer and may be greater than the thickness of each of the first wiring layer and the second wiring layer.

[0007] For example, according to one aspect of the present disclosure, a printed circuit board is provided, comprising: a first insulating layer having a first cavity; a first wiring layer and a second wiring layer, respectively arranged at the upper surface and the lower surface of the first insulating layer; a second insulating layer, arranged on the lower surface of the first insulating layer, covering at least a portion of the second wiring layer, and having a second cavity connected to the first cavity; and a third wiring layer, arranged on the lower surface of the second insulating layer, wherein, in the stacking direction of the printed circuit board, the first cavity can be arranged between the first wiring layer and the second wiring layer.

[0008] One of the effects of the present disclosure is to provide a printed circuit board in which the depth of a cavity can be easily adjusted, such as allowing the cavity to be formed deeper. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram schematically illustrating an example of an electronic device system;

[0011] Figure 2 is a perspective view schematically showing an example of an electronic device;

[0012] Figure 3 is a cross-sectional view schematically illustrating an example embodiment of a printed circuit board;

[0013] Figure 4 It is schematically shown Figure 3 A cross-sectional view of a modified example embodiment of a printed circuit board;

[0014] FIG. 5A to FIG. 5J is a schematic diagram showing the manufacturing Figure 3 and Figure 4 A process cross-sectional view of an example of a printed circuit board;

[0015] Figure 6 is a cross-sectional view schematically illustrating another example embodiment of a printed circuit board;

[0016] Figure 7 It is schematically shown Figure 6 A cross-sectional view of a modified example embodiment of a printed circuit board;

[0017] FIG. 8A to FIG. 8H is a schematic diagram showing the manufacturing Figure 6 and Figure 7 A process cross-sectional view of an example of a printed circuit board; and

[0018] Figures 9 to 11is a cross-sectional view schematically showing another example of a printed circuit board. DETAILED DESCRIPTION

[0019] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, the shapes and sizes of elements may be exaggerated or reduced for clearer description.

[0020] Electronic Devices

[0021] Figure 1 is a block diagram schematically illustrating an example of an electronic device system.

[0022] Reference Figure 1 , a main board 1010 is housed in the electronic device 1000. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These components may also be coupled to other electronic components to be described below via various signal lines 1090.

[0023] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM, flash memory), etc.; application processor chips, such as central processing units (e.g., CPU), graphics processors (e.g., GPU), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, and may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may have the form of a package including the above-mentioned chips and / or electronic components.

[0024] The network-related components 1030 may include components that are compatible with or communicate according to protocols such as: Wireless Fidelity (Wi-Fi) (such as the IEEE 802.11 series), Worldwide Interoperability for Microwave Access (WiMAX) (such as the IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, Wireless Local Area Network (Wireless LAN), Third Generation Mobile Communication Technology (3G) Protocol, Fourth Generation Mobile Communication Technology (4G) Protocol and Fifth Generation Mobile Communication Technology (5G) Protocol, as well as any other wireless standards or protocols and wired standards or protocols specified hereafter. However, the network-related component 1030 is not limited thereto, and may also include a component that is compatible with or communicates according to any one of a plurality of other wireless standards or protocols and wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020.

[0025] Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, other components are not limited thereto, and may also include passive components in the form of chip components for various other purposes. In addition, other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0026] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or that are not physically and / or electrically connected to the mainboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, these other electronic components are not limited thereto, but may also include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD) drive, a digital versatile disk (DVD) drive, etc. In addition to this, depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0027] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, or an automotive component. However, the electronic device 1000 is not limited thereto, and in addition to the above-mentioned electronic devices, the electronic device 1000 may also be any other electronic device capable of processing data.

[0028] Figure 2 is a perspective view schematically showing an example of an electronic device.

[0029] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. The mainboard 1110 may be housed in the smart phone 1100, and various components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the mainboard 1110 or that are not physically and / or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, component packages 1121, but the present disclosure is not limited thereto. The component package 1121 may have the form of a printed circuit board on which an electronic component (including an active component and / or a passive component) is surface-mounted. Alternatively, the component package 1121 may have the form of a printed circuit board in which an electronic component (including an active component and / or a passive component) is embedded. On the other hand, the electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

[0030] Printed Circuit Board

[0031] Figure 3 is a cross-sectional view schematically illustrating an example embodiment of a printed circuit board.

[0032] Reference Figure 3A printed circuit board 100A according to an example embodiment may include: a first insulating layer 111 having a first surface S1 and a second surface S2 opposite to each other in a first direction (i.e., a stacking direction of the layers of the printed circuit board 100A); a first wiring layer 121 disposed on the first surface S1 of the first insulating layer 111; a second wiring layer 122 disposed on the second surface S2 of the first insulating layer 111; a second insulating layer 112 having a third surface S3 and a fourth surface S4 opposite to each other in the first direction and disposed on the first insulating layer 111 such that the third surface S3 is connected to the second surface S2; a third wiring layer 123 disposed on the fourth surface S4 of the second insulating layer 112; a first cavity C1 penetrating a portion of the first insulating layer 111 from the second surface S2 in the first direction; and a second cavity C2 penetrating the second insulating layer 112 in the first direction and connected to the first cavity C1. The first cavity C1 and the second cavity C2 may have different wall surface inclinations. Based on the first direction, the depth of the first cavity C1 may be less than the thickness of the first insulating layer 111, and may be greater than the thickness of each of the first wiring layer 121 and the second wiring layer 122. In the first direction, the first cavity C1 may be disposed at a height between the first wiring layer 121 and the second wiring layer 122, and no wiring layer may be disposed between the first wiring layer 121 and the second wiring layer 122.

[0033] For example, the first cavity C1 may be formed by etching the metal buried in the first insulating layer 111 (see Fig.5I ), and a second cavity C2 can be formed in the second insulating layer 112 by laser processing (refer to Figure 5H ). Therefore, the inclination (or wall slope) of the wall surface of the first cavity C1 and the inclination of the wall surface of the second cavity C2 may be different from each other. For example, the wall slope of the second cavity C2 may be greater than the wall slope of the first cavity C1. For example, the first cavity C1 may have a substantially vertical wall surface (substantially vertical wall surface means that the wall surface is substantially parallel to the first direction), and the second cavity C2 may have a tapered wall surface, and in cross section, the width of the side of the second cavity C2 connected to the first cavity C1 is narrower than the width of the opposite side thereof. For example, a cross section may refer to a cross section parallel to the first direction (for example, Figure 3 The width may refer to the width in a direction perpendicular to the first direction (eg, Figure 3Here, the inclination of the wall surface of the cavity (or the wall slope) refers to the degree of inclination of the wall surface of the cavity relative to the first direction (for example, the degree of inclination of the boundary line of the wall surface of the cavity relative to the first direction in the cross section). In this case, the first cavity C1 and the second cavity C2 are connected so that the depth of the entire cavity can be increased, which can make it easier to control the depth of the cavity. In addition, in the cross section, the average width of the second cavity C2 can be greater than the average width of the first cavity C1. Therefore, the cavity can become wider toward the entrance, and thus it can become easier to install the component in the cavity. In addition, the first cavity C1 can be formed by etching a metal block formed separately from the first wiring layer 121 and the second wiring layer 122, so the depth of the first cavity C1 can be less than the thickness of the first insulating layer 111, but can be greater than the thickness of each of the first wiring layer 121 and the second wiring layer 122. In addition, in the first direction, the first cavity C1 can be set at a height between the first wiring layer 121 and the second wiring layer 122. As a result, the first cavity C1 can be formed to have various thicknesses in a relatively large range. Therefore, the depth of the cavity can be more easily controlled.

[0034] In addition, the printed circuit board 100A according to the example embodiment may further include: a first resist layer 141 having a fifth surface S5 and a sixth surface S6 opposite to each other in the first direction, disposed on the second insulating layer 112 so that the fifth surface S5 is connected to the fourth surface S4, and having a first opening h1 exposing at least a portion of the third wiring layer 123; and a third cavity C3 penetrating the first resist layer 141 in the first direction and connected to the second cavity C2. The second cavity C2 and the third cavity C3 may have different wall surface inclinations. For example, the wall slope of the third cavity C3 may be smaller than the wall slope of the second cavity C2. For example, the third cavity C3 may have a substantially vertical wall surface, or may have a tapered wall surface (in cross section, the width of one side of the third cavity C3 connected to the second cavity C2 is narrower than the width of the opposite side thereof). In this case, the first cavity C1, the second cavity C2, and the third cavity C3 are connected to each other, so that the depth of the entire cavity can be increased, which can make it easier to control the depth of the cavity. In addition, in cross section, the average width of the third cavity C3 may be greater than the average width of the second cavity C2. Therefore, the entrance of the cavity can be formed wider, and thus it may be easier to install the component in the cavity. In addition, since the third cavity C3 may be formed in a separate process from the first and second cavities C1 and C2, it may be easier to adjust the depth of the cavity.

[0035] In addition, the printed circuit board 100A according to the example embodiment may further include: a first via layer 131 penetrating the first insulating layer 111 in the first direction and connecting at least a portion of the first wiring layer 121 and at least a portion of the second wiring layer 122 to each other; and a second via layer 132 penetrating the second insulating layer 112 in the first direction and connecting at least a portion of the second wiring layer 122 and at least a portion of the third wiring layer 123 to each other. In addition, the printed circuit board 100A may further include: a plurality of buildup insulating layers 113 disposed on the first surface S1 of the first insulating layer 111; a plurality of buildup wiring layers 124 disposed on or in the plurality of buildup insulating layers 113 in the first direction, where the first wiring layer 121 may also be a buildup wiring layer; and a plurality of buildup via layers 133 penetrating at least one of the plurality of buildup insulating layers 113 in the first direction. In addition, the printed circuit board 100A may further include a second resist layer 142 disposed on the plurality of buildup insulating layers 113 and having a structure that allows the outermost layers (eg, Figure 3 The second opening h2 in which at least a portion of the built-up wiring layer 124 (the uppermost side relative to the first direction) is exposed. As described above, the printed circuit board 100A according to the example embodiment may have a multi-layer coreless board structure. In the first direction, the bottom surface of the first cavity C1 may be disposed at a height between the first surface S1 and the second surface S2 of the first insulating layer 111.

[0036] Hereinafter, components of a printed circuit board 100A according to example embodiments will be described in more detail with reference to the accompanying drawings.

[0037] Each of the first insulating layer 111 and the second insulating layer 112 and the plurality of stacked insulating layers 113 may include an insulating material. The insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material prepared by impregnating an inorganic filler, an organic filler and / or a glass fiber (for example, a glass fabric in the form of a glass cloth) in a resin. For example, the insulating material may be a non-photosensitive insulating material (such as an Ajinomoto stacked film (ABF) or a prepreg (PPG)), but the present disclosure is not limited thereto, and other polymer materials may be used as the insulating material. The first insulating layer 111 and the second insulating layer 112 and the plurality of stacked insulating layers 113 may include the same insulating material or may include different insulating materials. The first insulating layer 111 and the second insulating layer 112 and the plurality of stacked insulating layers 113 may have boundaries with each other, or may be integrated to the extent that the boundaries between them are not easily distinguished. Based on the first direction, the first insulating layer 111 may be thicker than the second insulating layer 112, but the present disclosure is not limited thereto.

[0038] Each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the plurality of built-up wiring layers 124 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or their alloys. The metal material may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the plurality of built-up wiring layers 124 may perform various functions according to the design. For example, the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the plurality of built-up wiring layers 124 may include a signal pattern, a power pattern, and a ground pattern. Each of these patterns may have various forms (such as lines, planes, and pads). Each of the first wiring layer 121, the second wiring layer 122, and the third wiring layer 123, and the plurality of built-up wiring layers 124 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, each of the first wiring layer 121, the second wiring layer 122, and the third wiring layer 123, and the plurality of built-up wiring layers 124 may include a metal foil (e.g., a copper foil) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, each of the first wiring layer 121, the second wiring layer 122, and the third wiring layer 123, and the plurality of built-up wiring layers 124 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer), and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Each of the first wiring layer 121, the second wiring layer 122, and the third wiring layer 123 and the plurality of built-up wiring layers 124 may include a sputtered layer instead of an electroless plating layer (e.g., a chemical copper plating layer), and may include both a sputtered layer and an electroless plating layer (e.g., a chemical copper plating layer) if necessary.

[0039] Each of the first via layer 131 and the second via layer 132 and the plurality of stacked via layers 133 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys. The metal material may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the first via layer 131 and the second via layer 132 and the plurality of stacked via layers 133 may include a micro via. The micro via may be a filled via that fills the via hole, or may be a conformal via arranged along the wall surface of the via hole. The micro via may be arranged as a stacking type and / or an interlaced type. The micro vias of each of the first via layer 131 and the second via layer 132 and the plurality of stacked via layers 133 may perform various functions according to the design of the corresponding layer. For example, the first via layer 131 and the second via layer 132 and the plurality of stacked via layers 133 may include a ground via, a power via, and a signal via. Each of the first via layer 131 and the second via layer 132 and the plurality of stacked via layers 133 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but the present disclosure is not limited thereto. Each of the first via layer 131 and the second via layer 132 and the plurality of stacked via layers 133 may have a sputtering layer to replace the electroless plating layer, and may include both the sputtering layer and the electroless plating layer. The micro vias of each of the first via layer 131 and the second via layer 132 may have a shape that tapers in the same direction. The micro vias of each of the plurality of stacked via layers 133 may have a shape that tapers in the same direction. The micro vias of the first via layer 131 and the second via layer 132 may taper in the opposite direction to the micro vias of the plurality of stacked via layers 133.

[0040] Each of the first resist layer 141 and the second resist layer 142 may include a liquid type solder resist or a film type solder resist, but is not limited thereto, and may include other types of insulating materials such as ABF. The first resist layer 141 and the second resist layer 142 may have a first opening h1 and a second opening h2, respectively, and a surface treatment layer may be formed on the pattern exposed by the first opening h1 and the second opening h2 as needed.

[0041] Figure 4 It is schematically shown Figure 3 A cross-sectional view of a modified example embodiment of a printed circuit board.

[0042] Reference Figure 4Compared with the printed circuit board 100A according to the above-described exemplary embodiment, the printed circuit board 100B according to the modified exemplary embodiment may further include a fourth cavity C4 that penetrates another portion of the first insulating layer 111 from the first cavity C1 in the first direction and is connected to the first cavity C1. The fourth cavity C4 may expose at least one of the plurality of built-up wiring layers (e.g., at least a portion of the first wiring layer 121). The first cavity C1 and the fourth cavity C4 may have different wall surface inclinations. For example, the wall surface inclination of the fourth cavity C4 may be greater than the wall surface inclination of the first cavity C1. For example, the first cavity C1 may have a substantially vertical wall surface, and the fourth cavity C4 may have a tapered wall, and in cross section, the width of the fourth cavity C4 on one side connected to the first cavity C1 is greater than the width of the opposite side thereof. In this case, the first cavity C1, the second cavity C2, the third cavity C3, and the fourth cavity C4 may be connected to each other, so that the depth of the entire cavity may be increased, which may make it easier to control the depth of the cavity. In addition, in cross section, the average width of the first cavity C1 may be greater than the average width of the fourth cavity C4. Therefore, the cavity may become wider toward the inlet, and thus mounting components in the cavity may become easier. In addition, the fourth cavity C4 may be formed in a separate process from the first cavity C1, which may make it easier to adjust the depth of the cavity.

[0043] The other contents are substantially the same as those described in the printed circuit board 100A according to the above-described exemplary embodiment, and thus redundant descriptions thereof will be omitted.

[0044] FIG. 5A to FIG. 5J is a schematic diagram showing the manufacturing Figure 3 and Figure 4 FIG. 1 is a process cross-sectional view of an example of a printed circuit board.

[0045] Reference Figure 5A , forming metal blocks 320 on both surfaces of the separation carrier 310 based on the first direction. The separation carrier 310 may include a body and copper foil disposed on both surfaces of the body, and the metal blocks 320 may be formed using the copper foil as a seed layer, for example, by electrolytic plating.

[0046] Reference Figure 5B , a first insulating layer 111 burying the metal block 320 is formed on both surfaces of the separation carrier 310. The first insulating layer 111 may be formed to be thicker than the metal block 320. The first insulating layer 111 may be formed in a lamination process. In addition, a first wiring layer 121 is formed on the first insulating layer 111 in a plating process. For example, the first wiring layer 121 may be formed using an additive process (AP), a semi-additive process (SAP), a modified semi-additive process (MSAP), a hole sealing (TT) process, or the like.

[0047] Reference Figure 5C, a plurality of stacked insulating layers 113, a plurality of stacked wiring layers 124, and a plurality of stacked via layers 133 are formed on the first insulating layer 111. The plurality of stacked insulating layers 113, the plurality of stacked wiring layers 124, and the plurality of stacked via layers 133 may be formed by a stacking process. The stacked insulating layers 113 may be formed by a lamination process. The plurality of stacked wiring layers 124 and the plurality of stacked via layers 133 may be formed by a plating process. In this case, laser drilling or mechanical drilling may be used to process the via holes. In addition, in Figure 5B In the structure shown in FIG. 1 , the first wiring layer 121 may not be formed, and the Figure 5C The first wiring layer 121 is formed in the same process as the process of forming the build-up wiring layer 124, so that the first wiring layer 121 can serve as the build-up wiring layer.

[0048] Reference Figure 5D , will be Figure 5C The stacked body manufactured in the embodiment is separated from the separation carrier 310. In this case, if necessary, the copper foil of the separation carrier 310 may remain in the stacked body.

[0049] Reference Figure 5E , a buildup process is further performed to form a second wiring layer 122 on and / or in the first insulating layer 111, and to form a first via layer 131 in the first insulating layer 111. In the process of forming the second wiring layer 122, the copper foil may be used as a seed layer, and excess copper foil may be removed after forming the second wiring layer 122. Alternatively, the copper foil may be removed before forming the second wiring layer 122. In addition, a buildup wiring layer 124 and a buildup via layer 133 are also formed on the outermost side of the stack.

[0050] Reference Fig. 5F , a buildup process is further performed to form a second insulating layer 112 on the first insulating layer 111. In addition, a third wiring layer 123 is formed on and / or in the second insulating layer 112, and a second via layer 132 is formed in the second insulating layer 112. In addition, more buildup insulating layers 113, more buildup wiring layers 124, and more buildup via layers 133 are also formed.

[0051] Reference Figure 5G ,exist Fig. 5F A first resist layer 141 and a second resist layer 142 are respectively formed on both surfaces of the stacked body formed in the embodiment of the present invention. The first resist layer 141 and the second resist layer 142 may be formed by coating or lamination. Next, a first opening h1 and a third cavity C3 are formed in the first resist layer 141, and a second opening h2 is formed in the second resist layer 142. Each of the first opening h1 and the second opening h2 and the third cavity C3 may be formed by laser processing, but the present disclosure is not limited thereto, and other methods such as etching may be used.

[0052] Reference Figure 5H , forming the second cavity C2 in the second insulating layer 112. The second cavity C2 may be formed by laser processing. For example, the second cavity C2 may be formed by laser processing the second insulating layer 112 exposed from the third cavity C3, and the metal block 320 buried in the first insulating layer 111 may be exposed.

[0053] Reference Fig.5I , a first cavity C1 is formed in the first insulating layer 111. The first cavity C1 may be formed by removing the metal block 320 by etching. Through a series of processes, the printed circuit board 100A according to the above-described example embodiment may be manufactured.

[0054] Reference Figure 5J , a fourth cavity C4 is formed in the first insulating layer 111. The fourth cavity C4 may be formed by laser processing. For example, the fourth cavity C4 may be formed by laser processing the first insulating layer 111 exposed from the first cavity C1, the second cavity C2, and the third cavity C3, and a portion of the first wiring layer 121 may be exposed. Through a series of processes, the printed circuit board 100B according to the above-described modified example embodiment may be manufactured.

[0055] The other contents are substantially the same as those described in the printed circuit board 100A according to the above-described exemplary embodiment and the printed circuit board 100B according to the modified exemplary embodiment thereof, and therefore, redundant descriptions thereof will be omitted.

[0056] Figure 6 is a cross-sectional view schematically illustrating another example embodiment of a printed circuit board.

[0057] Reference Figure 6 , in a printed circuit board 100C according to another exemplary embodiment, the first wiring layer 121, the second wiring layer 122, and the third wiring layer 123, and the first cavity C1 and the second cavity C2 may have different forms compared to the printed circuit board 100A according to the above exemplary embodiment. For example, the first wiring layer 121 may be buried in the first surface S1 of the first insulating layer 111, and the second wiring layer 122 may be provided on the second surface S2 of the first insulating layer 111. In addition, the first cavity C1 may penetrate a portion of the first insulating layer 111 from the first surface S1 in the first direction, and the second cavity C2 may be connected to the first cavity C1 by penetrating the second insulating layer 112 in the first direction and further penetrating another portion of the first insulating layer 111 from the second surface S2 to the first cavity C1. However, similarly, the first cavity C1 and the second cavity C2 may have different wall surface inclinations, and the depth of the first cavity C1 may be less than the thickness of the first insulating layer 111 based on the first direction, and may be greater than the thickness of each of the first wiring layer 121 and the second wiring layer 122.

[0058] In addition, compared with the printed circuit board 100A according to the above-described exemplary embodiment, in a printed circuit board 100C according to another exemplary embodiment, a plurality of stacked insulating layers 113-1, 113-2, and 113-3, a first wiring layer 121, a plurality of stacked wiring layers 124-1 and 124-2, and a plurality of stacked via layers 133-1, 133-2, and 133-3 may have a structure of a multi-layer core substrate rather than a multi-layer coreless substrate. For example, a plurality of stacked insulating layers 113-1, 113-2, and 113-3 may include a core insulating layer 113-1 located in a central portion thereof, and the core insulating layer 113-1 may be formed using a copper clad laminate (CCL) or other core insulating materials. Based on the first direction, the core insulating layer 113-1 may be thicker than each of the other stacked insulating layers 113-2 and 113-3. In addition, the plurality of stacked via layers 133-1, 133-2, and 133-3 may include a core via layer 133-1 that penetrates the core insulating layer 113-1, and the core via layer 133-1 may include a through-hole. The through-hole may include a plated through hole (PTH) formed by filling the via hole with the above-mentioned metal material, or a plated through hole (PTH) formed in the following manner: the above-mentioned metal material is conformally formed on the wall surface of the via hole by plating and the inside of the via hole is filled with an insulating material. In cross section, the through-hole may have a rectangular shape or an hourglass shape, but the present disclosure is not limited thereto. The bottom surface of the first cavity C1 may be provided by the exposed surface of the plurality of stacked insulating layers 113-2.

[0059] The other contents are substantially the same as those described in the printed circuit board 100A according to the above-described exemplary embodiment, and thus redundant descriptions thereof will be omitted.

[0060] Figure 7 It is schematically shown Figure 6 A cross-sectional view of a modified example embodiment of a printed circuit board.

[0061] Reference Figure 7 , the printed circuit board 100D according to the modified example embodiment may further include a fourth cavity C4, which penetrates at least one of the plurality of stacked insulating layers 113-1, 113-2, and 113-3 in the first direction and is connected to the first cavity C1. The fourth cavity C4 may expose at least a portion of at least one of the plurality of stacked wiring layers 124-1 and 124-2. The first cavity C1 and the fourth cavity C4 may have different wall surface inclinations. For example, the wall surface inclination of the fourth cavity C4 may be greater than the wall surface inclination of the first cavity C1. For example, the first cavity C1 may have a substantially vertical wall surface, and the fourth cavity C4 may have a tapered wall, and in cross section, the width of the fourth cavity C4 on one side connected to the first cavity C1 is greater than the width of the opposite side thereof.

[0062] The other contents are substantially the same as those described in the printed circuit board 100A according to the above-described example embodiment and the printed circuit board 100B according to the modified example embodiment thereof and the printed circuit board 100C according to the above-described other example embodiment, and therefore, redundant descriptions thereof will be omitted.

[0063] FIG. 8A to FIG. 8H is a schematic diagram showing the manufacturing Figure 6 and Figure 7 FIG. 1 is a process cross-sectional view of an example of a printed circuit board.

[0064] Reference Fig. 8A A double-sided buildup process is performed based on the core insulating layer 113-1, thereby forming a stacked body having a structure of a multi-layer core substrate, the stacked body including a plurality of built-up insulating layers 113-1 and 113-2, a first wiring layer 121, a plurality of built-up wiring layers 124-1, and a plurality of built-up via layers 133-1 and 133-2. In addition, based on the first direction, a first metal block 321 is formed on the built-up insulating layer 113-2 disposed on the outermost side (e.g., the uppermost side) of the plurality of built-up insulating layers 113-1 and 113-2 in a plating process.

[0065] Reference Figure 8B A second metal block 322 is further formed on the first metal block 321 by a plating process, thereby forming a metal block 320 that is thicker than the first wiring layer 121 in the first direction.

[0066] Reference Figure 8C , a first insulating layer 111 in which a metal block 320 is buried is formed on a plurality of built-up insulating layers 113-2 by a build-up process. In addition, a second wiring layer 122 is formed on and / or in the first insulating layer 111, and a first via layer 131 is formed in the first insulating layer 111. In this case, a built-up insulating layer 113-3, a built-up wiring layer 124-2, and a built-up via layer 133-3 are further formed on the opposite side thereof.

[0067] Reference Fig.8D , a second insulating layer 112 is formed on the first insulating layer 111 by a buildup process. In addition, a third wiring layer 123 is formed on and / or in the second insulating layer 112, and a second via layer 132 is formed in the second insulating layer 112. In this case, a buildup insulating layer 113-3, a buildup wiring layer 124-2, and a buildup via layer 133-3 are further formed on the opposite side thereof.

[0068] Reference Fig. 8E ,exist Fig.8DA first resist layer 141 and a second resist layer 142 are respectively formed on both surfaces of the stacked body formed in the embodiment. Next, a first opening h1 and a third cavity C3 are formed in the first resist layer 141 , and a second opening h2 is formed in the second resist layer 142 .

[0069] Reference Figure 8F , a second cavity C2 is formed in the first insulating layer 111 and the second insulating layer 112. The second cavity C2 may be formed by laser processing. For example, the second cavity C2 may be formed by laser processing the second insulating layer 112 exposed from the third cavity C3, and the metal block 320 buried in the first insulating layer 111 may be exposed.

[0070] Reference Figure 8G , a first cavity C1 is formed in the first insulating layer 111. The first cavity C1 may be formed by removing the metal block 320 by etching. Through a series of processes, the printed circuit board 100C according to the above another exemplary embodiment may be manufactured.

[0071] Reference Figure 8H , a fourth cavity C4 is formed in at least one of the plurality of stacked insulating layers 113-1, 113-2, and 113-3. The fourth cavity C4 may be formed by processing the stacked insulating layer 113-2 exposed from the first cavity C1, the second cavity C2, and the third cavity C3, which is disposed at the outermost side (e.g., the uppermost side) based on the first direction among the plurality of stacked insulating layers 113-1, 113-2, and 113-3, using a laser. The fourth cavity C4 may expose at least one of the plurality of stacked wiring layers 124-1 and 124-2 (e.g., a portion of the uppermost stacked wiring layer 124-1). Through a series of processes, the printed circuit board 100D according to the above-described modified example embodiment may be manufactured.

[0072] The other contents are substantially the same as those described in the printed circuit board 100A according to the above-described example embodiment and the printed circuit board 100B according to its modified example embodiment and the printed circuit board 100C according to the above-described other example embodiment and the printed circuit board 100D according to its modified example embodiment, and therefore, redundant descriptions thereof will be omitted.

[0073] Figures 9 to 11 is a cross-sectional view schematically showing another example of a printed circuit board.

[0074] Reference Fig. 9, a printed circuit board 100E according to another example embodiment may have a stacked package structure on which an electronic component 210 is mounted. For example, based on the first direction, the second package substrate 100-2 may be disposed on the first package substrate 100-1, the electronic component 210 may be disposed between the first package substrate 100-1 and the second package substrate 100-2, the first package substrate 100-1 and the second package substrate 100-2 may be connected by a first electrical connection metal 221, the electronic component 210 may be mounted on the first package substrate 100-1 by a second electrical connection metal 222, at least a portion of the electronic component 210 may be disposed in a cavity C of the second package substrate 100-2, and a third electrical connection metal 223 may be attached to the lower side of the first package substrate 100-1. The first package substrate 100-1 may be a core-type multilayer printed circuit board or a coreless multilayer printed circuit board. The second package substrate 100-2 may be the printed circuit board 100A according to the above-described example embodiment, but may have a smaller number of stacked insulating layers 113, stacked wiring layers 124, and stacked via layers 133. If necessary, the above-described printed circuit boards 100B, 100C, and 100D may be appropriately modified and applied to the second package substrate 100-2. The electronic component 210 may be an active component and / or a passive component, and may preferably include a semiconductor chip, but the present disclosure is not limited thereto. The first electrical connection metal 221, the second electrical connection metal 222, and the third electrical connection metal 223 may be solder balls or the like. In this way, a printed circuit board 100E according to another example embodiment may reduce the overall thickness of the printed circuit board by mounting electronic components via a cavity having the above-described structure.

[0075] Reference Fig.10 , a printed circuit board 100F according to another example embodiment may have a structure in which a mechanical part 230 is disposed in a cavity C of a package substrate. For example, a mechanical part 230 such as an optical cable may be disposed in a cavity C of a third package substrate 100-3. The third package substrate 100-3 may be a printed circuit board 100C according to the above-mentioned another example embodiment. If necessary, the above-mentioned printed circuit boards 100A, 100B, and 100D may be appropriately modified and applied to the third package substrate 100-3. In this way, in the case where a mechanical part such as an optical cable is placed in a package substrate, a printed circuit board 100F according to another example embodiment may provide a cavity having a large depth required to match the height of a chip and a mechanical part.

[0076] Reference Fig.11, a printed circuit board 100G according to another example embodiment may have a structure in which a thick component 250 is disposed in a cavity C of a package substrate. For example, a thick component 250 (such as a power inductor, etc.) may be disposed in a cavity C of a fourth package substrate 100-4 through a fourth electrical connection metal 224 (such as solder). The fourth package substrate 100-4 may be a printed circuit board 100D according to the above-mentioned modified example embodiment. If necessary, the above-mentioned printed circuit boards 100A, 100B, and 100C may be appropriately modified and applied to the fourth package substrate 100-4. In this way, a printed circuit board 100G according to another example embodiment may provide a cavity having a large depth required to place a thick component (such as a power inductor) on a package substrate.

[0077] The other contents are substantially the same as those described in the printed circuit board 100A according to the above-described example embodiment and the printed circuit board 100B according to its modified example embodiment and the printed circuit board 100C according to the above-described other example embodiment and the printed circuit board 100D according to its modified example embodiment, and therefore, redundant descriptions thereof will be omitted.

[0078] In the present disclosure, the slope of the wall surface can be compared by measuring the angle of the wall surface based on the second direction perpendicular to the first direction inside each cavity. The slope of the wall surface can be determined based on the size of the complementary angle of the angle of the wall surface relative to the second direction.

[0079] In the present disclosure, the expression "covering" may include the case of covering at least a part as well as the case of covering the whole, and may also include the case of direct covering and the case of indirect covering. In addition, the expression "filling" may include not only the case of complete filling but also the case of approximately filling, and may include, for example, the case of the presence of some holes or gaps.

[0080] In the present disclosure, as necessary, the wiring layer may be provided at a certain surface of the insulating layer, that is, including not only the case where the wiring layer is provided on the surface of the insulating layer but also the case where the wiring layer is partially or completely embedded in the surface of the insulating layer.

[0081] In the present disclosure, the meaning of "cross section" may refer to the cross-sectional shape when an object is cut vertically, or the shape when the object is viewed from a side perspective. In addition, the meaning of "plane" may refer to the shape when an object is cut horizontally, or the plane shape when the object is viewed from a top or bottom perspective.

[0082] In the present disclosure, the thickness, width, length, depth, etc. can be measured using a scanning microscope or an optical microscope based on a cross section in which the printed circuit board is polished or cut. The cut section can be a vertical section or a horizontal section, and each numerical value can be measured based on the desired cut section. When the numerical value is not constant, the numerical value can be determined as the average value of the values ​​measured at any five points. The width of the upper and / or lower ends of the via or cavity can be measured on a cross section obtained by cutting along the central axis of the via or cavity in the thickness direction of the substrate. The depth of the via or cavity can be measured as the distance from the upper end to the lower end of the via or cavity on a cross section obtained by cutting along the central axis of the via or cavity in the thickness direction of the substrate.

[0083] In the present disclosure, "lower" in lower side, lower part and lower surface is used to indicate the downward direction relative to the cross section of the drawings, and "upper" in upper side, upper part and upper surface is used to indicate the opposite direction thereto. In addition, "side" in side part, side surface, etc. is used to indicate the direction perpendicular to the up-down direction relative to the cross section of the drawings. However, the above directions are defined for convenience of explanation, and the scope of the claims is not specifically limited by the description of such directions, and the concepts of "upper" and "lower" may be changed at any time.

[0084] In the present disclosure, the meaning of "connection" is a concept that includes not only direct connection but also indirect connection through an adhesive layer or the like. In addition, the meaning of "electrical connection" is a concept that includes both physical connection and non-physical connection. In addition, expressions such as "first" and "second" are used to distinguish one component from another component and do not limit the order and / or importance of the components. In some cases, a first component may be referred to as a second component, or similarly, a second component may be referred to as a first component without departing from the scope of the claims.

[0085] The expression "exemplary embodiment" used in this disclosure does not mean the same embodiment, and is provided to explain different unique features. However, the exemplary embodiments presented above do not exclude being implemented in combination with features of other exemplary embodiments. For example, even if the content described in a specific exemplary embodiment is not described in other exemplary embodiments, these contents can also be understood as explanations related to other exemplary embodiments, unless there is an explanation contrary to or contradictory to the content in other exemplary embodiments.

[0086] The terms used in the present disclosure are only used to describe example embodiments and are not intended to limit the present disclosure. In this case, unless clearly indicated as a different meaning in the context, a singular expression includes a plural expression.

[0087] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: a first insulating layer having a first surface and a second surface opposite to each other in a first direction; a first wiring layer disposed on the first surface of the first insulating layer; a second wiring layer, disposed at the second surface of the first insulating layer; a second insulating layer having a third surface and a fourth surface opposite to each other in the first direction and disposed on the first insulating layer such that the third surface is connected to the second surface; a third wiring layer, disposed on the fourth surface of the second insulating layer; a first cavity penetrating a portion of the first insulating layer in the first direction; as well as a second cavity penetrating the second insulating layer in the first direction and connected to the first cavity, wherein the first cavity and the second cavity have different wall surface inclinations relative to the first direction, and Based on the first direction, a depth of the first cavity is smaller than a thickness of the first insulating layer and greater than a thickness of each of the first wiring layer and the second wiring layer.

2. The printed circuit board according to claim 1, wherein: An inclination of a wall surface of the second cavity relative to the first direction is greater than an inclination of a wall surface of the first cavity relative to the first direction.

3. The printed circuit board according to claim 2, wherein: The first cavity has a substantially vertical wall surface, and The second cavity has a tapered wall surface, and a width of a side of the second cavity connected to the first cavity is narrower than a width of an opposite side of the second cavity in cross section.

4. The printed circuit board according to claim 1, further comprising: a resist layer having a fifth surface and a sixth surface opposite to each other in the first direction, disposed on the second insulating layer so that the fifth surface is connected to the fourth surface, and having an opening exposing at least a portion of the third wiring layer; as well as A third cavity penetrates the resist layer in the first direction and is connected to the second cavity.

5. The printed circuit board according to claim 4, wherein: The second chamber and the third chamber have different inclinations of wall surfaces relative to the first direction.

6. The printed circuit board according to any one of claims 1 to 5, further comprising: a first via layer that penetrates the first insulating layer in the first direction and connects at least a portion of the first wiring layer and at least a portion of the second wiring layer to each other; a second via layer that penetrates the second insulating layer in the first direction and connects at least a portion of the second wiring layer and at least a portion of the third wiring layer to each other; A plurality of stacked insulating layers are disposed on the first surface of the first insulating layer; a plurality of built-up wiring layers, respectively arranged on the plurality of built-up insulating layers or in the plurality of built-up insulating layers in the first direction; as well as A plurality of stacked via layers respectively penetrate at least one stacked insulating layer among the plurality of stacked insulating layers in the first direction.

7. The printed circuit board according to claim 6, wherein: The first cavity penetrates a portion of the first insulating layer from the second surface in the first direction.

8. The printed circuit board according to claim 7, further comprising: a fourth cavity penetrating from the first cavity in the first direction through another portion of the first insulating layer and connected to the first cavity, wherein the fourth cavity exposes at least a portion of the first wiring layer, and An inclination of a wall surface of the fourth cavity relative to the first direction is greater than an inclination of a wall surface of the first cavity relative to the first direction.

9. The printed circuit board according to claim 8, wherein: The first cavity has a substantially vertical wall surface, and The fourth cavity has a tapered wall surface, and in cross section, a width of a side of the fourth cavity connected to the first cavity is greater than a width of an opposite side of the fourth cavity.

10. The printed circuit board according to claim 6, wherein: The first cavity penetrates a portion of the first insulating layer from the first surface in the first direction, and The second cavity further penetrates another portion of the first insulating layer from the second surface in the first direction to reach the first cavity.

11. The printed circuit board according to claim 10, further comprising: a fourth cavity penetrating at least a portion of at least one of the plurality of buildup insulating layers in the first direction and connected to the first cavity, The fourth cavity exposes at least a portion of at least one of the plurality of build-up wiring layers.

12. The printed circuit board according to claim 11, wherein An inclination of a wall surface of the fourth cavity relative to the first direction is greater than an inclination of a wall surface of the first cavity relative to the first direction.

13. The printed circuit board according to claim 12, wherein: The first cavity has a substantially vertical wall surface, and The fourth cavity has a tapered wall surface, and in cross section, a width of a side of the fourth cavity connected to the first cavity is greater than a width of an opposite side of the fourth cavity.

14. The printed circuit board according to claim 1, wherein: A bottom of the first cavity exposes a portion of the first insulating layer.

15. A printed circuit board, comprising: A first insulating layer having a first cavity; A first wiring layer and a second wiring layer are respectively arranged on the upper surface and the lower surface of the first insulating layer; a second insulating layer disposed on a lower surface of the first insulating layer, covering at least a portion of the second wiring layer, and having a second cavity connected to the first cavity; as well as a third wiring layer, disposed on the lower surface of the second insulating layer, Wherein, in the stacking direction of the printed circuit board, the first cavity is arranged between the first wiring layer and the second wiring layer.

16. The printed circuit board according to claim 15, wherein In the stacking direction of the printed circuit board, no wiring layer is provided between the first wiring layer and the second wiring layer.

17. The printed circuit board according to claim 15, further comprising: A resist layer is provided on a lower surface of the second insulating layer, covers the third wiring layer, has an opening exposing at least a portion of the third wiring layer, and has a third cavity connected to the second cavity.

18. The printed circuit board according to claim 17, wherein: The first insulating layer further includes a fourth cavity connected to the first cavity, In the stacking direction of the printed circuit board, the fourth cavity is provided between the first wiring layer and the second wiring layer, and The fourth cavity exposes at least a portion of the first wiring layer.

19. The printed circuit board according to claim 18, wherein In cross section, The average width of the first cavity is greater than the average width of the fourth cavity, The average width of the second cavity is greater than the average width of the first cavity, and The average width of the third cavity is greater than the average width of the second cavity.

20. The printed circuit board according to claim 15, wherein A bottom of the first cavity exposes a portion of the first insulating layer.

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