Preparation method of active region of semiconductor element

Abstract

The invention provides a preparation method of a semiconductor element. The method comprises the following steps: providing a substrate; forming a plurality of first mask layers on the substrate, wherein each of the first mask layers extends along a first direction; forming a plurality of second mask layers on the substrate, wherein each of the second mask layers extends along a second direction different from the first direction; forming a plurality of islands on the second mask layers; forming an opening pattern defining layer on the islands to define a plurality of second openings; removing the islands to form a plurality of third openings; forming a shear pattern by removing the second mask layers overlapping the second openings and the third openings along the third direction, wherein the third direction is orthogonal to the first direction and the second direction; patterning the first mask layers by means of the shear pattern; and patterning the substrate to define an active region. The opening pattern defining layer is formed by an atomic layer deposition process.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 2023115575462, filed on November 21, 2023, with the invention name of “Method for preparing the active region of a semiconductor element”. Application No. 2023115575462 claims priority and benefits of U.S. formal application No. 18 / 238,015 filed on August 25, 2023. The contents of the U.S. formal application are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a method for preparing a semiconductor element, and more particularly to a method for preparing an active region of a semiconductor element. Background Art

[0003] With the rapid development of the electronics industry, the development of integrated circuits (ICs) has achieved high performance and miniaturization. Technological advances in IC materials and design have produced many generations of ICs, each with smaller and more complex circuits than the previous generation.

[0004] Dynamic Random Access Memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Generally, DRAM is arranged in a square array with one capacitor and one transistor per cell. 2 DRAM cells are developed with vertical transistors, where F represents the minimum feature width or critical dimension (CD) of lithography. However, recently, as word line pitch continues to shrink, DRAM manufacturers are facing great challenges in reducing the memory cell area.

[0005] The above “prior art” description is only to provide background technology, and does not admit that the above “prior art” description reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0006] One aspect of the present disclosure provides a method for preparing a semiconductor element. The method includes: providing a substrate; forming a plurality of first mask layers on the substrate, wherein each of the first mask layers extends along a first direction; forming a plurality of second mask layers on the substrate, wherein each of the second mask layers extends along a second direction different from the first direction; forming a plurality of islands on the second mask layers; and forming an opening pattern definition layer on the islands to define a plurality of first openings; removing the islands to form a plurality of second openings; and forming a shear pattern by removing the second mask layers overlapping the first openings and the second openings along a third direction perpendicular to the first direction and the second direction; patterning the first mask layers by the shear pattern; and patterning the substrate to define an active region.

[0007] Another aspect of the present disclosure provides a method for preparing a semiconductor element. The method includes: providing a substrate; forming a plurality of first mask layers on the substrate, wherein each of the first mask layers extends along a first direction; forming a plurality of second mask layers on the substrate, wherein each of the second mask layers extends along a second direction different from the first direction; forming an opening pattern definition layer on the second mask layers to define a plurality of openings, which overlap with the second mask layers along a third direction, the third direction being substantially perpendicular to the first direction and the second direction; forming a first aperture modification layer to modify the size of the openings; patterning the second mask layers to form a shear pattern by removing the second mask layers overlapping the openings; patterning the first mask layers to form an active region definition pattern; and patterning the substrate to define an active region by the active region definition pattern.

[0008] The embodiments of the present disclosure provide a method for preparing a semiconductor element. In this embodiment, an aperture modification layer can be formed to reduce the size of an opening whose aperture is defined by a lithography process. Due to equipment limitations, the aperture defined by the lithography process cannot be reduced to a desired size, so an aperture modification layer can be formed to reduce the size of the opening. In this way, the semiconductor element can have an active area with a smaller pitch, which is conducive to forming more elements per unit area.

[0009] The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that form the subject of the claims of the present disclosure will be described below. Those with ordinary knowledge in the technical field to which the present disclosure belongs should understand that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A more complete understanding of the present disclosure may be obtained by referring to the detailed description and claims when considered in conjunction with the drawings, wherein like reference characters represent like elements throughout the drawings, and:

[0011] Figure 1A One or more stages of an exemplary method of fabricating a semiconductor device are shown according to some embodiments of the present disclosure.

[0012] Figure 1B According to some embodiments of the present disclosure, Figure 1A A cross-sectional view of the semiconductor device is shown along line AA'.

[0013] Figure 1C According to some embodiments of the present disclosure, Figure 1A A cross-sectional view of the semiconductor device taken along line BB' is shown.

[0014] Figure 2A One or more stages of an exemplary method of fabricating a semiconductor device are shown according to some embodiments of the present disclosure.

[0015] Figure 2B According to some embodiments of the present disclosure, Figure 2A A cross-sectional view of the semiconductor device is shown along line AA'.

[0016] Figure 2C According to some embodiments of the present disclosure, Figure 2A A cross-sectional view of the semiconductor device taken along line BB' is shown.

[0017] Figure 3A One or more stages of an exemplary method of fabricating a semiconductor device are shown according to some embodiments of the present disclosure.

[0018] Figure 3B According to some embodiments of the present disclosure, Figure 3A A cross-sectional view of the semiconductor device is shown along line AA'.

[0019] Figure 3C According to some embodiments of the present disclosure, Figure 3A A cross-sectional view of the semiconductor device taken along line BB' is shown.

[0020] Figure 4A One or more stages of an exemplary method of fabricating a semiconductor device are shown according to some embodiments of the present disclosure.

[0021] Figure 4B According to some embodiments of the present disclosure, Figure 4A A cross-sectional view of the semiconductor device is shown along line AA'.

[0022] Figure 4C According to some embodiments of the present disclosure, Figure 4A A cross-sectional view of the semiconductor device taken along line BB' is shown.

[0023] Figure 5A One or more stages of an exemplary method of fabricating a semiconductor device are shown according to some embodiments of the present disclosure.

[0024] Figure 5B According to some embodiments of the present disclosure, Figure 5A A cross-sectional view of the semiconductor device is shown along line AA'.

[0025] Figure 5C According to some embodiments of the present disclosure, Figure 5A A cross-sectional view of the semiconductor device taken along line BB' is shown.

[0026] Fig. 6A One or more stages of an exemplary method of fabricating a semiconductor device are shown according to some embodiments of the present disclosure.

[0027] Figure 6B According to some embodiments of the present disclosure, Fig. 6A A cross-sectional view of the semiconductor device is shown along line AA'.

[0028] Figure 6C According to some embodiments of the present disclosure, Fig. 6A A cross-sectional view of the semiconductor device taken along line BB' is shown.

[0029] Fig. 7A One or more stages of an exemplary method of fabricating a semiconductor device are shown according to some embodiments of the present disclosure.

[0030] Figure 7B According to some embodiments of the present disclosure, Fig. 7A A cross-sectional view of the semiconductor device is shown along line AA'.

[0031] Figure 7C According to some embodiments of the present disclosure, Fig. 7A A cross-sectional view of the semiconductor device taken along line BB' is shown.

[0032] Fig. 8A One or more stages of an exemplary method of fabricating a semiconductor device are shown according to some embodiments of the present disclosure.

[0033] Figure 8B According to some embodiments of the present disclosure, Fig. 8A A cross-sectional view of the semiconductor device is shown along line AA'.

[0034] Figure 8C According to some embodiments of the present disclosure, Fig. 8A A cross-sectional view of the semiconductor device taken along line BB' is shown.

[0035] Fig.9A One or more stages of an exemplary method of fabricating a semiconductor device are shown according to some embodiments of the present disclosure.

[0036] Fig. 9B According to some embodiments of the present disclosure, Fig.9A A cross-sectional view of the semiconductor device is shown along line AA'.

[0037] Fig. 9C According to some embodiments of the present disclosure, Fig.9A A cross-sectional view of the semiconductor device taken along line BB' is shown.

[0038] Fig. 10A One or more stages of an exemplary method of fabricating a semiconductor device are shown according to some embodiments of the present disclosure.

[0039] Fig. 10B According to some embodiments of the present disclosure, Fig. 10A A cross-sectional view of the semiconductor device is shown along line AA'.

[0040] Fig. 10C According to some embodiments of the present disclosure, Fig. 10A A cross-sectional view of the semiconductor device taken along line BB' is shown.

[0041] Fig.11A One or more stages of an exemplary method of fabricating a semiconductor device are shown according to some embodiments of the present disclosure.

[0042] Fig. 11B According to some embodiments of the present disclosure, Fig.11A A cross-sectional view of the semiconductor device is shown along line AA'.

[0043] Fig. 11C According to some embodiments of the present disclosure, Fig.11A A cross-sectional view of the semiconductor device taken along line BB' is shown.

[0044] Fig. 12A One or more stages of an exemplary method of fabricating a semiconductor device are shown according to some embodiments of the present disclosure.

[0045] Fig. 12B According to some embodiments of the present disclosure, Fig. 12A A cross-sectional view of the semiconductor device is shown along line AA'.

[0046] Fig. 12C According to some embodiments of the present disclosure, Fig. 12A A cross-sectional view of the semiconductor device taken along line BB' is shown.

[0047] Fig.13A One or more stages of an exemplary method of fabricating a semiconductor device are shown according to some embodiments of the present disclosure.

[0048] Fig. 13B According to some embodiments of the present disclosure, Fig.13A A cross-sectional view of the semiconductor device is shown along line AA'.

[0049] Fig. 13C According to some embodiments of the present disclosure, Fig.13A A cross-sectional view of the semiconductor device taken along line BB' is shown.

[0050] Fig.14A One or more stages of an exemplary method of fabricating a semiconductor device are shown according to some embodiments of the present disclosure.

[0051] Fig. 14B According to some embodiments of the present disclosure, Fig.14A A cross-sectional view of the semiconductor device is shown along line AA'.

[0052] Fig. 14C According to some embodiments of the present disclosure, Fig.14A A cross-sectional view of the semiconductor device taken along line BB' is shown.

[0053] Fig.15A One or more stages of an exemplary method of fabricating a semiconductor device are shown according to some embodiments of the present disclosure.

[0054] Fig. 15B According to some embodiments of the present disclosure, Fig.15A A cross-sectional view of the semiconductor device is shown along line AA'.

[0055] Fig. 15C According to some embodiments of the present disclosure, Fig.15A A cross-sectional view of the semiconductor device taken along line BB' is shown.

[0056] Fig.16A One or more stages of an exemplary method of fabricating a semiconductor device are shown according to some embodiments of the present disclosure.

[0057] Fig. 16B According to some embodiments of the present disclosure, Fig.16A A cross-sectional view of the semiconductor device taken along line CC' is shown.

[0058] Fig.17AOne or more stages of an exemplary method of fabricating a semiconductor device are shown according to some embodiments of the present disclosure.

[0059] Fig. 17B According to some embodiments of the present disclosure, Fig.17A A cross-sectional view of the semiconductor device taken along line CC' is shown.

[0060] Fig.18A and Fig.18B A flow chart of a method for preparing a semiconductor device is shown according to some embodiments of the present disclosure.

[0061] The reference numerals are described as follows:

[0062] 100: Semiconductor components

[0063] 102: Substrate

[0064] 102a: Active area

[0065] 102r: Groove

[0066] 106: Mask layer

[0067] 106a: Active area definition pattern

[0068] 108: Bottom

[0069] 112: Dielectric layer

[0070] 112a: Mask layer

[0071] 112b: Cut pattern

[0072] 114: Dielectric layer

[0073] 116: Dielectric layer

[0074] 118: Photosensitive layer

[0075] 120: Pitch definition layer

[0076] 122: Bottom

[0077] 124: Dielectric layer

[0078] 126: Dielectric layer

[0079] 128: Dielectric layer

[0080] 130: Photosensitive layer

[0081] 132: Island

[0082] 134: Opening pattern definition layer

[0083] 140: Aperture modification layer

[0084] 150: Aperture modification layer

[0085] 200: Methods

[0086] 202: Operation

[0087] 204: Operation

[0088] 206: Operation

[0089] 208: Operation

[0090] 210: Operation

[0091] 212: Operation

[0092] 214: Operation

[0093] 216: Operation

[0094] 218: Operation

[0095] 220: Operation

[0096] 222: Operation

[0097] 224: Operation

[0098] A-A': Line

[0099] B-B': Line

[0100] C-C': Line

[0101] G1: Clearance

[0102] G2: Gap

[0103] G3: Clearance

[0104] G4: Gap

[0105] O1: Opening

[0106] O2: Opening

[0107] O1': Opening

[0108] O2': Opening

[0109] O3: Opening

[0110] O4: Opening

[0111] P1: Pitch

[0112] P2: Pitch

[0113] P3: Pitch DETAILED DESCRIPTION

[0114] The following uses specific language to describe the embodiments or examples of the present disclosure shown in the drawings. It should be understood that it is not intended to limit the scope of the present disclosure. Any changes or modifications to the embodiments, and any further application of the principles described herein, are considered to be normal for those with ordinary knowledge in the technical field related to the present disclosure. Reference symbols can be reused in all embodiments, but this does not necessarily mean that the components of one embodiment are applicable to another embodiment, even if they use the same reference symbols.

[0115] It will be understood that when an element is referred to as being “connected to” or “coupled to” another element, the initial element may be directly connected or coupled to the other element or other intervening elements.

[0116] It should be understood that, although the first, second, third and other words can be used herein to describe various elements, components, regions, layers or parts, these elements, components, regions, layers or parts are not limited to these words. On the contrary, these words are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teaching of the present disclosure concept, the first element, component, region, layer or part discussed below can be referred to as the second element, component, region, layer or part.

[0117] The terms used herein are for the purpose of describing specific example embodiments only and are not intended to limit the concepts of the present disclosure. As used herein, the singular forms "a / an" and "the" also include the plural forms unless the context clearly indicates otherwise. It should be further understood that the terms "comprises" and "comprising" when used in this specification indicate the presence of the described parts, integers, steps, operations, elements, or components, but do not exclude the presence or increase of one or more parts, integers, steps, operations, elements, components, or combinations of the foregoing.

[0118] It should be noted that the word "approximately" to modify the amount of an ingredient, component, or reactant used in the present disclosure refers to quantitative variations that may occur, for example, through typical measurement and liquid handling procedures used to prepare concentrates or solutions. In addition, variations may occur due to inadvertent errors in measurement procedures, differences in the manufacture, source, or purity of the ingredients used to make the composition or implement the method. On the one hand, the word "approximately" means within 10% of the reported value. On the other hand, the word "approximately" means within 5% of the reported value. Again, on the other hand, the word "approximately" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0119] Figures 1A to 17AVarious stages of an exemplary method of preparing a semiconductor element are shown according to some embodiments of the present disclosure; Figures 1B to 15B Show along Figures 1A to 15A A cross-sectional view of the semiconductor element taken along line AA'; Figure 1C to Figure 15C Show along Figures 1A to 15A A cross-sectional view of the semiconductor element taken along line BB'; Fig. 16B and Fig. 17B Show along Fig.16A and Fig.17A A cross-section of a semiconductor element is shown along line CC'. It should be noted that some elements have been omitted for the sake of simplicity.

[0120] Reference Figure 1A , Figure 1B ,and Figure 1C , a substrate 102 may be provided. The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate 102 may include an elemental semiconductor including a single crystal form, a polycrystalline form, or an amorphous form of silicon or germanium; a compound semiconductor material including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or a combination of the foregoing. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy having a gradient Ge feature, wherein the Si and Ge composition changes from one ratio at one location of the gradient SiGe feature to another ratio at another location of the gradient SiGe feature. In another embodiment, the SiGe alloy is formed on a silicon substrate. In some embodiments, another material in contact with the SiGe alloy may cause the SiGe alloy to be mechanically strained. In some embodiments, the substrate 102 may have a multi-layer structure, or the substrate 102 may include a multi-layer compound semiconductor structure.

[0121] A plurality of mask layers 106 may be formed on the substrate 102. Each mask layer 106 may extend along a direction that is not parallel to the X-direction and the Y-direction. The mask layer 106 may be configured to define an active region of the substrate 102. A portion of the substrate 102 may be exposed by the mask layer 106. The mask layer 106 may include silicon oxycarbide, silicon carbide, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, or other suitable materials. The mask layer 106 may be fabricated using chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), or other suitable processes.

[0122] Reference Figure 2A , Figure 2B ,and Figure 2C , a bottom layer 108 may be formed on the mask layer 106. The bottom layer 108 may fill the opening defined by the mask layer 106. The bottom layer 108 may include a dielectric material, such as a polymer or other suitable material. For example, the manufacturing technology of the bottom layer 108 may include a spin coating process or other suitable processes.

[0123] A dielectric layer 112 may be formed on the bottom layer 108. The dielectric layer 112 may be configured to form a mask to define an active region definition pattern, which will be described later. The dielectric layer 112 may include silicon oxide, silicon oxycarbide, silicon carbide, silicon nitride, silicon carbonitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, or other suitable materials. The fabrication techniques of the dielectric layer 112 may include CVD, ALD, PVD, LPCVD, PECVD, or other suitable processes.

[0124] A dielectric layer 114 may be formed on the dielectric layer 112. The dielectric layer 114 may be configured to be used as a mask to define a pattern of the dielectric layer 112. In some embodiments, the dielectric layer 114 may include a carbon-containing material, such as amorphous carbon or other suitable materials. The fabrication techniques of the dielectric layer 114 may include CVD, ALD, PVD, LPCVD, PECVD, or other suitable processes.

[0125] A dielectric layer 116 may be formed on the dielectric layer 114. The dielectric layer 116 may be used as a dielectric anti-reflection coating (DARC). The dielectric layer 116 may include silicon oxynitride, silicon oxycarbide, silicon carbide, silicon nitride, silicon carbonitride, or a suitable material. The fabrication technique of the dielectric layer 116 may include CVD, ALD, PVD, LPCVD, PECVD, spin coating, or other suitable processes.

[0126] A photosensitive layer 118 (or a photoresist pattern) may be formed on the dielectric layer 116. The photosensitive layer 118 may extend along the Y direction. The photosensitive layer 118 may include photoresist or other suitable materials.

[0127] Reference Figure 3A , Figure 3B ,and Figure 3C , a pitch definition layer 120 may be formed on the dielectric layer 116 and on the side surface (not marked) of the photosensitive layer 118. Each segment of the pitch definition layer 120 may extend along the Y direction. The pitch definition layer 120 may include silicon oxynitride, silicon oxycarbide, silicon carbide, silicon nitride, silicon carbonitride, or a suitable material. The manufacturing technology of the pitch definition layer 120 may include CVD, ALD, PVD, LPCVD, PECVD, spin coating, or other suitable processes.

[0128] A portion of dielectric layer 116 may be exposed by photosensitive layer 118 and pitch definition layer 120. This portion of dielectric layer 116 may not vertically overlap photosensitive layer 118 and pitch definition layer 120 along the Z direction. In some embodiments, photosensitive layer 118 may be removed after pitch definition layer 120 is formed.

[0129] Reference Figure 4A , Figure 4B ,and Figure 4C , the dielectric layer 112 may be patterned to form a mask layer 112a. Portions of the dielectric layer 112 that do not overlap the pitch definition layer 120 may be removed. Next, the dielectric layer 114, the dielectric layer 116, and the pitch definition layer 120 may be removed. In some embodiments, the mask layer 112a may be fabricated using a self-aligning double patterning (SADP) process.

[0130] In some embodiments, the extension direction of the mask layer 112a and the extension direction of the mask layer 106 can define an angle θ in a top view. In some embodiments, the angle θ can range from about 20° to about 35°, such as 20°, 22°, 24°, 26°, 28°, 30°, 33°, or 35°.

[0131] In some embodiments, the width of the mask layer 112a may be defined by the pitch definition layer 120. In some embodiments, the pitch P1 of the mask layer 112a may be defined by the pitch definition layer 120. In some embodiments, the width of the pitch definition layer 120 may be controlled to determine the thickness of the mask layer 112a.

[0132] Reference Figure 5A , Figure 5B ,and Figure 5C , a bottom layer 122 may be formed on the bottom layer 108. The bottom layer 122 may fill the opening defined by the mask layer 112a. The bottom layer 122 may include a dielectric material, such as a polymer or other suitable material. For example, the manufacturing technology of the bottom layer 122 may include a spin coating process or other suitable processes.

[0133] A dielectric layer 124 may be formed on the bottom layer 122. The dielectric layer 124 may include silicon oxide, silicon oxycarbide, silicon carbide, silicon nitride, silicon carbonitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, or other suitable materials. The manufacturing technology of the dielectric layer 124 may include CVD, ALD, PVD, LPCVD, PECVD, or other suitable processes.

[0134] A dielectric layer 126 may be formed on the dielectric layer 124. The dielectric layer 126 may be configured to be used as a mask to define a pattern of the dielectric layer 124. In some embodiments, the dielectric layer 126 may include a carbon-containing material, such as amorphous carbon. The fabrication techniques of the dielectric layer 126 may include CVD, ALD, PVD, LPCVD, PECVD, or other suitable processes.

[0135] A dielectric layer 128 may be formed on the dielectric layer 126. The dielectric layer 128 may be used as a dielectric anti-reflective coating (DARC). The dielectric layer 128 may include silicon oxynitride, silicon oxycarbide, silicon carbide, silicon nitride, silicon carbonitride, or a suitable material. The fabrication technique of the dielectric layer 128 may include CVD, ALD, PVD, LPCVD, PECVD, spin coating, or other suitable processes.

[0136] Reference Fig. 6A , Figure 6B ,and Figure 6C , a photosensitive layer 130 (or photoresist pattern) may be formed on the dielectric layer 128. The photosensitive layer 130 may define a plurality of openings O1. The openings O1 may expose a portion of the dielectric layer 128. The photosensitive layer 130 may include photoresist or other suitable materials. The openings O1 may include a circular profile, an elliptical profile, or other suitable profiles. In some embodiments, the pitch of the openings O1 may be twice the pitch of the mask layer 112a along the X direction.

[0137] Reference Fig. 7A , Figure 7B ,and Figure 7C , a plurality of islands 132 may be formed in the opening O1 of the photosensitive layer 130. In some embodiments, the islands 132 may include silicon oxide, silicon oxycarbide, silicon carbide, silicon nitride, silicon carbonitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, or other suitable materials. The manufacturing technology of the islands 132 may include CVD, ALD, PVD, LPCVD, PECVD, or other suitable processes.

[0138] In some embodiments, a dielectric material may be deposited to cover the photosensitive layer 130, and then a polishing process (e.g., a chemical mechanical polishing (CMP) process) may be performed to remove the upper portion of the dielectric material until the photosensitive layer 130 is exposed, and then the photosensitive layer 130 may be removed. In some embodiments, the islands 132 may include a circular profile, an elliptical profile, or other suitable profiles. In some embodiments, the pitch of the islands 132 may be twice the pitch of the mask layer 112a.

[0139] Reference Fig. 8A , Figure 8B ,and Figure 8C , an opening pattern definition layer 134 may be formed. In some embodiments, the opening pattern definition layer 134 may be formed on the side surface (not marked) of the island 132. In some embodiments, the opening pattern definition layer 134 may include silicon nitride, silicon oxycarbide, silicon carbide, silicon oxide, silicon carbonitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, or other suitable materials. The manufacturing technology of the opening pattern definition layer 134 may include ALD, CVD, PVD, LPCVD, PECVD, or other suitable processes.

[0140] The opening pattern definition layer 134 may define a plurality of openings O2. In some embodiments, the profile of the openings O2 may be different from the profile of the openings O1. Fig. 8A The opening O2 is shown to have an irregular profile or a profile similar to a diamond profile, and the opening O2 may have other profiles, such as a circular profile or an elliptical profile, configured according to a deposition rate, temperature, or other process conditions to form the opening pattern definition layer 134. In some embodiments, the opening pattern definition layer 134 may include two or more materials formed in different stages to modify or control the profile of the opening pattern definition layer 134.

[0141] Reference Fig.9A , Fig. 9B ,and Fig. 9C, the island 132 may be removed. The opening O1 may be defined by the opening pattern definition layer 134. In some embodiments, the openings O1 and O2 may be configured alternately. One of the openings O1 may be surrounded or abutted by four openings O2. In some embodiments, the size (e.g., area or aperture) of the opening O1 may be substantially the same as the size of the opening O2.

[0142] In some embodiments, the pitch P2 of the openings O1 may be substantially the same as the pitch P3 of the openings O2 along the X direction. In some embodiments, the pitch P2 of the openings O1 may be twice the pitch P1 of the mask layer 112a along the X direction. Figure 4A In some embodiments, the pitch P3 of the opening O2 may be twice the pitch P1 of the mask layer 112a along the X direction. Figure 4A shown.

[0143] Reference Fig. 10A , Fig. 10B ,and Fig. 10C , an aperture modification layer 140 may be formed. In some embodiments, the aperture modification layer 140 may be formed on the side surface of the opening pattern definition layer 134. In some embodiments, the aperture modification layer 140 may be configured to define, control or modify the size of the openings O1 and O2, thereby defining openings O1' and O2' corresponding to the openings O1 and O2. In some embodiments, the size (e.g., area or aperture) of the opening O1' may be smaller than the size of the opening O1. In some embodiments, the size (e.g., area or aperture) of the opening O2' may be smaller than the size of the opening O2. The profile of the opening O2' may be modified or controlled by the aperture modification layer 140.

[0144] In some embodiments, the aperture modification layer 140 may include silicon oxide, silicon oxycarbide, silicon carbide, silicon nitride, silicon carbonitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, or other suitable materials. The manufacturing technology of the aperture modification layer 140 may include CVD, ALD, PVD, LPCVD, PECVD, or other suitable processes. The formation of the aperture modification layer 140 may be optional. In other embodiments, the formation of the aperture modification layer 140 may be omitted.

[0145] Reference Fig.11A , Fig. 11B ,and Fig. 11C, an etching process such as a dry etching process or a reactive ion etching (RIE) process may be performed. The opening pattern definition layer 134 and the aperture modification layer 140 may be used together as a hard mask, and a portion of the mask layer 112a, the bottom layer 122, the dielectric layer 124, the dielectric layer 126, and the dielectric layer 128 may be partially etched. In some embodiments, the mask layer 112a exposed by the opening O1' (or the opening O1) may be removed. In some embodiments, the mask layer 112a exposed by the opening O2' (or the opening O2) may be removed. As a result, a shear pattern 112b may be defined.

[0146] Reference Fig. 12A , Fig. 12B ,and Fig. 12C , the bottom layer 122, the dielectric layer 124, the dielectric layer 126, the dielectric layer 128, the opening pattern definition layer 134, and the aperture modification layer 140 may be removed to expose the shear pattern 112b. Fig. 12A As shown, each segment of the shear pattern 112b may extend along the Y direction. From a top view, the side surface of the shear pattern 112b may have a concave profile. The shear pattern 112b may define gaps G1 and G2 corresponding to the positions of the openings O1 and O2, respectively. In some embodiments, each segment of the shear pattern 112b may overlap vertically with two mask layers 106. In some embodiments, the length of one of the gaps G1 and G2 along the Y direction may be greater than the length of one of the mask layers 106 along the Y direction. In some embodiments, the size of the gaps G1 and G2 may be determined by the aperture modification layer 140.

[0147] Reference Fig.13A , Fig. 13B ,and Fig. 13C , an aperture modification layer 150 may be formed to define the openings O3 and O4. In some embodiments, the aperture modification layer 150 may be formed on the side surface of the shear pattern 112b. In some embodiments, the aperture modification layer 150 may include silicon oxide, silicon oxycarbide, silicon carbide, silicon nitride, silicon carbonitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, or other suitable materials. The fabrication technology of the aperture modification layer 150 may include ALD, CVD, PVD, LPCVD, PECVD, or other suitable processes.

[0148] In some embodiments, the aperture modification layer 150 may be configured to define, modify and / or control the size of the openings O3 and O4 to more accurately define the active area of ​​the substrate 102. The positions of the openings O3 and O4 may correspond to the positions of the openings O1 and O2, respectively. In some embodiments, the opening O3 may have a circular profile, an elliptical profile, or other suitable profiles. In some embodiments, the opening O4 may have a circular profile, an elliptical profile, or other suitable profiles. In some embodiments, the size (e.g., area or aperture) of the opening O3 may be smaller than the size of the opening O1. In some embodiments, the size (e.g., area or aperture) of the opening O4 may be smaller than the size of the opening O2. In some embodiments, the aperture modification layer 150 may include two or more materials formed by different stages or process conditions.

[0149] Reference Fig.14A , Fig. 14B ,and Fig. 14C , an etching process such as a dry etching process or an RIE process may be performed to etch a portion of the mask layer 106, the bottom layer 108, and the aperture modification layer 150. The mask layer 106 may be patterned. In some embodiments, the cut pattern 112 b and the aperture modification layer 150 may be used as a hard mask to define a pattern of the etched mask layer 106. The mask layer 106 exposed by the cut pattern 112 b and the aperture modification layer 150 may be removed.

[0150] Reference Fig.15A , Fig. 15B ,and Fig. 15C , the bottom layer 108 may be removed. The cut pattern 112b may be removed. The aperture modification layer 150 may be removed. The active area defining pattern 106a may be defined. The active area defining pattern 106a may be configured to define a pattern of an active area of ​​the substrate 102.

[0151] Each segment of the active area defining pattern 106a may extend in a direction that is not parallel to the X direction and the Y direction. In some embodiments, the active area defining pattern 106a may define gaps G3 and G4. The positions of the gaps G3 and G4 may correspond to the positions of the gaps G1 and G2, respectively. In some embodiments, the size (e.g., length or width) of the gap G3 may be smaller than the size of the gap G1. In some embodiments, the size (e.g., length or width) of the gap G4 may be smaller than the size of the gap G2.

[0152] Reference Fig.16A and Fig. 16B, the substrate 102 may be patterned to define an active region 102a. The substrate 102 exposed by the active region defining pattern 106a may be etched to form a recess 102r recessed from the upper surface of the substrate 102. In some embodiments, each segment of the active region 102a may have a circular profile, an elliptical profile, or other suitable profiles. In some embodiments, each segment of the active region 102a may have a long axis substantially parallel to the mask layer 106, such as Figure 1A shown.

[0153] Reference Fig.17A and Fig. 17B , the active region defining pattern 106a may be removed, and the active region 102a of the substrate 102 may be exposed. As a result, a semiconductor device 100 may be produced.

[0154] In some embodiments, the semiconductor element 100 can be configured to form a memory element. The memory element may include, for example, a dynamic random access memory (DRAM) element, a one-time programming (OTP) memory element, a static random access memory (SRAM) element, or other suitable memory elements. In some embodiments, the DRAM may include, for example, transistors, capacitors, and other components. During a read operation, the word line (WL) may be asserted, thereby turning on the transistor. The turned-on transistor allows the sense amplifier to read the voltage across the capacitor through the bit line (BL). During a write operation, the data to be written can be provided on the BL when the WL is asserted.

[0155] For example, the recess 102r may be filled with an isolation material to separate each segment of the active region 102a. Word lines, capacitors, and / or other devices may be formed on the active region 102a to create a memory device.

[0156] It should be noted that due to the topography of the structure, the etching rate is not uniform, so the contour of the etched object may not inherit the contour of the mask layer.

[0157] Fig.18A and Fig.18B A flow chart of a method 200 for manufacturing a semiconductor device is shown according to some embodiments of the present disclosure.

[0158] Reference Fig.18A The method 200 may begin at operation 202 by providing a substrate and forming a plurality of first mask layers on the substrate.

[0159] The method 200 may continue with operation 204 by forming a first dielectric layer on the first mask layers and forming a photoresist pattern on the first dielectric layer.

[0160] The method 200 may continue with operation 206 by forming a pitch definition layer on the side surfaces of the photoresist pattern.

[0161] The method 200 may continue with operation 208 by patterning the first dielectric layer to form a plurality of second mask layers. The first mask layer and the second mask layer may define an angle ranging from about 20° to about 35°.

[0162] The method 200 may continue to operation 210 by forming a second dielectric layer on the second mask layers, forming a photosensitive layer on the second dielectric layer, and defining a plurality of first openings overlapping the second mask layers.

[0163] The method 200 may continue with operation 212 where a plurality of islands may be formed within the first openings. The photosensitive layer may be removed.

[0164] Reference Fig.18B The method 200 may proceed to operation 214, where an opening pattern definition layer may be formed to define a plurality of second openings. The contours of the second openings may be different from the contours of the first openings. The second openings and the first openings may be alternately arranged.

[0165] The method 200 may continue to operation 216 where a first aperture modification layer may be formed to reduce the size of the first openings and the second openings. The profiles of the first openings and the second openings may be modified. The formation of the first aperture modification layer may be optional.

[0166] The method 200 may continue with operation 218 where the second mask layers may be patterned to form a shear pattern. The shear pattern defines a plurality of gaps vertically overlapping the first mask layers.

[0167] Method 200 may continue to operation 220, where a second aperture modification layer may be formed to form a plurality of third openings and a plurality of fourth openings. The positions of the third openings may correspond to the first openings. The positions of the fourth openings may correspond to the second openings. The size of the third openings may be smaller than the size of the first openings. The size of the fourth openings may be smaller than the size of the second openings.

[0168] The method 200 may continue to operation 222 where the first mask layers may be patterned to form an active area definition pattern.

[0169] The method 200 may continue to operation 224 where the substrate may be patterned to define an active region. As a result, a semiconductor device may be produced.

[0170] Method 200 is merely an example and is not intended to limit the present disclosure beyond what is explicitly stated in the claims. Additional operations may be provided before, during, or after each operation of method 200, and some of the operations described may be replaced, removed, or reordered for additional embodiments of the method. In some embodiments, method 200 may include: Fig.18A and Fig.18B In some embodiments, method 200 may include: Fig.18A and Fig.18B One or more operations depicted in .

[0171] One aspect of the present disclosure provides a method for preparing a semiconductor element. The method includes: providing a substrate; forming a plurality of first mask layers on the substrate, wherein each of the first mask layers extends along a first direction; forming a plurality of second mask layers on the substrate, wherein each of the second mask layers extends along a second direction different from the first direction; forming a plurality of islands on the second mask layers; and forming an opening pattern definition layer on the islands to define a plurality of first openings; removing the islands to form a plurality of second openings; and forming a shear pattern by removing the second mask layers overlapping the first openings and the second openings along a third direction perpendicular to the first direction and the second direction; patterning the first mask layers by the shear pattern; and patterning the substrate to define an active region.

[0172] Another aspect of the present disclosure provides a method for preparing a semiconductor element. The method includes: providing a substrate; forming a plurality of first mask layers on the substrate, wherein each of the first mask layers extends along a first direction; forming a plurality of second mask layers on the substrate, wherein each of the second mask layers extends along a second direction different from the first direction; forming an opening pattern definition layer on the second mask layers to define a plurality of openings, which overlap with the second mask layers along a third direction, the third direction being substantially perpendicular to the first direction and the second direction; forming a first aperture modification layer to modify the size of the openings; patterning the second mask layers to form a shear pattern by removing the second mask layers overlapping the openings; patterning the first mask layers to form an active region definition pattern; and patterning the substrate to define an active region by the active region definition pattern.

[0173] The embodiments of the present disclosure provide a method for preparing a semiconductor element. In this embodiment, an aperture modification layer can be formed to reduce the size of an opening whose aperture is defined by a lithography process. Due to equipment limitations, the aperture defined by the lithography process cannot be reduced to a desired size, so an aperture modification layer can be formed to reduce the size of the opening. In this way, the semiconductor element can have an active area with a smaller pitch, which is conducive to forming more elements per unit area.

[0174] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes may be implemented in different ways, and other processes or combinations of the above processes may be substituted for many of the above processes.

[0175] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A method for preparing a semiconductor element, comprising: providing a substrate; Forming a plurality of first mask layers on the substrate, wherein each of the plurality of first mask layers extends along a first direction; Forming a plurality of second mask layers on the substrate, wherein each of the plurality of second mask layers extends along a second direction different from the first direction; forming a plurality of islands on the plurality of second mask layers; forming an opening pattern definition layer on the plurality of islands to define a plurality of first openings; removing the plurality of islands to form a plurality of second openings; Forming a shear pattern by removing the second mask layers overlapping the first openings and the second openings along a third direction, wherein the third direction is orthogonal to the first direction and the second direction; patterning the plurality of first mask layers by using the shear pattern; as well as patterning the substrate to define an active region, The opening pattern definition layer is formed by an atomic layer deposition process. 2 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein an angle defined by the first direction and the second direction ranges from about 20° to about 35°.

3. The method for preparing a semiconductor device according to claim 1, further comprising: A first aperture modification layer is formed on the cut pattern to define a plurality of third openings which overlap with the plurality of first mask layers along the third direction. 4 . The method for manufacturing a semiconductor device as claimed in claim 3 , wherein patterning the plurality of first mask layers comprises removing the plurality of first mask layers overlapping the plurality of third openings along the third direction. 5 . The method for manufacturing a semiconductor device as claimed in claim 3 , wherein the manufacturing technology of the first aperture modification layer comprises an atomic layer deposition process. 6 . The method for manufacturing a semiconductor device as claimed in claim 3 , wherein the first aperture modification layer comprises oxide, nitride, oxynitride, or a combination thereof.

7. The method for preparing a semiconductor device according to claim 1, further comprising: A second aperture modification layer is formed on the plurality of islands to modify the sizes of the plurality of first openings and the plurality of second openings. 8 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the plurality of second openings and the plurality of first openings are arranged alternately. 9 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein a pitch of the plurality of second openings is substantially equal to a pitch of the plurality of first openings.

10. The method for manufacturing a semiconductor device as claimed in claim 1, wherein forming the plurality of second mask layers comprises: forming a dielectric layer on the plurality of first mask layers; forming a photoresist pattern on the dielectric layer; forming a pitch definition layer on the photoresist pattern; as well as The dielectric layer is patterned by removing portions of the dielectric layer that do not overlap the photoresist pattern and the pitch definition layer along the third direction. 11 . The method for manufacturing a semiconductor device as claimed in claim 10 , wherein a pitch of the plurality of second mask layers is defined by the pitch definition layer.

12. A method for preparing a semiconductor element, comprising: providing a substrate; Forming a plurality of first mask layers on the substrate, wherein each of the plurality of first mask layers extends along a first direction; Forming a plurality of second mask layers on the substrate, wherein each of the plurality of second mask layers extends along a second direction different from the first direction; forming an opening pattern definition layer on the plurality of second mask layers to define a plurality of first openings, which overlaps with the plurality of second mask layers along a third direction, the third direction being substantially perpendicular to the first direction and the second direction; patterning the plurality of second mask layers to form a shear pattern by removing the plurality of second mask layers overlapping the plurality of first openings; patterning the plurality of first mask layers to form an active area definition pattern; as well as The substrate is patterned to define an active region by the active region definition pattern.

13. The method for preparing a semiconductor device according to claim 12, further comprising: A first aperture modification layer is formed to modify the sizes of the plurality of first openings. 14 . The method for manufacturing a semiconductor device as claimed in claim 13 , wherein the first aperture modification layer comprises oxide, nitride, oxynitride, or a combination thereof. 15 . The method for manufacturing a semiconductor device as claimed in claim 12 , wherein an angle defined by the first direction and the second direction ranges from about 20° to about 35°.

16. The method for preparing a semiconductor device as claimed in claim 12, further comprising: A second aperture modification layer is formed on the cut pattern to define a plurality of second openings which overlap with the plurality of first mask layers along the third direction. 17 . The method for manufacturing a semiconductor device as claimed in claim 16 , wherein patterning the plurality of first mask layers comprises removing the first mask layers overlapping the plurality of second openings along the third direction. 18 . The method for manufacturing a semiconductor device as claimed in claim 16 , wherein the manufacturing technology of the second aperture modification layer comprises an atomic layer deposition process.

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