Bipolar junction transistor device
By setting up an isolation layer in the BJT device, the current gain drop caused by the emitter current edge collection effect is solved, and a higher current gain and more efficient emitter injection are achieved.
Patent Information
- Application Number
- CN202411629732.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-14
- Publication Date
- 2025-02-25
AI Technical Summary
There is an emitter current edge collection effect in traditional BJT devices, which leads to a decrease in the current gain and cannot fully utilize the area of the emitter junction.
By providing an isolation layer between the second heavily doped region and the first shallow groove isolation structure, the influence of the resistance voltage drop in the base region is reduced, and the emitter current edge collecting effect is effectively suppressed.
It effectively improves the current gain of the BJT device and significantly improves the injection efficiency of the emitter.
Smart Images
Figure CN119521690A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a bipolar junction transistor (BJT) device. Background Art
[0002] In the BCD process (BCD process is a monolithic integration process technology that integrates bipolar transistors (Bipolar), CMOS and DMOS devices on the same chip), in the traditional vertical NPN and PNP BJT devices, reference Figure 1 As shown, due to the existence of the base resistance, when the emitter junction of the BJT device is in a forward biased state, when the base current flows horizontally in the base region 200, a certain voltage drop will be generated on the base resistance, making the potentials of the points below the emitter region 100 different, resulting in a higher potential at the edge of the emitter junction and a lower potential at the center of the emitter junction, and the emitter junction current is concentrated at the edge of the emitter junction, that is, the emitter current gathering effect. Due to the existence of the emitter current gathering effect, the area of the emitter junction cannot be fully utilized, which reduces the injection efficiency of the emitter and reduces the current gain of the BJT device.
[0003] Traditional BJT devices have a SAB guard ring 300 (metal silicide barrier layer) at the edge of the emitter. The SAB guard ring prevents the formation of alkali metal silicide at the edge of the emitter junction, which increases the contact resistance at the edge of the emitter and can alleviate the current crowding effect to a certain extent. However, this method cannot significantly suppress the current crowding effect.
[0004] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention
[0005] The object of the present invention is to provide a bipolar junction transistor (BJT) device, which can solve the problem of BJT device gain reduction caused by the emitter current crowding effect, improve the current gain of the BJT device, and achieve better effect.
[0006] In order to achieve the above object, a technical solution provided by a specific embodiment of the present invention is as follows:
[0007] A bipolar junction transistor device, comprising:
[0008] A substrate, wherein a first well region and a second well region are disposed in the substrate;
[0009] A first heavily doped region, disposed in the first well region;
[0010] A second heavily doped region, disposed in the second well region;
[0011] A third heavily doped region, disposed in the second well region and having a first separation space formed between the third heavily doped region and the second heavily doped region;
[0012] A first shallow trench isolation structure is disposed in the second well region and is located in the first spacing space, and a second spacing space is formed between the first shallow trench isolation structure and the second heavily doped region;
[0013] The isolation layer is arranged in the second spacing space and partially extends into the second well region. The isolation layer is at least arranged in contact with the second heavily doped region.
[0014] In one or more embodiments of the present invention, the isolation layer partially covers the second heavily doped region.
[0015] In one or more embodiments of the present invention, the width of the second space is in the range of 0.5 μm-2 μm.
[0016] In one or more embodiments of the present invention, the isolation layer is disposed in contact with the first shallow trench isolation structure.
[0017] In one or more embodiments of the present invention, the isolation layer is formed by a silicon local oxidation isolation process.
[0018] In one or more embodiments of the present invention, the first well region is a collector region of a bipolar junction transistor device, and the first well region is led out to the top surface of the substrate through the first heavily doped region;
[0019] The second well region is a base region of a bipolar junction transistor device, and the second well region is led out to the top surface of the substrate through the third heavily doped region;
[0020] The second heavily doped region is an emitter region of a bipolar junction transistor device.
[0021] In one or more embodiments of the present invention, the first well region has a first doping type;
[0022] The first heavily doped region has a first doping type;
[0023] The second heavily doped region has a first doping type;
[0024] The second well region has a second doping type opposite to the first doping type;
[0025] The third heavily doped region has the second doping type.
[0026] In one or more embodiments of the present invention, the bipolar junction transistor device also includes a third well region, which is arranged in the substrate and below the second well region. The third well region is connected to the first well region, and the doping type of the third well region is the same as that of the first well region.
[0027] In one or more embodiments of the present invention, the first well region, the first heavily doped region, the third heavily doped region, and the isolation layer are all configured as a ring structure.
[0028] In one or more embodiments of the present invention, the bipolar junction transistor device further includes a second shallow trench isolation structure, which is disposed in the substrate and located between the adjacent first well region and the second well region.
[0029] Compared with the prior art, the bipolar junction transistor device of the present invention reduces the influence of the base resistance voltage drop by setting the interval between the second heavily doped region and the first shallow trench isolation structure and setting the isolation layer in the space between the two, and effectively suppresses the emitter current edge collection effect. At the same time, since the second heavily doped region is far away from the first shallow trench isolation structure, the composite current generated at the edge of the first shallow trench isolation structure can be effectively reduced, and the current of the second well region (base region) is also reduced, and the current gain of the BJT device is also improved.
[0030] The bipolar junction transistor device of the present invention first forms an isolation layer through the Locos process (silicon local oxidation isolation process) and then forms the second heavily doped region, so that the second heavily doped region is not formed in the area covered by the isolation layer, and the second heavily doped region is far away from the first shallow trench isolation structure, thereby reducing the recombination current at the edge of the first shallow trench isolation structure, reducing the influence of the base resistance voltage drop, effectively suppressing the emitter current edge effect, and improving the current gain of the BJT device.
[0031] The bipolar junction transistor device of the present invention directly utilizes the existing Locos process in the BCD process without requiring additional process costs, has low technical difficulty in process implementation, and is highly feasible. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0033] Figure 1 It is a cross-sectional schematic diagram of a traditional BJT device;
[0034] Figure 2 Schematic cross-sectional view of a bipolar junction transistor (BJT) device in Example 1 of the present invention;
[0035] Figure 3 for Figure 2 Detailed view of section C;
[0036] Figure 4 is a cross-sectional schematic diagram of a bipolar junction transistor (BJT) device in Example 2 of the present invention;
[0037] Figure 5 for Figure 4 Detailed view of section D in the middle;
[0038] Figure 6 This is a gain comparison diagram between the BJT device of the present invention and the traditional BJT device. DETAILED DESCRIPTION
[0039] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0040] As mentioned in the background technology, traditional vertical NPN and PNP BJT devices have emitter current gathering effect. The existence of emitter current gathering effect makes the area of the emitter junction unable to be fully utilized, reduces the injection efficiency of the emitter, and makes the current gain of the BJT device smaller, resulting in a decrease in gain.
[0041] Traditional BJT devices have a SAB guard ring 300 (metal silicide barrier layer) at the edge of the emitter. The SAB guard ring prevents the formation of alkali metal silicide at the edge of the emitter junction, which increases the contact resistance at the edge of the emitter and can alleviate the current crowding effect to a certain extent. However, this method cannot significantly suppress the current crowding effect.
[0042] Based on this, the present invention provides a bipolar junction transistor (BJT) device, which reduces the influence of the base resistance voltage drop by setting the interval between the second heavily doped region and the first shallow trench isolation structure and setting the isolation layer in the space between the two, and effectively suppresses the emitter current edge effect. At the same time, since the second heavily doped region is far away from the first shallow trench isolation structure, the composite current generated at the edge of the first shallow trench isolation structure can be effectively reduced, the current of the second well region (base region) is also reduced, and the current gain of the BJT device is also improved.
[0043] like Figure 2 As shown, the bipolar junction transistor device in Embodiment 1 of the present invention includes a substrate 10, a first well region 11, a second well region 12, a third well region 13, a first heavily doped region 21, a second heavily doped region 22, a third heavily doped region 23, a first shallow trench isolation structure 31, a second shallow trench isolation structure 32 and an isolation layer 40 formed in the substrate 10.
[0044] The substrate 10 is a P-type substrate.
[0045] The first well region 11 is arranged in a ring shape, and is arranged in the substrate 10 and close to the top surface of the substrate 10. The first well region 11 is an N-type well region and is a collector region of a bipolar junction transistor device.
[0046] The second well region 12 is disposed in the substrate 10 and is located within the range surrounded by the first well region 11. The second well region 12 is also close to the top surface of the substrate 10. The second well region 12 is a P-type well region. The second well region 12 is the base region of the bipolar junction transistor device.
[0047] The third well region 13 is disposed in the substrate 10 and is located below the second well region 12. The third well region 13 is disposed in communication with the first well region 11. The third well region 13 is a deep N-type well region (DNW).
[0048] The first heavily doped region 21 is arranged in a ring shape and is located in the first well region 11. The first heavily doped region 21 is an N+ region, and the first well region 11 is led out to the top surface of the substrate 10 through the first heavily doped region 21.
[0049] The second heavily doped region 22 is disposed in the second well region 12. The second heavily doped region 22 is also an N+ region, and the second heavily doped region 22 is an emitter region of the bipolar junction transistor device.
[0050] The third heavily doped region 23 is arranged in a ring shape and is located in the second well region 12. The third heavily doped region 23 is arranged between the first heavily doped region 21 and the second heavily doped region 22, and a first spacing space A is formed between the third heavily doped region 23 and the second heavily doped region 22. The third heavily doped region 23 is a P+ region, and the second well region 12 is led out to the top surface of the substrate 10 through the third heavily doped region 23.
[0051] like Figure 3As shown, the first shallow trench isolation structure 31 (STI) is disposed in the second well region 12 and is located in the first spacing space A between the third heavily doped region 23 and the second heavily doped region 22, and a second spacing space B is formed between the first shallow trench isolation structure 31 and the second heavily doped region 22. Taking the 5x5 BJT device as an example, the width of the second spacing space B is 0.5μm-2μm, preferably, the width ranges from 0.5μm to 1.93μm. The width of the second spacing space B is the spacing between the first shallow trench isolation structure 31 and the second heavily doped region 22.
[0052] The isolation layer 40 is formed by a silicon local oxidation isolation process. The isolation layer 40 is disposed in the second spacing space B and partially extends into the second well region 12. One side of the isolation layer 40 is disposed in contact with the second heavily doped region 22, and the other side is disposed in contact with the first shallow trench isolation structure 31. Preferably, the side of the isolation layer 40 in contact with the second heavily doped region 22 partially covers the second heavily doped region 22.
[0053] In the BCD process platform, the isolation layer 40 may be formed by using the Locos process first, and then the second heavily doped region 22 may be formed in the second well region 12 .
[0054] The second shallow trench isolation structure 32 (STI) is disposed in the substrate 10 and is located between the adjacent first well region 11 and the second well region 12 , and is also located between the first heavily doped region 21 and the third heavily doped region 23 .
[0055] The isolation layer 40 , the first shallow trench isolation structure 31 , and the second shallow trench isolation structure 32 are all silicon oxide.
[0056] In the present embodiment 1, a fourth well region 14 is further provided in the substrate 10. The fourth well region 14 is a P-type well region, the fourth well region 14 is located outside the first well region 11, and a fourth heavily doped region 24 is provided in the fourth well region 14, and the fourth heavily doped region 24 is a P+ region.
[0057] like Figure 4 As shown, the bipolar junction transistor device in Embodiment 2 of the present invention includes a substrate 10, a first well region 101, a second well region 102, a first heavily doped region 201, a second heavily doped region 202, a third heavily doped region 203, a first shallow trench isolation structure 31, a second shallow trench isolation structure 32 and an isolation layer 40 formed in the substrate 10.
[0058] The substrate 10 is a P-type substrate.
[0059] The first well region 101 is arranged in a ring shape, and is arranged in the substrate 10 and close to the top surface of the substrate 10. The first well region 101 is a P-type well region and is a collector region of a bipolar junction transistor device.
[0060] The second well region 102 is disposed in the substrate 10 and is located within the range surrounded by the first well region 101. The second well region 102 is also close to the top surface of the substrate 10. The second well region 102 is an N-type well region. The second well region 102 is the base region of the bipolar junction transistor device.
[0061] The first heavily doped region 201 is arranged in a ring shape and is located in the first well region 101. The first heavily doped region 201 is a P+ region, and the first well region 101 is led out to the top surface of the substrate 10 through the first heavily doped region 201.
[0062] The second heavily doped region 202 is disposed in the second well region 102. The second heavily doped region 202 is also a P+ region, and the second heavily doped region 202 is an emitter region of a bipolar junction transistor device.
[0063] The third heavily doped region 203 is arranged in a ring shape and is located in the second well region 102. The third heavily doped region 203 is arranged between the first heavily doped region 201 and the second heavily doped region 202, and a first spacing space A is formed between the third heavily doped region 203 and the second heavily doped region 202. The third heavily doped region 203 is an N+ region, and the second well region 102 is led out to the top surface of the substrate 10 through the third heavily doped region 203.
[0064] like Figure 5 As shown, the first shallow trench isolation structure 31 (STI) is disposed in the second well region 102 and is located in the first spacing space A between the third heavily doped region 203 and the second heavily doped region 202, and a second spacing space B is formed between the first shallow trench isolation structure 31 and the second heavily doped region 202. Taking the 5x5 BJT device as an example, the width of the second spacing space B is 0.5μm-2μm, preferably, the width ranges from 0.5μm to 1.93μm. The width of the second spacing space B is the spacing between the first shallow trench isolation structure 31 and the second heavily doped region 22.
[0065] The isolation layer 40 is formed by a silicon local oxidation isolation process. The isolation layer 40 is disposed in the second spacing space B and partially extends into the second well region 102. One side of the isolation layer 40 is disposed in contact with the second heavily doped region 202, and the other side is disposed in contact with the first shallow trench isolation structure 31. Preferably, the side of the isolation layer 40 in contact with the second heavily doped region 202 partially covers the second heavily doped region 202.
[0066] In the BCD process platform, the isolation layer 40 may be formed by using the Locos process first, and then the second heavily doped region 202 may be formed in the second well region 102 .
[0067] The second shallow trench isolation structure 32 (STI) is disposed in the substrate 10 and is located between the adjacent first well region 101 and the second well region 102 , and is also located between the first heavily doped region 201 and the third heavily doped region 203 .
[0068] The isolation layer 40 , the first shallow trench isolation structure 31 , and the second shallow trench isolation structure 32 are all silicon oxide.
[0069] The present invention creatively proposes to introduce an isolation layer formed by the Locos process at the emitter edge of a bipolar junction transistor (BJT) device. The introduction of the isolation layer effectively suppresses the emitter current edge effect and improves the current gain of the BJT device. At the same time, due to the blocking effect of the isolation layer on the area below it, the emitter heavily doped region (second heavily doped region) of the formed BJT device is away from the first shallow trench isolation structure region, reducing the recombination current at the edge of the first shallow trench isolation structure close to the emitter heavily doped region, further improving the current gain of the BJT device.
[0070] refer to Figure 6 As shown, taking 5x5 PNP BJT device as an example, Figure 6 : is a gain comparison diagram of the BJT device of the present invention and the traditional BJT device, wherein the horizontal axis is voltage and the vertical axis is β gain. Figure 6 It can be seen that the current gain of the BJT device of the present invention is increased by 50% compared with the traditional BJT device.
[0071] Compared with the prior art, the bipolar junction transistor device of the present invention reduces the influence of the base resistance voltage drop by setting the interval between the second heavily doped region and the first shallow trench isolation structure and setting the isolation layer in the space between the two, and effectively suppresses the emitter current edge collection effect. At the same time, since the second heavily doped region is far away from the first shallow trench isolation structure, the composite current generated at the edge of the first shallow trench isolation structure can be effectively reduced, and the current of the second well region (base region) is also reduced, and the current gain of the BJT device is also improved.
[0072] The bipolar junction transistor device of the present invention first forms an isolation layer through the Locos process (silicon local oxidation isolation process) and then forms the second heavily doped region, so that the second heavily doped region is not formed in the area covered by the isolation layer, and the second heavily doped region is far away from the first shallow trench isolation structure, thereby reducing the recombination current at the edge of the first shallow trench isolation structure, reducing the influence of the base resistance voltage drop, effectively suppressing the emitter current edge effect, and improving the current gain of the BJT device.
[0073] The bipolar junction transistor device of the present invention directly utilizes the existing Locos process in the BCD process without requiring additional process costs, has low technical difficulty in process implementation, and is highly feasible.
[0074] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.
[0075] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.
Claims
1. A bipolar junction transistor device, characterized in that: include: A substrate, wherein a first well region and a second well region are disposed in the substrate; A first heavily doped region, disposed in the first well region; A second heavily doped region, disposed in the second well region; A third heavily doped region, disposed in the second well region and having a first separation space formed between the third heavily doped region and the second heavily doped region; A first shallow trench isolation structure is disposed in the second well region and is located in the first spacing space, and a second spacing space is formed between the first shallow trench isolation structure and the second heavily doped region; The isolation layer is arranged in the second spacing space and partially extends into the second well region. The isolation layer is at least arranged in contact with the second heavily doped region.
2. The bipolar junction transistor device according to claim 1, characterized in that: The isolation layer partially covers the second heavily doped region.
3. The bipolar junction transistor device according to claim 2, characterized in that: The width of the second space is in the range of 0.5 μm to 2 μm.
4. The bipolar junction transistor device according to claim 1, characterized in that: The isolation layer is disposed in contact with the first shallow trench isolation structure.
5. The bipolar junction transistor device according to claim 1, characterized in that: The isolation layer is formed by a silicon local oxidation isolation process.
6. The bipolar junction transistor device according to claim 1, characterized in that: The first well region is a collector region of a bipolar junction transistor device, and the first well region is led out to the top surface of the substrate through the first heavily doped region; The second well region is a base region of a bipolar junction transistor device, and the second well region is led out to the top surface of the substrate through the third heavily doped region; The second heavily doped region is an emitter region of a bipolar junction transistor device.
7. The bipolar junction transistor device according to claim 1, characterized in that: The first well region has a first doping type; The first heavily doped region has a first doping type; The second heavily doped region has a first doping type; The second well region has a second doping type opposite to the first doping type; The third heavily doped region has the second doping type.
8. The bipolar junction transistor device according to claim 1, characterized in that: It also includes a third well region, which is arranged in the substrate and below the second well region. The third well region is connected to the first well region, and the doping type of the third well region is the same as that of the first well region.
9. The bipolar junction transistor device according to claim 1, characterized in that: The first well region, the first heavily doped region, the third heavily doped region and the isolation layer are all arranged as a ring structure.
10. The bipolar junction transistor device according to claim 1, characterized in that: It also includes a second shallow trench isolation structure, which is arranged in the substrate and located between the adjacent first well region and the second well region.