Surface-mounted fuse with voltage transient suppression function and preparation method thereof
By integrating voltage transient suppressors and patch fuses on the same substrate, the problems of large area and high cost in traditional packaging are solved, and intensive packaging and efficient packaging processing are achieved.
Patent Information
- Application Number
- CN202411649812.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-18
- Publication Date
- 2025-02-25
AI Technical Summary
Traditional voltage transient suppressors and patch fuses need to be made and packaged separately, resulting in large packaging area, high cost and increased labor costs, and cannot meet the requirements of intensive packaging.
Integrate the voltage transient suppressor and the patch fuse on the same substrate, and form a series-connected voltage transient suppression by preparing fuse lines, fine slits, pure glue layers, pressed layers, blind holes and laminates on the substrate. and fuse.
It has achieved the realization of saving packaging area and time, reducing labor costs, meeting intensive packaging requirements, and improving packaging processing efficiency.
Smart Images
Figure CN119521792A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of fuse preparation, and in particular to a chip fuse with a voltage transient suppression function and a preparation method thereof. Background Art
[0002] A transient voltage suppressor (TVS) is a component used to protect electronic devices from voltage transients. In consumer electronics, computer systems, instrumentation, automotive electronics, industrial control, and communications industries, the signal lines of many electronic devices such as ICs, FETs, and sensors may be damaged by transient voltages caused by load switching or lighting.
[0003] Chip fuses can be connected in series with transient suppressors. Once an overcurrent event occurs, the chip fuse will disconnect and cut off the current. However, traditional transient suppressors and chip fuses are made and packaged separately, which requires redesigning and re-layouting the PCB board. Nowadays, product packaging is becoming more and more dense, and the space on the PCB board is very limited. Separately made and packaged suppressors and fuses will not only increase costs, but also occupy more PCB board area, increasing labor costs. Summary of the invention
[0004] The embodiment of the present invention provides a chip fuse with a voltage transient suppression function and a preparation method thereof, so as to solve the problem that a voltage transient suppressor and a chip fuse need to be manufactured separately in a traditional package and packaged separately on a PCB board, the packaging area cannot meet the increasingly developed dense packaging requirements, and the labor cost increases.
[0005] In order to achieve the above object, in one embodiment, a method for preparing a chip fuse with a voltage transient suppression function is provided, comprising: providing a substrate; A voltage transient suppressor and a fuse are prepared on the substrate so that the voltage transient suppressor and the fuse are connected in series.
[0006] In one embodiment, a voltage transient suppressor and a surface mount fuse are prepared on the substrate, including: Preparing a fusible link on the substrate to form a fuse; Cutting a slit on a metal pattern on the substrate, wherein the metal pattern is connected to one end of the fuse; forming a pure adhesive layer on the metal pattern, the fuse line and the polypropylene layer of the substrate, and forming a laminating layer on the pure adhesive layer; Drilling holes in the pure adhesive layer and the laminating layer corresponding to the slit to form blind holes, and filling the blind holes and the slit with a preset material; A preset laminate is formed on the laminate layer, a cavity is arranged in the laminate, and the cavity is arranged above the preset material to form a voltage transient suppressor.
[0007] In one embodiment, after the voltage transient suppressor is formed, the method further includes: Drilling holes on the substrate to form through holes between the fuses with voltage transient suppression function; Electroplating the substrate with the through hole formed thereon to form a copper-plated layer; Etching the copper-plated layer on both sides and welding pads to obtain a substrate with pads; A solder resist layer is formed on the upper surface of the substrate with the pad, and surface treatment is performed. The substrate after the surface treatment is cut to form a plurality of chip fuses with the voltage transient suppression function.
[0008] In one embodiment, preparing a fusible link on the substrate to form a fuse specifically includes: Etching a metal pattern on the substrate to obtain an etched substrate; Depositing copper on the etched substrate to form a thin copper layer, the thickness of which can be adjusted according to different product specifications; Etching fuse lines and pad patterns on the thin copper layer; Pattern exposure is performed on the fusible wire to form a window pattern, and electroplating is performed on the window pattern to form a tin-plated layer. The fusible wire and the tin-plated layer together constitute the fuse.
[0009] In one embodiment, the width of the fuse line can be adjusted according to different specifications of the product, the length of the cavity is greater than the diameter of the blind hole, the range of the length of the cavity being greater than the diameter of the blind hole is: 150-200um, the thickness of the cavity is greater than the depth is greater than 40um, and the aperture size of the blind hole and the depth of the cavity can be adjusted according to different specifications of the product.
[0010] In one embodiment, a chip fuse with a voltage transient suppression function is provided, comprising: a substrate, a voltage transient suppressor, and a fuse, wherein the voltage transient suppressor and the fuse are located on the substrate, and the voltage transient suppressor and the fuse are connected in series.
[0011] In one embodiment, the voltage transient suppressor and the chip fuse on the substrate include: a slit, a metal pattern, a pure glue layer, a lamination layer, a blind hole, a laminate, and a preset material, wherein the fuse is located on the substrate, the slit is located on the metal pattern of the substrate, the metal pattern is connected to one end of the fuse, the pure glue layer is located on the metal pattern, the fuse and the polypropylene layer of the substrate, the lamination layer is located on the pure glue layer, the blind hole is located on the pure glue and the lamination layer corresponding to the slit, the preset material is located in the slit and the blind hole, the laminate is located on the lamination layer, a cavity is provided in the laminate, and the cavity is located above the preset material, so as to form the voltage transient suppressor.
[0012] In one embodiment, after the voltage transient suppressor is formed, it also includes: a through hole, a copper plating layer, a pad, a solder resist layer, and a tin oxide layer, wherein the through hole is located between the fuses with the voltage transient suppression function on the substrate, the copper plating layer is located on the surface of the substrate with the through hole, the pad is located on the lower surface of the substrate, the solder resist layer is located on the upper surface of the substrate with the pad, and the tin oxide layer is located on the surface of the substrate with the solder resist layer, so as to form a plurality of chip fuses with the voltage transient suppression function.
[0013] In one embodiment, the fuse on the substrate specifically includes: a metal pattern, a thin copper layer, a fusible line, a pad pattern, and a tin-plated layer, wherein the metal pattern is located on the substrate, the thin copper layer is located on the substrate having the metal pattern, the thickness of the thin copper layer can be adjusted according to different product specifications, the fusible line is located on the thin copper layer, the pad pattern is located on the lower surface of the substrate, and the tin-plated layer is located on the fusible line to form the fuse.
[0014] In one embodiment, the width of the fusible link in the fuse can be adjusted according to different product specifications, the cavity length of the laminate in the voltage transient suppressor is greater than the diameter of the blind hole in the voltage transient suppressor, the length of the cavity is greater than the diameter of the blind hole in the range of: 150-200um, the thickness of the cavity is greater than the depth is greater than 40um, and the aperture size of the blind hole and the depth of the cavity can be adjusted according to different product specifications.
[0015] The above-mentioned chip fuse with voltage transient suppression function and its preparation method combine the voltage transient suppressor and the chip fuse into the same structure for manufacturing and packaging together, which saves the time of traditional two devices being manufactured separately, saves the packaging area, upgrades the packaging device, improves the packaging processing efficiency, and reduces labor costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.
[0017] Figure 1 is a schematic diagram of a chip fuse with voltage transient suppression function in an embodiment; Figure 2 is a schematic diagram of a substrate in one embodiment; Figure 3 is a schematic diagram of a voltage transient suppressor and a fuse in one embodiment; Figure 4 is a schematic diagram of cutting to form a slit in one embodiment; Figure 5 is a schematic diagram of a laminating layer and a pure adhesive layer being pressed together onto a substrate in one embodiment; Figure 6 is a schematic diagram of filling a preset material into a blind hole in one embodiment; Figure 7 is a schematic diagram of laminating a laminate onto a laminating layer in one embodiment; Figure 8 is a schematic diagram of an embodiment after electroplating; Fig. 9 is a schematic diagram of a substrate after double-sided etching in one embodiment; Fig.10 is a schematic diagram of a substrate after surface treatment in one embodiment; Fig.11 is a schematic diagram of double-sided etching of a substrate when manufacturing a fuse in one embodiment; Fig.12 In one embodiment, a thin copper layer Fig.13 It is a schematic diagram of forming a fuse by tinning a fusible wire in one embodiment.
[0018] Figure numerals: 2 is a substrate, 30 is a voltage transient suppressor, 40 is a fuse, 3 is a fine gap, 4 is a lamination layer, 5 is a pure adhesive layer for fixing the lamination layer, 6 is a preset material, 7 is a laminate, 8 is a copper plating layer, 9 is a solder mask layer, 10 is a tinning layer, 11 is a pad pattern, 12 is a fuse, and 13 is a tin plating layer. DETAILED DESCRIPTION
[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0020] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.
[0021] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.
[0022] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.
[0023] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0024] In order to fully understand the present invention, detailed structures and steps will be presented in the following description to illustrate the technical solutions proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.
[0025] In one embodiment, a method for preparing a chip fuse with a voltage transient suppression function is provided, comprising: S101, providing a substrate; Wherein, the substrate 2 provided is as follows Figure 1 As shown, the substrate is composed of a copper layer 21 and a polypropylene layer 22. The copper layer 21 is a conductive layer in the substrate, which is usually responsible for the transmission of current. It has high thermal conductivity and good electrical conductivity, can effectively transmit current and help dissipate heat to maintain a stable operating temperature of electronic components. The polypropylene layer 22, also known as the PP layer, mainly plays the role of insulation and support.
[0026] S102, preparing a voltage transient suppressor and a fuse on the substrate so that the voltage transient suppressor and the fuse are connected in series.
[0027] Among them, Figure 3 As shown, the voltage transient suppressor 30 and the fuse 40 are connected in series and are both located on the substrate; The preparation method of this embodiment connects the voltage transient suppressor and the fuse in series and manufactures them on a substrate at the same time. Compared with the traditional method of manufacturing two devices separately, it saves time cost. The voltage transient suppressor and the fuse are integrated in the same package, which can save packaging area, meet the requirements of increasingly dense packaging area on PCB boards, and save labor costs.
[0028] In one embodiment, in the above step S102, that is, preparing a voltage transient suppressor and a chip fuse on the substrate, includes: S201, preparing a fusible link on the substrate to form a fuse; S202, cutting a slit on a metal pattern on the substrate, wherein the metal pattern is connected to one end of the fuse; Wherein, a fine slit 3 is cut on the metal pattern, such as Figure 4 As shown, after the cutting is completed, a preset material is filled in the slit 3, and the preset material is a polymer material.
[0029] S203, forming a pure adhesive layer on the metal pattern, the fuse line and the polypropylene layer of the substrate, and forming a laminating layer on the pure adhesive layer; The laminating layer 4 is a prepreg, and the laminating layer 4 and the pure adhesive layer 5 are pressed together onto the substrate. Figure 5 shown.
[0030] S204, drilling holes in the pure adhesive layer and the lamination layer corresponding to the slit to form blind holes, and filling the blind holes with a preset material; In which, laser drilling is performed on the lamination layer 4 and the pure adhesive layer 5 above the slit 3, such as Figure 6 As shown, a blind hole is formed, the preset materials are drilling polymer material and screen printing polymer slurry, and the preset material 6 is filled in the blind hole, and the filled preset material 6 is cured.
[0031] S205, forming a preset laminate on the laminated layer, wherein the laminate is provided with a cavity, and the cavity is provided above the preset material, to form a voltage transient suppressor.
[0032] The preset laminated board 7 is a phenolic resin board, such as Figure 7 As shown, the release film on the pure adhesive is peeled off, and the pure adhesive and the phenolic resin board are laminated onto the laminating layer.
[0033] In one embodiment, the above step S205, i.e. after forming the voltage transient suppressor, further includes: S301, drilling holes on the substrate to form through holes located between the fuses with voltage transient suppression function; S302, electroplating the substrate with the through hole formed thereon to form a copper-plated layer; The purpose of drilling through holes is to interconnect both sides of the substrate during electroplating, such as Figure 8 As shown, the electroplating operation is PTH electroplating (chemical copper plating), and the copper plated layer 8 enables double-sided interconnection of the substrate with through holes.
[0034] S303, performing double-sided etching on the copper plating layer, and welding pads to obtain a substrate with pads; Among them, when double-sided etching, Fig. 9 As shown, the upper surface of the copper-plated substrate is completely etched, and the pad pattern 11 is etched on the lower surface, and then the pad is soldered on the pad pattern 11.
[0035] S304, forming a solder resist layer on the upper surface of the substrate with the pad, performing surface treatment, and cutting the substrate after the surface treatment to form a plurality of chip fuses with the voltage transient suppression function.
[0036] Among them, after adding the solder mask layer 9 on the top surface of the substrate, the surface treatment is performed, such as Fig.10 As shown, during the surface treatment, the pad is tinned on the bot surface of the substrate to form a tinning layer 10, and finally cut to obtain a plurality of chip fuses with voltage transient suppression function.
[0037] In one embodiment, in the above step S201, preparing a fusible link on the substrate to form a fuse specifically includes: S401, etching a metal pattern on the substrate to obtain an etched substrate; Among them, Fig.11 As shown, during etching, the substrate is etched on both sides, a metal pattern is etched on the upper surface of the substrate, and a pad pattern 11 is etched on the lower surface of the substrate.
[0038] S402, depositing copper on the etched substrate to form a thin copper layer, wherein the thickness of the thin copper layer can be adjusted according to different product specifications; S403, etching a fuse line and a pad pattern on the thin copper layer; Among them, Fig.12 As shown, double-sided etching is performed on the thin copper layer, a pad pattern 11 is etched on the lower surface of the substrate on which the thin copper layer is formed, and a fuse 12 is etched on the thin copper layer.
[0039] S404, performing pattern exposure on the fusible wire to form a window pattern, performing electroplating on the window pattern to form a tin-plated layer, and the fusible wire and the tin-plated layer together constitute the fuse.
[0040] Among them, Fig.13 As shown, the tin-plated layer 13 formed by electroplating after forming a window pattern on the fuse and the fuse 12 together constitute a fuse.
[0041] In one embodiment, the width of the fuse line can be adjusted according to different product specifications, the length of the cavity of the laminate is greater than the diameter of the blind hole, the length of the cavity is greater than the diameter of the blind hole in the range of: 150-200um, the thickness of the cavity is greater than the depth is greater than 40um, and the aperture size of the blind hole and the depth of the cavity can be adjusted according to different product specifications.
[0042] Among them, since the chip fuse with voltage transient suppression function can be used in electronic devices of different specifications, the adjustable fuse line width and tin plating layer form a fuse, so that the width of the fuse is also adjusted to form fuses of different widths. The cavity thickness and blind hole size of the laminate can also be adjusted according to different specifications of the product, which can better meet the needs of the market.
[0043] In one embodiment, a chip fuse with a voltage transient suppression function is provided, comprising: a substrate, a voltage transient suppressor, and a fuse, wherein the voltage transient suppressor and the fuse are located on the substrate, and the voltage transient suppressor and the fuse are connected in series.
[0044] Among them, the voltage transient suppressor and the fuse are both located on the substrate, and the voltage transient suppressor and the fuse are connected in series, which can quickly respond to and absorb the transient voltage in the circuit, protect the circuit from damage by transient high voltage, and the fuse melts when the current exceeds the rated value, cuts off the circuit, and prevents the overcurrent from causing further damage to the circuit. In addition, the voltage fluctuation in the circuit can be effectively controlled to avoid the influence of voltage transient on the circuit performance.
[0045] In one embodiment, the voltage transient suppressor and the chip fuse on the substrate include: a slit, a metal pattern, a pure glue layer, a lamination layer, a blind hole, a laminate, and a preset material, wherein the fuse is located on the substrate, the slit is located on the metal pattern of the substrate, the metal pattern is connected to one end of the fuse, the pure glue layer is located on the metal pattern, the fuse and the polypropylene layer of the substrate, the lamination layer is located on the pure glue layer, the blind hole is located on the pure glue and the lamination layer corresponding to the slit, the preset material is located in the slit and the blind hole, the laminate is located on the lamination layer, a cavity is provided in the laminate, and the cavity is located above the preset material, so as to form the voltage transient suppressor.
[0046] Among them, voltage transient suppressors can effectively protect precision devices in electronic circuits from damage by various surge pulses, helping to maintain stable operation of the circuit.
[0047] In one embodiment, after the voltage transient suppressor is formed, it also includes: a through hole, a copper plating layer, a pad, a solder resist layer, and a tin oxide layer, wherein the through hole is located between the fuses with the voltage transient suppression function on the substrate, the copper plating layer is located on the surface of the substrate with the through hole, the pad is located on the lower surface of the substrate, the solder resist layer is located on the upper surface of the substrate with the pad, and the tin oxide layer is located on the surface of the substrate with the solder resist layer, so as to form a plurality of chip fuses with the voltage transient suppression function.
[0048] Among them, the pad is a basic unit, which is a part of the conductive pattern used for electrical connection, device fixation or both. The surface of the device is interconnected through the through hole, and a solder mask is formed on the surface of the device, which can protect the device from oxidation caused by air, extend the life of the circuit board, prevent solder from bridging between areas that should not be connected, avoid short circuits, and provide electrical insulation to prevent interference between adjacent circuits. After the tin layer is formed, the device is cut to obtain multiple chip fuses with voltage transient suppression function.
[0049] In one embodiment, the fuse on the substrate specifically includes: a metal pattern, a thin copper layer, a fusible line, a pad pattern, and a tin-plated layer, wherein the metal pattern is located on the substrate, the thin copper layer is located on the substrate having the metal pattern, the thickness of the thin copper layer can be adjusted according to different product specifications, the fusible line is located on the thin copper layer, the pad pattern is located on the lower surface of the substrate, and the tin-plated layer is located on the fusible line to form the fuse.
[0050] Among them, the fuse is an important electronic component used to protect the circuit from damage due to overload and short circuit. When the current exceeds the rated value, it will melt to cut off the current and prevent damage to other components.
[0051] In one embodiment, the width of the fusible link in the fuse can be adjusted according to different product specifications, the length of the cavity of the laminate in the voltage transient suppressor is greater than the diameter of the blind hole in the voltage transient suppressor, the length of the cavity is greater than the diameter of the blind hole in the range of: 150-200um, the thickness of the cavity is greater than the depth is greater than 40um, and the aperture size of the blind hole and the depth of the cavity can be adjusted according to different product specifications.
[0052] Among them, the chip fuse with voltage transient suppression function can adjust the size of the internal fuse and the blind hole and laminate cavity in the voltage transient suppressor according to different product requirements, so that the prepared chip fuse with voltage transient suppression function can better meet the needs of users and the market.
[0053] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.
Claims
1. A method for preparing a chip fuse with voltage transient suppression function, characterized in that: include: providing a substrate; A voltage transient suppressor and a fuse are prepared on the substrate so that the voltage transient suppressor and the fuse are connected in series.
2. The preparation method according to claim 1, characterized in that: A voltage transient suppressor and a chip fuse are prepared on the substrate, comprising: Preparing a fusible link on the substrate to form a fuse; Cutting a slit on a metal pattern on the substrate, wherein the metal pattern is connected to one end of the fuse; forming a pure adhesive layer on the metal pattern, the fuse line and the polypropylene layer of the substrate, and forming a laminating layer on the pure adhesive layer; Drilling holes in the pure adhesive layer and the laminating layer corresponding to the slit to form blind holes, and filling the blind holes and the slit with a preset material; A preset laminate is formed on the laminate layer, a cavity is arranged in the laminate, and the cavity is arranged above the preset material to form a voltage transient suppressor.
3. The preparation method according to claim 2, characterized in that: After forming the voltage transient suppressor, it also includes: Drilling holes on the substrate to form through holes between the fuses with voltage transient suppression function; Electroplating the substrate with the through hole formed thereon to form a copper-plated layer; Etching the copper-plated layer on both sides and welding pads to obtain a substrate with pads; A solder resist layer is formed on the upper surface of the substrate with the pad, and surface treatment is performed. The substrate after the surface treatment is cut to form a plurality of chip fuses with the voltage transient suppression function.
4. The preparation method according to claim 2, characterized in that: Preparing a fusible link on the substrate to form a fuse specifically includes: Etching a metal pattern on the substrate to obtain an etched substrate; Depositing copper on the etched substrate to form a thin copper layer, the thickness of which can be adjusted according to different product specifications; Etching fuse lines and pad patterns on the thin copper layer; Pattern exposure is performed on the fusible wire to form a window pattern, and electroplating is performed on the window pattern to form a tin-plated layer. The fusible wire and the tin-plated layer together constitute the fuse.
5. The preparation method according to claim 2, characterized in that: The width of the fuse line can be adjusted according to different product specifications. The length of the cavity is greater than the diameter of the blind hole. The range in which the length of the cavity is greater than the diameter of the blind hole is: 150-200um. The thickness of the cavity is greater than the depth by more than 40um. The aperture size of the blind hole and the depth of the cavity can be adjusted according to different product specifications.
6. A chip fuse with voltage transient suppression function, characterized in that: include: A substrate, a voltage transient suppressor, and a fuse, wherein the voltage transient suppressor and the fuse are located on the substrate, and the voltage transient suppressor and the fuse are connected in series.
7. The chip fuse according to claim 6, characterized in that: The voltage transient suppressor and the chip fuse on the substrate include: a slit, a metal pattern, a pure glue layer, a lamination layer, a blind hole, a laminate, and a preset material, wherein the fuse is located on the substrate, the slit is located on the metal pattern of the substrate, the metal pattern is connected to one end of the fuse, the pure glue layer is located on the metal pattern, the fuse and the polypropylene layer of the substrate, the lamination layer is located on the pure glue layer, the blind hole is located on the pure glue corresponding to the slit and the lamination layer, the preset material is located in the slit and the blind hole, the laminate is located on the lamination layer, a cavity is provided in the laminate, and the cavity is located above the preset material, so as to form the voltage transient suppressor.
8. The chip fuse according to claim 7, characterized in that: After the voltage transient suppressor is formed, it also includes: a through hole, a copper plating layer, a pad, a solder resist layer, and a tin-plated layer, wherein the through hole is located between the fuses with the voltage transient suppression function on the substrate, the copper plating layer is located on the surface of the substrate with the through hole, the pad is located on the lower surface of the substrate, the solder resist layer is located on the upper surface of the substrate with the pad, and the tin-plated layer is located on the surface of the substrate with the solder resist layer, so as to form a plurality of chip fuses with the voltage transient suppression function.
9. The chip fuse according to claim 6, characterized in that: The fuse on the substrate specifically includes: a metal pattern, a thin copper layer, a fuse line, a pad pattern, and a tin-plated layer, wherein the metal pattern is located on the substrate, the thin copper layer is located on the substrate with the metal pattern, the thickness of the thin copper layer can be adjusted according to different product specifications, the fuse line is located on the thin copper layer, the pad pattern is located on the lower surface of the substrate, and the tin-plated layer is located on the fuse line to form the fuse.
10. The chip fuse according to claim 6, characterized in that: The width of the fusible link in the fuse can be adjusted according to different product specifications. The length of the cavity of the laminate in the voltage transient suppressor is greater than the diameter of the blind hole in the voltage transient suppressor. The length of the cavity is greater than the diameter of the blind hole in the range of: 150-200um. The thickness of the cavity is greater than the depth by more than 40um. The aperture size of the blind hole and the depth of the cavity can be adjusted according to different product specifications.