Cadmium zinc telluride wafer surface shape control method

Abstract

The invention discloses a method for controlling the surface shape of a cadmium zinc telluride wafer. The method comprises the following steps: firstly, determining the universal change condition of the thickness and the surface shape of a damaged layer of the cadmium zinc telluride wafer along with a grinding and polishing process under an actual process condition; in combination with an analysis result, before each time of surface treatment of the tellurium-zinc-cadmium wafer, removing damaged layers on the two surfaces of the tellurium-zinc-cadmium wafer through a chemical corrosion method; and meanwhile, the surface shape of the wafer is measured before chemical polishing, and chemical polishing is carried out by adopting different process parameters according to the surface shape condition. A chemical corrosion solution in the process of removing the stress of the damaged layer through chemical corrosion is a corrosion solution with a specific concentration, and the chemical corrosion time is determined by the required removal thickness. A chemical polishing solution in the chemical polishing process is an etchant solution with a specific concentration, the chemical polishing time is determined by a surface shape value of a wafer measured before chemical polishing, and a chemical polishing carrier is a specially designed carrier. The method is simple in process, good in repeatability and controllable in process, can be used for surface shape control of the cadmium zinc telluride substrate, and has batch capacity.

Description

Technical Field

[0001] The invention belongs to the technical field of photoelectric detection, and in particular relates to a method for controlling the surface shape of a cadmium zinc telluride wafer. Background Art

[0002] Mercury cadmium telluride (HgCdTe) focal plane infrared detector is currently the most widely used and most mature infrared detector. It can detect the entire infrared band by adjusting the Cd component. The lattice constant of cadmium zinc telluride (CdZnTe) crystal can change with different zinc content, and can achieve a high lattice match with mercury cadmium telluride thin films of different detection cutoff wavelengths. CdZnTe has also become the most important epitaxial substrate material for the preparation of high-performance mercury cadmium telluride infrared detectors.

[0003] In order to achieve the superior performance of HgCdTe infrared detectors, obtaining CdZnTe wafers with high flatness and low surface damage is the basis and prerequisite. The preparation of CdZnTe wafers usually requires multiple processes such as crystal growth, cutting, grinding, polishing, cleaning, and chemical polishing. During the processing of CdZnTe wafers, surface layer damage is inevitable, causing processing stress and residual stress, which leads to deformation of CdZnTe wafers; at the same time, improper chemical polishing process will also cause surface collapse deformation, seriously affecting the subsequent processing of HgCdTe detectors.

[0004] In traditional chip processing technology, double-sided grinding and polishing is usually used to avoid chip deformation caused by residual stress. However, double-sided grinding and polishing has strict requirements on chip size and shape, and is not suitable for most mainstream CdZnTe chip processing technology. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a method for controlling the surface shape of a cadmium zinc telluride wafer in view of the above-mentioned deficiencies in the prior art. The method is achieved by controlling the PV value (Peak to Valley). The process is simple, repeatable and controllable, and the method is more suitable for industrial production. Even if there are differences between different processes, the method is still applicable. Therefore, the present invention is suitable for most mainstream cadmium zinc telluride wafer preparation processes.

[0006] The technical solution adopted by the present invention to solve the above technical problems is:

[0007] A method for controlling the surface shape of a cadmium zinc telluride wafer, the method comprising:

[0008] (1) Determine the universal changes in the thickness and surface shape of the damaged layer of CdZnTe wafers during the grinding and polishing process under actual process conditions;

[0009] (2) Before grinding or polishing the CdZnTe substrate each time, the stress of the damaged layer on both sides of the CdZnTe substrate is removed by chemical etching;

[0010] (3) Before chemical polishing, the PV value of the wafer is measured. According to the substrate PV value of the wafer, a suitable type of chemical polishing solution, chemical polishing solution concentration and chemical polishing time are selected and a chemical polishing carrier is used for chemical polishing.

[0011] According to the above scheme, the solutes of the chemical etching solution and the chemical polishing solution are selected from one or more of bromine, hydrobromic acid, hydrogen peroxide, potassium dichromate and nitric acid, and the concentrations are all 0.1% to 10.0%; the solvent includes a base solvent and a corresponding solute, and the base solvent is selected from one or more of water, methanol, ethanol and ethylene glycol.

[0012] According to the above scheme, the thickness of the damaged layer of the CdZnTe wafer and the required etching time are determined according to the following method:

[0013] (1) Prepare a CdZnTe substrate (its thickness must be consistent with that of a normal process substrate);

[0014] (2) The residual stress surface of the damaged layer of the CdZnTe substrate is marked as surface I, and the other surface is marked as surface II;

[0015] (3) After grinding and polishing the surface II, measure the PV value of the surface I of the substrate;

[0016] (4) Prepare a chemical etching solution of a specific concentration, place the substrate to be corroded into the chemical etching solution for etching, and take out the solution after each fixed etching time to measure the PV value of surface II and the thickness of the substrate until the PV value of surface II no longer changes. The difference between the substrate thickness at this time and the substrate thickness before etching is the thickness of the damaged layer; the time used at this time is the etching time.

[0017] According to the above scheme, the chemical polishing time is determined according to the following method:

[0018] (1) Measure the PV value of the CdZnTe substrate before chemical polishing, recorded as PV B ;Record the target PV value as PV G ;

[0019] (2) The time of basic chemical polishing is the shortest chemical polishing time that meets the epitaxial substrate index, denoted as t, where the epitaxial substrate index includes scratches and roughness;

[0020] (3) When PV B ≤PV G , the time of chemical polishing is t; when PV B >PV G The time of chemical polishing is t+a(PV B -PV G), where a is an empirical constant related to the chemical polishing solution and its concentration, which needs to be confirmed by experiments based on actual process conditions after the other chemical polishing process parameters are selected.

[0021] According to the above scheme, the chemical polishing carrier must follow the following design principles:

[0022] (1) The bottom surface of the chemical polishing carrier includes a wafer groove located at the center of the carrier and a guide groove located around the wafer;

[0023] (2) The flatness of the wafer groove surface should be less than 5μm;

[0024] (3) The wafer slot area is recorded as A1, the guide slot area is recorded as A2, and the remaining non-slot area is recorded as A3, which should satisfy A2÷(A1+A3)>30%;

[0025] (4) The width of the guide groove should be widened or narrowed in proportion to the increase or decrease of the chip groove area.

[0026] According to the above solution, the material of the chemical polishing carrier can resist the corrosion of the chemical polishing liquid; optional materials include polypropylene, polytetrafluoroethylene and polyvinylidene fluoride.

[0027] Compared with the prior art, the advantages of the present invention are:

[0028] (1) The present invention can be improved based on existing practical processes;

[0029] (2) The present invention prepares a high-planarity cadmium zinc telluride wafer material, which has a simple process, good repeatability, and controllable process, and is more suitable for industrial production;

[0030] (3) Even if there are differences between different processes, they are still applicable, so the present invention is suitable for most mainstream CdZnTe wafer preparation processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Schematic diagram of the cadmium zinc telluride wafer processing process.

[0032] Figure 2 A model of a specially designed chemical polishing carrier (left) and a schematic diagram of the bottom surface groove (right).

[0033] Figure 3 PV values ​​of Example, Comparative Example 1, Comparative Example 2 and Comparative Example 3 before chemical polishing.

[0034] Figure 4 PV values ​​after chemical polishing of Example, Comparative Example 1, Comparative Example 2 and Comparative Example 3. DETAILED DESCRIPTION

[0035] The present invention will be further described in detail below with reference to embodiments, but the present invention is not limited to the following embodiments.

[0036] Before starting this embodiment, it is necessary to determine the universal variation of the thickness of the damaged layer of the CdZnTe substrate under actual process conditions, and determine the components of the chemical etching solution or chemical polishing solution and the required processing time required for each grinding and polishing process.

[0037] The thickness of the damaged layer is determined according to the following method:

[0038] (1) Prepare a CdZnTe substrate (its thickness must be consistent with that of a normal process substrate);

[0039] (2) The residual stress surface of the damaged layer of the CdZnTe substrate is marked as surface I, and the other surface is marked as surface II;

[0040] (3) After grinding and polishing the surface II, measure the PV value of the surface I of the substrate;

[0041] (4) Prepare a chemical etching solution of a specific concentration, place the substrate to be corroded in the chemical etching solution for etching, and take out the solution after each fixed etching time to measure the PV value of surface II and the thickness of the substrate until the PV value of surface II no longer changes. The difference between the substrate thickness at this time and the substrate thickness before etching is the thickness of the damaged layer; the thickness of the damaged layer divided by the etching time is the corrosion rate.

[0042] like Figure 1 As shown, a method for controlling the surface shape of a cadmium zinc telluride wafer comprises the following steps:

[0043] 1) chemically etching a cadmium zinc telluride wafer cut from a cadmium zinc telluride single crystal, wherein the chemical etching solution is 1.5% bromine methanol, and the etching time is 6 minutes;

[0044] 2) Fix the etched CdZnTe wafer on the silicon wafer with paraffin wax, and grind and polish the A side (the front and back sides of the CdZnTe wafer are represented by B side and A side respectively). After grinding and polishing, remove the paraffin wax, and chemically etch the CdZnTe wafer again, the chemical etching solution is 0.8% bromomethanol, and the etching time is 6 minutes;

[0045] 3) Fix the etched CdZnTe wafer on the silicon wafer with paraffin wax, and grind and polish the B surface. After the treatment, cut it into wafers of the required size and clean it;

[0046] 4) Measure the PV value of the B side of the cleaned wafer first, then place the wafer into a special chemical polishing carrier (such as Figure 2 The chemical polishing liquid is 0.3% bromomethanol, and the chemical polishing time is determined according to the following method: the PV value of the cadmium zinc telluride wafer before chemical polishing is recorded as PV B , and record the target PV value as PV G, the basic chemical polishing time (the shortest time to meet the epitaxial index) is recorded as t, when PV B <PV G , chemical polishing time is t; when PV B >PV G , chemical polishing time is t+a(PV B -PV G ), a is a constant related to the concentration of the chemical polishing solution, which is confirmed by actual process conditions. In this embodiment, t is 2 and a is 1.45.

[0047] The cadmium zinc telluride wafer material prepared by the process of steps 1) to 4) above is taken as an example, and the cadmium zinc telluride wafer material without some processes is taken as comparative example 1, comparative example 2, and comparative example 3, and compared respectively, as shown in Table 1:

[0048] Table 1 Process details of Example 1, Comparison 1, 2, 3

[0049]

[0050]

[0051] like Figure 3 As shown, combined with Table 1, it can be seen that the cadmium zinc telluride wafer (Comparative Example 1) that has not undergone the chemical etching process has a significantly larger PV value of 5.6μm and poor flatness due to the deformation caused by residual stress; in contrast, after the chemical etching process, the PV values ​​of Example 1, Comparative Example 2, and Comparative Example 3 are all less than 3.0μm.

[0052] According to step 4) of the present invention, the PV value before chemical polishing is smaller than PV B =2.849μm, set the target value PV G =2.5μm, then according to t+a(PV B -PV G )The calculated chemical polishing time is 2.5 min.

[0053] like Figure 4As shown, the PV value of the embodiment after chemical polishing is close to the target value, and the PV value of the center part is consistent, and the overall flatness is good; while in Comparative Examples 1 and 2, even though the PV values ​​of the center part are mostly consistent, due to the lack of the use of a special chemical polishing carrier and the failure to control the chemical polishing time, the chemical corrosion effect on the edge of the wafer is strong, and an obvious edge collapse phenomenon occurs. Compared with before chemical polishing, the PV value increases significantly, and the overall flatness is poor; although Comparative Example 3 uses a special chemical polishing carrier to suppress the edge collapse phenomenon, the chemical polishing time is not controlled, and a slight edge collapse phenomenon occurs, the PV value increases slightly, and the overall flatness is poor. In summary, the method for preparing a high-flatness cadmium zinc telluride wafer material provided by the present invention is feasible.

[0054] The above examples are only some examples of the present invention and are not intended to limit the present invention. The protection scope of the present invention shall be the technical solutions recorded in the claims, including equivalent alternatives to the technical features in the technical solutions recorded in the claims. That is, equivalent replacement and improvement within this scope are also within the protection scope of the present invention.

Claims

1. A method for controlling the surface shape of a cadmium zinc telluride wafer, characterized in that: The following steps are involved: (1) Determine the universal changes in the thickness and surface shape of the damaged layer of CdZnTe wafers during the grinding and polishing process under actual process conditions; (2) Before grinding or polishing the CdZnTe substrate each time, the stress of the damaged layer on both sides of the CdZnTe substrate is removed by chemical etching; (3) Before chemical polishing, the PV value of the wafer is measured. According to the substrate PV value of the wafer, a suitable type of chemical polishing solution, chemical polishing solution concentration and chemical polishing time are selected and a chemical polishing carrier is used for chemical polishing.

2. The method for controlling the surface shape of a CdZnTe wafer according to claim 1, characterized in that: The parameters that need to be determined according to universal changes in the chemical etching process for removing stress from the damaged layer of the cadmium zinc telluride substrate include the thickness of the damaged layer, the type and concentration of the chemical etching solution, and the etching time; the parameters that need to be determined according to universal changes in the chemical polishing process include the type and concentration of the chemical polishing solution, and the chemical polishing time.

3. A CdZnTe wafer surface shape control method according to claim 2, characterized in that: The solutes of the chemical etching solution and the chemical polishing solution are selected from one or more of bromine, hydrobromic acid, hydrogen peroxide, potassium dichromate and nitric acid, and the concentrations are all 0.1% to 10.0%; the solvent includes a base solvent and a corresponding solute, and the base solvent is selected from one or more of water, methanol, ethanol and ethylene glycol.

4. A method for controlling the surface shape of a CdZnTe wafer according to claim 2, characterized in that: The thickness of the damaged layer of the CdZnTe wafer and the required etching time are determined according to the following method: (1) preparing a cadmium zinc telluride substrate, wherein the thickness of the substrate is consistent with the thickness of a normal process substrate; (2) The residual stress surface of the damaged layer of the CdZnTe substrate is marked as surface I, and the other surface is marked as surface II; (3) After grinding and polishing the surface II, measure the PV value of the surface I of the substrate; (4) Prepare a chemical etching solution of a specific concentration, place the substrate to be corroded into the chemical etching solution for etching, and take out the solution after each fixed etching time to measure the PV value of surface II and the thickness of the substrate until the PV value of surface II no longer changes. The difference between the substrate thickness at this time and the substrate thickness before etching is the thickness of the damaged layer; the time used at this time is the etching time.

5. The method for controlling the surface shape of a CdZnTe wafer according to claim 2, characterized in that: The time of the chemical polishing is determined according to the following method: (1) Measure the PV value of the CdZnTe substrate before chemical polishing, recorded as PV B ;Record the target PV value as PV G ; (2) The time of basic chemical polishing is the shortest chemical polishing time that meets the epitaxial substrate index, denoted as t, where the epitaxial substrate index includes scratches and roughness; (3) When PV B ≤PV G , the time of chemical polishing is t; when PV B >PV G The time of chemical polishing is t+a(PV B -PV G ), where a is an empirical constant related to the chemical polishing solution and its concentration, which needs to be confirmed by experiments based on actual process conditions after the other chemical polishing process parameters are selected.

6. A method for controlling the surface shape of a CdZnTe wafer according to any one of claims 1 to 5, characterized in that: The bottom surface of the chemical polishing carrier includes a wafer groove located at the center and guide grooves located around the wafer. The surface flatness of the wafer groove should be less than 5μm; the wafer groove area is recorded as A1, the guide groove area is recorded as A2, and the remaining non-groove area is recorded as A3, which should satisfy A2÷(A1+A3)>30%; the width of the guide groove should be widened or narrowed in proportion to the increase or decrease of the wafer groove area.

7. A method for controlling the surface shape of a CdZnTe wafer according to claim 6, characterized in that: The material of the chemical polishing carrier can resist corrosion from the chemical polishing liquid.

8. A method for controlling the surface shape of a CdZnTe wafer according to claim 7, characterized in that: The material of the chemical polishing carrier is selected from polypropylene, polytetrafluoroethylene and polyvinylidene fluoride which are resistant to corrosion by the chemical polishing liquid.

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