Program burning method and structure

Abstract

The invention provides a program burning method and structure. The method comprises the steps that a QSPI interface, an ISP interface and a configuration chip of a CPU / FPGA / DSP are connected in series through a QSPI interface signal; when the ISP signal cable is not used, the ISP interface is suspended, a signal in the QSPI interface is connected with the configuration chip, the power supply in the QSPI interface supplies power to the configuration chip through the conducted field effect transistor, the configuration chip is in a normal working state, and the functions of the CPU / FPGA / DSP and the configuration chip are completed; when the ISP signal cable is used, the programmer / programmer provides a QSPI signal and power supply for the configuration chip through the ISP signal cable, and program burning of the configuration chip can be completed by using the programmer / programmer without powering up a product. According to the invention, program burning can be conveniently completed without dismounting the configuration chip when the configuration information of the configuration chip is updated.

Description

Technical Field

[0001] The invention relates to the field of program burning, and in particular to a program burning method and structure. Background Art

[0002] Current electronic products usually need to run operating systems and applications. The hardware is usually designed with a configuration chip with a QSPI (QuadSerial Peripheral Interface, 6-wire SPI) or SPI interface (Serial Peripheral Interface, serial peripheral device interface), which stores the system's BIOS, bootloader, and firmware program information, and is used to boot the operating system or directly run the application when the product is powered on. In particular, computers / field programmable logic / digital signal processing systems based on CPU (Central Processing Unit, central processing unit), FPGA (Field Programmable Gate Array, field programmable logic gate array), and DSP (Digital Signal Process) will be installed with configuration chips to implement functions such as hardware initialization, loading boot programs, running firmware programs, or field programming of FPGAs when the system is powered on.

[0003] During the product development phase, the information stored in the configuration chip needs to be repeatedly adjusted and optimized, so the configuration chip needs to be frequently programmed. The industry's usual practice is to solder the configuration chip socket on the product's printed circuit board, and then install the configuration chip on the socket. When the configuration information needs to be updated, use tweezers or other tools to remove the configuration chip, then use a burner / programmer to program it, and finally install it back into the socket.

[0004] In the mass production stage of the product, in order to improve reliability, the configuration chip is directly soldered on the product's printed circuit board. When the product is maintained and upgraded, if the configuration information needs to be updated, the configuration chip must first be removed from the product's printed circuit board using a disassembly tool such as a soldering station, then the program is burned using a burner / programmer, and finally soldered back to the product's printed circuit board. This method of updating configuration information is usually inconvenient to operate at the product's site of use and can only be returned to the factory for processing, which reduces the efficiency of product maintenance and upgrades.

[0005] Some products still install the configuration chip on the printed circuit board socket during the mass production stage. In this case, the configuration chip and the socket pins will have poor contact due to oxidation. In addition, if the environment has strong vibration and impact, the configuration chip is very likely to loosen or even fall off, causing product malfunction.

[0006] As the industry uses a large number of configuration chips in BGA packages (Ball Grid Array), there is no suitable socket at present. Therefore, when using BGA packaged configuration chips, whether in the product development stage or mass production stage, the chips are directly soldered on the printed circuit board. When updating the configuration information, the BGA chip needs to be disassembled and soldered, which involves process requirements such as chip baking and soldering temperature curve control. The actual operation is cumbersome and time-consuming. Summary of the invention

[0007] The present invention aims to provide a program burning method and structure, so as to realize direct welding of a configuration chip on a printed circuit board, and to complete program burning using a burner / programmer without disassembling the configuration chip when updating configuration information.

[0008] The present invention provides a program burning method, comprising:

[0009] The QSPI interface, ISP interface and configuration chip of CPU / FPGA / DSP are connected in series through the QSPI interface signal to form a signal cascade structure;

[0010] Use ISP signal cable and field effect tube to control the power supply of configuration chip;

[0011] When the ISP signal cable is not used, the ISP interface is left floating, the signal in the QSPI interface of the CPU / FPGA / DSP is connected to the configuration chip, and the power supply in the QSPI interface of the CPU / FPGA / DSP supplies power to the configuration chip through the turned-on field effect transistor. The configuration chip is in normal working state, completing the functions of the CPU / FPGA / DSP and the configuration chip.

[0012] When using the ISP signal cable, insert one end of the ISP signal cable into the ISP interface, and the other end into the ISP interface of the burner / programmer. The burner / programmer provides QSPI signals and power supply to the configuration chip through the ISP signal cable. The product can complete the program burning of the configuration chip using the burner / programmer without powering on.

[0013] In some embodiments, the field effect transistor is a P-channel MOS field effect transistor; the drain of the P-channel MOS field effect transistor is connected to the power supply in the QSPI interface of the CPU / FPGA / DSP; the gate of the P-channel MOS field effect transistor is pulled down to ground and connected to the power supply output of the ISP interface; the source of the P-channel MOS field effect transistor is connected to the power supply input of the configuration chip; the power supply of the configuration chip is controlled by the voltage between the body diode and the gate source inside the P-channel MOS field effect transistor.

[0014] In some embodiments, when the ISP signal cable is not used, the ISP interface is not powered, and the power supply in the QSPI interface of the CPU / FPGA / DSP passes through the body diode of the field effect tube to meet the conduction condition of the field effect tube, thereby powering the configuration chip.

[0015] In some embodiments, the power supply output in the ISP interface of the burner / programmer is connected to a pin of the ISP interface through the ISP signal cable, and another pin of the ISP interface is connected to the power supply input of the configuration chip. The ISP signal cable connects the two power supply pins of the ISP interface by short-circuiting the corresponding two core wires, so that the burner / programmer powers the configuration chip through the ISP signal cable.

[0016] In some embodiments, during the device layout and signal routing of the QSPI interface of the CPU / FPGA / DSP, the ISP interface and the configuration chip in the hardware design, the ISP interface is located in the middle of the signal cascade structure, the CPU / FPGA / DSP and the configuration chip are located at the head and tail ends of the signal cascade structure respectively, and the total routing length of the QSPI signal on the printed circuit board needs to ensure that both the CPU / FPGA / DSP and the burner / programmer can read and write the configuration chip at high speed, meeting the system power-on time and fast program burning requirements.

[0017] In some embodiments, the ISP interface provides 4X data signals to support X1, X2 and X4 read and write operations of the configuration chip data interface.

[0018] In some embodiments, the ISP signal cable is a 10-core ISP signal cable.

[0019] The present invention also provides a program burning structure, comprising: a QSPI interface of a CPU / FPGA / DSP, an ISP interface and a configuration chip; the QSPI interface of the CPU / FPGA / DSP, the ISP interface and the configuration chip are connected in series through a QSPI interface signal to form a signal cascade structure;

[0020] When the ISP signal cable is not used, the ISP interface is left floating, and the signal in the QSPI interface of the CPU / FPGA / DSP is connected to the configuration chip, so that the power supply in the QSPI interface of the CPU / FPGA / DSP supplies power to the configuration chip through the turned-on field effect transistor, and the configuration chip is in normal working state, completing the functions of the CPU / FPGA / DSP and the configuration chip;

[0021] When using the ISP signal cable, connect the programmer / programmer to the configuration chip through the ISP signal cable, so that the programmer / programmer provides QSPI signals and power to the configuration chip through the ISP signal cable. The product can complete the program burning of the configuration chip using the programmer / programmer without powering on.

[0022] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0023] 1. The present invention directly connects the QSPI signal in the QSPI interface of the CPU / FPGA / DSP to the configuration chip, and the power supply in the QSPI interface of the CPU / FPGA / DSP is controlled by a field effect tube and then connected to the power supply input of the configuration chip. When the product is in normal use, the ISP interface is suspended, the field effect tube is turned on, the QSPI interface of the CPU / FPGA / DSP and the signal and power supply of the configuration chip are normally connected, and the functions of the CPU / FPGA / DSP and the configuration chip are completed.

[0024] 2. When the present invention uses a 10-core ISP signal cable, the burner / programmer supplies power to the configuration chip and provides a QSPI signal connection through the ISP interface, and program burning can be completed without powering the product. The burner / programmer supports configuration chips of various types and capacities, and does not require a dedicated simulator and development software during program burning, so it has universality. Since the product does not need to be powered on and the configuration chip does not need to be disassembled during program burning, the operation is convenient and fast, and is particularly suitable for product development and on-site maintenance and upgrade applications.

[0025] 3. The ISP interface of the present invention provides 4X data signals, supports the read and write operations of X1, X2 and X4 of the configuration chip data interface of the QSPI interface and the SPI interface, and the power supply range of the configuration chip supports 1.65V to 5.5V, which is only limited by the power supply requirements of the QSPI interface of the CPU / FPGA / DSP; since there are no special requirements for the power supply range, package type, capacity size, interface type and data width of the configuration chip, the adaptability to the configuration chip is strong. At the same time, since the QSPI signal is connected by a wiring on the printed circuit board between the CPU / FPGA / DSP, the SPI interface and the configuration chip, and there is no signal transmission delay caused by isolation / driving / buffering devices in the middle, the transmission speed of the QSPI signal is fast, and the configuration chip can be read and written quickly, reaching the highest read and write speed of the CPU / FPGA / DSP and the configuration chip QSPI signal, which is particularly suitable for applications where there are strict requirements on the reading and writing time of the configuration information when the system is powered on. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 The present invention provides a flowchart of a method for burning a program in an embodiment of the present invention.

[0027] Figure 2 Schematic diagram of the signal cascade structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0029] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] like Figure 1 As shown, this embodiment provides a program burning method, comprising the following steps:

[0031] The QSPI interface, ISP interface and configuration chip of CPU / FPGA / DSP are connected in series through the QSPI interface signal to form a signal cascade structure;

[0032] Taking the 10-core ISP signal cable as an example, the 10-core ISP signal cable and field effect transistor are used to control the power supply of the configuration chip;

[0033] When the 10-core ISP signal cable is not used, the ISP interface is left floating, the signal in the QSPI interface of the CPU / FPGA / DSP is connected to the configuration chip, and the power supply in the QSPI interface of the CPU / FPGA / DSP supplies power to the configuration chip through the turned-on field effect transistor. The configuration chip is in normal working state, completing the functions of the CPU / FPGA / DSP and the configuration chip.

[0034] When using a 10-core ISP signal cable, insert one end of the 10-core ISP signal cable into the ISP interface, and the other end into the ISP interface of the programmer / burner. The programmer / programmer provides QSPI signals and power supply to the configuration chip through the 10-core ISP signal cable. The product can complete the program burning of the configuration chip using the programmer / burner without powering on.

[0035] In this embodiment, if Figure 2As shown, the signal cascade structure includes: QSPI interface U1A1 of CPU / FPGA / DSP, ISP interface J1, configuration chip U2, field effect transistor Q1, pull-down resistor R1, pull-up resistor R2 and pull-up resistor R3; signals QSPI_CS, QSPI_D0, QSPI_D1, QSPI_SCLK, QSPI_D2, QSPI_D3 and power supply VDD in the QSPI interface of CPU / FPGA / DSP, QSPI signals CS, SI / D0, SO / D1, SCLK, WP / D2, HOLD / D3 and power supply VCC of configuration chip U2, signals CS, SI, SO, SCLK, D2, D3 and power supply VCC_ISP in the ISP interface. The QSPI interface U1A1 of the CPU / FPGA / DSP, the ISP interface J1, and the configuration chip U2 are connected in series through the above QSPI signals to form a signal cascade structure. The ISP interface J1 is in the middle of the signal cascade structure, and the CPU / FPGA / DSP and the configuration chip are respectively at the head and tail ends of the signal cascade structure, so that the configuration chip U2 is directly connected to the ISP interface and directly connected to the QSPI interface of the CPU / FPGA / DSP. Due to this layout, there is almost no bifurcation in the QSPI signal link, so the CPU / FPGA / DSP and the burner / programmer can read and write the configuration chip at high speed. QSPI_D2 and QSPI_D3 are provided with pull-up resistors, and the ISP interface provides 4X data signals to support the configuration chip of the QSPI interface. At the same time, pulling up D2~D3 also supports the X1, X2 and X4 read and write operations of the data interface of the configuration chip of the SPI interface.

[0036] In this embodiment, the power supply VDD in the QSPI interface of the CPU / FPGA / DSP is output to the power supply input VCC of the configuration chip after being controlled by the field effect transistor Q1, and the VCC is also connected to the No. 4 pin of the ISP interface.

[0037] In this embodiment, the 10-core ISP signal cable has 10-core connectors at both ends, and the core wires of the 10-core connector are connected one-to-one, wherein the No. 2 and No. 4 core wires are short-circuited, and the No. 6 core wire is not connected.

[0038] During normal use of the product, the ISP interface J1 is suspended, that is, the 10-core ISP signal cable is not used to insert the burner / programmer. At this time, the voltage value of VCC_ISP is 0V, and the gate voltage of the P-channel MOS field effect transistor Q1 that controls the power supply of the configuration chip U2 is 0V due to the pull-down resistor R1. VDD makes the body diode inside the P-channel MOS field effect transistor Q1 forward-conducted, so that the source voltage of the P-channel MOS field effect transistor Q1 is slightly lower than VDD, thereby making the voltage difference V between the gate (voltage is 0V) and the source (voltage is slightly lower than VDD) of the P-channel MOS field effect transistor Q1 GS meets the conduction condition of P-channel MOS field effect transistor Q1, so P-channel MOS field effect transistor Q1 is turned on, and finally VCC is approximately equal to VDD, that is, the power supply VCC of the configuration chip U2 is approximately equal to the power supply VDD in the QSPI interface of the CPU / FPGA / DSP, and VCC and VCC_ISP are isolated; because the signal in the QSPI interface of the CPU / FPGA / DSP is directly connected to the configuration chip; and then the signal connection and power supply of the CPU / FPGA / DSP and the configuration chip are normal, thus completing the functions of the CPU / FPGA / DSP and the configuration chip under normal use of the product. The power supply VCC of the configuration chip in the circuit supports 1.65V~5.5V, and the specific voltage is determined by VDD.

[0039] During the product development and field maintenance and upgrade process, the product does not need to be powered on. The ISP interface uses the 10-core ISP signal cable to connect to the burner / programmer. At this time, the voltage value of VCC_ISP output by the burner / programmer is the input voltage of the selected configuration chip U2. Since the No. 2 and No. 4 cores of the 10-core ISP signal cable are short-circuited, the power supply VCC of the configuration chip U2 is connected to the No. 4 core and then to the No. 2 core, that is, VCC is connected to VCC_ISP. Since the product is not powered on, the voltage of VDD is 0V, and VDD is connected to the drain of the P-channel MOS field effect transistor Q1. The gate voltage of the P-channel MOS field effect transistor Q1 is VCC_ISP, and the source voltage of the P-channel MOS field effect transistor Q1 is VCC. Since the voltages of VCC and VCC_ISP are the same, the voltage difference VGS between the gate and the source of the P-channel MOS field effect transistor Q1 does not meet the conduction condition of the P-channel MOS field effect transistor Q1, so VCC_ISP will not flow back to VDD, and the VDD voltage remains at 0V, so that the QSPI signal in the QSPI interface of the CPU / FPGA / DSP is in a high-impedance state, and thus will not affect the QSPI signal connection between the burner / programmer and the configuration chip. In this way, the QSPI signal pin of the configuration chip U2 is connected to the burner / programmer through the ISP interface, and at the same time, the power supply VCC of the configuration chip U2 is connected to the VCC_ISP output by the burner / programmer due to the insertion of the 10-core ISP signal cable, so that the burner / programmer can be used to conveniently complete the program burning when the product is not powered on.

[0040] Because some configuration chips only support SPI interface, QSPI_D2 and QSPI_D3 signals in QSPI interface signals are control signals for SPI interface. Resistors R2 and R3 are used to pull up at the configuration chip end to invalidate these control signals, so that the configuration chip with SPI interface can be programmed normally.

[0041] Based on the same technical concept, the embodiment of the present invention also provides a program burning structure, such as Figure 2 As shown, it includes: a QSPI interface of CPU / FPGA / DSP, an ISP interface and a configuration chip; the QSPI interface of CPU / FPGA / DSP, the ISP interface and the configuration chip are connected in series through the QSPI interface signal to form a signal cascade structure;

[0042] When the ISP signal cable is not used, the ISP interface is left floating, and the signal in the QSPI interface of the CPU / FPGA / DSP is connected to the configuration chip, so that the power supply in the QSPI interface of the CPU / FPGA / DSP supplies power to the configuration chip through the turned-on field effect transistor, and the configuration chip is in normal working state, completing the functions of the CPU / FPGA / DSP and the configuration chip;

[0043] When using the ISP signal cable, connect the programmer / programmer to the configuration chip through the ISP signal cable, so that the programmer / programmer provides QSPI signals and power to the configuration chip through the ISP signal cable. The product can complete the program burning of the configuration chip using the programmer / programmer without powering on.

[0044] The specific working principle of the above program burning structure can refer to the description of the above program burning method, which will not be repeated here.

[0045] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A program burning method, characterized in that: include: The QSPI interface, ISP interface and configuration chip of CPU / FPGA / DSP are connected in series through the QSPI interface signal to form a signal cascade structure; Use ISP signal cable and field effect tube to control the power supply of configuration chip; When the ISP signal cable is not used, the ISP interface is left floating, the signal in the QSPI interface of the CPU / FPGA / DSP is connected to the configuration chip, and the power supply in the QSPI interface of the CPU / FPGA / DSP supplies power to the configuration chip through the turned-on field effect transistor. The configuration chip is in normal working state, completing the functions of the CPU / FPGA / DSP and the configuration chip. When using the ISP signal cable, insert one end of the ISP signal cable into the ISP interface, and the other end into the ISP interface of the burner / programmer. The burner / programmer provides QSPI signals and power supply to the configuration chip through the ISP signal cable. The product can complete the program burning of the configuration chip using the burner / programmer without powering on.

2. The program burning method according to claim 1, characterized in that: The field effect tube is a P-channel MOS field effect tube; the drain of the P-channel MOS field effect tube is connected to the power supply in the QSPI interface of the CPU / FPGA / DSP; the gate of the P-channel MOS field effect tube is pulled down to the ground and connected to the power supply output of the ISP interface; the source of the P-channel MOS field effect tube is connected to the power supply input of the configuration chip; The power supply of the configuration chip is controlled by the voltage between the body diode and the gate source inside the P-channel MOS field effect transistor.

3. The program burning method according to claim 2, characterized in that: When the ISP signal cable is not used, the ISP interface has no power supply, and the power supply in the QSPI interface of the CPU / FPGA / DSP satisfies the conduction condition of the field effect tube after passing through the body diode of the field effect tube, thereby powering the configuration chip.

4. The program burning method according to claim 1, characterized in that: The power supply output in the ISP interface of the burner / programmer is connected to one pin of the ISP interface through the ISP signal cable, and the other pin of the ISP interface is connected to the power supply input of the configuration chip. The ISP signal cable connects the two power supply pins of the ISP interface by short-circuiting the corresponding two core wires, so that the burner / programmer supplies power to the configuration chip through the ISP signal cable.

5. The program burning method according to claim 1, characterized in that: During the device layout and signal routing of the QSPI interface of the CPU / FPGA / DSP, the ISP interface and the configuration chip in the hardware design, the ISP interface is located in the middle of the signal cascade structure, the CPU / FPGA / DSP and the configuration chip are located at the head and tail ends of the signal cascade structure respectively, and the total routing length of the QSPI signal on the printed circuit board needs to ensure that both the CPU / FPGA / DSP and the burner / programmer can read and write the configuration chip at high speed, so as to meet the requirements of system power-on time and fast program burning.

6. The program burning method according to claim 1, characterized in that: The ISP interface provides 4X data signals and supports X1, X2 and X4 read and write operations of the configuration chip data interface.

7. The program burning method according to any one of claims 1 to 6, characterized in that: The ISP signal cable is a 10-core ISP signal cable.

8. A program burning structure, characterized in that, include: QSPI interface, ISP interface and configuration chip of CPU / FPGA / DSP; the QSPI interface, ISP interface and configuration chip of CPU / FPGA / DSP are connected in series through QSPI interface signals to form a signal cascade structure; When the ISP signal cable is not used, the ISP interface is left floating, and the signal in the QSPI interface of the CPU / FPGA / DSP is connected to the configuration chip, so that the power supply in the QSPI interface of the CPU / FPGA / DSP supplies power to the configuration chip through the turned-on field effect transistor, and the configuration chip is in normal working state, completing the functions of the CPU / FPGA / DSP and the configuration chip; When using the ISP signal cable, connect the programmer / programmer to the configuration chip through the ISP signal cable, so that the programmer / programmer provides QSPI signals and power to the configuration chip through the ISP signal cable. The product can complete the program burning of the configuration chip using the programmer / programmer without powering on.

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