SOT-MRAM storage and calculation unit, array, system and method supporting XOR operation

Abstract

The invention provides an SOT-MRAM memory calculation unit, array, system and method supporting exclusive-or operation, which support data writing and reading and exclusive-or operation and complete common exclusive-or operation in a memory to reduce data transmission so as to relieve the storage wall problem. The SOT-MRAM storage and calculation unit provided by the invention comprises a first NMOS (N-channel Metal Oxide Semiconductor) tube, a first transmission gate and a magnetic tunnel junction SOT-MTJ, the SOT-MRAM storage and calculation array disclosed by the invention comprises four SOT-MRAM storage and calculation units which are arranged in a 2 * 2 manner; the SOT-MRAM storage and calculation system disclosed by the invention comprises an SOT-MRAM storage and calculation array, two induction circuit modules and an XOR operation circuit module, the SOT-MRAM storage and calculation method comprises the following steps of data writing operation, data reading operation and XOR operation.

Description

Technical Field

[0001] The present invention relates to a SOT-MRAM storage and calculation unit, array, system and method supporting XOR operation. Background Art

[0002] The main feature of traditional computers based on the von Neumann architecture is the separation of data storage and computing. With the emergence of high-performance parallel computing units such as GPUs, the memory that stores data cannot provide enough data for computing within the limited energy consumption and latency, which hinders the performance and improvement of computing units. This problem is called the storage wall.

[0003] In-memory computing is a feasible solution to overcome the memory wall problem. It allows the storage unit to have a certain computing power and can complete part of the computing processing work directly in the storage unit, avoiding the need to move data to the computing unit. Therefore, there is no delay and energy consumption in data transmission, thereby improving energy efficiency.

[0004] Spin transfer torque memory SOT-MRAM is an advanced non-volatile memory technology with many advantages such as non-volatility, low power consumption, high speed and high integration. Each SOT-MRAM storage unit includes a magnetic tunnel junction SOT-MTJ and ancillary circuits. The magnetic tunnel junction SOT-MTJ includes a spin Hall metal SHM and a magnetic tunnel junction MTJ, such as Figure 1 As shown. The MTJ is divided into three layers, the upper layer is a fixed magnetic layer, the middle layer is a tunnel barrier layer, and the lower layer is a free magnetic layer. MTJ is used to encode logical values ​​0 and 1 through its own high and low resistance states. When the magnetization direction of the free ferromagnetic layer is in the same direction as the fixed ferromagnetic layer, the resistance is in a low resistance state, indicating a logical value of 0; when the magnetization direction of the free ferromagnetic layer is changed and is opposite to the magnetization direction of the fixed ferromagnetic layer, the MTJ resistance is in a high resistance state, indicating a logical value of 1. The magnetization direction of the free ferromagnetic layer is controlled by the spin-orbit torque SOT generated by the current flowing through the SHM. The resistance value of the MTJ can be measured by the read current injected into it.

[0005] SOT-MRAM is an advanced technology with many advantages that is expected to replace DRAM as main memory. However, there is no effective solution for in-memory computing based on it, especially for the commonly used XOR operation. Summary of the invention

[0006] The present invention constructs an in-memory computing solution based on a novel memory to alleviate the memory wall problem, and provides a SOT-MRAM memory computing unit, array, system and method supporting XOR operation, which supports data writing, reading and XOR operation, and completes common XOR operation in the memory to reduce data transmission, thereby alleviating the memory wall problem.

[0007] The technical solution adopted by the present invention to solve the above-mentioned problem is: a SOT-MRAM storage and calculation unit supporting XOR operation, comprising a first NMOS tube, a first transmission gate and a magnetic tunnel junction SOT-MTJ; the gate of the first NMOS tube is connected to the read word line, and the source is connected to the fixed magnetic layer of the magnetic tunnel junction SOT-MTJ; the control end of the first transmission gate is connected to the write word line, one end of the first transmission gate is connected to the write bit line, the other end of the first transmission gate is connected to one end of the SHM layer of the magnetic tunnel junction SOT-MTJ, and the other end of the SHM layer of the magnetic tunnel junction SOT-MTJ is grounded.

[0008] The SOT-MRAM storage and computing array supporting XOR operation described in the present invention comprises four SOT-MRAM storage and computing units arranged in a 2×2 manner; the gates of the first NMOS tubes of two SOT-MRAM storage and computing units in the same horizontal row are connected to the same read word line, and the control ends of the first transmission gates of the two SOT-MRAM storage and computing units in the same horizontal row are connected to the same write word line.

[0009] In the SOT-MRAM storage and computing array described in the present invention, each SOT-MRAM storage and computing unit stores 1 bit of binary data, and the entire SOT-MRAM storage and computing array stores 4 bits of binary data.

[0010] A SOT-MRAM storage and computing system supporting XOR operation comprises the SOT-MRAM storage and computing array, two sensing circuit modules and an XOR operation circuit module; the drain of the first NMOS tube of each of two SOT-MRAM storage and computing units in the same row in the horizontal direction is connected to an sensing circuit module; and both sensing circuit modules are connected to the XOR operation circuit module.

[0011] The SOT-MRAM storage and computing system of the present invention, the sensing circuit module includes a sensing amplifier, a grounding resistor and two second transmission gates; one input end of the sensing amplifier is connected to the grounding resistor and the reference current source at the same time, the other input end of the sensing amplifier is connected to one end of the two second transmission gates and the read data current source at the same time, the control ends of the two second transmission gates are respectively connected to a read bit line, and the other ends of the two second transmission gates are respectively connected to the drains of the first NMOS tubes of two SOT-MRAM storage and computing units in the same row in a horizontal direction.

[0012] In the SOT-MRAM storage and computing system of the present invention, the output ends of the sensing amplifiers of the two sensing circuit modules are connected to the XOR operation circuit module, and the XOR operation circuit module includes a first inverter, a second inverter, a second NMOS tube and a third NMOS tube; the output end of the sensing amplifier of one sensing circuit module is connected to the input end of the first inverter and the gate of the third NMOS tube, and the output end of the sensing amplifier of the other sensing circuit module is connected to the input end of the second inverter and the drain of the second NMOS tube; the output end of the first inverter is connected to the gate of the second NMOS tube, and the output end of the second inverter is connected to the drain of the third NMOS tube; the source of the second NMOS tube and the source of the third NMOS tube together constitute the output end.

[0013] In the SOT-MRAM storage and computing system of the present invention, 1-bit data can be written into any two SOT-MRAM storage and computing units in the same row horizontally each time, 1-bit data stored in any two SOT-MRAM storage and computing units in the vertical direction can be read each time, and an XOR operation can be performed on any two SOT-MRAM storage and computing units in the vertical direction each time.

[0014] A SOT-MRAM storage and calculation method supporting XOR operation is implemented by using the SOT-MRAM storage and calculation system, and includes the following steps:

[0015] (1) Data writing operation:

[0016] Two SOT-MRAM storage units in the same row can write 1 bit of data at the same time. The corresponding write word line is set to be valid according to the row where the SOT-MRAM storage unit is located, so that the first transmission gate of the corresponding SOT-MRAM storage unit is connected, and then the write bit line is set to a positive voltage or a negative voltage according to the data to be written by the SOT-MRAM storage unit, so that the current in a specific direction flows through the SHM layer of the magnetic tunnel junction SOT-MTJ, setting the direction of the free magnetic layer, achieving high resistance or low resistance, and completing the data writing;

[0017] (2) Data reading operation:

[0018] Each time, the data in any two SOT-MRAM storage units in the vertical direction can be read. First, the read word line connected to the SOT-MRAM storage unit is set to be valid, and then the read bit line of the corresponding SOT-MRAM storage unit is set to be valid. The read current source injects current into the circuit, and at the same time, the reference current source injects a current of the same magnitude. The resistance of the magnetic tunnel junction SOT-MTJ is converted into the voltage at the input end of the sense amplifier; if the magnetic tunnel junction SOT-MTJ presents a high resistance, the corresponding voltage is greater than the other end of the sense amplifier, and the sense amplifier outputs a positive voltage, that is, the read value is 1; if the magnetic tunnel junction SOT-MTJ presents a low resistance, the corresponding voltage is less than the other input end of the sense amplifier, and the sense amplifier outputs a negative voltage, that is, the read value is 0;

[0019] (3) XOR operation:

[0020] The SOT-MRAM storage and computing array can perform an XOR operation on any two SOT-MRAM storage and computing units in the vertical direction at a time. First, the read data operation is activated to read the data of the two SOT-MRAM storage and computing units to the output of the sensing amplifier, and then pass through the XOR operation circuit module to realize the XOR operation.

[0021] Compared with the prior art, the present invention has the following advantages and effects:

[0022] 1. The present invention is a storage and computing unit, array, system and method constructed based on a novel non-volatile SOT-MRAM memory, which has significant advantages of high energy efficiency and fast response.

[0023] 2. Since the SOT-MRAM memory consumes almost no energy in a non-operating state, the present invention can achieve extremely low energy consumption while maintaining efficient data processing capabilities.

[0024] 3. The in-memory computing capability of the SOT-MRAM memory completes the common XOR operation on the memory side, and there is no need to send the data to the processor side, which reduces the data transmission between the processor and the memory, thereby effectively alleviating the storage wall problem, enabling the present invention to quickly process large amounts of data, significantly improve computing efficiency, avoid energy consumption of data transmission, and maximize energy efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a structural schematic diagram of the magnetic tunnel junction SOT-MTJ of the SOT-MRAM storage unit.

[0026] Figure 2 It is a structural schematic diagram of a SOT-MRAM storage and computing unit according to an embodiment of the present invention.

[0027] Figure 3It is a structural schematic diagram of a SOT-MRAM storage and computing system according to an embodiment of the present invention.

[0028] Figure 4 It is a schematic diagram of the structure of an XOR operation circuit module according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The present invention will be further described in detail below with reference to the accompanying drawings and by way of embodiments.

[0030] 1. Reference Figure 2 Each SOT-MRAM storage unit includes a first NMOS tube N, a first transmission gate TR and a magnetic tunnel junction SOT-MTJ. The gate of the first NMOS tube N is connected to the read word line BWL, and the source is connected to the fixed magnetic layer of the magnetic tunnel junction SOT-MTJ; the control end of the first transmission gate TR is connected to the write word line WWL, one end of the first transmission gate TR is connected to the write bit line SL, the other end of the first transmission gate TR is connected to one end of the SHM layer of the magnetic tunnel junction SOT-MTJ, and the other end of the SHM layer of the magnetic tunnel junction SOT-MTJ is grounded.

[0031] 2. Reference Figure 3 The SOT-MRAM memory array includes four SOT-MRAM memory units arranged in 2×2, and the four SOT-MRAM memory units are SOT-MRAM0 memory unit, SOT-MRAM1 memory unit, SOT-MRAM2 memory unit and SOT-MRAM3 memory unit. In the SOT-MRAM memory array, the first horizontal row is SOT-MRAM0 memory unit and SOT-MRAM2 memory unit, the second horizontal row is SOT-MRAM1 memory unit and SOT-MRAM3 memory unit, the first vertical column is SOT-MRAM0 memory unit and SOT-MRAM1 memory unit, and the second vertical column is SOT-MRAM2 memory unit and SOT-MRAM3 memory unit. Each SOT-MRAM memory unit stores 1 bit of binary data, and the entire SOT-MRAM memory array can store 4 bits of binary data.

[0032] The gates of the first NMOS tubes N of two SOT-MRAM storage and computing units in the same row laterally are connected to the same read word line BWL, for example, the gates of the first NMOS tubes N0 and N2 are connected to the same read word line BWL0, and the gates of the first NMOS tubes N1 and N3 are connected to the same read word line BWL1; the control ends of the first transmission gates TR of two SOT-MRAM storage and computing units in the same row laterally are connected to the same write word line WWL, for example, the control ends of the first transmission gates TR0 and TR2 are simultaneously connected to the write word line WWL0, and the control ends of the first transmission gates TR1 and TR3 are simultaneously connected to the write word line WWL1; at the same time, the right end of the SHM layer of the SOT-MTJ of each SOT-MRAM storage and computing unit is grounded.

[0033] 3. Reference Figure 3 The SOT-MRAM storage and computing system includes a SOT-MRAM storage and computing array, two sensing circuit modules and an XOR operation circuit module.

[0034] The sensing circuit module includes a sensing amplifier, a grounding resistor and two second transmission gates. One input end of the sensing amplifier is connected to the grounding resistor and the reference current source at the same time, the other input end of the sensing amplifier is connected to one end of the two second transmission gates and the read data current source at the same time, and the control ends of the two second transmission gates are respectively connected to a read bit line.

[0035] The drains of the first NMOS tubes N0 and N2 of the SOT-MRAM0 storage and calculation unit and the SOT-MRAM2 storage and calculation unit in the same horizontal row are connected to a sensing circuit module, which includes a sensing amplifier SA1, a grounding resistor R1, and two second transmission gates TR4 and TR5. One input end of the sensing amplifier SA1 is simultaneously connected to the grounding resistor R1 and the reference current source Iref1, and the other input end of the sensing amplifier SA1 is simultaneously connected to one end of the second transmission gate TR4 and one end of TR5, as well as the read data current source Isense1; the other end of the second transmission gate TR4 is connected to the drain of the first NMOS tube N0 of the SOT-MRAM0 storage and calculation unit, and the other end of the second transmission gate TR5 is connected to the drain of the first NMOS tube N2 of the SOT-MRAM2 storage and calculation unit; the control end of the second transmission gate TR4 is connected to the read bit line BL0, and the control end of the second transmission gate TR5 is connected to the read bit line BL2.

[0036] The drains of the first NMOS tubes N1 and N3 of the SOT-MRAM1 storage and calculation unit and the SOT-MRAM3 storage and calculation unit in the same horizontal row are connected to another sensing circuit module, which includes a sensing amplifier SA2, a grounding resistor R2 and two second transmission gates TR6 and TR7. One input end of the sensing amplifier SA2 is simultaneously connected to the grounding resistor R2 and the reference current source Iref2, and the other input end of the sensing amplifier SA2 is simultaneously connected to one end of the second transmission gate TR6 and one end of TR7, as well as the read data current source Isense2; the other end of the second transmission gate TR6 is connected to the drain of the first NMOS tube N1 of the SOT-MRAM1 storage and calculation unit, and the other end of the second transmission gate TR7 is connected to the drain of the first NMOS tube N3 of the SOT-MRAM3 storage and calculation unit; the control end of the second transmission gate TR6 is connected to the read bit line BL1, and the control end of the second transmission gate TR7 is connected to the read bit line BL3.

[0037] Reference Figure 4 The output ends of the sensing amplifiers SA1 and SA2 of the two sensing circuit modules are both connected to the XOR circuit module, which includes a first inverter Inv1, a second inverter Inv2, a second NMOS tube N11 and a third NMOS tube N12. The output end of one of the sensing amplifiers SA1 is connected to the input end of the first inverter Inv1 and the gate of the third NMOS tube N12, and the output end of the other sensing amplifier SA2 is connected to the input end of the second inverter Inv2 and the drain of the second NMOS tube N11; the output end of the first inverter Inv1 is connected to the gate of the second NMOS tube N11, and the output end of the second inverter Inv2 is connected to the drain of the third NMOS tube N12; the sources of the second NMOS tube N11 and the third NMOS tube N12 together constitute the output end.

[0038] Each time, any two SOT-MRAM storage and computing units in the same horizontal row can write 1 bit of data each, each time, any two SOT-MRAM storage and computing units in the vertical row can read 1 bit of data stored each time, and each time, any two SOT-MRAM storage and computing units in the vertical row can perform an XOR operation.

[0039] 4. A SOT-MRAM storage and calculation method supporting XOR operation is performed using the above-mentioned SOT-MRAM storage and calculation system, comprising the following steps:

[0040] 1. Data writing operation:

[0041] Two SOT-MRAM storage and computing units in the same row horizontally can write 1 bit of data each at the same time. According to the row where the SOT-MRAM storage and computing unit is located, the corresponding write word line WWL is set to be valid, so that the first transmission gate TR of the corresponding SOT-MRAM storage and computing unit is connected, and then the write bit line SL is set to a positive voltage or a negative voltage according to the data to be written by the SOT-MRAM storage and computing unit, so that the current in a specific direction flows through the SHM layer of the magnetic tunnel junction SOT-MTJ, setting the direction of the free magnetic layer, achieving high resistance or low resistance, and completing the data writing.

[0042] Specifically, taking the example of writing data 0 and 1 to the SOT-MRAM0 storage unit and the SOT-MRAM2 storage unit, respectively, the write word line WWL0 is set to be valid, so that the first transmission gates TR0 and TR2 are connected respectively; the write bit line SL0 is set to a positive voltage, so that the current flows from left to right through the SHM layer of the magnetic tunnel junction SOT-MTJ0, causing the magnetization direction of the free magnetic layer to be in the same direction as the fixed layer, thereby completing the writing of data 0; the write bit line SL1 is set to a negative voltage, so that the current flows from right to left through the SHM layer of the magnetic tunnel junction SOT-MRJ2, causing the magnetization direction of the magnetic layer to be opposite to the fixed layer, thereby completing the writing of data 1. The data writing operation of the SOT-MRAM1 storage unit and the SOT-MRAM3 storage unit in the second horizontal row is similar to the above, and the only difference is that the write word line WWL1 is set to be valid instead of WWL0.

[0043] 2. Data reading operation:

[0044] Each time, the data in any two SOT-MRAM storage and computing units in the vertical direction can be read. First, the read word line BWL connected to the SOT-MRAM storage and computing unit is set to be valid, and then the read bit line BL of the corresponding SOT-MRAM storage and computing unit is set to be valid. The read current source injects current into the circuit, and at the same time, the reference current source injects a current of the same magnitude. The resistance of the magnetic tunnel junction SOT-MTJ is converted into the voltage at the input end of the sense amplifier; if the magnetic tunnel junction SOT-MTJ presents a high resistance, the corresponding voltage is greater than the voltage at the other end of the sense amplifier, that is, the voltage connected to the ground resistor end, and the sense amplifier outputs a positive voltage, that is, the read value is 1; if the SOT-MTJ presents a low resistance, the corresponding voltage is less than the voltage at the other input end of the sense amplifier, that is, the voltage connected to the ground resistor end, and the sense amplifier outputs a negative voltage, that is, the read value is 0.

[0045] Specifically, taking the data in the storage and computing units SOT-MRAM0 and SOT-MRAM3 as an example, the read word lines BWL0 and BWL1 are simultaneously set to be valid, and then the read bit lines BL0 and BL3 are respectively set to be valid, so that the second transmission gates TR4 and TR7 are opened and connected; the read current source Isense1 injects current into the circuit, and the read current flows through the magnetic tunnel junction SOT-MTJ0 via the second transmission gate TR4 and the first NMOS tube N0. The reference current source Iref1 injects a current of the same magnitude as the read current source, and an input terminal of the sense amplifier SA1 can detect the voltage across the magnetic tunnel junction SOT-MTJ, which is proportional to its resistance, and then compared with the reference voltage of the grounding resistor R1, thereby reading the data stored on the magnetic tunnel junction SOT-MTJ0.

[0046] The same operation is performed for SOT-MTJ3. The read current source Isense2 injects current into the circuit. The read current flows through the magnetic tunnel junction SOT-MTJ3 via the second transmission gate TR7 and the first NMOS tube N3. The reference current source Iref2 injects a current of the same magnitude as the read current source. The sense amplifier SA2 detects the voltage across the first NMOS tube SOT-MTJ3, and its value is proportional to its resistance. The voltage is then compared with the reference voltage on the ground resistor R2 to read the data stored on the SOT-MTJ.

[0047] The data read operation of other SOT-MRAM storage units is similar to the above, the only difference is that the read bit line and read word line set to be valid each time must be adjusted according to the corresponding SOT-MRAM storage unit. It should be noted that the two SOT-MRAM storage units read at the same time cannot be in the same row, that is, the SOT-MRAM0 storage unit and the SOT-MRAM2 storage unit cannot be read at the same time, nor can the SOT-MRAM1 storage unit and the SOT-MRAM3 storage unit be read at the same time.

[0048] 3. XOR operation:

[0049] The SOT-MRAM storage and computing array can perform an XOR operation on any two SOT-MRAM storage and computing units in the vertical direction at a time. First, the read data operation is activated to read the data of the two SOT-MRAM storage and computing units to the output of the sensing amplifier, and then pass through the XOR operation circuit module to realize the XOR operation.

[0050] refer to Figure 4, take the output value of the sensing amplifier SA1 as 0 and the output value of the sensing amplifier SA2 as 1 as an example. The output of the sensing amplifier SA1 is 0 and is directly connected to the gate of the third NMOS tube N12, so the third NMOS tube N12 is invalid and remains cut off; the output of the sensing amplifier SA1 is output as 1 through the first inverter Inv1, and the output of the first inverter Inv1 is connected to the gate of the second NMOS tube N11, so the second NMOS tube N11 is turned on, so that the output value of Out is the output value 1 of the sensing amplifier SA2, as shown in the first row of Table 1. The process of generating the Out value by the other output values ​​of the sensing amplifier SA1 and the sensing amplifier SA2 is similar to the above process, and the specific result value is shown in Table 1, thereby realizing the XOR operation.

[0051] Table 1 XOR operation result table.

[0052] SA1 SA2 Out 0 1 1 1 0 1 0 0 0 1 1 0

[0053] In addition, it should be noted that the shapes and names of the parts and components of the specific embodiments described in this specification may be different, and the above content described in this specification is only an example of the structure of the present invention. All equivalent changes or simple changes made based on the structure, features and principles described in the patent concept of the present invention are included in the protection scope of the patent of the present invention. Technicians in the technical field of the present invention can make various modifications or supplements to the specific embodiments described or replace them in a similar manner, as long as they do not deviate from the structure of the present invention or exceed the scope defined by the claims, they should all fall within the protection scope of the present invention.

Claims

1. A SOT-MRAM storage and computing unit supporting XOR operation, characterized in that: It includes a first NMOS tube, a first transmission gate and a magnetic tunnel junction SOT-MTJ; the gate of the first NMOS tube is connected to the read word line, and the source is connected to the fixed magnetic layer of the magnetic tunnel junction SOT-MTJ; the control end of the first transmission gate is connected to the write word line, one end of the first transmission gate is connected to the write bit line, the other end of the first transmission gate is connected to one end of the SHM layer of the magnetic tunnel junction SOT-MTJ, and the other end of the SHM layer of the magnetic tunnel junction SOT-MTJ is grounded.

2. A SOT-MRAM storage and computing array supporting XOR operation, characterized in that: The invention comprises four SOT-MRAM storage and computing units according to claim 1 arranged in a 2×2 manner; the gates of the first NMOS tubes of two SOT-MRAM storage and computing units in the same horizontal row are connected to the same read word line, and the control ends of the first transmission gates of the two SOT-MRAM storage and computing units in the same horizontal row are connected to the same write word line.

3. The SOT-MRAM storage and computing array according to claim 2, characterized in that: Each SOT-MRAM storage unit stores 1 bit of binary data, and the entire SOT-MRAM storage array stores 4 bits of binary data.

4. A SOT-MRAM storage and computing system supporting XOR operation, characterized in that: The invention comprises a SOT-MRAM storage and computing array as claimed in claim 2 or 3, two sensing circuit modules and an XOR operation circuit module; the drain of each first NMOS tube of two SOT-MRAM storage and computing units in the same row in the horizontal direction is connected to a sensing circuit module; and both sensing circuit modules are connected to the XOR operation circuit module.

5. The SOT-MRAM storage and computing system according to claim 4, characterized in that: The sensing circuit module includes a sensing amplifier, a grounding resistor and two second transmission gates; one input end of the sensing amplifier is connected to the grounding resistor and the reference current source at the same time, the other input end of the sensing amplifier is connected to one end of the two second transmission gates and the read data current source at the same time, the control ends of the two second transmission gates are respectively connected to a read bit line, and the other ends of the two second transmission gates are respectively connected to the drains of the first NMOS tubes of two SOT-MRAM storage and calculation units in the same row in a horizontal direction.

6. The SOT-MRAM storage and computing system according to claim 5, characterized in that: The output ends of the sensing amplifiers of the two sensing circuit modules are connected to an XOR operation circuit module, which includes a first inverter, a second inverter, a second NMOS tube and a third NMOS tube; the output end of the sensing amplifier of one sensing circuit module is connected to the input end of the first inverter and the gate of the third NMOS tube, and the output end of the sensing amplifier of the other sensing circuit module is connected to the input end of the second inverter and the drain of the second NMOS tube; the output end of the first inverter is connected to the gate of the second NMOS tube, and the output end of the second inverter is connected to the drain of the third NMOS tube; The source of the second NMOS tube and the source of the third NMOS tube together form an output end.

7. The SOT-MRAM storage and computing system according to claim 6, characterized in that: Each time, any two SOT-MRAM storage and computing units in the same horizontal row can write 1 bit of data each, each time, any two SOT-MRAM storage and computing units in the vertical row can read 1 bit of data stored each time, and each time, any two SOT-MRAM storage and computing units in the vertical row can perform an XOR operation.

8. A SOT-MRAM storage and calculation method supporting XOR operation, characterized in that: The SOT-MRAM storage and computing system according to claim 6 is used, comprising the following steps: (1) Data writing operation: Two SOT-MRAM storage units in the same row can write 1 bit of data at the same time. The corresponding write word line is set to be valid according to the row where the SOT-MRAM storage unit is located, so that the first transmission gate of the corresponding SOT-MRAM storage unit is connected, and then the write bit line is set to a positive voltage or a negative voltage according to the data to be written by the SOT-MRAM storage unit, so that the current in a specific direction flows through the SHM layer of the magnetic tunnel junction SOT-MTJ, setting the direction of the free magnetic layer, achieving high resistance or low resistance, and completing the data writing; (2) Data reading operation: Each time, the data in any two SOT-MRAM storage units in the vertical direction can be read. First, the read word line connected to the SOT-MRAM storage unit is set to be valid, and then the read bit line of the corresponding SOT-MRAM storage unit is set to be valid. The read current source injects current into the circuit, and at the same time, the reference current source injects a current of the same magnitude. The resistance of the magnetic tunnel junction SOT-MTJ is converted into the voltage at the input end of the sense amplifier; if the magnetic tunnel junction SOT-MTJ presents a high resistance, the corresponding voltage is greater than the other end of the sense amplifier, and the sense amplifier outputs a positive voltage, that is, the read value is 1; if the magnetic tunnel junction SOT-MTJ presents a low resistance, the corresponding voltage is less than the other input end of the sense amplifier, and the sense amplifier outputs a negative voltage, that is, the read value is 0; (3) XOR operation: The SOT-MRAM storage and computing array can perform an XOR operation on any two SOT-MRAM storage and computing units in the vertical direction at a time. First, the read data operation is activated to read the data of the two SOT-MRAM storage and computing units to the output of the sensing amplifier, and then pass through the XOR operation circuit module to realize the XOR operation.

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