Manufacturing method of semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure. The manufacturing method comprises the following steps: providing a lead frame, wherein the lead frame comprises a plurality of pins, a plurality of first connecting parts and a plurality of second connecting parts; the pins are connected with the adjacent second connecting parts through the first connecting parts; each pin comprises a first surface and a second surface which are opposite to each other; a plastic package structure comprising a lead frame, a chip and a plastic package layer is formed, the chip faces the first surface, the plastic package layer packages the chip and the lead frame, and the second surface is exposed out of the plastic package layer; a groove is formed between the second connecting part and the pin connected with the second connecting part, at least part of the side face, facing the first connecting part connected with the pin, of each pin is exposed by the groove, and at least part of the surface, deviating from the chip, of the second connecting part is covered by the plastic packaging layer; forming a solder layer on the exposed surface of the lead frame; the obtained structure is cut along the cutting channel, and the second connecting part is removed; the orthographic projection of the cutting channel on the plane where the first surface is located falls in the orthographic projection of the groove on the plane.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure. Background Art

[0002] A chip packaging technology may include the following process: first, a lead frame is mounted on a carrier board, the lead frame includes a frame, a connecting part located in the frame and a plurality of pins, the pins are connected to the connecting part, and the connecting part is connected to the frame; then, the chip is mounted on the lead frame, and the pins are electrically connected to the chip pads; then, a plastic sealing layer is formed; then, cutting is performed to form grooves on the sides of the exposed pin parts; then, a tin plating layer is formed on the exposed surface of the lead frame by an electroplating process; finally, a cutting process is used to remove the connecting part and the frame.

[0003] In the above chip packaging technology, in the process of cutting and removing the connecting part, the tin-plated layer formed on the surface of the connecting part will produce tin wire. After the tin wire falls off, it will fall between adjacent pins, causing a short circuit between the adjacent pins, affecting the yield of the product. Summary of the invention

[0004] The present application provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure includes:

[0005] A lead frame is provided, wherein the lead frame comprises a plurality of pins, a plurality of first connecting portions and a second connecting portion; the pins are connected to adjacent second connecting portions through the first connecting portions; the pins comprise a first surface and a second surface opposite to each other;

[0006] Forming a plastic packaging structure, the plastic packaging structure comprising the lead frame, the chip and the plastic packaging layer, the chip faces the first surface, the plastic packaging layer encapsulates the chip and the lead frame, and the second surface exposes the plastic packaging layer;

[0007] A groove is formed between the second connection part and the pin connected thereto, the side of each pin facing the first connection part connected thereto is at least partially exposed by the groove, at least a portion of the surface of the second connection part facing away from the chip is covered by the plastic sealing layer, and the length of the area of ​​the surface of the second connection part facing away from the chip covered by the plastic sealing layer is equal to the length of the second connection part;

[0008] forming a solder layer on the exposed surface of the lead frame;

[0009] The obtained structure is cut along the cutting path, and the second connecting portion is removed to obtain at least one semiconductor structure, wherein the semiconductor structure includes at least one chip; the orthographic projection of the cutting path on the plane where the first surface is located falls within the orthographic projection of the groove on the plane.

[0010] In one embodiment, the second connecting portion includes a first portion and a second portion extending along the length direction, the first portion is located on the side of the second portion facing the first connecting portion, and the thickness of the first portion is less than the thickness of the second portion; after the groove is formed between the second connecting portion and the pin connected thereto, the surface of the first portion facing away from the chip is covered by the plastic packaging layer.

[0011] In one embodiment, the thickness of the second portion is equal to the thickness of the pin; after the groove is formed between the second connecting portion and the pin connected thereto, the second portion is away from the surface of the chip and exposes the plastic packaging layer.

[0012] In one embodiment, two sides of at least one of the second connecting parts are respectively connected to the first connecting part, and the second connecting part includes two first parts, and the two first parts are located at two opposite sides of the second part.

[0013] In one embodiment, the widths of the two first portions of the second connecting portion are the same.

[0014] In one embodiment, the thickness of each area of ​​the second connection part is smaller than the thickness of the pin. After the groove is formed between the second connection part and the pin connected thereto, the surface of the second connection part facing away from the chip is completely covered by the plastic packaging layer.

[0015] In one embodiment, the cutting width when the obtained structure is cut along the cutting street is smaller than the width of the groove.

[0016] In one embodiment, a recessed portion is provided on at least one side of the surface of the first connection portion facing away from the second surface, and an orthographic projection of the recessed portion on a plane where the first surface is located overlaps with an orthographic projection of the cutting path on the plane.

[0017] In one embodiment, after the groove is formed between the second connection portion and the pin connected thereto, the size of the portion of the pin exposed toward the side of the first connection portion connected thereto in the thickness direction of the pin is greater than or equal to half of the thickness of the pin.

[0018] In one embodiment, the lead frame includes a plurality of the second connection portions, and the plurality of the second connection portions are electrically connected.

[0019] The main technical effects achieved by the embodiments of the present application are:

[0020] The manufacturing method of the semiconductor structure provided in the embodiment of the present application has the following characteristics: since at least part of the side surface of the pin is exposed after a groove is formed between the second connecting part and the adjacent pin, a solder layer can be formed on the exposed side surface of the pin to meet the requirement of welding on the side surface of the pin; since at least part of the surface of the second connecting part facing away from the chip is covered by the plastic sealing layer after the groove is formed, the part of the surface of the second connecting part facing away from the chip covered by the plastic sealing layer will not form a solder layer, and the area of ​​the solder layer located on the surface of the second connecting part facing away from the chip is relatively small, which can reduce the probability of cutting the part of the solder layer located on the surface of the second connecting part facing away from the chip due to cutting errors during cutting, reduce the risk of wiredrawing caused by cutting the solder layer, thereby improving the problem of short circuit in the semiconductor structure caused by the wiredrawing falling between two adjacent first connecting parts after falling off, and improve the product yield of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a flow chart of a method for manufacturing a top view of a semiconductor structure provided by an exemplary embodiment of the present application;

[0022] Figure 2 is a partial top view of a lead frame provided by an exemplary embodiment of the present application;

[0023] Figure 3 yes Figure 2 The lead frame shown is a cross-sectional view obtained by cutting along AA;

[0024] Figure 4 is a partial top view of a lead frame provided by another exemplary embodiment of the present application;

[0025] Figure 5 yes Figure 4 The lead frame shown is a cross-sectional view obtained by cutting along CC;

[0026] Figure 6 yes Figure 2 The cross-sectional view of the lead frame shown is obtained by cutting along BB. Figure 3 The lead frame shown is a cross-sectional view obtained by cutting along DD;

[0027] Figure 7 is a partial cross-sectional view of a semiconductor package structure provided by an exemplary embodiment of the present application;

[0028] Figure 8 is a partial cross-sectional view of a semiconductor package structure provided by another exemplary embodiment of the present application;

[0029] Fig. 9 is a partial cross-sectional view of a first intermediate structure provided by an exemplary embodiment of the present application;

[0030] Fig.10 yes Fig. 9A schematic diagram of the three-dimensional structure of the first intermediate structure shown;

[0031] Fig.11 is a partial cross-sectional view of a first intermediate structure provided by another exemplary embodiment of the present application;

[0032] Fig.12 is a partial cross-sectional view of a second intermediate structure provided by an exemplary embodiment of the present application;

[0033] Fig.13 is a partial cross-sectional view of a second intermediate structure provided by another exemplary embodiment of the present application;

[0034] Fig.14 is a cross-sectional view of a semiconductor structure provided by an exemplary embodiment of the present application. Specific embodiments

[0035] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0036] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0037] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0038] Some embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0039] The present application provides a method for manufacturing a semiconductor structure. Figure 1As shown, the method for manufacturing the semiconductor structure includes the following steps 110 to 150 .

[0040] In step 110, a lead frame is provided, wherein the lead frame includes a plurality of pins, a plurality of first connection parts and a second connection part; the pins are connected to adjacent second connection parts through the first connection parts; and the pins include a first surface and a second surface opposite to each other.

[0041] In step 120, a plastic encapsulation structure is formed, the plastic encapsulation structure comprising the lead frame, the chip and a plastic encapsulation layer, the chip faces the first surface, the plastic encapsulation layer encapsulates the chip and the lead frame, and the second surface exposes the plastic encapsulation layer.

[0042] In step 130, a groove is formed between the second connection part and the pin connected thereto, the side of each pin facing the first connection part connected thereto is at least partially exposed by the groove, at least a portion of the surface of the second connection part facing away from the chip is covered by the plastic encapsulation layer, and the length of the area of ​​the surface of the second connection part facing away from the chip covered by the plastic encapsulation layer is equal to the length of the second connection part.

[0043] In step 140, a solder layer is formed on the exposed surface of the lead frame.

[0044] In step 150, the obtained structure is cut along the cutting line, and the second connecting portion is removed to obtain at least one semiconductor structure, wherein the semiconductor structure includes at least one chip; the orthographic projection of the cutting line on the plane where the first surface is located falls within the orthographic projection of the groove on the plane.

[0045] In the manufacturing method of the semiconductor structure provided in the embodiment of the present application, after a groove is formed between the second connecting part and the adjacent pin, at least part of the side surface of the pin is exposed, and a solder layer can be formed on the exposed side surface of the pin to meet the requirement of welding on the side surface of the pin; because at least part of the surface of the second connecting part facing away from the chip is covered by the plastic sealing layer after the groove is formed, the part of the surface of the second connecting part facing away from the chip covered by the plastic sealing layer will not form a solder layer, and the area of ​​the solder layer located on the surface of the second connecting part facing away from the chip is relatively small, which can reduce the probability of cutting the part of the solder layer located on the surface of the second connecting part facing away from the chip due to cutting errors during cutting, reduce the risk of wiredrawing caused by cutting the solder layer, thereby improving the problem of short circuit in the semiconductor structure caused by the wiredrawing falling between the two adjacent first connecting parts after falling off, and improve the product yield of the semiconductor structure.

[0046] The following is a detailed introduction to each step of the method for manufacturing a semiconductor structure provided in an embodiment of the present application.

[0047] In step 110, a lead frame is provided, wherein the lead frame includes a plurality of pins, a plurality of first connection parts and a second connection part; the pins are connected to adjacent second connection parts through the first connection parts; and the pins include a first surface and a second surface opposite to each other.

[0048] like Figures 2 to 5 As shown, the lead frame includes a pin 10, a first connection portion 20 and a second connection portion 30, one end of the first connection portion 20 is connected to the pin 10, and the other end is connected to the second connection portion 30. The same second connection portion 30 can be connected to multiple pins 10, and the multiple pins 10 connected to the same second connection portion 30 and located on the same side of the second connection portion 30 are arranged at intervals in the length direction of the second connection portion 30.

[0049] The "length" mentioned in the embodiments of this application refers to Figure 2 and Figure 4 The dimension in the X direction, "width" refers to Figure 2 and Figure 4 The dimension in the Y direction, "thickness" refers to Figure 3 and Figure 5 The size in the Z direction.

[0050] In one embodiment, the lead frame includes a plurality of second connection portions, and the plurality of second connection portions are electrically connected. In some embodiments, some of the plurality of second connection portions extend in a transverse direction, and the remaining second connection portions extend in a longitudinal direction, and the second connection portions extending in a transverse direction are connected to the second connection portions extending in a longitudinal direction.

[0051] In one embodiment, Figure 3 and Figure 5 As shown, the first connection part 20 includes a first sub-connection part 21 and a second sub-connection part 22 connected to the first sub-connection part 21. The maximum thickness of the first sub-connection part 21 may be the same as the thickness of the pin 10 and greater than the thickness of the second sub-connection part 22. The surface of the first sub-connection part 21 located on the same side as the second surface 12 of the pin 10 is flush with the second surface 12, and the surface of the first sub-connection part 21 located on the same side as the first surface 13 of the pin 10 is flush with the first surface 13. The surface of the second sub-connection part 22 located on the same side as the first surface 13 of the pin 10 is flush with the first surface 13, and the surface of the second sub-connection part 22 facing away from the first surface 13 is lower than the second surface 12. The first sub-connection part 21 is connected to the pin 10, and the second sub-connection part 22 is connected to the second connection part 30.

[0052] In one embodiment, Figure 2 and Figure 3As shown, the second connection portion 30 includes a first portion 31 and a second portion 32 extending in the length direction, and the length of the first portion 31 and the length of the second portion 32 are both the same as the length of the second connection portion 30. The thickness of the first portion 31 is less than the thickness of the second portion 32, and the thickness of the second portion 32 is the same as the thickness of the lead 10. The surface of the second portion 32 located on the same side as the second surface 12 of the lead 10 is flush with the second surface 12, and the surface of the second portion 32 located on the same side as the first surface 13 of the lead 10 is flush with the first surface 13. The surface of the first portion 31 located on the same side as the first surface 13 of the lead 10 is flush with the first surface 13, and the surface of the first portion 31 away from the first surface 13 is lower than the second surface 12. By setting the thickness of the second portion 32 to be greater than the thickness of the first portion 31, and the second portion 32 to be flush with the surface of the second surface 12 of the lead 10 on the same side, it is helpful to reduce the possibility of wire drawing in the subsequent cutting process while ensuring the strength of the lead frame.

[0053] In another embodiment, Figure 5 As shown, the thickness of each area of ​​the second connection portion 30 is less than the thickness of the pin 10, and the thickness of the second connection portion 30 is the same at all locations. The thickness of the second connection portion 30 may be the same as the thickness of the second sub-connection portion 22. The surface of the second connection portion 30 located on the same side as the first surface 13 of the pin 10 is flush with the first surface 13, and the surface of the second connection portion 30 facing away from the second surface 12 is flush with and lower than the second surface 12.

[0054] In one embodiment, Figure 6 As shown, at least one side of the surface of the first connection portion 20 facing away from the second surface 12 is provided with a recessed portion 211. The orthographic projection of the recessed portion 211 on the plane where the first surface 13 is located overlaps with the orthographic projection of the cutting path on the plane. With such an arrangement, when the obtained structure is cut in step 150, the cutting stress can be reduced and the cutting difficulty can be reduced; and compared with the scheme in which the recessed portion is arranged on the surface of the first connection portion 20 facing away from the first surface, the surface area of ​​the first connection portion 20 facing away from the first surface 13 can be larger, and thus the surface area of ​​the first connection portion that is not cut off in the final semiconductor structure facing away from the first surface 13 can be larger, which helps to increase the welding area between the semiconductor structure and other structures such as a circuit board. In some embodiments, the recessed portion 211 can be located in the first sub-connection portion 21. Figure 6 In the embodiment shown, the first connection portion 20 has two opposite sides of the surface facing away from the second surface 12, respectively, with recessed portions 211, so as to more effectively reduce the difficulty of cutting. In other embodiments, the first connection portion 20 may have only one side of the surface facing away from the second surface 12 with a recessed portion 211.

[0055] In step 120, a plastic encapsulation structure is formed, the plastic encapsulation structure comprising the lead frame, the chip and a plastic encapsulation layer, the chip faces the first surface, the plastic encapsulation layer encapsulates the chip and the lead frame, and the second surface exposes the plastic encapsulation layer.

[0056] Through step 120, the following can be obtained: Figure 7 or Figure 8 The semiconductor package structure shown in Figure 7 and Figure 8 As shown, the surface of the plastic encapsulation layer and the second surface of the lead 10 on the same side can be flush at all places. The semiconductor packaging structure may include a plurality of chips 50, the chips 50 are located on one side of the lead frame, and the chips 50 face the first surface of the lead 10; the plastic encapsulation layer 80 encapsulates the chips 50 and the lead frame, and the second surface of the lead 10 exposes the plastic encapsulation layer 80.

[0057] In one embodiment, Figure 7 and Figure 8 As shown, the lead frame may further include a base island 40, and the chip 50 is mounted on the base island 40 through an adhesive layer 60. The chip 50 may include a chip front side and a chip back side opposite to the chip front side, and the chip back side may be mounted on the base island 40 through an adhesive layer 60. The adhesive layer 60 may be, for example, solder paste or silver paste. In other embodiments, the material of the adhesive layer 60 may be a non-conductive adhesive such as a resin adhesive. A solder pad may be provided on the front side of the chip, and the solder pad may be electrically connected to the pin 10 through a bonding wire 70, so that the pin 10 may lead out the solder pad of the chip 50.

[0058] In one embodiment, the structure of the lead frame is Figure 3 The structure shown in FIG. 1 is a semiconductor package structure. Figure 7 As shown, the surface of the second part 32 facing away from the chip 50 exposes the plastic layer 80, the surface of the first sub-connection part 21 facing away from the chip 50 exposes the plastic layer 80, the surface of the second sub-connection part 22 facing away from the chip 50 and the surface of the first part 31 facing away from the chip 50 are covered by the plastic layer 80; the space between the first sub-connection part 21 and the second connection part 30 of the lead frame is filled with the plastic layer 80.

[0059] In another embodiment, the structure of the lead frame is Figure 5 The structure shown in FIG. 1 is a semiconductor package structure. Figure 8 As shown, part of the surface of the first sub-connection part 21 facing away from the chip 50 is exposed to the plastic layer 80, and the surface of the second sub-connection part 22 facing away from the chip 50 and the surface of the second connection part 30 facing away from the chip 50 are all covered by the plastic layer 80; the space between the two first sub-connection parts 21 of the lead frame is filled with the plastic layer 80.

[0060] In step 130, a groove is formed between the second connection part and the pin connected thereto, the side of each pin facing the first connection part connected thereto is at least partially exposed by the groove, at least a portion of the surface of the second connection part facing away from the chip is covered by the plastic encapsulation layer, and the length of the area of ​​the surface of the second connection part facing away from the chip covered by the plastic encapsulation layer is equal to the length of the second connection part.

[0061] In one embodiment, a cutting process can be used to form a groove 101 between the second connection part 30 and the pin 10 connected thereto. The width of the cutting knife used in cutting is relatively large. During the cutting process, since the feeding direction of the cutting knife is the same as the length direction of the second connection part 30, if the cutting knife squeezes the second connection part 30, the width of the second connection part 30 will increase. If the surface of the second connection part 30 facing away from the chip is fully exposed after step 130, the width of the part of the solder layer formed subsequently located on the second connection part 30 is relatively large, and it is easy to cut the solder layer on the second connection part during cutting in step 150, resulting in wire drawing.

[0062] In one embodiment, a semiconductor package structure such as Figure 7 As shown, through step 130, the following can be obtained: Fig. 9 and Fig.10 The first intermediate structure shown. Fig. 9 and Fig.10 As shown, a portion of the side surface 11 of the pin 10 facing the second connection part 30 is exposed from the plastic encapsulation layer 80, and the surface of the first part 31 facing away from the chip 50 is covered by the plastic encapsulation layer 80. When the groove 101 is formed, a portion of the first connection part 20 is removed, and after the groove 101 is formed, the surface of the first connection part 20 facing away from the chip 50 can be flush and exposed from the plastic encapsulation layer 80. Since the surface of the first part 31 of the second connection part 30 facing away from the chip 50 is covered by the plastic encapsulation layer 80, in the subsequent steps, no solder layer will be formed on the surface of the first part 31 facing away from the chip 50, which can reduce the width of the solder layer formed on the surface of the second connection part 30 facing away from the chip 50, thereby reducing the risk of cutting the surface portion of the solder layer located on the second connection part 30 due to cutting errors and the increase in the width of the second connection part 30 when the groove is formed by the cutting process in step 150, thereby improving the yield of the semiconductor structure.

[0063] Furthermore, if Fig. 9 and Fig.10 As shown, the surface of the second portion 32 facing away from the chip 50 exposes the plastic encapsulation layer 80. When the thickness of the second portion 32 is the same as the thickness of the lead 10, the surface of the second portion 32 facing away from the chip 50 exposes the plastic encapsulation layer 80.

[0064] Furthermore, if Fig. 9 and Fig.10 As shown, at least one of the second connection parts 30 is connected to the first connection part 20 at both sides; the second connection part 30 includes two first parts 31, and the two first parts 31 are located at opposite sides of the second part 32. When cutting in the subsequent step 150, the grooves 101 on both sides of the second connection part 30 need to be cut respectively. By providing the first parts 31 on the opposite sides of the second part 32, the distance between the pins on both sides of the second part 32 and the second part 32 can be made larger, and when cutting at the grooves 101 on both sides of the second connection part 30, it is possible to avoid cutting the part of the solder layer located on the surface of the second part 32.

[0065] Furthermore, the widths of the two first parts 31 of the second connection portion 30 are the same. This arrangement can avoid the situation where the width of one of the first parts 31 is smaller, resulting in a smaller distance between the pin of the first part 31 and the second part 32, and the part of the solder layer located on the surface of the second part 32 cannot be effectively avoided from being cut.

[0066] In another embodiment, a semiconductor package structure such as Figure 8 As shown, we get Fig.11 The first intermediate structure shown. Fig.11 As shown, a portion of the side surface 11 of the pin 10 facing the second connection part 30 is exposed from the plastic encapsulation layer 80, and the surface of the second connection part 30 facing away from the chip 50 is completely covered by the plastic encapsulation layer 80. When the groove 101 is formed, part of the first connection part 20 is removed, and after the groove 101 is formed, the surface of the first connection part 20 facing away from the chip 50 can be flush and exposed from the plastic encapsulation layer 80. Since the surface of the second connection part 30 facing away from the chip 50 is completely covered by the plastic encapsulation layer 80, in the subsequent steps, the surface of the second connection part 30 facing away from the chip 50 will not form a solder layer. Therefore, when cutting in step 150, even if the second connection part 30 is cut due to cutting errors, the solder layer can be prevented from drawing, which helps to improve the yield of the semiconductor structure.

[0067] In one embodiment, after the step of forming the groove between the second connection part and the pin connected thereto, the size of the portion of the pin 10 exposed toward the side of the first connection part 20 connected thereto in the thickness direction of the pin 10 is greater than or equal to half of the thickness of the pin 10. In this way, the size of the solder layer formed on the side of the semiconductor structure finally obtained in the thickness direction of the pin 10 is greater than or equal to half of the thickness of the pin 10, which helps to ensure the welding effect between the side of the semiconductor structure and other structures such as a circuit board. The size of the portion of the pin 10 exposed toward the side of the first connection part 20 connected thereto in the thickness direction of the pin 10 is the same as the depth of the groove 101.

[0068] In one embodiment, an extending direction of the groove 101 is the same as an extending direction of the second connecting portion 30 , and a length of the groove 101 is the same as a length of the second connecting portion 30 .

[0069] In one embodiment, when the pins 10 are respectively connected to two opposite sides of the second connection portion 30 , grooves 101 are respectively formed on two opposite sides of the second connection portion 30 .

[0070] In step 140, a solder layer is formed on the exposed surface of the lead frame.

[0071] In one embodiment, a solder layer may be formed on the exposed surface of the lead frame by an electroplating process. The exposed surface of the lead frame includes the surface of the pin 10 facing away from the chip 50, the portion of the pin 10 exposed toward the side of the first connection portion 20 connected thereto, the exposed surface of the first connection portion 20, and the exposed surface of the second connection portion 30. Since the second connection portions of the lead frame are electrically connected, and the pins are respectively connected to the second connection portions through the first connection portions, the various structures of the lead frame are electrically connected, and a solder layer may be formed on the exposed surface of the lead frame at the same time during electroplating.

[0072] In one embodiment, the material of the solder layer is tin.

[0073] In one embodiment, the first intermediate structure is as Fig. 9 As shown, through step 140, the following can be obtained: Fig.12 The second intermediate structure shown. Fig.12 As shown, the solder layer 90 is partially located on the surface of the pin 10 facing away from the chip 50, partially located on the portion of the side 11 of the pin 10 exposed by the groove 101, partially located on the surface of the second portion 32 facing away from the chip 50, and partially located on the surface of the first connection portion 20 facing away from the chip 50.

[0074] In another embodiment, the first intermediate structure is as Fig.11 As shown, through step 150, the following can be obtained: Fig.13 The second intermediate structure shown. Fig.13 As shown, the solder layer 90 is partially located on the surface of the pin 10 facing away from the chip 50, partially located on the portion of the side 11 of the pin 10 exposed by the groove 101, and partially located on the surface of the first connecting part 20 facing away from the chip 50. The surface of the second connecting part 30 facing away from the chip 50 is not formed with the solder layer 90.

[0075] In step 150, the obtained structure is cut along the cutting line, and the second connecting portion is removed to obtain at least one semiconductor structure, wherein the semiconductor structure includes at least one chip; the orthographic projection of the cutting line on the plane where the first surface is located falls within the orthographic projection of the groove on the plane.

[0076] In one embodiment, the cutting width when the structure is cut along the cutting path is smaller than the width of the groove. Since the orthographic projection of the cutting path on the plane where the first surface is located falls within the orthographic projection of the groove on the plane, by setting the cutting width when the structure is cut along the cutting path to be smaller than the width of the groove, when a solder layer is formed on the surface of the second connection part 30 away from the chip 50, even if there is a cutting error, the portion of the solder layer located on the surface of the second connection part 30 can be effectively avoided from being cut during cutting, thereby effectively preventing the solder layer from drawing.

[0077] In one embodiment, the width of the groove 101 ranges from 0.3 mm to 1.0 mm, and the cutting width ranges from 0.2 mm to 0.35 mm when the structure is cut along the cutting path. In some embodiments, the width of the groove 101 is 0.5 mm, and the cutting width ranges from 0.25 mm when the structure is cut along the cutting path.

[0078] In one embodiment, the semiconductor structure may be Fig.14 As shown, the semiconductor structure includes a portion where the first connection portion 20 is connected to the lead 10. In other embodiments, when the cutting accuracy is relatively high, the semiconductor structure may not include a portion where the first connection portion 20 is connected to the lead.

[0079] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0080] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0081] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The manufacturing method comprises: A lead frame is provided, wherein the lead frame comprises a plurality of pins, a plurality of first connecting portions and a second connecting portion; the pins are connected to adjacent second connecting portions through the first connecting portions; the pins comprise a first surface and a second surface opposite to each other; Forming a plastic packaging structure, the plastic packaging structure comprising the lead frame, the chip and the plastic packaging layer, the chip faces the first surface, the plastic packaging layer encapsulates the chip and the lead frame, and the second surface exposes the plastic packaging layer; A groove is formed between the second connection part and the pin connected thereto, the side of each pin facing the first connection part connected thereto is at least partially exposed by the groove, at least a portion of the surface of the second connection part facing away from the chip is covered by the plastic sealing layer, and the length of the area of ​​the surface of the second connection part facing away from the chip covered by the plastic sealing layer is equal to the length of the second connection part; forming a solder layer on the exposed surface of the lead frame; The obtained structure is cut along the cutting path, and the second connecting portion is removed to obtain at least one semiconductor structure, wherein the semiconductor structure includes at least one chip; the orthographic projection of the cutting path on the plane where the first surface is located falls within the orthographic projection of the groove on the plane.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The second connecting part includes a first part and a second part extending along the length direction, the first part is located on the side of the second part facing the first connecting part, and the thickness of the first part is less than the thickness of the second part; after the groove is formed between the second connecting part and the pin connected to it, the surface of the first part facing away from the chip is covered by the plastic packaging layer.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The thickness of the second portion is equal to the thickness of the pin; after the groove is formed between the second connecting portion and the pin connected thereto, the second portion is away from the surface of the chip and exposes the plastic packaging layer.

4. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: Two sides of at least one of the second connecting parts are respectively connected to the first connecting part, and the second connecting part includes two first parts, and the two first parts are located at two opposite sides of the second part.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that: The two first portions of the second connecting portion have the same width.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The thickness of each area of ​​the second connection part is smaller than the thickness of the pin. After the groove is formed between the second connection part and the pin connected thereto, the surface of the second connection part facing away from the chip is completely covered by the plastic packaging layer.

7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The cutting width when the obtained structure is cut along the cutting road is smaller than the width of the groove.

8. The method for manufacturing a semiconductor structure according to claim 1, wherein: A recessed portion is provided on at least one side of a surface of the first connection portion facing away from the second surface, and an orthographic projection of the recessed portion on a plane where the first surface is located overlaps with an orthographic projection of the cutting path on the plane.

9. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: After the groove is formed between the second connection part and the pin connected thereto, the size of the portion of the pin exposed toward the side of the first connection part connected thereto in the thickness direction of the pin is greater than or equal to half of the thickness of the pin.

10. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The lead frame includes a plurality of second connection portions, and the plurality of second connection portions are electrically connected.

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