Preparation method of metal interconnection structure
By forming the titanium nitride layer in two times in semiconductor manufacturing, the problem that the titanium nitride barrier layer cannot effectively block the titanium layer is solved, the occurrence of volcanic defects is avoided, and the electrical performance and yield are improved. This method is easy to implement.
Patent Information
- Application Number
- CN202411794960.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-06
- Publication Date
- 2025-02-28
AI Technical Summary
In the BEOL metal interconnection process of semiconductor manufacturing, the titanium nitride barrier layer cannot effectively block the titanium layer, resulting in the conductive interconnection structure forming volcanic defects, affecting the product electrical properties and reducing yield.
The titanium nitride layer is formed in two times. The first titanium nitride layer formed isolates the lower titanium layer before high temperature annealing and the second time before deposition of the metal layer, to prevent the titanium layer from being oxidized in contact with oxygen, and after high temperature annealing, a second titanium nitride layer is formed to fill the cracks.
The generation of volcanic defects is effectively avoided, the electrical performance of the metal interconnect structure is improved, and the product yield is ensured. This preparation method does not require the introduction of additional process equipment, which is easy to implement.
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Figure CN119542253A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a method for preparing a metal interconnection structure. Background Art
[0002] In the process of preparing integrated circuit devices, the semiconductor front-end process is first carried out to prepare various functional devices, such as transistors, resistors and capacitors, and then the back-end of line (BEOL) process is carried out to prepare metal wires to electrically lead out the various functional devices prepared by the front-end process. These metal wires that transmit signals are interconnects. Interconnects are important signal transmission carriers in integrated circuits.
[0003] In the metal interconnection through-holes in the integrated circuit manufacturing process, W is usually used to fill the metal interconnection holes to make the upper and lower conductive layers electrically connected. At present, in the BEOL metal interconnection process of semiconductor manufacturing, a Ti / TiN / W conductive interconnection structure is generally used. In the Ti / TiN / W structure, Ti is used as an adhesion layer and TiN is used as a barrier layer. Since W is deposited using a metal-organic chemical vapor deposition (MOCVD) process, its reaction gas contains F elements, such as the commonly used WF6 gas. WF6 gas and Ti are prone to violent reactions, WF6+Ti→W+TiF3, which will form volcano-shaped defects. Therefore, when the TiN barrier layer does not effectively block the Ti adhesion layer, a volcano-shaped defect will be formed on the conductive interconnection structure. The volcano-shaped defect will form a pore in the conductive interconnection structure after the subsequent planarization process. In severe cases, the pore will expose the lower structure, thereby affecting the electrical properties of the product and reducing the yield. Summary of the invention
[0004] In view of the shortcomings of the prior art described above, an object of the present invention is to provide a method for preparing a metal interconnect structure, which is used to solve the problem that in the prior art, in the metal interconnect structure using titanium as an adhesion layer, titanium nitride as a barrier layer and a metal layer as a connecting metal wire in the BEOL metal interconnect process of semiconductor manufacturing, the titanium nitride barrier layer cannot effectively block the Ti adhesion layer, resulting in the formation of volcano-shaped defects in the conductive interconnect structure, thereby forming pores after the subsequent planarization process, affecting the electrical properties of the product and resulting in a reduced yield.
[0005] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a metal interconnect structure, the method comprising:
[0006] Providing a substrate, wherein a silicon layer is exposed in a preset area on the surface of the substrate;
[0007] forming a dielectric layer on the surface of the substrate;
[0008] forming grooves and / or through holes in the dielectric layer, wherein the grooves and / or through holes expose the surface of the silicon layer;
[0009] forming a titanium layer and a first titanium nitride layer in sequence on the surface of the dielectric layer and the surface of the groove and / or through hole, wherein the first titanium nitride layer completely covers the titanium layer;
[0010] Performing a high temperature annealing process on the substrate formed with the titanium layer and the first titanium nitride layer, so that a portion of the titanium layer reacts with the silicon layer to form a metal silicide layer;
[0011] forming a second titanium nitride layer on the surface of the first titanium nitride layer;
[0012] Depositing a metal layer on the surface of the second titanium nitride layer, wherein the metal layer at least fills the grooves and / or through holes; and
[0013] The metal layer, the second titanium nitride layer, the first titanium nitride layer and the titanium layer are planarized to obtain a metal interconnection structure.
[0014] Optionally, during high-temperature annealing of the substrate on which the titanium layer and the first titanium nitride layer are formed, cracks are generated between the titanium layer and the first titanium nitride layer due to stress release.
[0015] Optionally, the thickness of the first titanium nitride layer is
[0016] Optionally, a DMOS semiconductor device is formed in the substrate.
[0017] Optionally, the thickness of the titanium layer is The thickness of the first titanium nitride layer is The thickness of the second titanium nitride layer is
[0018] Optionally, the metal layer is a tungsten metal layer; and the metal layer is deposited on the surface of the second titanium nitride layer using a MOCVD process.
[0019] Furthermore, the deposition source gas used to deposit the metal layer on the surface of the second titanium nitride layer using the MOCVD process includes WF6.
[0020] Optionally, the dielectric layer is a single-layer structure of any one of a SiO2 layer, a SiN layer and a SiNO layer, or a stacked structure of at least two layers.
[0021] Optionally, the titanium layer is formed by a sputtering process, and the first titanium nitride layer and the second titanium nitride layer are formed by an MOCVD process.
[0022] Optionally, the metal layer, the second titanium nitride layer, the first titanium nitride layer and the titanium layer are planarized by a CMP process or a dry etching process.
[0023] As described above, the preparation method of the metal interconnect structure of the present invention forms the titanium nitride layer twice, the first time before high-temperature annealing to form a metal silicide layer, and the second time before depositing the metal layer. The formed first titanium nitride layer can better isolate the underlying titanium layer to prevent the titanium layer from contacting oxygen and being oxidized. Although the first titanium nitride layer may still crack during the high-temperature annealing process, a second titanium nitride layer is continuously formed on the surface of the first titanium nitride layer after the high-temperature annealing and before the metal layer deposition process. The second titanium nitride layer can effectively fill the cracks formed in the first titanium nitride layer, so that during the metal layer deposition process, the deposition source gas of the deposited metal layer can be effectively prevented from contacting the titanium layer below the titanium nitride layer, thereby reducing or even avoiding the generation of volcano-shaped defects, thereby effectively improving the electrical performance of the subsequently formed metal interconnect structure and ensuring the product yield. In addition, the preparation method does not require the introduction of additional process equipment and is easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 The cross-sectional structure diagram of a titanium layer and a titanium nitride layer formed during the preparation process of an exemplary tungsten metal interconnect structure is shown.
[0025] Figure 2 The cross-sectional structure diagram of a metal silicide layer formed during the preparation process of an exemplary tungsten metal interconnect structure is shown.
[0026] Figure 3 The figure shows a schematic cross-sectional structure of a tungsten metal layer formed during the preparation process of an exemplary tungsten metal interconnect structure.
[0027] Figure 4 The top view SEM image of the structure of a volcano defect generated after a tungsten metal layer is formed during the preparation process of an exemplary tungsten metal interconnect structure.
[0028] Figure 5 Display as Figure 4 Distribution of the volcano defects across the wafer.
[0029] Figure 6 and Figure 7 The cross-sectional structure schematic diagram shows planarization of a formed tungsten metal interconnect structure during the preparation process of an exemplary tungsten metal interconnect structure.
[0030] Figure 8 Display as Figure 6 TEM image of the cross-sectional structure.
[0031] Fig. 9 Show as pair Figure 6EDX spectrum of the structure subjected to EDX analysis.
[0032] Fig.10 Display as Figure 6 Distribution of void defects in the wafer.
[0033] Figures 11 to 18 It is a schematic diagram of the cross-sectional structure of each step in the method for preparing the metal interconnect structure of the present invention.
[0034] Fig.19 The figure shows the distribution of void defects on the entire wafer generated by the tungsten metal interconnect structure prepared by the method for preparing the metal interconnect structure of the present invention.
[0035] Component number description
[0036] 10 Base
[0037] 100 Silicon Layer
[0038] 101 Dielectric Layer
[0039] 102 Grooves and / or through holes
[0040] 103 Titanium layer
[0041] 104 first titanium nitride layer
[0042] 105 Metal silicide layer
[0043] 106 second titanium nitride layer
[0044] 107 Metal Layer
[0045] 11 Metal Interconnect Structure
[0046] 12 Rift
[0047] 20 Silicon layer
[0048] 21 Dielectric layer
[0049] 22 Titanium layer
[0050] 23 Titanium nitride layer
[0051] 24 Metal silicide layer
[0052] 25 Tungsten metal layer
[0053] 26 Volcano-shaped defect
[0054] 27 Rift
[0055] 28 Tungsten Metal Interconnect Structure
[0056] 29 Porosity DETAILED DESCRIPTION
[0057] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0058] See also Figures 1 to 19 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0059] As described in the background technology, in the BEOL metal interconnection process of semiconductor manufacturing, a Ti / TiN / W conductive interconnection structure is currently used. During the preparation process, W is deposited using the MOCVD process, and its reaction gas is generally selected to contain the element F. The element F and Ti react violently to form volcano-shaped defects. After the subsequent planarization process, the volcano-shaped defects will form pores in the conductive interconnection structure. In severe cases, the pores will expose the underlying structure, thereby affecting the electrical properties of the product and reducing the yield. The inventors have conducted an in-depth analysis of this phenomenon, such as Figures 1 to 10 FIG. 1 is a diagram showing a conventional example of a tungsten metal interconnect structure preparation process:
[0060] like Figure 1 As shown, a dielectric layer 21 is first formed on the surface of the silicon layer 20, and a through hole is formed in the dielectric layer 21 to expose the surface of the silicon layer 20;
[0061] like Figure 1 As shown, a titanium layer 22 and a titanium nitride layer 23 are then deposited on the surface of the dielectric layer 21 and the surface of the through hole in sequence;
[0062] like Figure 2 As shown, the titanium layer 22 is then subjected to a high temperature annealing process to react with the silicon layer 20 to form a low-resistance metal silicide layer 24; in this step, the titanium nitride layer 23 may crack at the step due to stress release caused by the high temperature annealing process, as shown in FIG. Figure 2 A crack 27 is generated at the step, and the crack 27 exposes the underlying titanium layer 22. Figure 2 Only one crack 27 is shown in the figure, and in practice, cracks 27 may also be generated in other places due to stress release;
[0063] like Figure 3As shown, the MOCVD process is then used to fill the through hole, and the deposited tungsten metal layer 25 fills the through hole. Since the surface of the titanium nitride layer 23 has cracks 27 that expose the surface of the titanium layer 22, in this step, the F-containing gas will enter the surface of the titanium layer 22 and react violently with it, forming a volcano-shaped defect 26, as shown in FIG. Figure 4 In the SEM image, it can be seen that a volcano-shaped defect 26 is formed on the surface of the wafer, and due to the large warping of the wafer edge, as shown in FIG. Figure 5 As shown, the density of the volcano-shaped defects 26 formed at the edge of the wafer is higher;
[0064] like Figure 6 As shown, the titanium layer 22, the titanium nitride layer 23 and the tungsten metal layer 25 are then planarized to obtain a tungsten metal interconnect structure; due to the presence of the volcano-shaped defect 26, the volcano-shaped defect 26 is opened during the planarization process to form a pore 29, as shown in FIG. Figure 8 and Fig. 9 As shown, a pore 29 is formed at the step of the tungsten metal interconnect structure, and the pore 29 may affect the electrical properties of the tungsten metal interconnect structure. Figure 7 As shown, the pores 29 will expose the underlying structure and even create a short circuit risk, affecting the electrical performance and yield of the device. Fig.10 As shown, based on Figure 5 The density of the volcano-shaped defects 26 formed at the edge of the wafer is higher, so after planarization, the distribution density of the pores 29 is also higher at the edge of the wafer.
[0065] As the inventors' above research and analysis show, the reason for the volcano-shaped defect 26 is that during the high-temperature annealing process to form a low-resistance metal silicide layer, titanium nitride will release stress at high temperature to form cracks, exposing the surface of the underlying titanium layer, resulting in a violent reaction between the fluorine-containing gas and the titanium layer during the MOCVD process to form a volcano-shaped defect 26. Based on this, this embodiment proposes a method for preparing a metal interconnect structure from the perspective of avoiding contact between the fluorine-containing gas and the titanium layer during the MOCVD process, including the following steps:
[0066] S1, providing a substrate, wherein a silicon layer is exposed in a preset area on the surface of the substrate;
[0067] S2, forming a dielectric layer on the surface of the substrate, and forming grooves and / or through holes in the dielectric layer, wherein the grooves and / or through holes expose the surface of the silicon layer;
[0068] S3, forming a titanium layer and a first titanium nitride layer on the surface of the dielectric layer and the surface of the groove and / or through hole in sequence, wherein the first titanium nitride layer completely covers the titanium layer;
[0069] S4, performing a high temperature annealing process on the substrate formed with the titanium layer and the first titanium nitride layer, so that a portion of the titanium layer reacts with the silicon layer to form a metal silicide layer;
[0070] S5, forming a second titanium nitride layer on the surface of the first titanium nitride layer;
[0071] S6, depositing a metal layer on the surface of the second titanium nitride layer, wherein the metal layer at least fills the grooves and / or through holes;
[0072] S7, planarizing the metal layer, the second titanium nitride layer, the first titanium nitride layer and the titanium layer to obtain a metal interconnection structure.
[0073] The preparation method of the metal interconnect structure of the present embodiment forms the titanium nitride layer twice, the first time before high-temperature annealing to form the metal silicide layer, and the second time before depositing the metal layer. The formed first titanium nitride layer can better isolate the underlying titanium layer to prevent the titanium layer from contacting oxygen and being oxidized. Although the first titanium nitride layer may still crack during the high-temperature annealing process, a second titanium nitride layer is continuously formed on the surface of the first titanium nitride layer after the high-temperature annealing and before the metal layer deposition process. The second titanium nitride layer can effectively fill the cracks formed in the first titanium nitride layer, so that during the metal layer deposition process, the deposition source gas of the deposited metal layer can be effectively prevented from contacting the titanium layer under the titanium nitride layer, thereby reducing or even avoiding the generation of volcano-shaped defects, thereby effectively improving the electrical performance of the subsequently formed metal interconnect structure and ensuring the product yield. In addition, the preparation method does not require the introduction of additional process equipment and is easy to implement.
[0074] The method for preparing the metal interconnect structure of this embodiment is described in detail below with reference to the specific drawings.
[0075] like Fig.11 As shown, firstly, step S1 is performed to provide a substrate 10, wherein a silicon layer 100 is exposed in a preset area on the surface of the substrate 10; the silicon layer 100 is subsequently used as a contact layer for leading out a metal interconnect structure circuit.
[0076] The size of the base 10 is set as required, such as the common 6 inches, 8 inches, 12 inches, etc.; in addition, the thickness of the base 10 is also set as required.
[0077] As an example, a device structure prepared by a front end of line process, such as a DMOS device structure, is formed in the substrate 10 .
[0078] The material of the substrate 10 can be any substrate material suitable for preparing semiconductor devices known in the art, for example, it can be at least one of the following materials: silicon, germanium, red phosphorus, germanium silicon, silicon carbide, carbon germanium silicon, indium arsenide, gallium arsenide, indium phosphide or other III / V compound semiconductors, and can also include a multilayer structure formed by these semiconductors, or silicon on insulator, stacked silicon on insulator, stacked silicon germanium on insulator, silicon germanium on insulator and germanium on insulator, or it can also be a double-sided polished silicon wafer, or it can be a ceramic substrate such as aluminum oxide, quartz or glass substrate, etc., which is selected according to actual needs. In this embodiment, the substrate 10 is selected as a silicon substrate.
[0079] It should be noted here that, for ease of understanding, the cross-sectional structural schematic diagrams in the subsequent process are all based on Fig.11 The diagram is illustrated using area A in FIG.
[0080] like Fig.13 As shown, step S2 is then performed to form a dielectric layer 101 on the surface of the substrate, and to form grooves and / or through holes 102 in the dielectric layer 101 , wherein the grooves and / or through holes 102 expose the surface of the silicon layer 100 .
[0081] As a specific example, the method of forming the groove and / or through hole 102 includes: Fig.12 As shown, a dielectric layer 101 is first deposited on the substrate surface, including but not limited to any suitable deposition process, such as a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, etc.; Fig.13 As shown, a photoresist layer is then coated on the dielectric layer 101 and patterned by photolithography to form a patterned photoresist layer; then the dielectric layer 101 is etched based on the patterned photoresist layer to form the grooves and / or through holes 102; finally, the patterned photoresist layer is removed.
[0082] As an example, the material of the dielectric layer 101 is generally a low-K material or an ultra-low-K material, such as a SiO2 material, a SiN material, or a SiNO material. The structure of the dielectric layer 101 can be a single-layer structure of a single material, or a stacked structure of different materials, which is selected according to actual conditions. For example, it can be a single-layer structure of a SiO2 layer, a SiN layer, or a SiNO layer, or a stacked structure of at least two layers of a SiO2 layer, a SiN layer, and a SiNO layer.
[0083] like Fig.14As shown, step S3 is then performed to sequentially form a titanium layer 103 and a first titanium nitride layer 104 on the surface of the dielectric layer 101 and the surface of the groove and / or through hole 102, wherein the first titanium nitride layer 104 completely covers the titanium layer 103. Here, the surface of the groove and / or through hole 102 includes the sidewall and bottom wall of the groove and / or through hole 102.
[0084] As an example, the titanium layer 103 is deposited by a sputtering process, and the first titanium nitride layer 104 is formed by a MOCVD process. However, this is not limited thereto, and other suitable deposition processes are also possible, such as an ALD process.
[0085] In this embodiment, the titanium layer 103 serves as both an adhesion layer and a metal layer for subsequently forming a metal silicide layer during the preparation of the entire metal interconnect structure. Therefore, the thickness of the titanium layer 103 is relatively thicker than that of the titanium nitride layer, and is generally selected to be
[0086] The main function of the first titanium nitride layer 104 in this step is to achieve good coverage of the titanium layer 103 to prevent the titanium layer 103 from contacting the external oxygen-containing environment. Since the first titanium nitride layer 104 may crack during the subsequent high-temperature annealing process, the thickness of the first titanium nitride layer 104 in this step should not be too thick or too thin. The preferred thickness range is Better for
[0087] like Fig.15 As shown, step S4 is then performed to perform a high temperature annealing process on the substrate 10 formed with the titanium layer 103 and the first titanium nitride layer 104 , so that a portion of the titanium layer 103 reacts with the silicon layer 100 to form a metal silicide layer 105 .
[0088] The silicon layer 100 is exposed at the bottom of the groove and / or through hole 102. Therefore, in this step, the titanium layer 103 formed on the bottom of the groove and / or through hole 102 will react with the silicon layer 100 to form a low-resistance metal silicide layer 105, so that the subsequently formed metal interconnect structure and the silicon layer 100 can achieve ohmic contact. In addition, the titanium layer 103 formed on the sidewall of the groove and / or through hole 102 is mainly used as an adhesion layer. Finally, in this step, the first titanium nitride layer 104 may also crack in some crack-prone areas due to stress release, resulting in cracks 12, such as Fig.12 Cracks 12 are generated at the steps at the tops of the trenches and / or vias 102 .
[0089] The specific process parameters for the high temperature annealing of the titanium layer 103 and the silicon layer 100 adopt the existing conventional silicide process parameters, which are selected according to actual conditions and are not excessively restricted here.
[0090] like Fig.16 As shown, step S5 is then performed to form a second titanium nitride layer 106 on the surface of the first titanium nitride layer 104 .
[0091] As an example, the second titanium nitride layer 106 is formed by using a MOCVD process, but it is not limited thereto, and other suitable deposition processes are also possible, such as an ALD process.
[0092] In this step, the second titanium nitride layer 106 mainly acts as a barrier layer and can also repair the cracks 12 formed in step S4, thereby improving the barrier effect of the titanium nitride layer and reducing or even avoiding the contact between the deposition source gas and the titanium layer 102 during the subsequent metal layer deposition process.
[0093] The thickness of the second titanium nitride layer 106 can be flexibly adjusted according to actual needs. In this embodiment, the thickness of the first titanium nitride layer 104 can be selected to be the same as the thickness of the second titanium nitride layer 106. For example, when the thickness range of the first titanium nitride layer 104 is selected to be and better yet When the thickness of the second titanium nitride layer 106 is also selected to be and better yet
[0094] like Fig.17 As shown, step S6 is then performed to deposit a metal layer 107 on the surface of the second titanium nitride layer 106 , wherein the metal layer 107 at least fills the grooves and / or through holes 102 .
[0095] As a preferred example, the metal layer 107 is a tungsten metal layer. In this step, the MOCVD process is used to deposit the tungsten metal layer on the surface of the second titanium nitride layer 106. The MOCVD process generally uses a tungsten-containing deposition source gas to deposit the tungsten metal layer. However, since the second titanium nitride layer 106 has effectively repaired the cracks 12 formed in the first titanium nitride layer 104, when the metal layer 107 of tungsten material is formed by reaction in this step, the reaction source gas (i.e., reaction precursor), such as WF6 gas, cannot contact the titanium layer 102, so that the volcano-shaped defects can be effectively suppressed. Based on this improvement mechanism, those skilled in the art can know that the metal layer 107 can also be other metal materials similar to the tungsten metal deposition process. If the precursor gas used in the deposition process of the metal material comes into contact with the titanium layer 102, it will react violently to produce volcano-shaped defects. Fig.18 As shown, step S7 is finally performed to planarize the metal layer 107 , the second titanium nitride layer 106 , the first titanium nitride layer 104 and the titanium layer 103 to obtain a metal interconnect structure 11 .
[0096] As an example, the metal layer 107 , the second titanium nitride layer 106 , the first titanium nitride layer 104 and the titanium layer 103 may be planarized by using a chemical mechanical polishing (CMP) process or a dry etching process.
[0097] contrast Fig.10 and Fig.19 It can be seen that after this step, the defect of the gaps on the entire wafer is greatly reduced.
[0098] In summary, the present invention provides a method for preparing a metal interconnect structure, wherein the titanium nitride layer is formed twice, the first time before high-temperature annealing to form a metal silicide layer, and the second time before depositing a metal layer, the first titanium nitride layer formed can better isolate the underlying titanium layer to prevent the titanium layer from contacting oxygen and being oxidized, although the first titanium nitride layer may still crack during the high-temperature annealing process, but after the high-temperature annealing and before the metal layer deposition process, the second titanium nitride layer continues to form on the surface of the first titanium nitride layer, the second titanium nitride layer can effectively fill the cracks formed in the first titanium nitride layer, so that during the metal layer deposition process, the deposition source gas of the deposited metal layer can be effectively prevented from contacting the titanium layer under the titanium nitride layer, thereby reducing or even avoiding the generation of volcanic defects, thereby effectively improving the electrical performance of the subsequent metal interconnect structure and ensuring the product yield; in addition, the preparation method does not require the introduction of additional process equipment and is easy to implement. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.
[0099] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for preparing a metal interconnect structure, characterized in that: The preparation method comprises: Providing a substrate, wherein a silicon layer is exposed in a preset area on the surface of the substrate; forming a dielectric layer on the surface of the substrate; forming grooves and / or through holes in the dielectric layer, wherein the grooves and / or through holes expose the surface of the silicon layer; forming a titanium layer and a first titanium nitride layer in sequence on the surface of the dielectric layer and the surface of the groove and / or through hole, wherein the first titanium nitride layer completely covers the titanium layer; Performing a high temperature annealing process on the substrate formed with the titanium layer and the first titanium nitride layer, so that a portion of the titanium layer reacts with the silicon layer to form a metal silicide layer; forming a second titanium nitride layer on the surface of the first titanium nitride layer; Depositing a metal layer on the surface of the second titanium nitride layer, wherein the metal layer at least fills the grooves and / or through holes; and, The metal layer, the second titanium nitride layer, the first titanium nitride layer and the titanium layer are planarized to obtain a metal interconnection structure.
2. The method for preparing a metal interconnect structure according to claim 1, characterized in that: During the high-temperature annealing process of the substrate on which the titanium layer and the first titanium nitride layer are formed, cracks are generated between the titanium layer and the first titanium nitride layer due to stress release.
3. The method for preparing a metal interconnect structure according to claim 1, characterized in that: The thickness of the first titanium nitride layer is 4. The method for preparing a metal interconnect structure according to claim 1, characterized in that: A DMOS semiconductor device is formed in the substrate.
5. The method for preparing a metal interconnect structure according to claim 1, characterized in that: The thickness of the titanium layer is The thickness of the first titanium nitride layer is The thickness of the second titanium nitride layer is 6. The method for preparing a metal interconnect structure according to claim 1, characterized in that: The metal layer is a tungsten metal layer; The metal layer is deposited on the surface of the second titanium nitride layer by using a MOCVD process.
7. The method for preparing a metal interconnect structure according to claim 6, characterized in that: The metal layer is deposited on the surface of the second titanium nitride layer using an MOCVD process, and the deposition source gas used includes WF6.
8. The method for preparing a metal interconnect structure according to claim 1, characterized in that: The dielectric layer is a single-layer structure of any one of a SiO2 layer, a SiN layer and a SiNO layer, or a stacked-layer structure of at least two layers.
9. The method for preparing a metal interconnect structure according to claim 1, characterized in that: The titanium layer is formed by a sputtering process, and the first titanium nitride layer and the second titanium nitride layer are formed by an MOCVD process.
10. The method for preparing a metal interconnect structure according to claim 1, characterized in that: The metal layer, the second titanium nitride layer, the first titanium nitride layer and the titanium layer are planarized by using a CMP process or a dry etching process.