Packaging structure and packaging method

Abstract

The invention discloses a packaging structure and a packaging method, and the packaging structure comprises a substrate which comprises a bonding surface; the first device chip is bonded on the bonding surface of the substrate and is electrically connected with the substrate, the first device chip comprises a first chip front surface and a first chip back surface which are opposite to each other, the first chip front surface and the bonding surface are oppositely arranged, and power is supplied to devices of the first device chip through the first chip back surface; and the second device chip is bonded on the first device chip and electrically connected with the first device chip, the second device chip comprises a second chip front surface and a second chip back surface which are opposite to each other, and the second chip front surface and the first chip back surface are oppositely arranged. According to the invention, the power supply of the device of the first device chip is realized through the back surface of the first chip, the circuit is simplified, and the integration level of the packaging structure is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a packaging structure and a packaging method. Background Art

[0002] Conventional chip manufacturing technologies are being pushed to their limits in terms of the size of a single chip. However, applications are eager to use the latest technology to achieve the capabilities of large-scale integrated circuits, and achieving high-speed and small-volume interconnections between chips is a major challenge.

[0003] One current solution is to use a smaller integrated circuit of a silicon bridge (Si Bridge) chip embedded in a silicon substrate to interconnect chips through the silicon bridge chip, thereby providing a heterogeneous chip package.

[0004] However, the current packaging structure is relatively complex, and the integration level between chips still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a packaging structure and a packaging method, thereby improving the integration of the packaging structure.

[0006] To solve the above problems, the present invention provides a packaging structure, including: a substrate, including a bonding surface; a first device chip, bonded to the bonding surface of the substrate and electrically connected to the substrate, the first device chip including a first chip front side and a first chip back side opposite to each other, the first chip front side and the bonding surface are arranged opposite to each other, and the device of the first device chip is powered by the back side of the first chip; a second device chip, bonded to the first device chip and electrically connected to the first device chip, the second device chip including a second chip front side and a second chip back side opposite to each other, and the second chip front side and the back side of the first chip are arranged opposite to each other.

[0007] Optionally, the first device chip includes a backside interconnection layer located on the back side of the first chip, the backside interconnection layer is electrically connected to the second device chip, and the backside interconnection layer is also electrically connected to the device of the first device chip.

[0008] Optionally, the first device chip further includes a substrate and a device layer on the substrate, wherein the device layer is located on a surface of the substrate facing the front side of the first chip; and the backside interconnection layer is located on a surface of the substrate facing the back side of the first chip.

[0009] Optionally, a first interconnect structure located on the front side of the first chip is formed in the first device chip, and a backside interconnect layer of the first device chip is electrically connected to the substrate through the first interconnect structure.

[0010] Optionally, a second interconnect structure located on the front side of the second chip is formed in the second device chip, and the devices of the second device chip are electrically connected to the first device chip through the second interconnect structure.

[0011] Optionally, the device of the second device chip is electrically connected to the substrate through the first device chip.

[0012] Optionally, the packaging structure further includes: a conductive bump, which is located between the first device chip and the substrate and electrically connects the first device chip and the substrate.

[0013] Optionally, the packaging structure further includes: a sealing layer filling the gaps between adjacent conductive bumps and covering the conductive bumps.

[0014] Correspondingly, an embodiment of the present invention also provides a packaging method, including: providing a first device chip, including a first chip front side and a first chip back side opposite to each other; providing a second device chip, including a second chip front side and a second chip back side opposite to each other; bonding the first device chip to the second device chip, and electrically connecting them to each other, with the second chip front side and the first chip back side opposite to each other; providing a substrate, including a bonding surface; after bonding the first device chip to the second device chip, bonding the first device chip to the substrate, and electrically connecting it to the substrate, with the first chip front side and the bonding surface opposite to each other, and the device of the first device chip is powered through the back side of the first chip.

[0015] Optionally, the step of bonding the first device chip to the second device chip includes: providing a carrier substrate; bonding the first device chip to the carrier substrate with the front side of the first chip facing the carrier substrate; after bonding the first device chip to the carrier substrate, bonding the first device chip to the second device chip; after bonding the first device chip to the second device chip, removing the carrier substrate.

[0016] Optionally, after the first device chip is bonded to the carrier substrate and before the first device chip is bonded to the second device chip, the packaging method further includes: performing back side thinning treatment on the first device chip through the back side of the first chip; after the back side thinning treatment, forming a back side interconnection layer on the back side of the first chip, the back side interconnection layer being electrically connected to the device of the first device chip; in the step of bonding the first device chip to the second device chip, the back side interconnection layer is electrically connected to the second device chip.

[0017] Optionally, in the step of providing a first device chip, the first device chip includes a substrate and a device layer located on the substrate, the substrate is located on the back side of the first chip, and the device layer is located on the front side of the first chip; in the step of performing back thinning on the first device chip through the back side of the first chip, a portion of the thickness of the substrate is removed; in the step of forming a back interconnection layer on the back side of the first chip, a back interconnection layer is formed on the substrate, and the back interconnection layer is located on the surface of the substrate facing the back side of the first chip.

[0018] Optionally, in the step of providing a first device chip, a first interconnection structure located on the front side of the first chip is formed in the first device chip; in the step of forming a back interconnection layer on the back side of the first chip, the back interconnection layer is electrically connected to the first interconnection structure; in the step of bonding the first device chip to a substrate, the back interconnection layer of the first device chip is electrically connected to the substrate through the first interconnection structure.

[0019] Optionally, in the step of providing a second device chip, a second interconnect structure located on the front side of the second chip is formed in the second device chip, and the second interconnect structure is electrically connected to the device of the second device chip; in the step of bonding the first device chip to the second device chip, the device of the second device chip is electrically connected to the first device chip through the second interconnect structure.

[0020] Optionally, in the step of bonding the first device chip to the substrate, the device of the second device chip is electrically connected to the substrate through the first device chip.

[0021] Optionally, the step of bonding the first device chip to the substrate includes: forming a conductive bump on the front side of the first device chip, or on a bonding surface; bonding the first device chip to the substrate using the conductive bump, wherein the conductive bump electrically connects the first device chip to the substrate.

[0022] Optionally, after the first device chip is bonded to the substrate, the packaging method further includes: filling a sealing layer in the gaps between adjacent conductive bumps, wherein the sealing layer covers the conductive bumps.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0024] An embodiment of the present invention provides a packaging structure, wherein a first device chip is bonded to a bonding surface of a substrate and is electrically connected to the substrate, the first device chip comprises a first chip front side and a first chip back side opposite to each other, the first chip front side is arranged opposite to the bonding surface, and the device of the first device chip is powered through the back side of the first chip, and a second device chip is bonded to the first device chip and is electrically connected to the first device chip, the second device chip comprises a second chip front side and a second chip back side opposite to each other, the second chip front side is arranged opposite to the back side of the first chip; in the embodiment of the present invention, the first device chip is bonded to the substrate, and the device of the first device chip is powered through the back side of the first chip, which is conducive to simplifying the circuit and improving the integration of the packaging structure, and the second device chip is bonded to the first device chip, which increases the total thickness of the structure when the first device chip is bonded to the substrate, which is conducive to increasing the bonding strength of the first device chip, thereby facilitating the solution of bonding the first device chip to the substrate for back power supply, and realizing the electrical connection between the first device chip and the second device chip at the same time, which is conducive to increasing the diversity of the circuit structure and improving the applicability of the packaging structure.

[0025] The embodiment of the present invention provides a packaging method, providing a first device chip, including a first chip front side and a first chip back side opposite to each other, providing a second device chip, including a second chip front side and a second chip back side opposite to each other, bonding the first device chip to the second device chip and electrically connecting them to each other, the second chip front side and the first chip back side opposite to each other, providing a substrate, including a bonding surface, bonding the first device chip to the substrate and electrically connecting them to the substrate after bonding the first device chip to the second device chip, the first chip front side and the bonding surface opposite to each other, and the device of the first device chip is powered by the back side of the first chip; in the embodiment of the present invention, the first device chip is bonded to the substrate, and the power supply to the device of the first device chip is realized by the back side of the first chip, which is conducive to simplifying the circuit and improving the integration of the packaging structure, and the second device chip is bonded to the first device chip, which increases the total thickness of the structure when the first device chip is bonded to the substrate, which is conducive to increasing the bonding strength of the first device chip, thereby facilitating the solution of bonding the first device chip to the substrate for back power supply, and realizing the electrical connection between the first device chip and the second device chip at the same time, which is conducive to increasing the diversity of the circuit structure and improving the applicability of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a structural schematic diagram of an embodiment of a packaging structure of the present invention;

[0027] Figures 2 to 11 It is a schematic structural diagram corresponding to each step in an embodiment of a packaging method of the present invention. DETAILED DESCRIPTION

[0028] As can be seen from the background technology, usually only the front side of the chip is electrically connected to the outside of the two opposite sides of the chip. At present, the back side power delivery network (BSPDN) technology is developed, that is, an interconnection pad will also be formed on the back side of the chip for electrical connection with the outside, for example, as described in document 10.1109 / TED.2019.2954301. However, there is currently no method to electrically lead out the back side of the chip to achieve electrical connection between the front and back sides of the chip, making it difficult to improve the packaging integration.

[0029] In order to solve the technical problem, an embodiment of the present invention provides a packaging structure, including: a substrate, including a bonding surface; a first device chip, bonded to the bonding surface of the substrate and electrically connected to the substrate, the first device chip including a first chip front side and a first chip back side opposite to each other, the first chip front side and the bonding surface are arranged opposite to each other, and the device of the first device chip is powered by the back side of the first chip; a second device chip, bonded to the first device chip and electrically connected to the first device chip, the second device chip including a second chip front side and a second chip back side opposite to each other, and the second chip front side and the back side of the first chip are arranged opposite to each other.

[0030] In an embodiment of the present invention, a first device chip is bonded to a substrate, and power is supplied to the device of the first device chip through the back side of the first chip, which is beneficial to simplifying the circuit and improving the integration of the packaging structure. Moreover, a second device chip is bonded to the first device chip, which increases the total thickness of the structure when the first device chip is bonded to the substrate, and is beneficial to increasing the bonding strength of the first device chip, thereby facilitating the solution of bonding the first device chip to the back side of the substrate for power supply, and at the same time realizing the electrical connection between the first device chip and the second device chip, which is beneficial to increasing the diversity of the circuit structure and improving the applicability of the packaging structure.

[0031] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] Figure 1 It is a structural schematic diagram of an embodiment of a packaging structure of the present invention.

[0033] The packaging structure includes: a substrate 100, including a bonding surface 100a; a first device chip 200, bonded to the bonding surface 100a of the substrate 100 and electrically connected to the substrate 100, the first device chip 200 includes a first chip front side 200a and a first chip back side 200b opposite to each other, the first chip front side 200a and the bonding surface 100a are arranged opposite to each other, and the device of the first device chip 200 is powered by the first chip back side 200b; a second device chip 300, bonded to the first device chip 200 and electrically connected to the first device chip 200, the second device chip 300 includes a second chip front side 300a and a second chip back side 300b opposite to each other, and the second chip front side 300a and the first chip back side 200b are arranged opposite to each other.

[0034] The substrate 100 is used to provide a process operation basis for realizing the bonding of the first device chip 200 . Specifically, the bonding surface 100 a of the substrate 100 is a process operation platform.

[0035] In this embodiment, the substrate 100 includes an interconnection structure layer, and the exposed surface of the interconnection structure layer is a bonding surface 100a.

[0036] The interconnection structure layer is used to achieve bonding with the first device chip 200 , thereby achieving electrical connection with the first device chip 200 . The interconnection structure layer is also used to achieve electrical connection between the first device chip 200 and the outside.

[0037] In this embodiment, the interconnection structure layer is a redistribution structure. Specifically, the redistribution structure may include one or more redistribution layers. In this embodiment, the redistribution structure includes multiple redistribution layers as an example for description.

[0038] Specifically, in this embodiment, the substrate 100 is a packaging substrate, and the packaging substrate is a printed circuit board (PCB).

[0039] The first device chip 200 is used to be electrically connected to the substrate 100 to form a corresponding packaging structure to achieve corresponding functions.

[0040] In this embodiment, the first chip front side 200 a is bonded to the bonding surface 100 a and is electrically connected to the substrate 100 , thereby achieving electrical connection between the first chip front side 200 a and the substrate 100 .

[0041] In this embodiment, the devices of the first device chip 200 are powered through the first chip back side 200 b.

[0042] In this embodiment, the first device chip 200 is bonded to the substrate 100, and the power supply to the device of the first device chip 200 is realized through the back side 200b of the first chip, which is beneficial to simplify the circuit and improve the integration of the packaging structure.

[0043] Specifically, in the present embodiment, power is supplied to the device of the first device chip 200 through the back side 200b of the first chip, and signal electrical connection is made to the device of the first device chip 200 through the front side 200a of the first chip. Compared with the scheme in which both the power supply line and the signal line are electrically connected from the front side of the first chip of the first device chip, the present scheme is conducive to reducing the mutual interference between the power supply line and the signal line, and is conducive to making the power supply line electrically connected through the back side 200b of the first chip have a higher degree of freedom in design and a larger formation space, which is conducive to reducing the resistance of the power supply line, thereby reducing the probability of the voltage drop affecting the working performance of the device due to the excessive resistance of the power supply line, thereby improving the working performance of the device. At the same time, the signal line electrically connected through the front side 200a of the first chip also has a larger formation space, so that the device of the first device chip 200 achieves better working performance.

[0044] In this embodiment, the first device chip 200 includes a backside interconnection layer 220 located on the backside 200 b of the first chip. The backside interconnection layer 220 is electrically connected to the second device chip 300 and is also electrically connected to the devices of the first device chip 200 .

[0045] The backside interconnection layer 220 is used to realize electrical connection between the devices in the first device chip 200 and the outside through the first chip backside 200 b . The backside interconnection layer 220 is also used to realize electrical connection between the second device chip 300 and the outside.

[0046] It should be noted that, in this embodiment, a through-silicon-via (TSV) structure is used to electrically connect the backside interconnect layer 220 to the device of the first device chip 200 , which is beneficial for making electrical transmission more direct and rapid.

[0047] In this embodiment, the first device chip 200 further includes a substrate 210 and a device layer 230 located on the substrate 210 . The device layer 230 is located on a surface of the substrate 210 facing the first chip front side 200 a .

[0048] The device layer 230 is used to form the devices of the first device chip 200. The device layer 230 is located on the surface of the substrate 210 facing the front side 200a of the first chip, leaving space for forming the interconnection layer 220 on the other side of the substrate 210, so that the back interconnection layer 220 formed on the other side of the substrate 210 can face the back side 200b of the first chip, thereby realizing back power supply to the devices in the device layer 230.

[0049] Specifically, in this embodiment, in the process of packaging structure, the first device chip 200 includes a substrate 210 and a device layer 230 located on the substrate 210, the substrate 210 is located on the back side 200b of the first chip, and the device layer 210 is located on the front side 200a of the first chip, then the substrate 210 can provide a process platform for the formation of the device layer 230, the substrate 210 also provides a process platform for forming a back interconnection layer 220, the substrate 210 is subjected to back thinning treatment, a portion of the thickness of the substrate 210 is removed through the back side 200b of the first chip, and after back thinning, a back interconnection layer 220 is formed on the remaining substrate 210.

[0050] Accordingly, in this embodiment, the backside interconnection layer 220 is located on the surface of the substrate 210 facing the backside 200 b of the first chip.

[0051] In this embodiment, a first interconnection structure located on the first chip front side 200 a is formed in the first device chip 200 , and a backside interconnection layer 220 of the first device chip 200 is electrically connected to the substrate 100 via the first interconnection structure.

[0052] The first interconnect structure is used to penetrate the substrate 210 and electrically connect with the back interconnect layer 220, so as to realize electrical connection between the back interconnect layer 220 and the outside. The first interconnect structure is located on the side of the front side 200a of the first chip, and the first interconnect structure can be electrically connected to the substrate 100 through the front side 200a of the first chip, so that the back interconnect layer 220 is electrically connected to the substrate 100 through the first interconnect structure.

[0053] In this embodiment, the back interconnect layer 220 is electrically connected to the first chip front side 200a of the first device chip 200 through the first interconnect structure wiring, and then electrically connected to the substrate 100 through the first chip front side 200a. The wiring of the first interconnect structure is conducive to making the electrical transmission more accurate.

[0054] It should be noted that, in the present embodiment, the first interconnection structure includes a through-silicon-via (TSV) structure, which is beneficial for making electrical transmission more direct and rapid.

[0055] In this embodiment, the material of the first interconnect structure is a metal material, for example, one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride.

[0056] The second device chip 300 is used to be electrically connected to the first device chip 200 to realize the basic circuit structure between the second device chip 300 and the first device chip 200. The second device chip 300 is also used to be electrically connected to the substrate 100 to realize the electrical connection between the second device chip 300 and the outside.

[0057] In this embodiment, the second device chip 300 is bonded to the first device chip 200, which increases the total thickness of the structure when the first device chip 200 is bonded to the substrate 100, which is beneficial to increase the bonding strength of the first device chip 200, thereby facilitating the implementation of a solution for bonding the first device chip 200 to the substrate 100 for back-side power supply, while achieving electrical connection between the first device chip 200 and the second device chip 300, which is beneficial to increasing the diversity of the circuit structure and improving the applicability of the packaging structure.

[0058] In this embodiment, a second interconnect structure located on the second chip front side 300 a is formed in the second device chip 300 , and the devices of the second device chip 300 are electrically connected to the first device chip 200 via the second interconnect structure.

[0059] The second interconnect structure is an electrical connection structure for realizing electrical connection between the devices of the second device chip 300 and the first device chip 200 .

[0060] In this embodiment, the material of the second interconnect structure is a metal material, for example, one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride.

[0061] In this embodiment, the devices of the second device chip 300 are electrically connected to the substrate 100 through the first device chip 200 .

[0062] The devices of the second device chip 300 are electrically connected to the substrate 100 through the first device chip 200 , thereby realizing electrical connection between the devices of the second device chip 300 and the outside and realizing basic circuit functions in the second device chip 300 .

[0063] In this embodiment, the packaging structure further includes: a conductive bump 110 , which is located between the first device chip 200 and the substrate 100 and electrically connects the first device chip 200 and the substrate 100 .

[0064] The conductive bumps 110 are used to realize electrical connection between the substrate 100 and the first device chip 200 .

[0065] In this embodiment, the material of the conductive bump 110 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the conductive bump 110 is tin.

[0066] For example, the conductive bump 110 can be C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, under the same first conductive bump spacing, the I / O number can be very high and is not limited by the size of the rewiring structure. In addition, it is suitable for mass production and greatly reduces size and weight.

[0067] In other embodiments, the conductive bump may also be a micro bump (uBump).

[0068] In this embodiment, the packaging structure further includes: a sealing layer 130 filling the gaps between adjacent conductive bumps 110 and covering the conductive bumps 110 .

[0069] The sealing layer 130 is used to achieve sealing between the first device chip 200 and the substrate 100 , and to achieve sealing between the second device chip 300 and the substrate 100 , and is also used to achieve sealing of the conductive bump 110 .

[0070] It should be noted that in the actual process, when a buried power rail (BPR) structure and a power delivery network (PDN) structure are used, higher requirements are placed on chip size and integration, and this embodiment is particularly applicable.

[0071] In this embodiment, the aforementioned conductive bump 110 is a first conductive bump 110, and the packaging structure further includes: a second conductive bump 120, located on the surface of the substrate 100 facing away from the bonding surface 100a, and the second conductive bump 120 is used to realize the electrical connection between the packaging structure and the external circuit.

[0072] The second conductive bumps 120 are used to realize electrical connection between the package structure and the external circuit, thereby realizing electrical connection between the first device chip 200 and the second device chip 300 and the external circuit.

[0073] In this embodiment, the material of the second conductive bump 120 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the second conductive bump 120 is tin.

[0074] For example, the second conductive bump 120 can be C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, under the condition of the same second conductive bump 120 spacing, the number of I / Os can be very high and is not limited by the size of the rewiring structure. In addition, it is suitable for mass production and greatly reduces the size and weight.

[0075] In other embodiments, the second conductive bump may also be a ball grid array (BGA) structure.

[0076] Figures 2 to 11 It is a schematic structural diagram corresponding to each step in an embodiment of a packaging method of the present invention.

[0077] refer to Figure 2 , providing a first device chip 200, including a first chip front side 200a and a first chip back side 200b opposite to each other.

[0078] The first device chip 200 is used for subsequent electrical connection with the substrate to form a corresponding packaging structure to achieve corresponding functions, wherein the first chip front side 200a and the first chip back side 200b are both used for subsequent electrical connection with the outside.

[0079] In this embodiment, in the step of providing the first device chip 200, the first device chip 200 includes a substrate 210 and a device layer 220 located on the substrate 210, the substrate 210 is located on the back side 200b of the first chip, and the device layer 220 is located on the front side 200a of the first chip.

[0080] The substrate 210 is used to provide a process platform for forming the device layer 220 , and is also used to provide a process platform for subsequently forming a backside interconnection layer.

[0081] In this embodiment, the substrate 210 is located on the back side 200b of the first chip, and the device layer 220 is located on the front side 200a of the first chip. The substrate 210 is located on the back side 200b of the first chip, leaving space for forming a back interconnection layer, so that the subsequently formed back interconnection layer is located on the surface of the substrate 210 facing the back side 200b of the first chip.

[0082] In this embodiment, in the step of providing the first device chip 200 , a first interconnection structure located on a side of the first chip front side 200 a is formed in the first device chip 200 .

[0083] The backside interconnect layer 220 of the first device chip 200 is electrically connected to the substrate 100 via a first interconnect structure.

[0084] The first interconnect structure is used to subsequently electrically connect with the back interconnect layer to realize electrical connection between the back interconnect layer and the outside. The first interconnect structure is located on the side of the front side 200a of the first chip. Then, the first interconnect structure can subsequently be electrically connected to the substrate through the front side 200a of the first chip, and accordingly, the back interconnect layer is electrically connected to the substrate through the first interconnect structure.

[0085] It should be noted that, in this embodiment, the first interconnection structure includes a through-silicon-via (TSV) structure, which is conducive to making electrical transmission more direct and rapid.

[0086] In this embodiment, the material of the first interconnect structure is a metal material, for example, one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride.

[0087] refer to Figure 3 , providing a second device chip 300 , including a second chip front side 300 a and a second chip back side 300 b opposite to each other.

[0088] The second device chip 300 is used to be subsequently bonded with the first device chip 200 to achieve electrical connection with the first device chip 200 , and correspondingly achieve electrical connection with the substrate through the first device chip 200 .

[0089] In this embodiment, in the step of providing the second device chip 300 , a second interconnect structure located on the second chip front side 300 a is formed in the second device chip 300 , and the second interconnect structure is electrically connected to the devices of the second device chip 300 .

[0090] Subsequently, the devices of the second device chip 300 are electrically connected to the first device chip 200 via the second interconnect structure.

[0091] The second interconnect structure is an electrical connection structure for realizing electrical connection between the devices of the second device chip 300 and the first device chip 200 .

[0092] In this embodiment, the material of the second interconnect structure is a metal material, for example, one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride.

[0093] Combined with reference Figures 4 to 7 The first device chip 200 is bonded to the second device chip 300 and electrically connected to each other, and the second chip front side 300a is arranged opposite to the first chip back side 200b.

[0094] The second device chip 300 is electrically connected to the first device chip 200 to realize the basic circuit structure between the second device chip 300 and the first device chip 200. Subsequently, the second device chip 300 is also used to electrically connect to the substrate to realize the electrical connection between the second device chip 300 and the outside.

[0095] In this embodiment, the second device chip 300 is bonded to the first device chip 200, which increases the total thickness of the structure when the first device chip 200 is subsequently bonded to the substrate, which is beneficial to increase the bonding strength of the first device chip 200, thereby facilitating the subsequent implementation of the solution of bonding the first device chip 200 to the substrate for back-side power supply, and at the same time realizing the electrical connection between the first device chip 200 and the second device chip 300, which is beneficial to increase the diversity of the circuit structure and improve the applicability of the packaging structure.

[0096] In this embodiment, in the step of bonding the first device chip 200 to the second device chip 300 , the devices of the second device chip 300 are electrically connected to the first device chip 200 via the second interconnect structure.

[0097] The devices of the second device chip 300 and the first device chip 200 can be electrically connected to each other through the second interconnect structure, thereby subsequently electrically connecting the devices of the second device chip 300 to the substrate.

[0098] refer to Figure 4 The step of bonding the first device chip 200 to the second device chip 300 includes: providing a carrier substrate 400 .

[0099] The carrier substrate 400 is used to provide support for the subsequent backside thinning of the first device chip 200 .

[0100] In this embodiment, the carrier substrate 400 includes a carrier wafer or a glass substrate.

[0101] Continue to refer Figure 4 , bonding the first device chip 200 to the carrier substrate 400 , with the front side 200 a of the first chip facing the carrier substrate 400 .

[0102] The first device chip 200 is bonded to the carrier substrate 400 , with the front side 200 a of the first chip facing the carrier substrate 400 , exposing the back side 200 b of the first chip, in preparation for subsequent back side thinning processing.

[0103] refer to Figure 5 After bonding the first device chip 200 to the carrier substrate 400 and before subsequently bonding the first device chip 200 to the second device chip 300 , the packaging method further includes: performing backside thinning processing on the first device chip 200 through the backside 200b of the first chip.

[0104] The first device chip 200 is subjected to backside thinning processing through the first chip backside 200 b to remove excess substrate 210 material.

[0105] In this embodiment, the back side thinning process is performed on the first device chip 200, and the carrier substrate 400 is used to provide support during the back side thinning process. The first chip front side 200a of the first device chip 200 faces the carrier substrate 400, which is beneficial to protect the circuit structure of the first chip front side 200a from being contaminated during the back side thinning process.

[0106] In this embodiment, in the step of performing backside thinning on the first device chip 200 through the first chip backside 200 b , a portion of the thickness of the substrate 210 is removed.

[0107] A portion of the thickness of the substrate 210 is removed, and the remaining portion of the thickness of the substrate 210 is retained to serve as a process platform for subsequently forming a backside interconnection layer.

[0108] refer to Figure 6 After the back side thinning process is performed, a back side interconnection layer 230 is formed on the back side 200 b of the first chip, and the back side interconnection layer 230 is electrically connected to the devices of the first device chip 200 .

[0109] The backside interconnection layer 220 is used to realize electrical connection between the devices in the first device chip 200 and the outside through the first chip backside 200 b . The backside interconnection layer 220 is also used to realize electrical connection between the second device chip 300 and the outside.

[0110] It should be noted that, in this embodiment, a through-silicon-via (TSV) structure is used to electrically connect the backside interconnect layer 220 to the device of the first device chip 200 , which is beneficial for making electrical transmission more direct and rapid.

[0111] In this embodiment, in the step of forming the backside interconnection layer 230 on the backside 200 b of the first chip, the backside interconnection layer 230 is formed on the substrate 210 , and the backside interconnection layer 230 is located on the surface of the substrate 210 facing the backside 200 b of the first chip.

[0112] The backside interconnection layer 230 is located on the surface of the substrate 210 facing the backside 200 b of the first chip, so that the backside interconnection layer 230 is used to subsequently implement a solution of backside power supply to the devices of the first device chip 200 .

[0113] In this embodiment, in the step of forming the backside interconnection layer 230 on the backside 200 b of the first chip, the backside interconnection layer 230 is electrically connected to the first interconnection structure.

[0114] The backside interconnection layer 230 is electrically connected to the first interconnection structure, so that the backside interconnection layer 230 is electrically connected to the substrate through the first interconnection structure.

[0115] In this embodiment, the back interconnect layer 220 is electrically connected to the first chip front side 200a of the first device chip 200 through the first interconnect structure wiring, and is subsequently electrically connected to the substrate through the first chip front side 200a. The wiring of the first interconnect structure is conducive to more accurate electrical transmission.

[0116] refer to Figure 7 After the first device chip 200 is bonded to the carrier substrate 400 , the first device chip 200 is bonded to the second device chip 300 .

[0117] After the first device chip 200 is bonded to the carrier substrate 400 , the first device chip 200 can be easily bonded to the second device chip 300 with the carrier substrate 400 as support.

[0118] In this embodiment, in the step of bonding the first device chip 200 to the second device chip 300 , the backside interconnection layer 230 is electrically connected to the second device chip 300 .

[0119] The backside interconnection layer 230 is electrically connected to the second device chip 300 , so that the second device chip 300 can be electrically connected to the substrate later through the backside interconnection layer 230 .

[0120] refer to Figure 8 After the first device chip 200 is bonded to the second device chip 300 , the carrier substrate 400 is removed.

[0121] After the first device chip 200 is bonded to the second device chip 300 , the carrier substrate 400 is removed to prepare for subsequently bonding the first device chip 200 to the substrate.

[0122] refer to Fig. 9 , providing a substrate 100 including a bonding surface 100a.

[0123] The substrate 100 is used to provide a process operation basis for realizing the bonding of the first device chip 200 . Specifically, the bonding surface 100 a of the substrate 100 is a process operation platform.

[0124] In this embodiment, the substrate 100 includes an interconnection structure layer, and the exposed surface of the interconnection structure layer is a bonding surface 100a.

[0125] The interconnection structure layer is used to subsequently achieve bonding with the first device chip 200 , thereby achieving electrical connection with the first device chip 200 . The interconnection structure layer is also used to achieve electrical connection between the first device chip 200 and the outside.

[0126] In this embodiment, the interconnection structure layer is a redistribution structure. Specifically, the redistribution structure may include one or more redistribution layers. In this embodiment, the redistribution structure includes multiple redistribution layers as an example for description.

[0127] Specifically, in this embodiment, the substrate 100 is a packaging substrate, and the packaging substrate is a printed circuit board (PCB).

[0128] Combined with reference Fig.10 and Fig.11 After the first device chip 200 is bonded to the second device chip 300, the first device chip 200 is bonded to the substrate 100 and electrically connected to the substrate 100, the front side 200a of the first chip is arranged opposite to the bonding surface 100a, and the device of the first device chip 200a is powered through the back side 200b of the first chip.

[0129] After the first device chip 200 is bonded to the second device chip 300 , the first device chip 200 is bonded to the substrate 100 to form a corresponding packaging structure to achieve corresponding functions.

[0130] In this embodiment, the first chip front side 200 a is bonded to the bonding surface 100 a and is electrically connected to the substrate 100 , thereby achieving electrical connection between the first chip front side 200 a and the substrate 100 .

[0131] In this embodiment, the devices of the first device chip 200 are powered through the first chip back side 200 b.

[0132] In this embodiment, the first device chip 200 is bonded to the substrate 100, and the power supply to the device of the first device chip 200 is realized through the back side 200b of the first chip, which is beneficial to simplify the circuit and improve the integration of the packaging structure.

[0133] Specifically, in the present embodiment, power is supplied to the device of the first device chip 200 through the back side 200b of the first chip, and signal electrical connection is made to the device of the first device chip 200 through the front side 200a of the first chip. Compared with the scheme in which both the power supply line and the signal line are electrically connected from the front side of the first chip of the first device chip, the present scheme is conducive to reducing the mutual interference between the power supply line and the signal line, and is conducive to making the power supply line electrically connected through the back side 200b of the first chip have a higher degree of freedom in design and a larger formation space, which is conducive to reducing the resistance of the power supply line, thereby reducing the probability of the voltage drop affecting the working performance of the device due to the excessive resistance of the power supply line, thereby improving the working performance of the device. At the same time, the signal line electrically connected through the front side 200a of the first chip also has a larger formation space, so that the device of the first device chip 200 achieves better working performance.

[0134] In this embodiment, in the step of bonding the first device chip 200 to the substrate 100 , the backside interconnection layer 230 of the first device chip 200 is electrically connected to the substrate 100 via the first interconnection structure.

[0135] The first interconnect structure passes through the substrate 210 and is electrically connected to the back interconnect layer 220, thereby realizing electrical connection between the back interconnect layer 220 and the outside. The first interconnect structure is located on the side of the front side 200a of the first chip, and the first interconnect structure can be electrically connected to the substrate 100 through the front side 200a of the first chip, and accordingly, the back interconnect layer 220 is electrically connected to the substrate 100 through the first interconnect structure.

[0136] In this embodiment, the back interconnect layer 220 is electrically connected to the first chip front side 200a of the first device chip 200 through the first interconnect structure wiring, and then electrically connected to the substrate 100 through the first chip front side 200a. The wiring of the first interconnect structure is conducive to making the electrical transmission more accurate.

[0137] In this embodiment, in the step of bonding the first device chip 200 to the substrate 100 , the devices of the second device chip 300 are electrically connected to the substrate 100 through the first device chip 200 .

[0138] The devices of the second device chip 300 are electrically connected to the substrate 100 through the first device chip 200 , thereby achieving electrical connection between the devices of the second device chip 300 and the outside.

[0139] In this embodiment, the step of bonding the first device chip 200 to the substrate 100 includes: forming a conductive bump 110 on the first chip front side 200 a of the first device chip 200 , or on the bonding surface 100 a .

[0140] The conductive bumps 110 are used to realize electrical connection between the substrate 100 and the first device chip 200 .

[0141] In this embodiment, the material of the conductive bump 110 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the conductive bump 110 is tin.

[0142] For example, the conductive bump 110 can be C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, under the same first conductive bump spacing, the I / O number can be very high and is not limited by the size of the rewiring structure. In addition, it is suitable for mass production and greatly reduces size and weight.

[0143] In other embodiments, the conductive bump may also be a micro bump (uBump).

[0144] Specifically, refer to Fig.10 As an example, in this embodiment, a conductive bump 110 is formed on the first chip front side 200 a of the first device chip 200 .

[0145] refer to Fig.11 The first device chip 200 is bonded to the substrate 100 by using the conductive bumps 110 , and the conductive bumps 110 electrically connect the first device chip 200 to the substrate 100 .

[0146] Continue to refer Fig.11 After bonding the first device chip 200 to the substrate 100 , the packaging method further includes: filling a sealing layer 130 in the gaps between adjacent conductive bumps 110 , wherein the sealing layer 130 covers the conductive bumps 110 .

[0147] The sealing layer 130 is used to achieve sealing between the first device chip 200 and the substrate 100 , and to achieve sealing between the second device chip 300 and the substrate 100 , and is also used to achieve sealing of the conductive bump 110 .

[0148] It should be noted that in the actual process, when a buried power rail (BPR) structure and a power delivery network (PDN) structure are used, higher requirements are placed on chip size and integration, and this embodiment is particularly applicable.

[0149] In this embodiment, the aforementioned conductive bump 110 is used as the first conductive bump 110, and the packaging method further includes: forming a second conductive bump 120 on the surface of the substrate 100 facing away from the bonding surface 100a, and the second conductive bump 120 is used to realize the electrical connection between the packaging structure and the external circuit.

[0150] The second conductive bumps 120 are used to realize electrical connection between the package structure and the external circuit, thereby realizing electrical connection between the first device chip 200 and the second device chip 300 and the external circuit.

[0151] In this embodiment, the material of the second conductive bump 120 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the second conductive bump 120 is tin.

[0152] For example, the second conductive bump 120 can be C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, under the condition of the same second conductive bump 120 spacing, the number of I / Os can be very high and is not limited by the size of the rewiring structure. In addition, it is suitable for mass production and greatly reduces the size and weight.

[0153] In other embodiments, the second conductive bump may also be a ball grid array (BGA) structure.

[0154] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A packaging structure, characterized in that: include: a substrate, including a bonding surface; a first device chip, bonded to the bonding surface of the substrate and electrically connected to the substrate, the first device chip comprising a first chip front side and a first chip back side opposite to each other, the first chip front side is arranged opposite to the bonding surface, and the device of the first device chip is powered by the first chip back side; The second device chip is bonded to the first device chip and electrically connected to the first device chip. The second device chip includes a second chip front side and a second chip back side opposite to each other. The second chip front side is arranged opposite to the first chip back side.

2. The packaging structure according to claim 1, characterized in that: The first device chip comprises a backside interconnection layer located on the back side of the first chip, the backside interconnection layer is electrically connected to the second device chip, and the backside interconnection layer is also electrically connected to the device of the first device chip.

3. The packaging structure according to claim 2, characterized in that: The first device chip further includes a substrate and a device layer located on the substrate, wherein the device layer is located on a surface of the substrate facing the front side of the first chip; The backside interconnection layer is located on a surface of the substrate facing the backside of the first chip.

4. The packaging structure according to claim 2, characterized in that: A first interconnection structure located at a front side of the first chip is formed in the first device chip, and a backside interconnection layer of the first device chip is electrically connected to the substrate through the first interconnection structure.

5. The packaging structure according to any one of claims 1 to 4, characterized in that: A second interconnect structure located on the front side of the second device chip is formed in the second device chip, and the devices of the second device chip are electrically connected to the first device chip through the second interconnect structure.

6. The packaging structure according to claim 5, characterized in that: The devices of the second device chip are electrically connected to the substrate through the first device chip.

7. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: a conductive bump, which is located between the first device chip and the substrate and electrically connects the first device chip and the substrate.

8. The packaging structure according to claim 7, characterized in that: The packaging structure further includes a sealing layer, which fills the gaps between adjacent conductive bumps and covers the conductive bumps.

9. A packaging method, characterized in that: include: Providing a first device chip, including a first chip front side and a first chip back side opposite to each other; Providing a second device chip, including a second chip front side and a second chip back side opposite to each other; Bonding the first device chip to the second device chip and electrically connecting them to each other, with the front side of the second chip facing the back side of the first chip; providing a substrate, including a bonding surface; After bonding the first device chip to the second device chip, the first device chip is bonded to the substrate and electrically connected to the substrate, the front side of the first chip is arranged opposite to the bonding surface, and the device of the first device chip is powered through the back side of the first chip.

10. The packaging method according to claim 9, characterized in that: The step of bonding the first device chip to the second device chip includes: providing a carrier substrate; Bonding the first device chip to the carrier substrate, with the front side of the first chip facing the carrier substrate; After bonding the first device chip to the carrier substrate, bonding the first device chip to the second device chip; After bonding the first device chip to the second device chip, the carrier substrate is removed.

11. The packaging method according to claim 10, characterized in that: After bonding the first device chip to the carrier substrate and before bonding the first device chip to the second device chip, the packaging method further comprises: performing a backside thinning process on the first device chip through the backside of the first chip; After the backside thinning process is performed, a backside interconnection layer is formed on the backside of the first chip, and the backside interconnection layer is electrically connected to the device of the first device chip; In the step of bonding the first device chip to the second device chip, the backside interconnect layer is electrically connected to the second device chip.

12. The packaging method according to claim 11, characterized in that: In the step of providing the first device chip, the first device chip includes a substrate and a device layer located on the substrate, wherein the substrate is located on a back side of the first chip, and the device layer is located on a front side of the first chip; In the step of performing backside thinning on the first device chip through the backside of the first chip, a portion of the thickness of the substrate is removed; In the step of forming a backside interconnection layer on the backside of the first chip, the backside interconnection layer is formed on the substrate, and the backside interconnection layer is located on a surface of the substrate facing the backside of the first chip.

13. The packaging method according to claim 11, characterized in that: In the step of providing the first device chip, a first interconnect structure located on a front side of the first chip is formed in the first device chip; In the step of forming a backside interconnection layer on the backside of the first chip, the backside interconnection layer is electrically connected to the first interconnection structure; In the step of bonding the first device chip to the substrate, the backside interconnection layer of the first device chip is electrically connected to the substrate through the first interconnection structure.

14. The packaging method according to any one of claims 9 to 13, characterized in that: In the step of providing the second device chip, a second interconnect structure located on the front side of the second chip is formed in the second device chip, and the second interconnect structure is electrically connected to the device of the second device chip; In the step of bonding the first device chip to the second device chip, the devices of the second device chip are electrically connected to the first device chip through the second interconnect structure.

15. The packaging method according to claim 14, characterized in that: In the step of bonding the first device chip to the substrate, the device of the second device chip is electrically connected to the substrate through the first device chip.

16. The packaging method according to claim 9, characterized in that: The step of bonding the first device chip to the substrate comprises: forming a conductive bump on the first chip front side of the first device chip or on the bonding surface; The first device chip is bonded to the substrate by using the conductive bumps, and the conductive bumps electrically connect the first device chip to the substrate.

17. The packaging method according to claim 16, characterized in that: After bonding the first device chip to the substrate, the packaging method further includes: filling a sealing layer in the gaps between adjacent conductive bumps, wherein the sealing layer covers the conductive bumps.

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