Chip-scale semiconductor package with back-side metal layer and front-side bump and method of manufacturing same

Abstract

A chip scale semiconductor package having a backside metal layer and front side bumps includes a silicon layer, a backside metal layer, and a plurality of front side pads. Each of the plurality of front pads includes a respective copper member and a respective solder member. A method comprising the steps of: providing a wafer; grinding the back surface of the wafer to form a peripheral ring; applying a metallization process to the ground surface; the peripheral ring is removed; forming a front seed layer; forming a front photoresist layer; applying a photoetching process; applying a front copper plating process; applying a front solder electroplating process; stripping the photoresist layer on the front surface; etching the front seed layer; and applying a singulation process.

Description

Technical Field

[0001] The present invention mainly relates to the technical field of semiconductor packaging, and in particular to a chip-level semiconductor package with a back metal layer and a front protrusion and a manufacturing method thereof. Background Art

[0002] Conventional chip-scale power semiconductor packages include flat pads that cause horizontal soldering issues on a printed circuit board (PCB), thereby increasing the chances of the conventional chip-scale power semiconductor package peeling off the PCB.

[0003] The present invention introduces raised pads to improve PCB horizontal soldering reliability. Each raised pad includes a copper component and a solder component, thereby increasing the wettable area during the solder reflow process and increasing the space for forming the bottom filling process. The thick metal layer in the range of 25 microns to 50 microns improves the electrical performance. The optional molded encapsulation layer further improves the mechanical strength of the chip-level semiconductor package. Summary of the invention

[0004] The purpose of the present invention is to provide a chip-level semiconductor package with a back metal layer and a front protrusion and a manufacturing method thereof, which can improve the reliability of horizontal welding of a printed circuit board and improve the mechanical strength of the chip-level semiconductor package and has great practical value.

[0005] In order to achieve the above-mentioned purpose, the present invention provides a chip-level semiconductor package with a back metal layer and a front protrusion, comprising: a silicon layer; a back metal layer on the back side of the silicon layer; a front metal layer, the front metal layer is on the front side opposite to the back side of the silicon layer; and a plurality of front solder pads extending from the front metal layer; wherein each of the plurality of front solder pads comprises: a corresponding copper component; a corresponding solder component; and the rear surface of each solder component is directly attached to the front surface of each copper component.

[0006] Preferably, the thickness of the corresponding copper member of each of the plurality of front pads is in the range from 25 microns to 50 microns; the thickness of the corresponding solder member of each of the plurality of front pads is in the range from 1 micron to 5 microns.

[0007] Preferably, the semiconductor package is attached to a printed circuit board; wherein the attached corresponding solder directly contacts the side wall of the corresponding copper component of each of the multiple front pads; wherein the corresponding solder component of each of the multiple front pads directly contacts the printed circuit board.

[0008] Preferably, the chip-scale semiconductor package having a back metal layer and a front protrusion further comprises a bottom filling layer located between the silicon layer of the semiconductor package and the printed circuit board.

[0009] Preferably, the printed circuit board further comprises a plurality of pads; and a front surface area of ​​a corresponding copper member of each of the plurality of front pads is smaller than a surface area of ​​a corresponding pad of the plurality of sub-pads of the printed circuit board.

[0010] Preferably, the chip-scale semiconductor package having a back metal layer and a front protrusion further comprises a molded packaging layer directly attached to the back side of the back metal layer.

[0011] Preferably, the chip-level semiconductor package having a back metal layer and a front protrusion further comprises a first molded packaging layer covering the front surface of the front metal layer.

[0012] Preferably, the chip-level semiconductor package having a back metal layer and a front protrusion is characterized by further comprising a second molded packaging layer directly attached to the back side of the back metal layer.

[0013] The present invention provides a method for manufacturing a chip-level semiconductor package with a back metal layer and a front protrusion, comprising the following steps: providing a wafer, the wafer comprising a front side and a back side opposite to the front side; grinding the back side of the wafer; applying a metallization process to the ground surface; forming a front side seed layer; forming a front side photoresist layer; applying a photolithography process; applying a front side copper plating process; applying a front side solder electroplating process; stripping off the front side photoresist layer; etching the front side seed layer; and applying a singulation process to separate the chip-level semiconductor package.

[0014] Preferably, the step of forming the front seed layer is after the step of applying a metallization process to the ground surface; and wherein the step of forming the front photoresist layer is after the step of forming the front seed layer.

[0015] Preferably, the step of forming the front seed layer is before the step of forming the front photoresist layer; and the step of forming the front photoresist layer is before the step of grinding the back side of the wafer.

[0016] Preferably, the step of forming the front seed layer is before the step of forming the front photoresist layer; and the step of forming the front photoresist layer is before the step of applying the photolithography process; and the step of applying the front solder plating process is before the step of grinding the back side of the chip.

[0017] Preferably, the method for manufacturing a chip-level semiconductor package having a back metal layer and a front protrusion further comprises forming a molded packaging layer on the metal layer formed by a metallization process.

[0018] Preferably, the chip-level semiconductor package comprises: a silicon layer; a back metal layer; a plurality of front pads; wherein each of the plurality of front pads comprises: a corresponding copper component; a corresponding solder component; wherein the rear surface of each solder component is directly attached to the front surface of each copper component.

[0019] Preferably, the thickness of the corresponding copper component of each of the plurality of front pads is in the range from 25 microns to 50 microns; and the thickness of the corresponding solder component of each of the plurality of front pads is in the range from 1 micron to 5 microns.

[0020] The present invention also provides a method for manufacturing a chip-level semiconductor package having a back metal layer and a front protrusion, comprising the following steps: providing a wafer, the wafer comprising a front side and a back side opposite to the front side; forming a front side molded packaging layer; grinding the back side of the wafer; applying a metallization process to the ground surface; applying a laser drilling process; forming a front side seed layer; forming a front side photoresist layer; applying a photolithography process; applying a front side copper plating process; applying a front side solder electroplating process; stripping off the front side photoresist layer; etching the front side seed layer; and applying a singulation process to separate the chip-level semiconductor package.

[0021] Preferably, before the step of applying the laser drilling process, a backside molding encapsulation layer is formed.

[0022] Preferably, the chip-level semiconductor package comprises: a silicon layer; a back metal layer; a plurality of front pads; wherein each of the plurality of front pads comprises: a corresponding copper component; a corresponding solder component; wherein the rear surface of each solder component is directly attached to the front surface of each copper component.

[0023] Preferably, the thickness of the corresponding copper component of each of the plurality of front pads is in the range from 25 microns to 50 microns; and the thickness of the corresponding solder component of each of the plurality of front pads is in the range from 1 micron to 5 microns.

[0024] In summary, compared with the prior art, the present invention provides a chip-level semiconductor package with a back metal layer and a front protrusion and a manufacturing method thereof, which can improve the reliability of horizontal welding of a printed circuit board and improve the mechanical strength of the chip-level semiconductor package, and has great practical value.

[0025] The details of various examples are set forth in the drawings and the description that follows.Other features and advantages will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1A , 1B, 1C and 1D are perspective views of corresponding chip-level semiconductor packages in examples of the present invention.

[0027] Figure 2 It is a cross-sectional view of a chip-level semiconductor package and a PCB in an example of the present invention.

[0028] Figure 3 A flow chart of a process for developing multiple chip-scale semiconductor packages in an example of the present invention.

[0029] Figure 4A , 4B , 4C, 4D, 4E, 4F, 4G, 4H, 4I, 4J, 4K, 4L and 4M are cross-sectional views of process steps for manufacturing multiple chip-level semiconductor packages in an example of the present invention.

[0030] Figure 5 Flowchart of a process for developing other multiple chip-level semiconductor packages in an example of the present invention.

[0031] Fig. 6A , 6B , 6C, 6D, 6E, 6F, 6G, 6H, 6I, 6J, 6K, 6L and 6M are cross-sectional views of process steps for manufacturing other multiple chip-level semiconductor packages in examples of the present invention.

[0032] Figure 7 Flowchart of a process for developing other multiple chip-scale semiconductor packages in an example of the present invention.

[0033] Fig. 8A , 8B , 8C, 8D, 8E, 8F, 8G, 8H, 8I, 8J, 8K, 8L and 8M are cross-sectional views of process steps for manufacturing additional multiple chip-level semiconductor packages in an example of the present invention.

[0034] Fig. 9 Flowchart of a process for developing additional multiple chip-scale semiconductor packages in an example of the present invention.

[0035] Fig. 10A , 10B , 10C, 10D, 10E, 10F, 10G, 10H, 10I, 10J, 10K, 10L, 10M, 10N and 10O are cross-sectional views of process steps for manufacturing other multiple chip-level semiconductor packages in an example of the present invention. DETAILED DESCRIPTION

[0036] Figure 1AThe chip-scale semiconductor package 100 in the example of the present disclosure is shown in a perspective view. In one example, the chip-scale semiconductor package 100 is a common drain power semiconductor package. The chip-scale semiconductor package 100 has a front side 101 and a back side 103. The chip-scale semiconductor package 100 includes a silicon layer 110, a back metal layer 112 and a plurality of front pads 120. In one example, the silicon layer 110 includes a first MOSFET transistor and a second MOSFET transistor formed thereon. Each of the first MOSFET transistor and the second MOSFET transistor includes a gate region and a source region on the front side of the silicon layer 110, and a drain region on the back side of the silicon layer 110 opposite to the front side. The back metal layer forms a common drain of the first MOSFET and the second MOSFET. The plurality of front pads 120 include a first gate pad connected to the first gate metal 105 of the first MOSFET, one or more first source pads connected to the first source metal 106 of the first MOS field effect transistor, and a second gate pad connected to the second gate metal 107 of the second MOS field effect transistor, and one or more second source pads connected to the second source metal 108 of the second MOS field effect transistor. Each of the plurality of front side pads 120 includes a corresponding copper member 122 and a corresponding solder member 124. A rear surface 124B of each solder member 124 is directly attached to a front surface 122F of each copper member 122.

[0037] In one example, the thickness of the corresponding copper member 122 of each of the plurality of front pads 120 is in the range of 25 microns to 50 microns. The thickness of the corresponding solder member 124 of each of the plurality of front pads 120 is in the range of 1 micron to 5 microns. The thickness of the silicon layer 110 is in the range of 30 microns to 100 microns. The first gate metal 105, the first source metal 106, the second gate metal 107 and the second source metal 108 are electrically connected to the gate region and the source region of the first and second MSOFET transistors, respectively, and can be formed by patterning the front metal layer of aluminum or aluminum alloy covering the front of the silicon layer 110. The front surface of the front metal layer forms the outermost front surface of the chip-scale semiconductor package 100. The passivation layer can cover the periphery of each of the first gate metal, the first source metal, the second gate metal and the second source metal. The copper member of each front pad extends from the front surface of the front metal layer to a height in the range of 25 microns to 50 microns. In one example, the corresponding solder member 124 includes Sn. In another example, the respective solder members 124 contain Sn and Ni. In yet another example, the respective solder members 124 contain Sn, Ni, and Au.

[0038] Figure 1B1 shows a perspective view of a chip-scale semiconductor package 140 in an example of the present disclosure. The chip-scale semiconductor package 140 includes a silicon layer 110, a backside metal layer 112, a plurality of frontside pads 120, and a molded encapsulation layer 152 directly attached to a backside 112B of the backside metal layer.

[0039] Figure 1C 1 shows a perspective view of a chip-scale semiconductor package 160 in an example of the present disclosure. The chip-scale semiconductor package 160 includes a silicon layer 110, a back metal layer 112, a plurality of front pads 120, a first molded encapsulation layer 171 attached to the front side 110F of the silicon layer 110, and a second molded encapsulation layer 173 directly attached to the back side 112B of the back metal layer 112B. The front surface of the first molded encapsulation layer 171 forms the outermost front surface of the chip-scale semiconductor package 160. The copper member of each front pad extends from the front surface of the front metal layer to a height above the outermost front surface.

[0040] Figure 1D 1 shows a perspective view of a chip-scale semiconductor package 180 in an example of the present disclosure. The chip-scale semiconductor package 180 includes a silicon layer 110, a back metal layer 112, a plurality of front pads 120, and a molded encapsulation layer 191 attached to the front side 110F of the silicon layer 110. The front surface of the first molded encapsulation layer 191 forms the outermost front surface of the chip-scale semiconductor package 160. The copper member of each front pad extends from the front surface of the front metal layer to a height above the outermost front surface.

[0041] Figure 2 2 shows a cross-sectional view of a chip-scale semiconductor package 200 attached to a PCB 210 in an example of the present disclosure. The chip-scale semiconductor package 200 includes a plurality of front-side pads 220 connected to connection pads on the PCB 210. Each of the plurality of front-side pads 220 includes a corresponding copper member 222 and a corresponding solder member 224. After the solder reflow process, additional corresponding solders 233 directly contact the sidewalls 223 of the corresponding copper member 222 of each of the plurality of front-side pads 220. In one example, the additional respective solders 233 are tapered in shape having a larger horizontal dimension toward the PCB 210 and a smaller horizontal dimension toward the back side of the respective copper member 222. The corresponding solder member 224 of each of the plurality of front-side pads 220 directly contacts the corresponding connection pad on the PCB 210. The chip-scale semiconductor package 200 may be Figures 1A to 1D One of the chip-scale semiconductor packages shown in .

[0042] An underfill layer 252 is located between the outermost front surface of the chip-scale semiconductor package 200 and the PCB 210. In order to properly apply the underfill layer 252, a minimum distance between the outermost front surface of the chip-scale semiconductor package 200 and the PCB 210 is required. The minimum distance (e.g., greater than 5 microns) is greater than the thickness of the solder member 224 of each of the plurality of front pads 220, i.e., for example, in the range from 1 micron to 5 microns.

[0043] The front surface area 229 of the corresponding copper member 222 of each of the plurality of front side pads 220 is smaller than the surface area 279 of the corresponding connection pad of the plurality of connection pads of the PCB 210 .

[0044] Figure 3 is a flow chart of a process 300 of developing a plurality of chip-level semiconductor packages in an example of the present disclosure. Figures 4A-4M A cross section of a corresponding step is shown. Process 300 may begin at block 302 .

[0045] In block 302, reference is now made to Figure 4A , providing a wafer 402. Wafer 402 includes a front side 404 and a back side 406 opposite to the front side 404. In one example, wafer 402 is a silicon wafer including a plurality of semiconductor devices formed thereon, each semiconductor device including a front metal layer patterned into a plurality of front electrodes (not shown). Wafer 402 may be a wafer having a diameter of 4 inches, 6 inches, 8 inches, 12 inches, or 18 inches. Block 302 may be followed by block 304.

[0046] In block 304, reference is now made to Figure 4B , a grinding process is applied to the back side 406 of the wafer 402 to thin the wafer 402 from its back side. In one example, the grinding process is applied only to the central portion of the back side 46 of the wafer 402 to form a recess 412 and a peripheral ring 414. The recess 412 is cylindrical in shape. The peripheral ring 414 has a torus shape. The peripheral ring 414 may be a Taiko ring. Under the metallization process of block 306, the peripheral ring 6140 provides the strength required to support the wafer. Block 304 may be followed by block 306.

[0047] In block 306, reference is now made to Figure 4C , a metallization process is applied to form a metal layer 418 in the recess 412. The metal layer 418 is deposited on the back side of the wafer. In one example, the metal layer 418 is made of copper. Block 306 may be followed by block 308.

[0048] In block 308, reference is now made to Figure 4D, a peripheral ring 414 (in one example, a Taiko ring) is removed to form a flat circular rear surface 422. A metal layer 418 covers the entire back side of the thinned layer 424. Block 308 may be followed by either block 310 or block 312.

[0049] In optional block 310 (shown in dashed lines), reference is now made to Figure 4E , forming a molded encapsulation layer 432 covering the metal layer 418. In one example, the molded encapsulation material is different from the lamination compound material. Block 310 may be followed by block 312.

[0050] In block 312, reference is now made to Figure 4F , a front conductive seed layer 436 is formed on the front side of the wafer on top of the patterned front metal layer (before forming the front seed layer 438 , the wafer is flipped so that the front side is on top). Block 312 may be followed by block 314 .

[0051] In block 314, reference is now made to Figure 4G , forming a front side photoresist layer 442 covering the seed layer 436. Block 314 may be followed by block 316.

[0052] In block 316, reference is now made to Figure 4H A photolithography process is applied to form pattern 452 to selectively expose regions of seed layer 436 located on each front electrode formed by the patterned front metal layer. Block 316 may be followed by block 318.

[0053] In block 318, reference is now made to Fig. 4I , a front copper plating process is applied to form a plurality of copper features 462 on the exposed seed layer regions that are electrically connected to the respective front electrodes. Block 318 may be followed by block 320 .

[0054] In block 320, reference is now made to Figure 4J , a front side solder plating process is applied to form a plurality of solder features 464 on top of each copper feature 462. Block 320 may be followed by block 322.

[0055] In block 322, reference is now made to Figure 4K , the front side photoresist layer 442 is stripped to expose areas of the front side seed layer 436 that are not covered by the copper member 462. Block 322 may be followed by block 324.

[0056] In block 324, reference is now made to Figure 4L , etching the exposed front seed layer 436. A plurality of solder members 464 are on top of the plurality of copper members 462. Block 324 may be followed by block 326.

[0057] In block 326, reference is now made to Figure 4M , a singulation process is applied to separate the plurality of chip-scale semiconductor packages 499. Without performing optional block 310, each of the plurality of chip-scale semiconductor packages 499 is Figure 1A The chip-scale semiconductor package 100 includes executing optional block 310, each of the plurality of chip-scale semiconductor packages 499 is Figure 1B Chip-level semiconductor package 140.

[0058] Figure 5 A flow chart showing a process 500 for developing a plurality of chip-scale semiconductor packages in an example of the present disclosure. Figures 6A-6M The cross section of the corresponding step is shown. Process 500 is similar to process 300 except that the steps of forming a front seed layer and forming a front photoresist layer precede the step of grinding the back side of the wafer. Process 500 may begin at block 502 .

[0059] In block 502, reference is now made to Fig. 6A , providing a wafer 602. Wafer 602 includes a front side 604 and a back side 606 opposite to the front side 604. In one example, wafer 602 is a silicon wafer including a plurality of semiconductor devices formed thereon, each semiconductor device including a front metal layer patterned into a plurality of front electrodes (not shown). Wafer 602 may be a wafer having a diameter of 4 inches, 6 inches, 8 inches, 12 inches, or 18 inches. Block 502 may be followed by block 504.

[0060] In block 504, reference is now made to Figure 6B A front conductive seed layer 636 is formed on the front side of the wafer on top of the patterned front metal layer. Block 504 may be followed by block 506 .

[0061] In block 506, reference is now made to Figure 6C , a front side photoresist layer 642 is formed covering the seed layer 636. Block 506 may be followed by block 508.

[0062] In block 508, reference is now made to Fig.6D , a grinding process is applied to the back side 606 of the wafer 602 so as to thin the wafer 602 from its back side (before applying the grinding process, the wafer is flipped so that the back side is on the top). In one example, the grinding process is applied only to the central portion of the back side 606 of the wafer 602 to form a recess 612 and a peripheral ring 614. The recess 612 is cylindrical in shape. The peripheral ring 614 has a torus shape. The peripheral ring 614 may be a Taiko ring. Under the metallization process of block 510, the peripheral ring 6140 provides the strength required to support the wafer. Block 508 may be followed by block 510.

[0063] In block 510, reference is now made to Fig. 6E , a metallization process is applied to form a metal layer 618 in the recess 612. The metal layer 618 is deposited on the back side of the wafer. In one example, the metal layer 618 is made of copper. Block 510 may be followed by block 512.

[0064] In block 512, reference is now made to Fig. 6F , a peripheral ring 614 (in one example, a Taiko ring) is removed to form a flat circular rear surface 622. A metal layer 618 covers the entire back side of the thinned layer 624. Block 512 may be followed by either block 514 or block 516.

[0065] In optional block 514 (shown in dashed lines), reference is now made to Figure 6G , forming a molded encapsulation layer 632 covering the metal layer 618. In one example, the molded encapsulation material is different from the lamination compound material. Block 514 may be followed by block 516.

[0066] In block 516, reference is now made to Figure 6H , a photolithography process is applied to form pattern 652 to selectively expose regions of seed layer 636 located on each front electrode formed by the patterned front metal layer (before applying the photolithography process, the wafer is flipped so that the front side is on top). Block 516 may be followed by block 518.

[0067] In block 518, reference is now made to Fig.6I , a front copper plating process is applied to form a plurality of copper features 662 on the exposed seed layer regions that are electrically connected to the respective front electrodes. Block 518 may be followed by block 520.

[0068] In block 520, reference is now made to Figure 6J , a front side solder plating process is applied to form a plurality of solder features 664. Block 520 may be followed by block 522.

[0069] In block 522, reference is now made to Figure 6K , the front side photoresist layer 642 is stripped to expose areas of the front side seed layer 636 not covered by the copper member 662. Block 322 may be followed by block 524.

[0070] In block 524, reference is now made to Figure 6L , etching the exposed front seed layer 636. A plurality of solder members 664 are on top of the plurality of copper members 662. Block 524 may be followed by block 526.

[0071] In block 526, reference is now made to Figure 6M, a singulation process is applied to separate them from multiple chip-level semiconductor packages 699.

[0072] Figure 7 A flow chart showing a process 700 for developing a plurality of chip-level semiconductor packages in an example of the present disclosure. Figures 8A-8M The cross-section of the corresponding step is shown. The process 700 is similar to the process 500 except that the steps of applying a photolithography process, applying a front copper plating process, and applying a front solder electroplating process are after the step of removing the peripheral ring. The process 700 may begin at block 702 .

[0073] In block 702, reference is now made to Fig. 8A , providing a wafer 802. The wafer 802 includes a front side 804 and a back side 806 opposite to the front side 804. In one example, the wafer 802 is a silicon wafer including a plurality of semiconductor devices formed thereon, each semiconductor device including a front metal layer patterned into a plurality of front electrodes (not shown). The wafer 802 may be a wafer having a diameter of 4 inches, 6 inches, 8 inches, 12 inches, or 18 inches. Block 702 may be followed by block 704.

[0074] In block 704, reference is now made to Figure 8B A front conductive seed layer 836 is formed on the front side of the wafer on top of the patterned front metal layer. Block 704 may be followed by block 706 .

[0075] In block 706, reference is now made to Figure 8C , forming a front side photoresist layer 842 covering the seed layer 836. Block 706 may be followed by block 708.

[0076] In block 708, reference is now made to Fig.8D A photolithography process is applied to form a pattern 852 to selectively expose a region of the seed layer 836 located on each front electrode formed by the patterned front metal layer. Block 708 may be followed by block 710.

[0077] In block 710, reference is now made to Fig. 8E , a front copper plating process is applied to form a plurality of copper features 862 on the exposed seed layer regions that are electrically connected to the respective front electrodes. Block 710 may be followed by block 712.

[0078] In block 712, reference is now made to Fig.8F , a front side solder plating process is applied to form a plurality of solder features 864. Block 712 may be followed by block 714.

[0079] In block 714, reference is now made to Figure 8G, a grinding process is applied to the back side 806 of the wafer 802 so as to thin the wafer 802 from its back side (before applying the grinding process, the wafer is flipped so that the back side is on the top). In one example, the grinding process is applied only to the central portion of the back side 806 of the wafer 802 to form a recess 812 and a peripheral ring 814. The recess 812 is cylindrical in shape. The peripheral ring 814 has a torus shape. The peripheral ring 814 may be a Taiko ring. Under the metallization process in block 716, the peripheral ring 816 provides the strength required to support the wafer. Block 714 may be followed by block 716.

[0080] In block 716, reference is now made to Figure 8H , a metallization process is applied to form a metal layer 818 in the recess 812. The metal layer 818 is deposited on the back side of the wafer. In one example, the metal layer 818 is made of copper. Block 716 may be followed by block 718.

[0081] In block 718, reference is now made to Fig.8I , the peripheral ring 814 (in one example, a Taiko ring) is removed to form a flat circular rear surface 822. A metal layer 818 covers the entire back side of the thinned layer 824. Block 718 may be followed by either block 720 or block 722.

[0082] In optional block 720 (shown in dashed lines), reference is now made to Figure 8J , forming a molded encapsulation layer 832 covering the metal layer 818. In one example, the molded encapsulation material is different from the lamination compound material. Block 720 may be followed by block 722.

[0083] In block 722, reference is now made to Figure 8K , strip the front photoresist layer 842 to expose the areas of the front seed layer 836 not covered by the copper member 862 (before stripping the front photoresist layer 842, flip the wafer so that the front side is on top). Block 722 may be followed by block 724.

[0084] In block 724, reference is now made to Figure 8L , etching the exposed front seed layer 836. A plurality of solder features 864 are on top of the plurality of copper features 862. Block 724 may be followed by block 726.

[0085] In block 726, reference is now made to Figure 8M , a singulation process is applied to separate them from multiple chip-level semiconductor packages 899.

[0086] Fig. 9 A flow chart showing a process 900 for developing a plurality of chip-level semiconductor packages in an example of the present disclosure. Figures 10A-10OA cross section of a corresponding step is shown. Process 900 may begin at block 902 .

[0087] In block 902, reference is now made to Fig. 10A , providing a wafer 1002. The wafer 1002 includes a front side 1004 and a back side 1006 opposite to the front side 1004. In one example, the wafer 1002 is a silicon wafer including a plurality of semiconductor devices formed thereon, each semiconductor device including a front metal layer patterned into a plurality of front electrodes (not shown). The wafer 1002 may be a wafer having a diameter of 4 inches, 6 inches, 8 inches, 12 inches, or 18 inches. Block 902 may be followed by block 904.

[0088] In block 904, reference is now made to Fig. 10B , forming a front side mold encapsulation layer 1009. In one example, the mold encapsulation material is different from the lamination compound material. Block 904 may be followed by block 906.

[0089] In block 906, reference is now made to Fig. 10C , a grinding process is applied to the back side 1006 of the wafer 1002 so as to thin the wafer 1002 from its back side (before applying the grinding process, the wafer is flipped so that the back side is on the top). In one example, the grinding process is applied only to the central portion of the back side 1006 of the wafer 1002 to form a recess 1012 and a peripheral ring 1014. The recess 1012 is cylindrical in shape. The peripheral ring 1014 has a torus shape. The peripheral ring 1014 may be a Taiko ring. Under the metallization process in block 908, the peripheral ring 1012 provides the strength required to support the wafer. Block 906 may be followed by block 908.

[0090] In block 908, reference is now made to Fig. 10D , a metallization process is applied to form a metal layer 1018 in the recess 1012. The metal layer 1018 is deposited on the back side of the wafer. In one example, the metal layer 1018 is made of copper. Block 908 may be followed by block 910.

[0091] In block 910, reference is now made to Fig.10E , a peripheral ring 1014 (in one example, a Taiko ring) is removed to form a flat circular rear surface 1022. The metal layer 1018 covers the entire back side of the thinned layer 1024. Block 910 may be followed by block 912 or block 914.

[0092] In optional block 912 (shown in dashed lines), reference is now made to Fig.10F A mold encapsulation layer 1032 is formed on the metal layer 1018. In one example, the mold encapsulation material is different from the lamination compound material. Block 912 may be followed by block 914.

[0093] In block 914, reference is now made to Figure 10G , a drilling process is applied to form a patterned front side mold encapsulation layer 1011 (before the drilling process is applied, the wafer is flipped so that the front side is on top). The metal layer on the front side is exposed through the drilled holes. Block 914 may be followed by block 916.

[0094] In block 916, reference is now made to Fig. 10H , a front conductive seed layer 1036 is disposed on the front side of the wafer. The exposed front metal layer is covered by the seed layer. Block 916 may be followed by block 918.

[0095] In block 918, reference is now made to Fig.10I , forming a front photoresist layer 1042 covering the entire seed layer 1036. Block 918 may be followed by block 920.

[0096] In block 920, reference is now made to Fig.10J , a photolithography process is applied to form a pattern 1052 to expose the seed layer at the bottom of the drilled hole. Block 920 may be followed by block 922 .

[0097] In block 922, reference is now made to Figure 10K , a front side copper plating process is applied to form a plurality of copper features 1062. Block 922 may be followed by block 924.

[0098] In block 924, reference is now made to Fig.10L , a front side solder plating process is applied to form a plurality of solder features 1064. Block 924 may be followed by block 926.

[0099] In block 926, reference is now made to Figure 10M , the front photoresist layer 1042 is stripped to expose the front seed layer 1036 on top of the front mold encapsulation layer 1009. Block 926 may be followed by block 928.

[0100] In block 928, reference is now made to Fig.10N , etching the exposed front seed layer 1036. A plurality of solder features 1064 are located on top of the plurality of copper features 1062. Block 928 may be followed by block 930.

[0101] In block 930, reference is now made to Fig.10O , applying a singulation process to separate from the plurality of chip-scale semiconductor packages 1099. Without performing optional block 912, each of the plurality of chip-scale semiconductor packages 1099 is Figure 1CThe chip-scale semiconductor package 180 includes executing optional block 912, each of the plurality of chip-scale semiconductor packages 1099 is Figure 1D Chip-level semiconductor packaging 160.

[0102] Those skilled in the art will recognize that modifications to the examples disclosed herein are possible. For example, the number of the plurality of front side pads 120 may vary. Other modifications may be made by those skilled in the art, and all such modifications are considered to fall within the scope of the invention as defined by the claims.

Claims

1. A chip-scale semiconductor package having a back metal layer and a front protrusion, characterized in that: include: a silicon layer; a back metal layer on the back side of the silicon layer; a front metal layer on a front side opposite to a back side of the silicon layer; as well as a plurality of front side pads extending from the front side metal layer; Each of the plurality of front side pads comprises: a corresponding copper member; and a corresponding welded component; and Wherein, the rear surface of each welding component is directly attached to the front surface of each copper component.

2. The chip-scale semiconductor package with a back metal layer and a front protrusion according to claim 1, characterized in that: wherein the thickness of the respective copper member of each of the plurality of front side pads is in a range from 25 microns to 50 microns; and Wherein a thickness of the corresponding solder member of each of the plurality of front side pads is in a range from 1 micrometer to 5 micrometers.

3. The chip-scale semiconductor package with a back metal layer and a front protrusion according to claim 1, characterized in that: The semiconductor package is attached to a printed circuit board; wherein the attached respective solder directly contacts a sidewall of the respective copper member of each of the plurality of front side pads; and wherein the corresponding solder member of each of the plurality of front side pads directly contacts the printed circuit board.

4. The chip-scale semiconductor package with a back metal layer and a front protrusion according to claim 3, characterized in that: Also included is an underfill layer located between the silicon layer of the semiconductor package and the printed circuit board.

5. The chip-scale semiconductor package with a back metal layer and a front protrusion according to claim 4, characterized in that: The printed circuit board further comprises a plurality of pads; and The front surface area of ​​the corresponding copper member of each of the plurality of front side pads is smaller than the surface area of ​​the corresponding pad of the plurality of sub-pads of the printed circuit board.

6. The chip-scale semiconductor package with a back metal layer and a front protrusion according to claim 1, characterized in that: Also included is a molded encapsulation layer directly attached to the back side of the back metal layer.

7. The chip-scale semiconductor package with a back metal layer and a front protrusion according to claim 1, characterized in that: Also included is a first molded encapsulation layer covering the front surface of the front metal layer.

8. The chip-scale semiconductor package with a back metal layer and a front protrusion according to claim 1, characterized in that: Also included is a second molded encapsulation layer directly attached to the back side of the back side metal layer.

9. A method for manufacturing a chip-scale semiconductor package having a back metal layer and a front bump, characterized in that: The following steps are involved: Providing a wafer, the wafer comprising a front side and a back side opposite to the front side; grinding the back side of the wafer; Applying a metallization process to the ground surface; forming a front seed layer; forming a front photoresist layer; Apply photolithography technology; Apply the front copper plating process; Applying front solder plating process; stripping the front photoresist layer; etching the front seed layer; as well as And applying a singulation process to separate the chip-level semiconductor package.

10. The method for manufacturing a chip-scale semiconductor package having a backside metal layer and a frontside protrusion according to claim 9, characterized in that: wherein the step of forming the front seed layer is after the step of applying a metallization process to the polished surface; and The step of forming the front photoresist layer is after the step of forming the front seed layer.

11. The method for manufacturing a chip-scale semiconductor package having a backside metal layer and a frontside protrusion according to claim 9, characterized in that: wherein the step of forming the front seed layer is before the step of forming the front photoresist layer; and The step of forming the front side photoresist layer is before the step of grinding the back side of the wafer.

12. The method for manufacturing a chip-scale semiconductor package having a back metal layer and a front bump according to claim 9, characterized in that: wherein the step of forming the front seed layer is before the step of forming the front photoresist layer; and The step of forming the front photoresist layer is before the step of applying the photolithography process; and the step of applying the front solder plating process is before the step of grinding the back side of the wafer.

13. The method for manufacturing a chip-scale semiconductor package having a backside metal layer and a frontside protrusion according to claim 9, characterized in that: The method also includes forming a molded encapsulation layer on the metal layer formed by the metallization process.

14. The method for manufacturing a chip-scale semiconductor package having a backside metal layer and a frontside protrusion according to claim 9, characterized in that: The chip-scale semiconductor package comprises: Silicon layer; a back metal layer; Multiple front side pads; Each of the plurality of front side pads comprises: corresponding copper components; a corresponding welded member; The rear surface of each soldering member is directly attached to the front surface of each copper member.

15. The method for manufacturing a chip-scale semiconductor package having a backside metal layer and a frontside protrusion according to claim 14, characterized in that: wherein the thickness of the respective copper member of each of the plurality of front side pads is in a range from 25 microns to 50 microns; And wherein a thickness of the corresponding solder member of each of the plurality of front side pads is in a range from 1 micrometer to 5 micrometers.

16. A method for manufacturing a chip-scale semiconductor package having a back metal layer and a front bump, characterized in that: The following steps are involved: Providing a wafer, the wafer comprising a front side and a back side opposite to the front side; forming a front side molding encapsulation layer; grinding the back side of the wafer; Applying a metallization process to the ground surface; Apply laser drilling technology; forming a front seed layer; forming a front photoresist layer; Apply photolithography technology; Apply the front copper plating process; Applying front solder plating process; stripping the front photoresist layer; etching the front seed layer; as well as A singulation process is applied to separate the chip-scale semiconductor packages.

17. The method for manufacturing a chip-scale semiconductor package having a backside metal layer and a frontside protrusion according to claim 16, characterized in that: The method also includes forming a backside molding encapsulation layer before the step of applying the laser drilling process.

18. The method for manufacturing a chip-scale semiconductor package having a backside metal layer and a frontside protrusion according to claim 16, characterized in that: The chip-scale semiconductor package comprises: a silicon layer; a back metal layer; Multiple front side pads; Each of the plurality of front side pads comprises: corresponding copper components; a corresponding welded member; The rear surface of each soldering member is directly attached to the front surface of each copper member.

19. The method for manufacturing a chip-scale semiconductor package having a backside metal layer and a frontside protrusion according to claim 18, characterized in that: wherein the thickness of the respective copper member of each of the plurality of front side pads is in a range from 25 microns to 50 microns; And wherein a thickness of the corresponding solder member of each of the plurality of front side pads is in a range from 1 micrometer to 5 micrometers.

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