Packaging substrate and chip packaging structure

Abstract

The technical scheme of the invention discloses a packaging substrate and a chip packaging structure, a grounding layer comprises a first area metal layer and a second area metal layer, the second area metal layer is located at an internal hollow part of the first area metal layer, and an insulation gap is formed between the second area metal layer and the first area metal layer; the packaging substrate further comprises a plurality of conductive structures which are electrically connected with different conductive layers in the longitudinal direction. The conductive structure comprises: a first conductive structure for grounding; a second conductive structure for connecting a power supply; in the grounding layer, the first conductive structure is electrically connected with the first area metal layer, and the second area metal layer is electrically connected with the multiple second conductive structures extending to the grounding layer. And in the plurality of second conductive structures connected with the second region metal layer, the distance between at least two second conductive structures is greater than the transverse size of the second conductive structures. According to the technical scheme, the packaging substrate can improve the power supply integrity of the chip packaging structure.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and more specifically, to a packaging substrate and a chip packaging structure. Background Art

[0002] With the continuous development of science and technology, more and more electronic devices are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable and important tool for people today.

[0003] The core component of electronic devices to achieve various functions is the chip. In order to protect the chip and facilitate the connection between the chip and the external circuit, the chip needs to be packaged and protected by a packaging substrate. The packaging substrate includes a stacked structure formed by stacking multiple conductive layers in sequence, and there is an insulating layer between adjacent conductive layers. When the chip is packaged and protected using an existing packaging substrate, the power integrity of the chip packaging structure is poor. Summary of the invention

[0004] In view of this, the present application provides a packaging substrate and a chip packaging structure, and the scheme is as follows:

[0005] The technical solution of the present application provides a packaging substrate on one hand, the packaging substrate includes a plurality of stacked conductive layers, and an insulating layer is provided between adjacent conductive layers, wherein at least one of the plurality of conductive layers includes a grounding layer, and the grounding layer includes a first-region metal layer and a second-region metal layer, and the second-region metal layer is located in an internal hollow of the first-region metal layer and has an insulating gap with the first-region metal layer;

[0006] The packaging substrate further comprises a plurality of conductive structures electrically connecting different conductive layers in a longitudinal direction; the conductive structures comprise: a first conductive structure for grounding; and a second conductive structure for connecting a power source;

[0007] Among them, in the grounding layer, the first conductive structures are all electrically connected to the first area metal layer, and the second area metal layer is electrically connected to a plurality of the second conductive structures extending to the grounding layer; among the plurality of the second conductive structures connected to the second area metal layer, the spacing between at least two of the second conductive structures is greater than the lateral dimension of the second conductive structure.

[0008] Preferably, in the above-mentioned packaging substrate, the plurality of conductive layers are sequentially from the 1st conductive layer to the Nth conductive layer in the stacking direction, where N is a positive integer greater than 2; the Nth conductive layer includes a capacitor welding area for welding capacitors; at least the Nth conductive layer is the ground layer;

[0009] The Nth conductive layer includes a first capacitor pad and a second capacitor pad located in the capacitor welding area, the first capacitor pad is used to connect the positive pin of the capacitor, and the second capacitor pad is used to connect the negative pin of the capacitor; within a preset range from the capacitor welding area, it has the second conductive structure, and the second area metal layer connects the second conductive structure and the first capacitor pad.

[0010] Preferably, in the above-mentioned packaging substrate, a single capacitor welding area has two first capacitor pads and two second capacitor pads;

[0011] The two second capacitor pads are respectively arranged on two sides of a line connecting the two first capacitor pads.

[0012] Preferably, in the above-mentioned packaging substrate, for the Nth conductive layer, the second region metal layer has a first sub-region and a second sub-region intersecting with each other;

[0013] Two ends of the first sub-region located on both sides of the intersection region are respectively connected to at least one of the second conductive structures;

[0014] Two ends of the second sub-region located on both sides of the intersection region are respectively connected to at least one of the second conductive structures;

[0015] Wherein, the capacitor is fixedly connected at the intersection position.

[0016] Preferably, in the above-mentioned packaging substrate, in the same ground layer, two second conductive structures with a spacing smaller than a set threshold are electrically connected based on the second region metal layer.

[0017] Preferably, in the above-mentioned packaging substrate, in the same ground layer, two second conductive structures with a spacing greater than a set threshold are connected based on the second region metal layer, and there is no first conductive structure on the connection path of the second conductive structure.

[0018] Preferably, in the above-mentioned packaging substrate, the set threshold is less than or equal to a lateral dimension of the second conductive structure.

[0019] On the other hand, the present application also provides a chip packaging structure, including:

[0020] A packaging substrate; the packaging substrate comprises a plurality of stacked conductive layers, with an insulating layer between adjacent conductive layers, wherein at least one of the plurality of conductive layers comprises a grounding layer, the grounding layer comprises a first-region metal layer and a second-region metal layer, the second-region metal layer is located at an internal hollowing-out of the first-region metal layer and has an insulating gap between the second-region metal layer and the first-region metal layer; the packaging substrate further comprises a plurality of conductive structures electrically connected to different conductive layers in a longitudinal direction; the conductive structures comprise: a first conductive structure for grounding; a second conductive structure for connecting a power source; wherein, in the grounding layer, the first conductive structures are all electrically connected to the first-region metal layer, and the second-region metal layer is electrically connected to a plurality of the second conductive structures extending to the grounding layer; among the plurality of the second conductive structures connected to the second-region metal layer, the spacing between at least two of the second conductive structures is greater than the lateral dimension of the second conductive structure;

[0021] A chip is fixed on one side surface of the packaging substrate, and the first area metal layer and the second metal layer are electrically connected to a power module in the chip.

[0022] Preferably, in the above chip packaging structure, the plurality of conductive layers are sequentially from the first conductive layer to the Nth conductive layer in the stacking direction, N is a positive integer greater than 2, and at least the Nth conductive layer is the ground layer; the first conductive layer is welded to fix the chip;

[0023] The chip packaging structure also includes a capacitor fixed on the Nth conductive layer, having a positive pin and a negative pin, which are electrically connected to the second region metal layer and the first region metal layer of the Nth conductive layer respectively.

[0024] Preferably, in the above chip packaging structure, the Nth conductive layer includes a first capacitor pad and a second capacitor pad located in the capacitor welding area;

[0025] The first capacitor pad is used to connect the positive pin of the capacitor, and the second capacitor pad is used to connect the negative pin of the capacitor; within a preset range from the capacitor welding area, there is a second conductive structure, and the second area metal layer connects the second conductive structure and the first capacitor pad.

[0026] From the above description, it can be known that in the packaging substrate and chip packaging structure provided by the technical solution of the present application, the grounding layer includes a first-region metal layer and a second-region metal layer, the second-region metal layer is located in the internal hollowing of the first-region metal layer and has an insulating gap with the first-region metal layer; the packaging substrate also includes a plurality of conductive structures that electrically connect different conductive layers in a longitudinal direction; the conductive structure includes: a first conductive structure for grounding; a second conductive structure for connecting a power supply; wherein, in the grounding layer, the first conductive structures are all electrically connected to the first-region metal layer, and the second-region metal layer is electrically connected to a plurality of second conductive structures extending to the grounding layer; among the plurality of second conductive structures connected to the second-region metal layer, the spacing between at least two second conductive structures is greater than the lateral dimension of the second conductive structure. The packaging substrate of the technical solution of the present application can improve the power integrity of the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0028] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0029] Figure 1 A cross-sectional view of a packaging substrate provided in an embodiment of the present application;

[0030] Figure 2 for Figure 1 A top view of a ground layer in a package substrate shown;

[0031] Figure 3 A top view of an N-th conductive layer provided in an embodiment of the present application;

[0032] Figure 4 A schematic diagram of the principle of reducing loop inductance based on a back-mounted capacitor in a packaging substrate provided in an embodiment of the present application;

[0033] Figure 5 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0034] Figure 6A PDN impedance curve of a chip packaging structure provided in an embodiment of the present application;

[0035] Figure 7 A simulation system architecture diagram for a chip packaging structure provided in an embodiment of the present application;

[0036] Figure 8 A time domain simulation waveform diagram of a chip packaging structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0038] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0039] refer to Figure 1 and Figure 2 As shown, Figure 1 A cross-sectional view of a packaging substrate provided in an embodiment of the present application, Figure 2 for Figure 1 The top view of the grounding layer in the packaging substrate is shown, the packaging substrate includes a plurality of stacked conductive layers 11, and an insulating layer 12 is provided between adjacent conductive layers 11, wherein at least one of the plurality of conductive layers 11 includes a grounding layer 110, and the grounding layer 110 includes a first-region metal layer 21 and a second-region metal layer 22, and the second-region metal layer 22 is located at the internal hollow of the first-region metal layer 21 and has an insulating gap between the second-region metal layer 21; the packaging substrate also includes a plurality of conductive structures 13 that electrically connect different conductive layers 11 in a longitudinal direction; the conductive structure 13 includes: a first conductive structure 131 for grounding; and a second conductive structure 132 for connecting a power supply.

[0040] Among them, in the grounding layer 110, the first conductive structures 131 are electrically connected to the first regional metal layer 21, and the second regional metal layer 22 is electrically connected to multiple second conductive structures 132 extending to the grounding layer 110; among the multiple second conductive structures 132 connected to the second regional metal layer 22, the spacing between at least two second conductive structures 132 is greater than the lateral dimension of the second conductive structure 132.

[0041] In the embodiment of the present application, in the ground layer 110, multiple second conductive structures 132 are connected through the second area metal layer 22, so as to strengthen the power connection, reduce the loop inductance value, thereby improving the power integrity, and optimizing the product performance of the chip packaging structure.

[0042] exist Figure 1 In the illustrated method, the bottommost conductive layer 11 is taken as the grounding layer 110 for illustration. Based on the chip packaging structure requirements, one or more conductive layers 11 can be set as the grounding layer 110 in the packaging substrate, and the embodiment of the present application is not limited to this. When there are multiple layers of grounding layers 110, the conductive layer graphic structure of each grounding layer 110 can be the same graphic structure or different graphic structures based on requirements, and the embodiment of the present application is not limited to this. In the drawings of the embodiment of the present application, the packaging substrate area shown is mainly the area of ​​the packaging substrate used to connect the power module of the chip.

[0043] As the functions and complexity of SOC (system-on-chip) increase, the requirements for high-speed signal lines and power supplies are getting higher and higher. From the perspective of power supply, adding a certain number of passive components on the side of the packaging substrate away from the chip can help improve the stability of the power distribution network (PDN). When the chip is packaged and protected using the packaging substrate provided in the embodiment of the present application, the chip and the passive components can be bound to the opposite sides of the packaging substrate to reduce the size of the chip packaging structure. Among them, the passive components include capacitors.

[0044] refer to Figure 3 As shown, Figure 3 An overhead view of an Nth conductive layer is provided in an embodiment of the present application. In this method, a plurality of conductive layers 11 are set to be the 1st conductive layer to the Nth conductive layer in the stacking direction, N is a positive integer greater than 2; the Nth conductive layer includes a capacitor welding area 23, and the capacitor welding area 23 is used to weld capacitors; in this method, at least the Nth conductive layer is a ground layer 110.

[0045] exist Figure 3 In the illustrated method, the Nth conductive layer includes a first capacitor pad 31 and a second capacitor pad 32 located in the capacitor welding area 23, the first capacitor pad 31 is used to connect the positive pin of the capacitor, and the second capacitor pad 32 is used to connect the negative pin of the capacitor; within a preset range from the capacitor welding area 23, there is a second conductive structure 132, and the second area metal layer 22 connects the second conductive structure 132 and the first capacitor pad 31. In this method, in the Nth conductive layer, multiple second conductive structures 132 are connected through the second area metal layer 22 and connected to the first capacitor pad 31, so that the power connection can be strengthened to achieve the effect of strengthening the capacitor, and the loop inductance value can be reduced well.

[0046] In the embodiment of the present application, the first conductive structure 131 and the second conductive structure 132 may be conductive vias passing through the multiple conductive layers 11. The conductive vias may be designed based on the circuit layout, and different conductive layers 11 may be connected through one or more conductive vias. The conductive vias may extend from any conductive layer 11 to another conductive layer 11, and are not limited to Figure 1 In the illustrated embodiment, the conductive via extends from the first conductive layer to the Nth conductive layer.

[0047] In the Nth conductive layer, the first region metal layer 21 connects all the first conductive structures 131 extending to the Nth conductive layer and connects to the second capacitor pad 32 to ensure the integrity of the ground plane and compensate for the grounding effect of the capacitor.

[0048] In conventional packaging substrates, taking N=10 as an example, when the 10th conductive layer is used as the ground plane and the four-pin capacitor is welded and fixed, the two positive pins in the four corner capacitors are respectively connected to separate positive pads of the capacitors, and each conductive through-hole extending to the 10th conductive layer is distributed in multiple separate metal layer areas, resulting in poor integrity of the power plane. It is necessary to connect the positive pins to a metal layer above the 10th conductive layer as the power plane. For example, taking the 8th layer as the power plane, the two positive pads of the capacitors connected to the same capacitor on the 10th conductive layer need to extend to the power plane of the 8th conductive layer through conductive through-holes, and be connected in series using the 8th conductive layer with higher power integrity. Although this method can improve product performance to a certain extent by connecting capacitors on the Nth conductive layer, the large grounded metal layer in the Nth conductive layer is too strongly connected, which will lead to insufficient power connection and fewer current paths at the power supply end. In order to solve these problems, it can be used Figure 3 The method shown.

[0049] like Figure 3 As shown, there are two first capacitor pads 31 and two second capacitor pads 32 in a single capacitor welding area 23; wherein the two second capacitor pads 32 are respectively arranged on both sides of the connection line of the two first capacitor pads 31. In this way, a four-pin capacitor with two positive pins and two negative pins can be connected in the capacitor welding area 23 through two first capacitor pads 31 and two second capacitor pads 32 in the Nth conductive layer, and the two first capacitor pads 31 are connected based on the second area metal layer 22 of the Nth conductive layer, so that the two positive pins of the four-pin capacitor are connected in the Nth conductive layer. This method can utilize the four-pin capacitor and the second conductive structure 132 within the preset range to connect to the same second area metal layer to form a larger area of ​​the power plane to compensate for the integrity of the power plane, so as to achieve the effect of strengthening the capacitor and reduce the loop inductance value.

[0050] The two first capacitor pads 31 connected to the Nth conductive layer can be connected to the power plane in the ath conductive layer through the second conductive structure 132 respectively. Wherein, a is a positive integer greater than 1 and less than N. For example, when N=10, a can be 8. The values ​​of N and a corresponding to the embodiment of the present application are not limited, and the values ​​of N and a can be set based on the design requirements of the packaging substrate.

[0051] refer to Figure 4 As shown, Figure 4 A schematic diagram of the principle of reducing loop inductance based on a back-mounted capacitor in a packaging substrate provided in an embodiment of the present application, wherein the surface of the first conductive layer of the packaging substrate is used for welding and fixing with the pins 41 of the chip, and the surface of the Nth conductive layer has solder balls 43 and capacitor pads for welding the back-mounted capacitors 42.

[0052] like Figure 4 As shown, on the upper and lower sides of the packaging substrate, not only can the back-mounted capacitor 41 form a loop path with the upper chip as shown by the vertical thin solid line, but also the second conductive structure 132 connected by the solder ball 43 can form a loop path with the upper chip as shown by the vertical thick solid line. The first conductive structure 131 connected by the solder ball 43 can also form a loop path with the upper chip as shown by the vertical dotted line. By superimposing multiple loop paths, the loop inductance value is reduced.

[0053] In some implementations of the embodiments of the present application, for the Nth conductive layer, the second region metal layer 22 has a first sub-region and a second sub-region intersecting, such as Figure 2 or Figure 3 As shown, the first sub-region and the second sub-region intersect in an X shape; the two ends of the first sub-region located on both sides of the intersection region are respectively connected to at least one second conductive structure 132; the two ends of the second sub-region located on both sides of the intersection region are respectively connected to at least one second conductive structure 1321; wherein the capacitor is fixedly connected at the intersection position, and the capacitor welding area 23 includes the intersection position.

[0054] In the same ground layer 110, two second conductive structures 132 with a spacing smaller than a set threshold are electrically connected based on the second region metal layer 22. In this way, the integrity of the power plane can be improved.

[0055] The set threshold value can be set based on demand, for example, the set threshold value can be set to be no greater than the lateral size of the second conductive structure 132. In this way, in the same ground layer 110, two second conductive structures 132 with a spacing less than the set threshold value are connected through the second region metal layer 22, thereby better improving the integrity of the power plane.

[0056] In some implementations of the embodiments of the present application, in the same ground layer 110, two second conductive structures 132 with a spacing greater than a set threshold are connected based on the second region metal layer 2, and there is no first conductive structure 131 on the connection path of the second conductive structure 132. In this way, in the same ground layer 110, two second conductive structures 132 with a spacing greater than a set threshold and no first conductive structure 131 between them can be connected through the second region metal layer 22, thereby better improving the integrity of the power plane.

[0057] As described above, the threshold is set to be less than or equal to the lateral dimension of the second conductive structure. Thus, in the same ground layer 110, two second conductive structures 132 with a spacing less than the set threshold are bound to be directly connected without being blocked by the first conductive structure 131, thereby better improving the integrity of the power plane.

[0058] Based on the above-mentioned packaging substrate embodiment, another embodiment of the present application further provides a chip packaging structure, which can be as follows Figure 5 shown.

[0059] refer to Figure 5 As shown, Figure 5 A schematic diagram of a chip packaging structure provided in an embodiment of the present application, combined with Figure 1 , Figure 3 and Figure 5 As shown, the chip packaging structure includes:

[0060] A packaging substrate 10; the packaging substrate 10 includes a plurality of stacked conductive layers 11, with an insulating layer 12 between adjacent conductive layers 11, wherein at least one of the plurality of conductive layers 11 includes a grounding layer 110, and the grounding layer 110 includes a first-region metal layer 21 and a second-region metal layer 22, wherein the second-region metal layer 22 is located at an internal hollow portion of the first-region metal layer 21 and has an insulating gap with the first-region metal layer 21; the packaging substrate also includes a plurality of conductive structures 13 electrically connecting different conductive layers in a longitudinal direction; the conductive structure 13 includes: a first conductive structure 131 for grounding; a second conductive structure 132 for connecting a power source; wherein, in the grounding layer 110, the first conductive structures 131 are all electrically connected to the first-region metal layer 21, and the second-region metal layer 22 is electrically connected to a plurality of second conductive structures 132 extending to the grounding layer 110; among the plurality of second conductive structures 132 connected to the second-region metal layer 22, the spacing between at least two second conductive structures 132 is greater than the lateral dimension of the second conductive structure 132;

[0061] The chip 40 is fixed on one side surface of the package substrate 10 , and the first region metal layer 21 and the second metal layer 22 are electrically connected to the power module in the chip 40 .

[0062] The chip packaging structure provided in the embodiment of the present application adopts the packaging substrate 10 provided in the above embodiment, which can improve the power integrity in the ground layer 110 and improve product performance.

[0063] Optionally, the plurality of conductive layers 110 are sequentially arranged from the 1st conductive layer to the Nth conductive layer in the stacking direction, N is a positive integer greater than 2, and at least the Nth conductive layer is a ground layer 110; the 1st conductive layer is welded to fix the chip 40; the chip packaging structure also includes a capacitor 42, which is fixed on the Nth conductive layer and has a positive pin and a negative pin, which are electrically connected to the second area metal layer 22 and the first area metal layer 21 of the N conductive layer, respectively.

[0064] One or more capacitors 42 may be welded and fixed on the packaging substrate 10 . The capacitor 42 is welded and fixed on the Nth conductive layer and is a back-mounted capacitor, which can reduce loop inductance.

[0065] Optionally, the Nth conductive layer includes a first capacitor pad 31 and a second capacitor pad 32 located in the capacitor welding area 23; the first capacitor pad 31 is used to connect the positive pin of the capacitor, and the second capacitor pad 32 is used to connect the negative pin of the capacitor; within a preset range from the capacitor welding area 23, there is a second conductive structure 132, and the second area metal layer 22 connects the second conductive structure 132 and the first capacitor pad 31.

[0066] As mentioned above, the capacitor 42 can be a four-pin capacitor, and the characteristic relationship between the four-pin capacitor and the second conductive structure 132 within a preset range is used to compensate for the integrity of the power plane, so as to achieve the effect of strengthening the capacitor and reduce the loop inductance. The back-mounted capacitor arranged on the surface of the Nth conductive layer is not limited to a four-pin capacitor, but can also be a two-pin capacitor.

[0067] refer to Figure 6 As shown, Figure 6 A PDN impedance curve of a chip packaging structure provided in an embodiment of the present application. The horizontal axis is impedance in Ω, and the vertical axis is frequency in MHz. The dotted line is the PDN impedance curve of a conventional chip packaging structure, and the solid line is the PDN impedance curve of a chip packaging structure using the packaging substrate described in an embodiment of the present application.

[0068] in, Figure 6 The conventional chip packaging structure and the chip packaging structure of the present application differ only in the pattern of the Nth conductive layer, and the other structures are the same, so as to serve as a reference for comparison. Figure 6It can be seen that for the chip packaging structure using a conventional packaging substrate, the impedance at the peak position of the curve is 170mohm, and the loop inductance is 45.29pH. For the chip packaging structure using the packaging substrate described in the embodiment of the present application, the impedance at the peak position of the curve is 153mohm, and the loop inductance is 26.79pH. Compared with the conventional chip packaging structure, the chip packaging structure provided in the embodiment of the present application reduces the impedance and loop inductance.

[0069] refer to Figure 7 and Figure 8 As shown, Figure 7 A simulation system architecture diagram for a chip packaging structure provided in an embodiment of the present application, Figure 8 A time domain simulation waveform diagram of a chip packaging structure provided in an embodiment of the present application.

[0070] like Figure 7 As shown, the simulation system includes a circuit board 52 and a power management chip 51 and a chip packaging structure arranged on the circuit board, wherein the chip 54 is welded on the packaging substrate 53 to form a packaging structure and then fixedly connected to the circuit board 52 through solder balls at the bottom of the packaging substrate.

[0071] in, Figure 8 The curve in the upper middle figure is a time domain simulation waveform of a chip packaging structure prepared using a conventional packaging substrate, and the curve in the lower middle figure is a time domain simulation waveform of a chip packaging structure prepared using a packaging substrate provided in an embodiment of the present application.

[0072] in, Figure 8 The conventional chip packaging structure and the chip packaging structure of the present application differ only in the pattern of the Nth conductive layer, and the other structures are the same, so as to facilitate mutual comparison and reference. When a high inversion is made in the chip, for example, when a high load is connected, a large amount of current will be required, which will cause the voltage drop of the power output pin. Based on Figure 8 It can be seen from the voltage drop point of the chip pin in the simulation waveform shown that the voltage of the conventional chip packaging structure with four-pin capacitors at the voltage drop point drops from 950mV to 776mV, a drop of about 174mV, and the voltage stability is poor, which affects the chip performance. In the chip packaging structure provided in the embodiment of the present application, the chip packaging structure based on the above-mentioned four-pin capacitor can make the voltage at the voltage drop point drop from 950mV to 786mV, a drop of about 164mV. Compared with the conventional chip packaging structure, a 10mV voltage boost is obtained at the voltage drop point, an increase of 1.05%. Compared with the conventional chip packaging structure, the voltage stability is good, which can improve the performance of the chip.

[0073] The various embodiments in this specification are described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0074] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same drawings throughout the embodiments of the specification mark the same structure. In addition, for the sake of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It is also understood that when an element such as a layer, film, region or substrate is referred to as "on" another element, the element may be directly on the other element or there may be an intermediate element. In addition, "on" refers to positioning an element on or below another element, but does not essentially mean positioning on the upper side of another element according to the direction of gravity.

[0075] The terms "upper", "lower", "top", "bottom", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0076] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0077] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A packaging substrate, characterized in that: The packaging substrate comprises a plurality of stacked conductive layers, and an insulating layer is provided between adjacent conductive layers, wherein at least one of the plurality of conductive layers comprises a grounding layer, and the grounding layer comprises a first-region metal layer and a second-region metal layer, and the second-region metal layer is located at an inner hollow of the first-region metal layer and has an insulating gap with the first-region metal layer; The packaging substrate further comprises a plurality of conductive structures electrically connecting different conductive layers in a longitudinal direction; the conductive structures comprise: a first conductive structure for grounding; and a second conductive structure for connecting a power source; Among them, in the grounding layer, the first conductive structures are all electrically connected to the first area metal layer, and the second area metal layer is electrically connected to a plurality of the second conductive structures extending to the grounding layer; among the plurality of the second conductive structures connected to the second area metal layer, the spacing between at least two of the second conductive structures is greater than the lateral dimension of the second conductive structure.

2. The packaging substrate according to claim 1, characterized in that: The plurality of conductive layers are sequentially from the first conductive layer to the Nth conductive layer in the stacking direction, where N is a positive integer greater than 2; the Nth conductive layer comprises a capacitor welding area for welding capacitors; at least the Nth conductive layer is the ground layer; The Nth conductive layer includes a first capacitor pad and a second capacitor pad located in the capacitor welding area, the first capacitor pad is used to connect the positive pin of the capacitor, and the second capacitor pad is used to connect the negative pin of the capacitor; within a preset range from the capacitor welding area, it has the second conductive structure, and the second area metal layer connects the second conductive structure and the first capacitor pad.

3. The packaging substrate according to claim 2, characterized in that: A single capacitor welding area has two first capacitor pads and two second capacitor pads; The two second capacitor pads are respectively arranged on two sides of a line connecting the two first capacitor pads.

4. The packaging substrate according to claim 2 or 3, characterized in that: For the Nth conductive layer, the second region metal layer has a first sub-region and a second sub-region intersecting with each other; Two ends of the first sub-region located on both sides of the intersection region are respectively connected to at least one of the second conductive structures; Two ends of the second sub-region located on both sides of the intersection region are respectively connected to at least one of the second conductive structures; Wherein, the capacitor is fixedly connected at the intersection position.

5. The packaging substrate according to claim 1, characterized in that: In the same ground layer, two second conductive structures with a spacing smaller than a set threshold are electrically connected based on the second region metal layer.

6. The packaging substrate according to claim 1, characterized in that: In the same ground layer, two second conductive structures with a spacing greater than a set threshold are connected based on the second region metal layer, and there is no first conductive structure on the connection path of the second conductive structure.

7. The packaging substrate according to claim 5 or 6, characterized in that: The set threshold is less than or equal to a lateral dimension of the second conductive structure.

8. A chip packaging structure, characterized in that: include: Package substrate; The packaging substrate comprises a plurality of stacked conductive layers, with an insulating layer between adjacent conductive layers, wherein at least one of the plurality of conductive layers comprises a grounding layer, and the grounding layer comprises a first-region metal layer and a second-region metal layer, wherein the second-region metal layer is located at an internal hollowing-out portion of the first-region metal layer and has an insulating gap between the second-region metal layer and the first-region metal layer; the packaging substrate further comprises a plurality of conductive structures electrically connected to different conductive layers in a longitudinal direction; the conductive structures comprise: a first conductive structure for grounding; a second conductive structure for connecting a power source; wherein, in the grounding layer, the first conductive structures are all electrically connected to the first-region metal layer, and the second-region metal layer is electrically connected to a plurality of the second conductive structures extending to the grounding layer; among the plurality of the second conductive structures connected to the second-region metal layer, the spacing between at least two of the second conductive structures is greater than the lateral dimension of the second conductive structure; A chip is fixed on one side surface of the packaging substrate, and the first area metal layer and the second metal layer are electrically connected to a power module in the chip.

9. The chip packaging structure according to claim 8, characterized in that: The plurality of conductive layers are sequentially from the first conductive layer to the Nth conductive layer in the stacking direction, N is a positive integer greater than 2, and at least the Nth conductive layer is the ground layer; the first conductive layer is soldered to fix the chip; The chip packaging structure also includes a capacitor fixed on the Nth conductive layer, having a positive pin and a negative pin, which are electrically connected to the second region metal layer and the first region metal layer of the Nth conductive layer respectively.

10. The chip packaging structure according to claim 9, characterized in that: The Nth conductive layer includes a first capacitor pad and a second capacitor pad located in the capacitor welding area; The first capacitor pad is used to connect the positive pin of the capacitor, and the second capacitor pad is used to connect the negative pin of the capacitor; within a preset range from the capacitor welding area, there is a second conductive structure, and the second area metal layer connects the second conductive structure and the first capacitor pad.

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