Half-bridge driving circuit and method in multi-level topology based on FPGA

Abstract

The invention discloses a half-bridge driving circuit and method in a multi-level topology based on an FPGA (Field Programmable Gate Array), the half-bridge driving circuit comprises an MCU (Microprogrammed Control Unit), an FPGA logic circuit and a signal isolation circuit, the FPGA logic circuit gathers fault signals of other circuits in a complete machine, when other circuits fail, the circuit is notified to carry out shutdown operation, and when the other circuits fail, the FPGA logic circuit does not fail, the signal isolation circuit does not fail. In the process of switching on to switching off and the process of switching off to switching on, a transition state that switching-on voltage and switching-off voltage are invalid exists in a period of time, impact in the state switching process is solved, soft switching-off of an outer tube and an inner tube of a power main device in the multi-level topology from outside to inside is achieved in case of a fault, and soft switching-off of the outer tube and the inner tube of the power main device in the multi-level topology is achieved. The gate driver has the advantages that the gate driver is simple in structure, combinational logic and complex sequential logic functions can be realized at low cost, the signal isolation circuit is used for controlling conversion and isolation of PWM (pulse-width modulation) pulse to voltage required by gate control signals of a power device of a main circuit, peak voltage limitation and inner and outer tube switching time sequences are realized, various faults can be monitored, and fault protection can be safely implemented.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductor drivers, and in particular relates to a half-bridge driving circuit and method in a multi-level topology based on FPGA. Background Art

[0002] After 30 years of development, power electronics is still in the ascendant. Its application fields have expanded from the initial offline switching power supply to uninterruptible power supply UPS, home appliances, grid-connected / off-grid new energy converters, new energy vehicle electric drives and chargers, and the most cutting-edge energy storage converters; power has expanded from the initial watt level to the current megawatt level; semiconductor devices have evolved from the initial thyristors to Si-based IGBTs, MOSFETs, and now SiC and GaN. Thanks to the expansion of application demand and the development of power device technology, the main circuit topology has evolved from the initial single-tube and dual-tube to two-level half-bridges and then to multi-level based on clamping technology; it can be said that more and more of the world's electric energy will be converted by power electronic converters before reaching the final load.

[0003] As the capacity of a single machine increases, in order to reduce the current, the voltage of the equipment is also gradually increasing, which puts forward new requirements for the insulation withstand voltage of the equipment, and at the same time, there are new requirements for the gate drive circuit. As we all know, the switching speed of power electronic switches is usually very fast. For IGBT, it is about several us (microseconds), and for MOSFET, it is in the sub-us level. Because the busbar, connecting wires and devices in the circuit have parasitic inductance, there will be commutation (that is, the current flow path will change) during the switching process of the semiconductor device in the circuit. At this time, a spike voltage will be generated in the circuit, and its value can be expressed by the formula get.

[0004] Since the switching time dt is very small, a very high peak voltage can occur under very small current conditions. Due to the inherent characteristics of semiconductor devices, they all have about 2 to 3 times the overcurrent capacity, but no overvoltage capacity, so they are very sensitive to this peak voltage and must be limited by reasonable switching time configuration; in addition, multi-level topology is mostly used for power electronic products such as grid-connected / off-grid converters. From the perspective of gate drive, its multiple switches can be split into several two-level half-bridge circuits, but most of the two-level drive modules on the market are for ordinary half-bridge applications, that is, only the upper and lower tubes cannot be turned on at the same time. In addition to avoiding direct connection of the upper and lower tubes, the two-level circuit separated in the multi-level topology also needs to consider the turn-on and turn-off sequence of the upper and lower tubes.

[0005] Since conventional two-level gate drivers can neither control the peak voltage during the switching process nor realize the upper and lower tube timing logic required for multi-level (the upper and lower tubes and the power main switches at the upper or lower positions in the power main circuit diagram can be IGBTs or MOSFETs or other power semiconductor devices, also called internal and external tubes in multi-level topologies, this article stipulates that the upper tube is the outer tube, prefixed with "U_" below, and the lower tube is the inner tube, prefixed with "D_" below) it is necessary to design a gate driver for multi-level that can not only realize the peak voltage limitation, but also realize the internal and external tube switching timing, and can also monitor various faults and safely implement fault protection. Summary of the invention

[0006] In view of this, the present invention provides a half-bridge drive circuit in a multi-level topology based on FPGA, the controller MCU outputs the original PWM pulse, and the signal isolation circuit completes the conversion and isolation of the control PWM pulse to the voltage required for the gate control signal of the main circuit power device, which is specifically implemented by the following technical solution.

[0007] In a first aspect, the present invention provides a half-bridge driving circuit in a multi-level topology based on FPGA, wherein the driving circuit comprises an MCU, an FPGA logic circuit and a signal isolation circuit connected in sequence, and the FPGA logic circuit comprises:

[0008] The Dly_1S submodule is used for 1S delay reset after power-on. The n_Reset signal it outputs maintains the L level within 1S after power-on, and outputs the H level after 1S to perform POR reset operation on other functional submodules;

[0009] The IO_Switch_IN1 submodule is used to filter the U_Pls0, D_Pls0, and Partner_Err0 of the MCU input FPGA logic circuit within 1S of power-on, and its output signals are U_Pls1, D_Pls1, and Partner_Err1;

[0010] IO_Switch_IN2 submodule is used to force the input signals U_Er_0, U_ErP_0, D_Er_0, and D_ErP_0 to the L level within 1S after power-on and to perform a direct pass operation after 1S. The corresponding four output signals are U_Er_1, U_ErP_1, D_Er_1, and D_ErP_1.

[0011] The IO_Switch_OUT1 submodule is used to force the L level in the first 1S of the output fault signal and directly operate after 1S. The corresponding output signals are U_Er_O0, U_ErP_O0, D_Er_O0, D_ErP_O0 and U_Er_O1, U_ErP_O1, D_Er_O1, D_ErP_O1;

[0012] The Fault_Check submodule is used to filter the external input fault signals U_Er_1, U_ErP_1, D_Er_1, D_ErP_1, Partner_Err1 after 1S delay processing and the internal and external tube pulse logic error signal Out_Iner_Err output by the Pulse_Check_Divide submodule, and output them to the MCU for fault signals U_Er_O0, U_ErP_O0, D_Er_O0, D_ErP_O0, and output three levels of high, medium and low according to the external fault type. Different fault signals are given to the Pulse_Check_Divide submodule for pulse processing of different types of faults. The corresponding fault types are Fault_H, Fault_M, and Fault_L, respectively. Fault_H is obtained by the short-circuit signals U_Er_0 and D_Er_0, Fault_M is obtained by the power supply fault signals U_ErP_0 and D_ErP_0, and Fault_L is obtained by the external fault signal Partner_Err1 and the internal and external tube pulse logic error signal Out_Iner_Err.

[0013] Among them, the input signals of the signal isolation circuit include U_Pls0 for the outer tube pulse signal, D_Pls0 for the inner tube pulse signal, U_Er_0 for the outer tube short circuit signal, U_ErP_0 for the outer tube power supply fault signal, D_Er_0 for the inner tube short circuit signal, and D_ErP_0 for the inner tube power supply fault signal; Partner_Err0 is the external fault signal.

[0014] As a preferred embodiment of the above technical solution, the FPGA logic circuit also includes a Fisrt_PosEdge_Switch sub-module. When the Dly_1S sub-module outputs n_Reset and sets it to H, and both the outer tube and inner tube pulses are in an L level state, the Fisrt_PosEdge_Switch sub-module is used to delay the first time after the first rising edge of the inner tube pulse to control the passage of the outer tube pulse.

[0015] As a preferred embodiment of the above technical solution, the FPGA logic circuit also includes a Pulse_DeJetter submodule, which is used for pulse dejittering, limiting the H-level pulse and the L-level pulse to pass pulses with a width less than the second time. The outer tube pulse after dejittering is U_Pls2, and the inner tube pulse is U_Pls23.

[0016] As a preferred embodiment of the above technical solution, the FPGA logic circuit also includes a Pulse_Order submodule, which is used to drive the shaping of the inner tube and outer tube pulses so that when the inner tube of the half-bridge power device in the multi-level is in the off state, the outer tube is not in the on state.

[0017] As a preferred embodiment of the above technical solution, Pre_Ordering of the Pulse_Order submodule is used to illustrate the processing when it is turned on. After the rising edge of the pulse D_Pls23 of the inner tube is delayed for the third time, the pulse of the outer tube is allowed to pass normally, and U_Pls4 is forced to be set to L level. The pulse passes normally until the falling edge of the inner tube pulse, and U_Pls4 is forced to be set to L level again.

[0018] As a preferred embodiment of the above technical solution, Post_Ordering of the Pulse_Order submodule is used to illustrate the processing during shutdown. According to the normal passage of the inner tube pulse before the rising edge of the outer tube pulse U_Pls4, the inner tube pulse is forced to be at H level, and after the outer tube falling edge is delayed for the fourth time, the inner tube pulse is allowed to pass normally again.

[0019] As a preferred embodiment of the above technical solution, the Pulse_Check_Divide submodule distributes the pulse data U_Pls4 processed by the Pulse_Order submodule through the inner and outer tube logic into the outer tube shutdown signal U_Pls_Off, the outer tube opening signal U_Pls_On, the outer tube on-pulse forced low signal U_Force_L, and the inner tube shutdown signal D_Pls_Off, the inner tube on-signal D_Pls_On, and the inner tube on-pulse forced low signal D_Force_L.

[0020] As a preferred embodiment of the above technical solution, the H level corresponding to the shutdown signal of the external tube makes the signal isolation circuit output a low voltage of -10V, the H level corresponding to the opening signal of the external tube makes the signal isolation circuit output a high voltage of +15V, and the H level corresponding to the forced low control signal of the opening pulse of the external tube makes the input opening signal U_Pls_On of the signal isolation circuit invalid;

[0021] The H level corresponding to the shutdown signal D_Pls_Off of the inner tube makes the signal isolation circuit output a low voltage of -10V, the H level corresponding to the opening signal D_Pls_On of the inner tube makes the signal isolation circuit output a high voltage of +15V, and the H level corresponding to the opening pulse forced low control signal D_Force_L of the inner tube makes the input opening signal D_Pls_On of the signal isolation circuit invalid;

[0022] Among them, U_Er_O1, U_ErP_O1, D_Er_O1, and D_ErP_O1 are respectively signals of the input signals U_Er_0, U_ErP_0, D_Er_0, and D_ErP_0 processed by the FPGA logic circuit and output to the MCU.

[0023] As a preferred embodiment of the above technical solution, when the n_Reset signal maintains an L level within 1S after power-on, the three signals U_Pls0, D_Pls0, and Partner_Err0 all maintain an L level;

[0024] When the n_Reset signal maintains the H level after 1S, the IO_Switch_IN1 submodule is in the pass-through mode.

[0025] In a second aspect, the present invention further provides a half-bridge driving method in a multi-level topology based on FPGA, which is applied to the above-mentioned half-bridge driving circuit in the multi-level topology based on FPGA, and the driving method comprises the following steps:

[0026] After power-on, initialize the FPGA logic circuit;

[0027] The driving circuit is delayed for 1S, the input port and the output port of the FPGA chip in the FPGA circuit are closed, and they are forced to be set to 0;

[0028] Performing fault judgment and pulse shaping operations on the driving circuit to determine whether there is a fault;

[0029] If not, the normal wave-generating function of opening the inner tube, opening the outer tube, closing the outer tube, and closing the inner tube is performed cyclically according to the pulse data;

[0030] If yes, the machine will enter the fault shutdown function of outer tube 0 pressure, delay X us, inner tube 0 pressure, delay Y us, outer tube and inner tube negative pressure, and then shut down.

[0031] The present invention provides a half-bridge driving circuit and method in a multi-level topology based on FPGA. By setting an MCU, an FPGA logic circuit and a signal isolation circuit, the FPGA logic circuit summarizes the fault signals of other circuits in the whole machine. When other circuits fail, the circuit is notified to perform a shutdown operation. In the process of switching from on to off and from off to on, there is a transition state in which both the on-voltage and off-voltage of the slice are invalid for a period of time, so as to solve the impact in the state conversion process, that is, soft shutdown, and realize the soft shutdown of the outer tube and the inner tube of the power main device in the multi-level topology first, then the inner tube in the case of a fault. The soft shutdown is still realized by the 0 voltage state, which is the same as the normal pulse. The difference from the normal pulse is that the starting and lasting time of the 0 voltage state of the outer tube and the inner tube pulse are different. The combinational logic and complex sequential logic functions can be realized at a low cost. The signal isolation circuit completes the conversion and isolation of the voltage required by the control PWM pulse to the gate control signal of the power device of the main circuit, realizes the peak voltage limitation and the switching timing of the inner and outer tubes, and can also monitor multiple faults and safely implement the gate driver of fault protection. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 The overall hardware block diagram corresponding to the half-bridge drive circuit in the FPGA-based multi-level topology provided by the present invention;

[0034] Figure 2 A functional schematic diagram of the Pulse_Order submodule provided by the present invention;

[0035] Figure 3 This is a schematic diagram of the normal function of the Pulse_Check_Divide submodule provided by the present invention;

[0036] Figure 4 A schematic diagram of the fault handling of the Pulse_Check_Divide submodule provided by the present invention;

[0037] Figure 5 A flow chart of a half-bridge driving method in a multi-level topology based on FPGA provided by the present invention;

[0038] Figure 6 This is a schematic diagram of the measured pulse waveform provided by the present invention. DETAILED DESCRIPTION

[0039] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0040] Traditional combinational sequential logic design is realized by combining multiple gate circuits with analog devices such as resistors and capacitors. However, for circuits composed of gate circuits and resistors and capacitors, only combinational logic and simple sequential logic can be realized, and it is difficult to realize complex sequential logic with strict time requirements. Due to the consistency problem between different devices, it is difficult to ensure the consistency of batch products, thus limiting the realization of excellent design ideas. Thanks to the mature application of domestic FPGA (field programmable gate array) devices, combinational logic and complex sequential logic functions can be realized at low cost.

[0041] See also Figure 1 The present invention provides a half-bridge driving circuit in a multi-level topology based on FPGA, the driving circuit comprises an MCU, an FPGA logic circuit and a signal isolation circuit connected in sequence, and the FPGA logic circuit comprises:

[0042] The Dly_1S submodule is used for 1S delay reset after power-on. The n_Reset signal it outputs maintains the L level within 1S after power-on, and outputs the H level after 1S to perform POR reset operation on other functional submodules;

[0043] The IO_Switch_IN1 submodule is used to filter the U_Pls0, D_Pls0, and Partner_Err0 of the MCU input FPGA logic circuit within 1S of power-on, and its output signals are U_Pls1, D_Pls1, and Partner_Err1;

[0044] IO_Switch_IN2 submodule is used to force the input signals U_Er_0, U_ErP_0, D_Er_0, and D_ErP_0 to the L level within 1S after power-on and to perform a direct pass operation after 1S. The corresponding four output signals are U_Er_1, U_ErP_1, D_Er_1, and D_ErP_1.

[0045] The IO_Switch_OUT1 submodule is used to force the L level in the first 1S of the output fault signal and directly operate after 1S. The corresponding output signals are U_Er_O0, U_ErP_O0, D_Er_O0, D_ErP_O0 and U_Er_O1, U_ErP_O1, D_Er_O1, D_ErP_O1;

[0046] The Fault_Check submodule is used to filter the external input fault signals U_Er_1, U_ErP_1, D_Er_1, D_ErP_1, Partner_Err1 after 1S delay processing and the internal and external tube pulse logic error signal Out_Iner_Err output by the Pulse_Check_Divide submodule, and output them to the MCU for fault signals U_Er_O0, U_ErP_O0, D_Er_O0, D_ErP_O0, and output three levels of high, medium and low according to the external fault type. Different fault signals are given to the Pulse_Check_Divide submodule for pulse processing of different types of faults. The corresponding fault types are Fault_H, Fault_M, and Fault_L, respectively. Fault_H is obtained by the short-circuit signals U_Er_0 and D_Er_0, Fault_M is obtained by the power supply fault signals U_ErP_0 and D_ErP_0, and Fault_L is obtained by the external fault signal Partner_Err1 and the internal and external tube pulse logic error signal Out_Iner_Err.

[0047] Among them, the input signals of the signal isolation circuit include U_Pls0 for the outer tube pulse signal, D_Pls0 for the inner tube pulse signal, U_Er_0 for the outer tube short circuit signal, U_ErP_0 for the outer tube power supply fault signal, D_Er_0 for the inner tube short circuit signal, and D_ErP_0 for the inner tube power supply fault signal; Partner_Err0 is the external fault signal.

[0048] In this embodiment, the FPGA logic circuit also includes a Fisrt_PosEdge_Switch submodule. When the Dly_1S submodule outputs n_Reset to H, and the outer tube and inner tube pulses are both in the L level state, the Fisrt_PosEdge_Switch submodule is used to delay the first time after the first rising edge of the inner tube pulse to control the passage of the outer tube pulse. The FPGA logic circuit also includes a Pulse_DeJetter submodule. The Pulse_DeJetter submodule is used for pulse de-jittering, and limits the width of both the H level pulse and the L level pulse to be less than the second time. The outer tube pulse after de-jittering is U_Pls2, and the inner tube pulse is U_Pls23. The FPGA logic circuit also includes a Pulse_Order submodule. The Pulse_Order submodule is used to drive the shaping of the inner tube and outer tube pulses so that when the power device of the half bridge in the multi-level is in the inner tube off state, the outer tube is not in the on state. When the n_Reset signal maintains an L level within 1 second after power-on, the three signals U_Pls0, D_Pls0, and Partner_Err0 all maintain an L level; when the n_Reset signal maintains an H level after 1 second, the IO_Switch_IN1 submodule is in a pass-through mode, wherein the first time is 3us and the second time is 1us.

[0049] It should be noted that each module uses the same clock signal "Clk" as the unified time base of the entire system. For the input signal of the entire system, "U_Pls0" is the external tube pulse signal, and "D_Pls0" is the internal tube pulse signal; "U_Er_0" is the external tube short circuit signal, and "U_ErP_0" is the external tube power supply fault signal; "D_Er_0" is the internal tube short circuit signal, and "D_ErP_0" is the internal tube power supply fault signal. These signals are all derived from the signal isolation circuit of the later stage of the present invention; "Partner_Err0" is an external fault signal, specifically, it is a summary of the fault signals of other circuits in the whole machine where this power main circuit is located, and is used to notify this circuit to shut down when other circuits fail. The output signals of the whole system are mainly divided into hardware drive signals and fault status output signals, among which "U_Pls_Off" is the shutdown signal of the external tube, and its H level can make the subsequent signal isolation circuit output a low voltage of -10V, "U_Pls_On" is the opening signal of the external tube, and its H level can make the subsequent signal isolation circuit output a high voltage of +15V, and "U_Force_L" is the open pulse forced low control signal of the external tube, and its H level can make the input opening signal "U_Pls_On" of the subsequent signal isolation circuit invalid (forced to L level); correspondingly, "D_Pls_Off", "D_Pls_On", and "D_Force_L" are control signals for the inner tube, and their functions are the same and will not be repeated here; and "U_Er_O1", "U_ErP_O1", "D_Er_O1", and "D_ErP_O1" are respectively the aforementioned "U_Er_0", "U_ErP_0", "D_Er_0", and "D_ErP_0" input signals processed by FPGA, and their function is to output to the MCU of the previous stage of the present invention for protection processing.

[0050] Specifically, the entire control logic is divided into multiple sub-modules, mainly as follows: the Dly_1S sub-module is a 1S delay reset after power-on, and its output n_Reset signal maintains an L level within 1S after power-on, and outputs an H level after 1S, which is used for the POR reset operation of other functional sub-modules; the IO_Switch_IN1 sub-module filters the "U_Pls0", "D_Pls0", and "Partner_Err0" input from the MCU to the FPGA within 1S after power-on, that is, when the "n_Reset" signal maintains an L level within 1S after power-on, the three signals all maintain an L low level ( Figure 1 Indicated by "0" in the figure), when the "n_Reset" signal maintains the H level after 1S, the submodule changes to the pass-through mode, that is, the output is equal to the input, corresponding to the three input signals, the output signals of this module are "U_Pls1", "D_Pls1", and "Partner_Err1";

[0051] Similarly, the IO_Switch_IN2 submodule forces "U_Er_0", "U_ErP_0", "D_Er_0", and "D_ErP_0" to be at L level within 1S after power-on, and performs direct-through operation after 1S. The corresponding four output signals are "U_Er_1", "U_ErP_1", "D_Er_1", and "D_ErP_1".

[0052] Similarly, the IO_Switch_OUT1 submodule is used to output the fault signal. The first 1S is forced to be L level, and the next 1S is direct operation. The corresponding input and output signals are "U_Er_O0", "U_ErP_O0", "D_Er_O0", "D_ErP_O0" and "U_Er_O1", "U_ErP_O1", "D_Er_O1", "D_ErP_O1"; in order to prevent the MCU end from being in the pulse state when power is on, and the front-end Dly_1S submodule n_Reset is set to H, the outer tube and the inner tube pulses are both in the L level state, and the lead The inner tube and the outer tube are turned on at the same time, so the Fisrt_PosEdge_Switch submodule is used to delay 3us after the first rising edge of the inner tube pulse to control the passage of the outer tube pulse (here 3us is only for functional description, and other reasonable values ​​are within the scope of application of the present invention); the Pulse_DeJetter submodule is used for pulse de-jittering. For both H-level pulses and L-level pulses, pulses with a width less than 1us are limited to pass (here 1us is only for functional description, and other reasonable values ​​are within the scope of application of the present invention). The outer tube pulse after de-jittering is "U_Pls2", and the inner tube pulse is "U_Pls23";

[0053] As mentioned above, the driving pulse of the inner and outer tubes of the multi-level half-bridge requires that the outer tube of the half-bridge power device cannot be in the on state when the inner tube is off. In other words, when turning on, the inner tube needs to be turned on first, and then the outer tube is turned on after a delay. When turning off, the outer tube is turned off first, and then the inner tube is turned off after a delay. This function is implemented by the Pulse_Order submodule.

[0054] Optionally, Pre_Ordering of the Pulse_Order submodule is used to illustrate the processing when it is turned on. After the rising edge of the pulse D_Pls23 of the inner tube is delayed for a third time, the pulse of the outer tube is allowed to pass normally, and U_Pls4 is forced to be set to the L level. The pulse passes normally until the falling edge of the inner tube pulse, and U_Pls4 is forced to be set to the L level again.

[0055] In this embodiment, Post_Ordering of the Pulse_Order submodule is used to illustrate the processing during shutdown. According to the normal passage of the inner tube pulse before the rising edge of the outer tube pulse U_Pls4, the inner tube pulse is forced to be at the H level, and after the outer tube falling edge is delayed for the fourth time, the inner tube pulse is allowed to pass normally again.

[0056] The Pulse_Check_Divide submodule distributes the pulse data U_Pls4 processed by the Pulse_Order submodule through the inner and outer tube logic into the outer tube shutdown signal U_Pls_Off, the outer tube opening signal U_Pls_On, the outer tube open pulse forced low signal U_Force_L, and the inner tube shutdown signal D_Pls_Off, the inner tube opening signal D_Pls_On, and the inner tube open pulse forced low signal D_Force_L. The H level corresponding to the outer tube shutdown signal makes the signal isolation circuit output a low voltage of -10V, the H level corresponding to the outer tube opening signal makes the signal isolation circuit output a high voltage of +15V, and the H level corresponding to the outer tube open pulse forced low control signal makes the input opening signal U_Pls_On of the signal isolation circuit invalid; the H level corresponding to the inner tube shutdown signal D_Pls_Off makes the signal isolation circuit output a low voltage of -10V, and the inner tube opening signal D_Pls_On The corresponding H level makes the signal isolation circuit output a high voltage of +15V, and the H level corresponding to the inner tube's open pulse forced low control signal D_Force_L makes the input opening signal D_Pls_On of the signal isolation circuit invalid; U_Er_O1, U_ErP_O1, D_Er_O1, D_ErP_O1 are respectively the input signals U_Er_0, U_ErP_0, D_Er_0, D_ErP_0 processed by the FPGA logic circuit and output to the MCU.

[0057] like Figure 2 As shown, Pulse_Order is divided into two functions: the leading edge and the trailing edge, which are responsible for opening and closing respectively. Figure 2 (2-1) Pre_Ordering in the figure is used to explain the processing when it is turned on. Specifically, the rising edge of the pulse (D_Pls23) of the inner tube is marked as point a. After the delay of #(T_Pre_dly) time to point b, the pulse of the outer tube is allowed to pass normally (U_Pls3→U_Pls4). In the time before point b, U_Pls4 is forced to be at the L level. The pulse passes normally until point c. At the falling edge of the inner tube pulse, U_Pls4 is forced to be at the L level again. This part can avoid turning on the outer tube when the inner tube is turned off. Figure 2((2-2)Post_Ordering in it is used to illustrate the processing when shutting down. For the aforementioned outer tube pulse U_Pls4, the inner tube pulse passes normally before the rising edge at point d (D_Pls23→D_Pls4). After point d, the inner tube pulse is forced to the H level, and the outer tube falls at point e. After a delay of point f of #(T_Post_dly), the inner tube pulse is allowed to pass normally again. This part can avoid the inner tube not being turned on when the outer tube is turned on. Among them, the third time is recorded as #(T_Pre_dly) and the fourth time is recorded as #(T_Post_dly).

[0058] Specifically, the Fault_Check submodule filters the external input fault signals "U_Er_1", "U_ErP_1", "D_Er_1", "D_ErP_1", "Partner_Err1" and the internal and external tube pulse logic error signal "Out_Iner_Err" output by Pulse_Check_Divide, and outputs the fault signals "U_Er_O0", "U_ErP_O0", "D_Er_O0", and "D_ErP_O0" to the MCU, and outputs three levels of high, medium and low according to the external fault type. Different fault signals are given to the Pulse_Check_Divide submodule for pulse processing of different types of faults, namely "Fault_H", "Fault_M" and "Fault_L". Among them, "Fault_H" is obtained by the short-circuit signal "U_Er_0" and "D_Er_0", "Fault_M" is obtained by the power supply fault signal "U_ErP_0" and "D_ErP_0", and "Fault_L" is obtained by the external fault signal "Partner_Err1" and the internal and external tube pulse logic error signal "Out_Iner_Err". The Pulse_Check_Divide submodule is responsible for distributing the pulse data "U_Pls4" and "D_Pls4" that have been processed by the internal and external tube logic of the front-end Pulse_Order submodule into the external tube shutdown signal "U_Pls_Off", the external tube opening signal "U_Pls_On", and the external tube open pulse forced low signal "U_Force_L", as well as the internal tube shutdown signal "D_Pls_Off", the internal tube opening signal "D_Pls_On", and the internal tube open pulse forced low signal "D_Force_L".

[0059] In addition, the external tube is used to illustrate the corresponding relationship between the pulse and the power device gate "G_Up" signal level after being processed by the subsequent hardware circuit. When "U_Pls_Off" is high, "G_Up" is a negative voltage, and when "U_Pls_On" is high, "G_Up" is a positive voltage. When "U_Pls_Off" and "U_Pls_On" are both low, "G_Up" is 0 voltage. The basic function is divided into two processes: opening ("ON") and closing ("OFF"). Taking the external tube as an example, the opening process is: Figure 3 At point a, the pulse "U_Pls4" is high level, and "U_Pls_Off" changes from high level to low level. After the delay T_dly_on time, Figure 3 At point b, "U_Pls_On" changes from low level to high level. During the T_dly_on period, both the shutdown signal and the open signal are in the "invalid" state, that is, the "0 voltage state". The shutdown process: Figure 3 At point c, the pulse "U_Pls4" is low level, and "U_Pls_On" changes from high level to low level. After the delay T_dly_off time, Figure 3 At point d, "U_Pls_Off" changes from low level to high level. During the T_dly_off time period, both the shutdown signal and the opening signal are in the "invalid" state, that is, the "0 voltage state";

[0060] In summary, the basic design principle of the present invention is that in the process of "on" to "off" and in the process of "off" to "on", there is a transition state in which both the on-voltage and off-voltage of the chip are "invalid" for a period of time, so as to solve the impact in the state conversion process, that is, "soft shutdown". In the event of a fault, the "soft shutdown of the outer tube first and the inner tube later" of the outer tube and the inner tube of the power main device is realized. Specifically, the soft shutdown is still realized by "0 voltage state" as in the normal pulse. The difference from the normal pulse is that the starting and duration of the "0 voltage state" of the outer tube and the inner tube pulse are different.

[0061] like Figure 4As shown in the figure, a serious fault "Fault_H" is used to illustrate. Assuming that a fault occurs at point a during normal pulse transmission, the on-signal "U_Pls_On" of the outer tube immediately changes from high level to low level, and the off-signal "U_Pls_Off" of the outer tube remains at a low level. In other words, the outer tube pulse enters the "0 voltage state" and is slowly turned off; the on-signal "D_Pls_On" of the inner tube at point a remains at a high level, and the off-signal "D_Pls_Off" of the inner tube remains at a low level, that is, the "positive pressure" on state; after a delay of X us, the on-signal "D_Pls_On" of the inner tube at point b changes to a low level, that is, it enters the "0 voltage state"; after a delay of Y At point c after us, the shutdown signal "U_Pls_Off" of the outer tube and the shutdown signal "D_Pls_Off" of the inner tube are both high level, and both the inner tube and the outer tube enter the "negative pressure" state, thus completing the fault shutdown operation; it should be emphasized that when the opening signal "U_Pls_On" of the outer tube turns to a low level at point a, "U_Force_L" will turn to a low level at the same time, and when the opening signal "D_Pls_On" of the outer tube turns to a low level at point b, "D_Force_L" will turn to a low level at the same time, ensuring that the opening signals of the outer tube and the inner tube will not turn to a high level again after the fault, thereby ensuring reliable judgment of the power device. The delays X us and Y us involved in the above process are not fixed to a certain value, and can be set according to different system voltage and current levels in actual applications; and because the other two low-severity faults "Fault_M" and "Fault_L" are handled in the same way, only the delays are different, so they are not repeated, but all delay values ​​are in the present invention.

[0062] See also Figure 5 The present invention also provides a half-bridge driving method in a multi-level topology based on FPGA, which is applied to the above-mentioned half-bridge driving circuit in the multi-level topology based on FPGA. The driving method comprises the following steps:

[0063] After power-on, initialize the FPGA logic circuit;

[0064] The driving circuit is delayed for 1S, the input port and the output port of the FPGA chip in the FPGA circuit are closed, and they are forced to be set to 0;

[0065] Performing fault judgment and pulse shaping operations on the driving circuit to determine whether there is a fault;

[0066] If not, the normal wave-generating function of opening the inner tube, opening the outer tube, closing the outer tube, and closing the inner tube is performed cyclically according to the pulse data;

[0067] If yes, the machine will enter the fault shutdown function of outer tube 0 pressure, delay X us, inner tube 0 pressure, delay Y us, outer tube and inner tube negative pressure, and then shut down.

[0068] In this embodiment, as mentioned above, after power-on, the FPGA chip is first initialized, mainly to set the working main frequency clock, perform initial level configuration on the special-purpose IO port, etc.; the second step is to delay for 1S, and this 1S time is to wait for the peripheral circuit to enter a stable state. During this period of time, the input and output ports are closed and forced to 0; after the 1S delay is completed, the third step is entered, and the fault judgment and pulse shaping are parallel operations. If there is no fault, the [normal wave transmission] function of "open inner tube" → "open outer tube" → "close outer tube" → "close inner tube" will be performed according to the pulse data cycle. If a fault occurs, the [fault shutdown] function of "external tube 0 pressure" → "delay X us" → "internal tube 0 pressure" → "delay Y us" → "external tube and inner tube negative pressure" is entered, and then the machine is shut down.

[0069] It should be noted that Figure 6 In order to measure the waveform data with a logic analyzer, the on / off logic of the internal and external tubes and the "0 pressure state" during on / off are intuitively displayed. At the same time, the 0 pressure delay and negative pressure shutdown logic when a fault occurs are also displayed. Figure 6 (6-1) in is the full cycle waveform. Figure 6 (6-2) is the pulse diagram when opening and closing. Figure 6 (6-3) in the figure is the pulse during a fault.

[0070] In all examples shown and described herein, any specific values ​​should be interpreted as merely exemplary and not as limiting, and thus other examples of the exemplary embodiments may have different values.

[0071] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0072] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A half-bridge driving circuit in a multi-level topology based on FPGA, characterized in that: The driving circuit includes an MCU, an FPGA logic circuit and a signal isolation circuit connected in sequence, and the FPGA logic circuit includes: The Dly_1S submodule is used for 1S delay reset after power-on. The n_Reset signal it outputs maintains the L level within 1S after power-on, and outputs the H level after 1S to perform POR reset operation on other functional submodules; The IO_Switch_IN1 submodule is used to filter the U_Pls0, D_Pls0, and Partner_Err0 of the MCU input FPGA logic circuit within 1S of power-on, and its output signals are U_Pls1, D_Pls1, and Partner_Err1; IO_Switch_IN2 submodule is used to force the input signals U_Er_0, U_ErP_0, D_Er_0, and D_ErP_0 to the L level within 1S after power-on and to perform a direct pass operation after 1S. The corresponding four output signals are U_Er_1, U_ErP_1, D_Er_1, and D_ErP_1. The IO_Switch_OUT1 submodule is used to force the fault signal to be at L level 1S before outputting it, and then directly operate after 1S. The corresponding output signals are U_Er_O0, U_ErP_O0, D_Er_1, D_ErP_1 and U_Er_O1, U_ErP_O1, D_Er_O1, D_ErP_O1; The Fault_Check submodule is used to filter the external input fault signals U_Er_1, U_ErP_1, D_Er_1, D_ErP_1, Partner_Err1 after 1S delay processing and the internal and external tube pulse logic error signal Out_Iner_Err output by the Pulse_Check_Divide submodule, and output them to the MCU for fault signals U_Er_O0, U_ErP_O0, D_Er_O0, D_ErP_O0, and output three levels of high, medium and low according to the external fault type. Different fault signals are given to the Pulse_Check_Divide submodule for pulse processing of different types of faults. The corresponding fault types are Fault_H, Fault_M, and Fault_L, respectively. Fault_H is obtained by the short-circuit signals U_Er_0 and D_Er_0, Fault_M is obtained by the power supply fault signals U_ErP_0 and D_ErP_0, and Fault_L is obtained by the external fault signal Partner_Err1 and the internal and external tube pulse logic error signal Out_Iner_Err. Among them, the input signals of the signal isolation circuit include U_Pls0 for the outer tube pulse signal, D_Pls0 for the inner tube pulse signal, U_Er_0 for the outer tube short circuit signal, U_ErP_0 for the outer tube power supply fault signal, D_Er_0 for the inner tube short circuit signal, and D_ErP_0 for the inner tube power supply fault signal; Partner_Err0 is the external fault signal.

2. The half-bridge driving circuit in a multi-level topology based on FPGA according to claim 1, characterized in that: The FPGA logic circuit also includes a Fisrt_PosEdge_Switch submodule. When the Dly_1S submodule outputs n_Reset and sets it to H, and both the outer tube and inner tube pulses are in an L level state, the Fisrt_PosEdge_Switch submodule is used to delay the first time after the first rising edge of the inner tube pulse to control the passage of the outer tube pulse.

3. The half-bridge driving circuit in a multi-level topology based on FPGA according to claim 2, characterized in that: The FPGA logic circuit also includes a Pulse_DeJetter submodule, which is used for pulse dejittering. The H-level pulse and the L-level pulse are limited to have a width less than the second time. The outer tube pulse after dejittering is U_Pls2, and the inner tube pulse is U_Pls23.

4. The half-bridge driving circuit in a multi-level topology based on FPGA according to claim 3, characterized in that: The FPGA logic circuit also includes a Pulse_Order submodule, which is used to drive the shaping of the inner tube and outer tube pulses so that when the inner tube of the power device of the half bridge in the multi-level is in the off state, the outer tube is not in the on state.

5. The half-bridge driving circuit in a multi-level topology based on FPGA according to claim 4, characterized in that: The Pre_Ordering of the Pulse_Order submodule is used to illustrate the processing when it is turned on. After the rising edge of the pulse D_Pls23 of the inner tube is delayed for the third time, the pulse of the outer tube is allowed to pass normally, and U_Pls4 is forced to be at the L level. The pulse passes normally until the falling edge of the inner tube pulse, and U_Pls4 is forced to be at the L level again.

6. The half-bridge driving circuit in a multi-level topology based on FPGA according to claim 4, characterized in that: Post_Ordering of the Pulse_Order submodule is used to illustrate the processing during shutdown. According to the normal passage of the inner tube pulse before the rising edge of the outer tube pulse U_Pls4, the inner tube pulse is forced to be at H level, and after the outer tube falling edge is delayed for the fourth time, the inner tube pulse is allowed to pass normally again.

7. The half-bridge driving circuit in a multi-level topology based on FPGA according to claim 1, characterized in that: The Pulse_Check_Divide submodule distributes the pulse data U_Pls4 processed by the Pulse_Order submodule through the inner and outer tube logic into the outer tube shutdown signal U_Pls_Off, the outer tube opening signal U_Pls_On, the outer tube on-pulse forced low signal U_Force_L, and the inner tube shutdown signal D_Pls_Off, the inner tube on-signal D_Pls_On, and the inner tube on-pulse forced low signal D_Force_L.

8. The half-bridge driving circuit in a multi-level topology based on FPGA according to claim 1, characterized in that: The H level corresponding to the off signal U_Pls_Off of the external tube makes the signal isolation circuit output a low voltage of -10V, the H level corresponding to the on signal U_Pls_On of the external tube makes the signal isolation circuit output a high voltage of +15V, and the H level corresponding to the on pulse forced low control signal U_Force_L of the external tube makes the input on signal U_Pls_On of the signal isolation circuit invalid; The H level corresponding to the shutdown signal D_Pls_Off of the inner tube makes the signal isolation circuit output a low voltage of -10V, the H level corresponding to the opening signal D_Pls_On of the inner tube makes the signal isolation circuit output a high voltage of +15V, and the H level corresponding to the opening pulse forced low control signal D_Force_L of the inner tube makes the input opening signal D_Pls_On of the signal isolation circuit invalid; Among them, U_Er_O1, U_ErP_O1, D_Er_O1, and D_ErP_O1 are respectively signals of the input signals U_Er_0, U_ErP_0, D_Er_0, and D_ErP_0 processed by the FPGA logic circuit and output to the MCU.

9. The half-bridge driving circuit in a multi-level topology based on FPGA according to claim 1, characterized in that: When the n_Reset signal maintains the L level within 1S after power-on, the three signals U_Pls0, D_Pls0, and Partner_Err0 all maintain the L level; When the n_Reset signal maintains the H level after 1S, the IO_Switch_IN1 submodule is in the pass-through mode.

10. A half-bridge driving method in a multi-level topology based on FPGA, characterized in that: Applied to the half-bridge driving circuit in the multi-level topology based on FPGA as claimed in any one of claims 1 to 9, the driving method comprises the following steps: After power-on, initialize the FPGA logic circuit; The driving circuit is delayed for 1S, the input port and the output port of the FPGA chip in the FPGA circuit are closed, and are forced to be set to 0; Performing fault judgment and pulse shaping operations on the driving circuit to determine whether there is a fault; If not, the normal wave-generating function of opening the inner tube, opening the outer tube, closing the outer tube, and closing the inner tube is performed cyclically according to the pulse data; If yes, the machine will enter the fault shutdown function of outer tube 0 pressure, delay X us, inner tube 0 pressure, delay Y us, outer tube and inner tube negative pressure, and then shut down.

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