Low-noise differential sampling phase-locked loop system and method with high-linearity sampling

Abstract

The invention provides a low-noise differential sampling phase-locked loop system and method with high-linearity sampling, and the system at least comprises a single-to-double circuit, a differential sampling phase discriminator, a voltage shifter and a multi-phase clock generation circuit, the single-to-double circuit converts an input single-ended reference signal into a differential reference signal, and the differential sampling phase discriminator outputs the differential reference signal to the multi-phase clock generation circuit; a differential reference signal is input into the differential sampling phase discriminator, the voltage offset device provides offset voltage for the differential sampling phase discriminator, and the multi-phase clock generation circuit is used for generating a three-phase non-overlapping clock serving as a sampling clock of the differential sampling phase discriminator, an offset control clock of the voltage offset device and a holding clock of the voltage offset device. The method is based on the system. Whether the digital clock is enabled or not is preset for the multi-phase clock generation circuit, the proportion of the offset capacitance of the voltage offset device to the total sampling capacitance is adjusted, the voltage offset device flexibly generates different offset voltages, phase noise deterioration caused by current source thermal noise injection is effectively relieved, and the sampling voltage linearity is improved.

Description

Technical Field

[0001] The present invention relates to the field of radio frequency integrated circuit design, and in particular to a low-noise differential sampling phase-locked loop system and method with high linear sampling. Background Art

[0002] The statements in this section merely provide background information related to the present disclosure and do not necessarily constitute prior art.

[0003] Phase-Locked Loop (PLL) frequency synthesizer is mainly used to generate stable and accurate output frequency, usually used to synchronize the frequency of input signal with the frequency of reference signal. Its basic principle is to compare the phase difference between input signal and reference signal, and adjust the frequency of output signal through feedback control to keep phase synchronization with reference signal.

[0004] As the core module of wireless communication and internal clock, the phase-locked loop frequency synthesizer has become a bottleneck restricting the overall performance of integrated wireless communication with the demand for low voltage, low power consumption and high integration. The pure spectrum, high frequency resolution, wide output frequency coverage and fast locking phase-locked loop have become bottlenecks restricting the overall performance of integrated wireless communication. It is of great significance to study high-performance phase-locked loop system. The urgent demand for high-performance phase-locked loop in wireless communication has spawned the research and development of several new phase-locked loop circuit structures.

[0005] Traditional phase-locked loops usually need to have the same sampling rate as the input signal to achieve accurate phase detection and frequency synthesis. As one of the types of phase-locked loops, the subsampling phase-locked loop (SSPLL) operates at a rate lower than the input signal sampling rate. Its basic principle is to use the high-frequency components of the input signal to obtain a low-frequency signal after subsampling, and then perform phase-locking operation on this low-frequency signal. Therefore, the subsampling phase-locked loop greatly suppresses the in-band phase noise with its high phase-lock gain and has no divider power consumption, but its phase-lock gain has poor robustness with process technology, power supply voltage, and temperature changes and is difficult to calibrate. For this reason, the divider circuit in the traditional phase-locked loop circuit is retained in the main loop of the sampling phase-locked loop, which can achieve high phase-lock gain while ensuring the accuracy and programmability of the phase-lock gain.

[0006] However, the voltage sampling phase detector has poor linearity, which causes high-frequency quantization noise aliasing in the fractional working mode, resulting in deterioration of phase noise and spurious performance. Although the charge-discharge sampling phase detector can greatly improve linearity and avoid high-frequency quantization noise aliasing in the fractional working mode, its operating range is limited and the current source thermal noise is introduced to dominate the phase noise of the phase detector.

[0007] In addition, the existing single-ended sampling phase-locked loop is very sensitive to power supply noise and common-mode noise caused by the buffer. Differential sampling can naturally resist common-mode noise, but the charge-discharge sampling phase detector has a narrow operating range and does not support differential operation. Summary of the invention

[0008] The object of the present invention is to provide a low-noise differential sampling phase-locked loop system and method with high linear sampling. By presetting whether the digital clock of the multi-phase clock generation circuit is enabled, the ratio of the offset capacitance of the voltage shifter to the total sampling capacitance is adjusted, so that the voltage shifter can flexibly generate different offset voltages, and then generate different current source conduction times, effectively alleviating the phase noise deterioration caused by the thermal noise injection of the current source and improving the linearity of the sampling voltage, so that the differential sampling phase detector can be configured as a differential working mode, thereby further suppressing the in-band noise with twice the phase detection gain, so that the system has good common-mode disturbance resistance.

[0009] The technical solution for achieving the purpose of the present invention is as follows:

[0010] In one aspect, the present invention provides a low-noise differential sampling phase-locked loop system with high linear sampling, comprising: a single-turn dual circuit, a differential sampling phase detector, a voltage shifter, and a multi-phase clock generation circuit;

[0011] The single-to-dual circuit converts the input single-ended reference signal into a differential reference signal;

[0012] The differential sampling phase detector is connected to the single-to-dual circuit, and the differential reference signal output by the single-to-dual circuit is input into the differential sampling phase detector;

[0013] The voltage shifter is connected to the differential sampling phase detector, and the voltage shifter provides an offset voltage for the differential sampling phase detector, and the offset voltage improves the phase noise by reducing the conduction time of the current source in the differential sampling phase detector, and enables the differential sampling phase detector to operate within a range with good linearity;

[0014] The multi-phase clock generating circuit is used to generate three-phase non-overlapping clocks as the sampling clock of the differential sampling phase detector, the shift control clock of the voltage shifter and the holding clock of the voltage shifter.

[0015] Based on one aspect, in one embodiment of the present invention, it further includes: a transconductance amplifier, a low-pass filter, a voltage-controlled oscillator and a multi-mode frequency divider;

[0016] The transconductance amplifier converts the holding voltage signal output by the voltage shifter and containing loop phase error information into a current signal;

[0017] The low-pass filter converts the current signal output by the transconductance amplifier into a voltage signal, and filters the high-frequency noise of the voltage signal to output a control voltage;

[0018] The voltage-controlled oscillator outputs an output signal of a corresponding frequency according to the control voltage output by the low-pass filter and its own voltage-controlled gain;

[0019] The multi-mode frequency divider divides the frequency of the output signal output by the voltage-controlled oscillator to obtain a frequency-divided signal;

[0020] The multi-phase clock generating circuit generates a three-phase non-overlapping clock according to the frequency-divided signal output by the multi-mode frequency divider.

[0021] Based on one aspect, in one embodiment of the present invention, the differential sampling phase detector includes a bias circuit, a charging type sampling phase detector and a discharging type sampling phase detector;

[0022] The bias circuit receives the bias voltage generated by the single-to-dual circuit as the P-terminal bias voltage of the charging type sampling phase detector, and the bias circuit generates the N-terminal bias voltage of the discharge type sampling phase detector through its self-bias;

[0023] The charging type sampling phase detector is used to compare the P-terminal bias voltage with the output of the multi-phase clock generation circuit. a phase difference between the clocks, and converting the phase difference into a first voltage;

[0024] The discharge type sampling phase detector is used to compare the N-terminal bias voltage with the output of the multi-phase clock generation circuit. The phase difference between the clocks is converted into a second voltage.

[0025] Based on one aspect, in one embodiment of the present invention, the bias circuit includes a PMOS tube Mp1, a PMOS tube Mp2, an NMOS tube Mn1, an NMOS tube Mn2, a decoupling capacitor C P and decoupling capacitor C N ;

[0026] The source of the PMOS tube Mp1 is connected to the power supply voltage, the gate of the PMOS tube Mp1 is connected to the ground potential, and the drain of the PMOS tube Mp1 is connected to the PMOS tube Mp2;

[0027] The source of the NMOS tube Mn1 is connected to the power supply voltage, the gate of the NMOS tube Mn1 is connected to the ground potential, and the drain of the NMOS tube Mn1 is connected to the NMOS tube Mn2;

[0028] The PMOS tube Mp2 is used to generate a bias current. The gate of the PMOS tube Mp2 is connected to a bias voltage VB generated by an external bandgap reference circuit, and is connected to the gate of the PMOS tube Mp4 to generate a charging current.

[0029] The NMOS tube Mn2 is used to generate a bias voltage. The drain of the NMOS tube Mn2 is connected to the drain of the PMOS tube Mp2. The gate and drain of the NMOS tube Mn2 are short-circuited into a diode connection to generate a gate bias voltage of the NMOS tube Mn4.

[0030] Decoupling capacitor C P , decoupling capacitor C N The second end of the decoupling capacitor C P , decoupling capacitor C N The first ends are respectively connected to the gates of the PMOS tube Mp2 and the NMOS tube Mn2, and are used to stabilize the bias voltage VB and the bias voltage IBN and filter out the noise of the PMOS tube Mp2 and the NMOS tube Mn2 respectively.

[0031] Based on one aspect, in one embodiment of the present invention, the charging type sampling phase detector includes: a PMOS tube Mp3, a PMOS tube Mp4, an NMOS tube Mn5, a capacitor C S,P , switch S 1P ;

[0032] The source of the PMOS tube Mp3 is connected to the power supply voltage, the drain of the PMOS tube Mp3 is connected to the source of the PMOS tube Mp4, and the gate of the PMOS tube Mp3 is connected to the P-terminal reference voltage REFP;

[0033] The gate of the PMOS tube Mp4 is connected to the bias voltage VB generated by the external bandgap reference circuit.

[0034] The drain of the NMOS tube Mn5 is connected to the drain of the PMOS tube Mp4, the gate of the NMOS tube Mn5 is connected to the P-terminal reference voltage REFP, and the source of the NMOS tube Mn5 is connected to the ground potential;

[0035] Capacitor C S,P The second end of the capacitor C S,P The first end is connected through the switch S 1P The drain of the current source tube Mp4 and the output sampling voltage V S,P .

[0036] Based on one aspect, in one embodiment of the present invention, the discharge type sampling phase detector includes: NMOS tube Mn3, NMOS tube Mn4, PMOS tube Mp5, capacitor C S,N and switch S 1N ;

[0037] The source of the NMOS tube Mn3 is connected to the ground potential, the drain of the NMOS tube Mn3 is connected to the source of the NMOS tube Mn4, and the gate of the NMOS tube Mn3 is connected to the P-terminal reference voltage REFN;

[0038] The gate and drain of the NMOS tube Mn2 are short-circuited into a diode connection to generate a gate bias voltage of the NMOS tube Mn4;

[0039] The source of the PMOS tube Mp5 is connected to the power supply voltage, the drain of the PMOS tube Mp5 is connected to the drain of the NMOS tube Mn4, and the gate of the PMOS tube Mp5 is connected to the P-end reference voltage REFN;

[0040] Capacitor C S,N The second end of the capacitor C S,N The first end is connected through the switch S 1N Connect the drain of NMOS tube Mn4 and the output sampling voltage V S,N .

[0041] The PMOS tube Mp2, the NMOS tube Mn2, the PMOS tube Mp4, and the NMOS tube Mn4 of the present invention are respectively current source tubes.

[0042] Based on one aspect, in one embodiment of the present invention, the voltage shifter includes: a first voltage shift circuit and a first holder, a second voltage shift circuit and a second holder;

[0043] The first voltage shift circuit outputs the multi-phase clock generation circuit according to the Clocks are generated in different configurations Three voltage offsets, VDD is the power supply voltage;

[0044] The first keeper is outputted by the multi-phase clock generating circuit. When the clock is high, the first voltage and Either offset voltage is passed to the holding capacitor;

[0045] The second voltage shift circuit outputs the multi-phase clock generation circuit according to the Different clock configurations can generate Three voltage offsets, VDD represents the power supply voltage;

[0046] The second keeper is outputted by the multi-phase clock generating circuit. When the clock is high, the second voltage and Either offset voltage is passed to the holding capacitor.

[0047] Based on one aspect, in one embodiment of the present invention, the first voltage shift circuit and the first holder are a P-terminal two-bit voltage shift circuit and a holder; the second voltage shift circuit and the second holder are an N-terminal two-bit voltage shift circuit and a holder;

[0048] The P-terminal two-bit voltage shift circuit and keeper include: NMOS tube Mn1, PMOS tube Mp1, NMOS tube Mn3, PMOS tube Mp3, capacitor C O1,P , capacitor C O2,P , switch S 2P and capacitor C H,P ;

[0049] The N-terminal two-bit voltage offset circuit and the keeper include: NMOS tube Mn2, PMOS tube Mp2, NMOS tube Mn4, PMOS tube Mp4, capacitor C O1,N , capacitor C O2,N , switch S 2N and capacitor C H,N ;

[0050] Capacitor C O1,P , capacitor C O2,P The first end is connected to the sampling voltage V S,P , capacitor C O1,P The second end of the capacitor C is connected to the source of the NMOS tube Mn1 and the drain of the PMOS tube Mp1. O2,P The second end of the capacitor C is connected to the source of the NMOS tube Mn3 and the drain of the PMOS tube Mp3 respectively; O1,N , capacitor C O2,N The first end is connected to the sampling voltage V S,N , capacitor C O1,N The second end of the capacitor C is connected to the source of the NMOS tube Mn2 and the drain of the PMOS tube Mp2. O2,N The second end of the capacitor C is connected to the source of the NMOS tube Mn4 and the drain of the PMOS tube Mp4 respectively; H,P , capacitor C H,N The second end of the capacitor C is connected to the ground potential. H,P The first end is connected to the output holding voltage V H,P , capacitor C H,N The first end is connected to the output holding voltage V H,N .

[0051] On the other hand, the present invention provides a low-noise differential sampling phase-locked loop method with high linear sampling, comprising:

[0052] The single-ended reference signal is converted into a differential reference signal and input into a differential sampling phase detector;

[0053] One of the three-phase non-overlapping clocks generated by the multi-phase clock generation circuit is used as a sampling clock of the differential sampling phase detector;

[0054] The voltage shifter provides an offset voltage for the differential sampling phase detector;

[0055] Two of the three-phase non-overlapping clocks generated by the multi-phase clock generation circuit serve as the offset control clock and the holding clock of the voltage shifter.

[0056] Based on another aspect, in one embodiment of the present invention, it also includes:

[0057] When the rising edge of the P-end reference clock and the falling edge of the N-end reference clock generated by the multi-phase clock generation circuit arrive, the differential sampling phase detector starts sampling, and the PMOS tube Mp4 starts to supply the capacitor C S,P Charging, NMOS tube Mn4 starts to supply capacitor C S,N Discharge, P terminal sampling node voltage V S,P Starts to rise, N-terminal sampling node voltage V S,N Start to descend;

[0058] As the sampling clock of the differential sampling phase detector When the falling edge arrives, the sampling ends and the voltage V S,P and the N-terminal sampling node voltage V S,N Keep;

[0059] Offset-controlled clock as voltage shifter When the rising edge arrives, the charge is injected into the capacitor C O1,P , capacitor C O1,N , capacitor C O2,P , capacitor C O2,N , P terminal sampling node voltage V S,P Generate an upward voltage step, N-terminal sampling node voltage V S,N Produces a downward voltage step;

[0060] Holding Clock as Voltage Shifter When the rising edge arrives, the P terminal sampling node voltage V S,P Transferred to the holding capacitor C H,P , N-terminal sampling node voltage V S,N Transferred to the holding capacitor C H,N ;

[0061] As the sampling clock of the differential sampling phase detector When the rising edge arrives, the P terminal sampling node voltage V S,P and the N-terminal sampling node voltage V S,N Hold to start resetting.

[0062] Compared with the prior art, the present invention has the following beneficial effects:

[0063] The present invention presets whether the digital clock is enabled for the multi-phase clock generation circuit to adjust the ratio of the offset capacitance of the voltage shifter to the total sampling capacitance, so that the voltage shifter can flexibly generate different offset voltages, and then generate different current source conduction times, effectively alleviating the phase noise deterioration caused by the thermal noise injection of the current source and improving the sampling voltage linearity, so that the differential sampling phase detector can be configured as a differential working mode, thereby further suppressing the in-band noise with twice the phase detection gain, so that the system has good common-mode disturbance resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 A circuit structure diagram of a low-noise differential sampling phase-locked loop system with high linear sampling provided by an embodiment of the present invention;

[0065] Figure 2 A circuit diagram of a differential sampling phase detector provided by an embodiment of the present invention;

[0066] Figure 3 A circuit diagram of a voltage shifter provided by an embodiment of the present invention;

[0067] Figure 4 A circuit diagram of a switch unit provided in an embodiment of the present invention;

[0068] Figure 5 The present invention provides a timing diagram of the operation of the differential sampling phase detector and the voltage shifter provided in the embodiment of the present invention. DETAILED DESCRIPTION

[0069] The present invention is described in detail below in conjunction with the various embodiments shown in the accompanying drawings, but it should be noted that these embodiments are not limitations of the present invention, and any equivalent transformations or substitutions in functions, methods, or structures made by ordinary technicians in the field based on these embodiments are all within the scope of protection of the present invention.

[0070] See also Figure 1 , Figure 1A circuit structure diagram of a low-noise differential sampling phase-locked loop system with high linear sampling provided by an embodiment of the present invention. A low-noise differential sampling phase-locked loop system with high linear sampling provided by an embodiment of the present invention includes: a single-to-dual circuit, a differential sampling phase detector, a voltage shifter, a transconductance amplifier, a low-pass filter, a voltage-controlled oscillator, a multi-mode frequency divider, and a multi-phase clock generation circuit. Among them: the single-to-dual circuit converts the input single-ended reference signal into a differential reference signal. The differential sampling phase detector is connected to the single-to-dual circuit, and the differential reference signal output by the single-to-dual circuit is input to the differential sampling phase detector. The voltage shifter is connected to the differential sampling phase detector, and the voltage shifter provides an offset voltage for the differential sampling phase detector. The offset voltage improves the phase noise by reducing the conduction time of the current source in the differential sampling phase detector, and enables the differential sampling phase detector to work within a range with good linearity. The multi-phase clock generation circuit is used to generate a three-phase non-overlapping clock as a sampling clock of the differential sampling phase detector, an offset control clock of the voltage shifter, and a holding clock of the voltage shifter. The transconductance amplifier converts the hold voltage signal output by the voltage shifter containing the loop phase error information into a current signal. The low-pass filter converts the current signal output by the transconductance amplifier into a voltage signal, and filters the high-frequency noise of the voltage signal to output the control voltage. The voltage-controlled oscillator outputs an output signal of the corresponding frequency according to the control voltage output by the low-pass filter and its own voltage-controlled gain. The multi-mode divider divides the output signal output by the voltage-controlled oscillator to obtain a divided signal; the multi-phase clock generation circuit generates a three-phase non-overlapping clock according to the divided signal output by the multi-mode divider.

[0071] The differential sampling phase detector of the embodiment of the present invention comprises a bias circuit, a charging sampling phase detector and a discharging sampling phase detector; the bias circuit receives the bias voltage generated by the single-to-dual circuit as the P-terminal bias voltage of the charging sampling phase detector, and the bias circuit generates the N-terminal bias voltage of the discharging sampling phase detector through its self-bias; the charging sampling phase detector is used to compare the P-terminal bias voltage with the output of the multi-phase clock generation circuit. The phase difference between the clocks is converted into a first voltage; the discharge type sampling phase detector is used to compare the N-terminal bias voltage and the multi-phase clock generation circuit output The phase difference between the clocks is converted into a second voltage.

[0072] See also Figure 2 , Figure 2 The circuit diagram of the differential sampling phase detector provided by the embodiment of the present invention, the above-mentioned bias circuit includes PMOS tube Mp1, PMOS tube Mp2, NMOS tube Mn1, NMOS tube Mn2, decoupling capacitor C P and decoupling capacitor C N; The source of the PMOS tube Mp1 is connected to the power supply voltage, the gate of the PMOS tube Mp1 is grounded, and the drain of the PMOS tube Mp1 is connected to the PMOS tube Mp2; the source of the NMOS tube Mn1 is connected to the power supply voltage, the gate of the NMOS tube Mn1 is grounded, and the drain of the NMOS tube Mn1 is connected to the NMOS tube Mn2; the PMOS tube Mp2 is used to generate a bias current, the gate of the PMOS tube Mp2 is connected to the bias voltage VB generated by the external bandgap reference circuit, and it is connected to the gate of the PMOS tube Mp4 to generate a charging current; the NMOS tube Mn2 is used to generate a bias voltage, the drain of the NMOS tube Mn2 is connected to the drain of the PMOS tube Mp2, and the gate and drain of the NMOS tube Mn2 are short-circuited into a diode connection form to generate a gate bias voltage of the NMOS tube Mn4; the decoupling capacitor C P , decoupling capacitor C N The second end of the decoupling capacitor C P , decoupling capacitor C N The first ends are respectively connected to the gates of the PMOS tube Mp2 and the NMOS tube Mn2, and are used to stabilize the bias voltage VB and the bias voltage IBN and filter out the noise of the PMOS tube Mp2 and the NMOS tube Mn2 respectively.

[0073] See also Figure 2 , Figure 2 The circuit diagram of the differential sampling phase detector provided by the embodiment of the present invention, the charging type sampling phase detector comprises: a PMOS tube Mp3, a PMOS tube Mp4, an NMOS tube Mn5, a capacitor C S,P , switch S 1P The source of the PMOS tube Mp3 is connected to the power supply voltage, the drain of the PMOS tube Mp3 is connected to the source of the PMOS tube Mp4, and the gate of the PMOS tube Mp3 is connected to the P-terminal reference voltage REFP; the gate of the PMOS tube Mp4 is connected to the bias voltage VB generated by the external bandgap reference circuit, the drain of the NMOS tube Mn5 is connected to the drain of the PMOS tube Mp4, the gate of the NMOS tube Mn5 is connected to the P-terminal reference voltage REFP, and the source of the NMOS tube Mn5 is grounded; the capacitor C S,P The second end of the capacitor C S,P The first end is connected through the switch S 1P The drain of the current source tube Mp4 and the output sampling voltage V S,P .

[0074] See also Figure 2 , Figure 2 The circuit diagram of the differential sampling phase detector provided by the embodiment of the present invention, the above-mentioned discharge type sampling phase detector includes: NMOS tube Mn3, NMOS tube Mn4, PMOS tube Mp5, capacitor C S,N and switch S 1N; The source of the NMOS tube Mn3 is connected to the ground potential, the drain of the NMOS tube Mn3 is connected to the source of the NMOS tube Mn4, and the gate of the NMOS tube Mn3 is connected to the P-terminal reference voltage REFN; the gate and drain of the NMOS tube Mn2 are short-circuited into a diode connection form to generate a gate bias voltage of the NMOS tube Mn4; the source of the PMOS tube Mp5 is connected to the power supply voltage, the drain of the PMOS tube Mp5 is connected to the drain of the NMOS tube Mn4, and the gate of the PMOS tube Mp5 is connected to the P-terminal reference voltage REFN; the capacitor C S,N The second end of the capacitor C S,N The first end is connected through the switch S 1N Connect the drain of NMOS tube Mn4 and the output sampling voltage V S,N .

[0075] It should be noted that the PMOS tube Mp2, the NMOS tube Mn2, the PMOS tube Mp4, and the NMOS tube Mn4 of the embodiment of the present invention are current source tubes respectively.

[0076] Please continue reading Figure 1 In order to illustrate how the low noise differential sampling phase-locked loop system of the embodiment of the present invention improves linearity and phase noise, the open-loop transfer function G(s) and the closed-loop transfer function H(s) of the low noise differential sampling phase-locked loop system of the embodiment of the present invention can be expressed as:

[0077]

[0078]

[0079] Then its loop bandwidth BW and phase margin PM can be approximately expressed as:

[0080]

[0081]

[0082] Among them, K DSPD represents the phase gain of the differential sampling phase detector, gm represents the transconductance of the transconductance amplifier, and Z LF represents the impedance of the loop filter, K VCO represents the voltage control gain of the voltage control circuit, N represents the frequency division ratio, BW represents the loop bandwidth, R represents the loop filter compensation resistor, ω c ,ω z ,ω p3 are the wide-path bandwidth, zero position, and non-zero third pole position in angular frequency form, respectively.

[0083] For a single-ended sampling phase detector, the phase detector gain expression is:

[0084]

[0085] Among them, SR REF represents the sampling voltage slew rate, t res represents the remaining charge and discharge time under the locked state, i.e. the current source conduction time, f REF Indicates the reference frequency.

[0086] For the differential sampling phase detector, the phase gain expression is:

[0087]

[0088] For a differential sampling phase detector, its phase noise is mainly composed of two parts: current thermal noise and sampling circuit KT / C noise. Among them, K is the Boltzmann constant, T is the Kelvin temperature, and C is the capacitance.

[0089] For the KT / C noise of differential two-stage master-slave sampling, if the total size of the sampling capacitor and offset capacitor at the P and N ends is C S , keep the capacitance value C H , sampling clock and offset control clock Inject C S The noise voltage is equal to (KT / C S ) 1 / 2 , corresponding to the charge (KTC S ) 1 / 2 , the noise charge in When the clock edge arrives, it is shared to capacitor C H , generating noise voltage (KT / C S ) 1 / 2 / (C S +C H ), the square of the noise voltage plus the Clock Injection C H The thermal noise of the differential sampling phase detector is the remaining charge and discharge time t after locking. res Determined by, the total output noise can be expressed as:

[0090]

[0091] According to the closed-loop transfer function of the differential sampling phase-locked loop in equation (2), the noise transfer function expression from the differential sampling phase detector noise to the output can be given as:

[0092]

[0093] Therefore, the noise contributed by the differential sampling phase detector at the output of the phase-locked loop can be expressed as:

[0094]

[0095] Similarly, the noise contributed by the transconductance amplifier at the output of the phase-locked loop can be expressed as:

[0096]

[0097] According to equations (4) and (5), the phase detector gain of differential sampling is twice that of single-ended sampling, so the differential sampling phase detector and its back-end circuit have a 6dB phase noise optimization in the transfer function. Since differential sampling doubles the phase detector noise source, it brings a 3dB noise improvement to the differential sampling phase detector noise.

[0098] The two-stage master-slave sampler actually forms a switched capacitor filter, which will introduce an extra pole and seriously affect the loop stability. According to the charge conservation relationship, V S and V H The voltage transmission relationship of the node can be expressed as:

[0099]

[0100] For an accurate solution to this pole, a z-domain analysis method must be used. If the total capacitance of the sampling node and the holding node satisfies V S and V H The voltage transmission relationship of the node can be rewritten as:

[0101]

[0102] Therefore, the introduced pole can be expressed as ω p,s =-ln(1-α)·f s , then the phase margin of the differential sampling phase-locked loop should be rewritten as:

[0103]

[0104] To ensure that the additional pole does not affect the phase margin, ω must be satisfied. p,s >10ω c , then the total capacitance of the sampling node C S and the total capacitance C of the holding node H Must meet C S >>C H Therefore, the KT / C noise of the differential sampling phase detector is mainly caused by the holding capacitor C H The total noise can be approximately expressed as:

[0105]

[0106] For the sampling circuit, a certain sampling accuracy must be guaranteed. The switched capacitor sampling circuit charges the capacitor through the switch on-resistance, generating an exponential response. The time required to reach the final value within 0.1% error is called 0.1% stabilization time t s To ensure a 0.1% stabilization time, t S ≈7R on C S , so half a clock cycle must be the time constant R on C S In order to obtain low noise, a large capacitor must be used, but the stabilization time becomes longer, that is, the sampling accuracy is reduced. Therefore, the value of the total capacitance of the sampling node is a compromise between sampling accuracy and noise.

[0107] When the bias control clock is disabled, the bias capacitor is equivalent to grounding; when the bias capacitor is enabled, the bias control clock When the edge arrives, charge is injected into the bias capacitor. According to the charge conservation relationship, we can get:

[0108] C O VDD=C S ΔV (15)

[0109] Among them, C O is the effective bias capacitance, C S is the total capacitance of the sampling node, and VDD is the power supply voltage. If the effective bias capacitance C O The total capacitance C of the sampling node S The proportional relationship is expressed as The bias voltage can be expressed as ΔV = β·VDD. If the sampling capacitor and the bias capacitor satisfy the proportional relationship (C S,P =C S,N ):(C O1,P =C O1,N ):(C O2,P =C O2,N )=5:2:1, When the two bits of enable terminals [1:0] are configured as (0,1), (1,0), and (1,1), the offset voltages are

[0110] In the locked state, the voltage of the sampling node can be expressed as If the offset voltage is Remaining charge and discharge time t res If the switch S is reduced by half, the noise of the differential sampling phase detector is improved by 6dB. 1P and switch S 1N At the sampling node, rise or fall to During this period, the node V S,P The voltage at node V S,NThe voltage of the current source tube Mp4 and the current source tube Mn4 is reduced, and the drain-source voltage of the current source tube Mp4 and the current source tube Mn4 is reduced, making it easy for them to enter the linear region. Therefore, the bias technology prevents the current source tube Mp4 and the current source tube Mn4 from entering the linear region, which greatly improves the linearity of the differential sampling phase detector.

[0111] The voltage shifter in the embodiment of the present invention comprises: a first voltage shift circuit and a first holder, a second voltage shift circuit and a second holder; the first voltage shift circuit outputs a clock according to the multi-phase clock generating circuit; Clocks are generated in different configurations Three voltage offsets, VDD is the power supply voltage; the first keeper is at the output of the multi-phase clock generation circuit When the clock is high, the first voltage and Any offset voltage is transmitted to the holding capacitor; the second voltage offset circuit is based on the output of the multi-phase clock generation circuit Different clock configurations can generate Three voltage offsets, VDD represents the power supply voltage; the second keeper is at the output of the multi-phase clock generation circuit When the clock is high, the second voltage and Either offset voltage is passed to the holding capacitor.

[0112] See also Figure 3 , Figure 3 A circuit diagram of a voltage shifter provided in an embodiment of the present invention. The first voltage shift circuit and the first retainer are a two-bit voltage shift circuit and retainer at the P end; the second voltage shift circuit and the second retainer are a two-bit voltage shift circuit and retainer at the N end; wherein: the two-bit voltage shift circuit and retainer at the P end include: NMOS tube Mn1, PMOS tube Mp1, NMOS tube Mn3, PMOS tube Mp3, capacitor C O1,P , capacitor C O2,P , switch S 2P and capacitor C H,P The N-terminal two-bit voltage offset circuit and the keeper include: NMOS tube Mn2, PMOS tube Mp2, NMOS tube Mn4, PMOS tube Mp4, capacitor C O1,N , capacitor C O2,N , switch S 2N and capacitor C H,N ; Capacitor C O1,P , capacitor C O2,P The first end is connected to the sampling voltage V S,P , capacitor C O1,P The second end of the capacitor C is connected to the source of the NMOS tube Mn1 and the drain of the PMOS tube Mp1. O2,PThe second end of the capacitor C is connected to the source of the NMOS tube Mn3 and the drain of the PMOS tube Mp3 respectively; O1,N , capacitor C O2,N The first end is connected to the sampling voltage V S,N , capacitor C O1,N The second end of the capacitor C is connected to the source of the NMOS tube Mn2 and the drain of the PMOS tube Mp2. O2,N The second end of the capacitor C is connected to the source of the NMOS tube Mn4 and the drain of the PMOS tube Mp4 respectively; H,P , capacitor C H,N The second end of the capacitor C is connected to the ground potential. H,P The first end is connected to the output holding voltage V H,P , capacitor C H,N The first end is connected to the output holding voltage V H,N .

[0113] See also Figure 4 , Figure 4 A circuit diagram of a switch unit provided in an embodiment of the present invention. Figure 4 The switch unit is Figure 3 Switch S 2P and switch S 2N ,use Figure 4 The symbol of the switch unit replaces Figure 3 Switch S 2P and switch S 2N . Figure 4 The switch unit selects PMOS tubes of the same size and connects them in parallel, and NMOS tubes in series so that the effective size ratio of the two is 3:1, so as to enhance the ability of the PMOS tube to transmit high voltage, and the redundant NMOS tubes are used as dummy tubes to offset clock feedthrough and charge injection, and as capacitors to balance the clock loads driving the NMOS tubes and the PMOS tubes; the switch circuit includes: PMOS tubes Mp1, PMOS tubes Mp2 and PMOS tubes Mp3, NMOS tubes Mn1, NMOS tubes Mn2 and NMOS tubes Mn3; wherein the gate of the PMOS tube Mp2 is connected to the gate of the PMOS tube Mp1, the gate of the PMOS tube Mp3 All are connected to the clock signal CKB, the drain of the PMOS tube Mp2 is connected to the source of the PMOS tube Mp3 and the source of the PMOS tube Mp1, that is, the input A terminal, and the source of the PMOS tube Mp2 is connected to the drain of the PMOS tube Mp1 and the drain of the PMOS tube Mp3, that is, the output B terminal; the gate of the NMOS tube Mn2 and the gate of the NMOS tube Mn2 and the PMOS tube Mn3 are all connected to the clock signal CK, the source of the NMOS tube Mn2 is connected to the drain and source of the NMOS tube Mn1, that is, the input A terminal, and the drain of the NMOS tube Mn2 is connected to the source and drain of the NMOS tube Mn3, that is, the output B terminal.

[0114] See also Figure 5 , Figure 5 The working timing diagram of the differential sampling phase detector and the voltage shifter provided in the embodiment of the present invention. When the reference clock at the P end rises and the reference clock at the N end falls, the differential sampling phase detector starts sampling, and the current source tube Mp4 starts to supply the capacitor C S,P Charging, current source tube Mn4 starts to supply capacitor C S,N Discharge, P terminal sampling node voltage V S,P Starts to rise, N-terminal sampling node voltage V S,N starts to fall; when the sampling clock When the falling edge arrives, the sampling ends and the voltage V S,P and the N-terminal sampling node voltage V S,N Hold; when voltage offset controls clock When the rising edge arrives, the charge is injected into the offset capacitor C O1,P , C O1,N , C O2,P , C O2,N , P terminal sampling node voltage V S,P Generate an upward voltage step, N-terminal sampling node voltage V S,N Generates a downward voltage step; while holding the clock When the rising edge arrives, the P terminal sampling node voltage V S,P Transferred to the holding capacitor C H,P , N-terminal sampling node voltage V S,N Transferred to the holding capacitor C H,N ; When the sampling clock When the rising edge arrives, the P terminal sampling node voltage V S,P and the N-terminal sampling node voltage V S,N Hold to start resetting.

[0115] An embodiment of the present invention also provides a low-noise differential sampling phase-locked loop method with high linear sampling, comprising: converting a single-ended reference signal into a differential reference signal and inputting it into a differential sampling phase detector; using one of the three-phase non-overlapping clocks generated by a multi-phase clock generating circuit as a sampling clock for the differential sampling phase detector; a voltage shifter providing an offset voltage for the differential sampling phase detector; and using two of the three-phase non-overlapping clocks generated by the multi-phase clock generating circuit as an offset control clock and a holding clock for the voltage shifter.

[0116] When the rising edge of the P-end reference clock and the falling edge of the N-end reference clock generated by the multi-phase clock generation circuit arrive, the differential sampling phase detector starts sampling, and the PMOS tube Mp4 starts to supply the capacitor C S,P Charging, NMOS tube Mn4 starts to supply capacitor C S,N Discharge, P terminal sampling node voltage V S,P Starts to rise, N-terminal sampling node voltage V S,NStarts to fall; serves as the sampling clock for the differential sampling phase detector When the falling edge arrives, the sampling ends and the voltage V S,P and the N-terminal sampling node voltage V S,N Hold; offset control clock as voltage shifter When the rising edge arrives, the charge is injected into the capacitor C O1,P , capacitor C O1,N , capacitor C O2,P , capacitor C O2,N , P terminal sampling node voltage V S,P Generate an upward voltage step, N-terminal sampling node voltage V S,N Generates a downward voltage step; acts as a holding clock for a voltage shifter When the rising edge arrives, the P terminal sampling node voltage V S,P Transferred to the holding capacitor C H,P , N-terminal sampling node voltage V S,N Transferred to the holding capacitor C H,N ; As the sampling clock of the differential sampling phase detector When the rising edge arrives, the P terminal sampling node voltage V S,P and the N-terminal sampling node voltage V S,N Hold to start resetting.

[0117] The embodiment of the present invention presets whether the digital clock is enabled for the multi-phase clock generation circuit to adjust the ratio of the offset capacitance of the voltage shifter to the total sampling capacitance, so that the voltage shifter can flexibly generate different offset voltages and then generate different current source conduction times, effectively alleviating the phase noise degradation caused by the thermal noise injection of the current source and improving the sampling voltage linearity, so that the differential sampling phase detector can be configured as a differential working mode, thereby further suppressing the in-band noise with twice the phase detection gain, so that the system has good common-mode disturbance resistance.

[0118] The terms "first" and "second" in this specification are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0119] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0120] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in a claim. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0121] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A low noise differential sampling phase locked loop system with high linear sampling, characterized in that: include: Single-to-dual circuits, differential sampling phase detectors, voltage shifters, and multi-phase clock generation circuits; The single-to-dual circuit converts the input single-ended reference signal into a differential reference signal; The differential sampling phase detector is connected to the single-to-dual circuit, and the differential reference signal output by the single-to-dual circuit is input into the differential sampling phase detector; The voltage shifter is connected to the differential sampling phase detector, and the voltage shifter provides an offset voltage for the differential sampling phase detector, and the offset voltage improves the phase noise by reducing the conduction time of the current source in the differential sampling phase detector, and enables the differential sampling phase detector to operate within a range with good linearity; The multi-phase clock generating circuit is used to generate three-phase non-overlapping clocks as the sampling clock of the differential sampling phase detector, the shift control clock of the voltage shifter and the holding clock of the voltage shifter.

2. A low noise differential sampling phase locked loop system with high linear sampling according to claim 1, characterized in that: Also includes: transconductance amplifiers, low-pass filters, voltage-controlled oscillators, and multi-mode frequency dividers; The transconductance amplifier converts the holding voltage signal output by the voltage shifter and containing loop phase error information into a current signal; The low-pass filter converts the current signal output by the transconductance amplifier into a voltage signal, and filters the high-frequency noise of the voltage signal to output a control voltage; The voltage-controlled oscillator outputs an output signal of a corresponding frequency according to the control voltage output by the low-pass filter and its own voltage-controlled gain; The multi-mode frequency divider divides the frequency of the output signal output by the voltage-controlled oscillator to obtain a frequency-divided signal; The multi-phase clock generating circuit generates a three-phase non-overlapping clock according to the frequency-divided signal output by the multi-mode frequency divider.

3. The low-noise differential sampling phase-locked loop system with high linear sampling according to claim 1, characterized in that: The differential sampling phase detector comprises a bias circuit, a charging type sampling phase detector and a discharging type sampling phase detector; The bias circuit receives the bias voltage generated by the single-to-dual circuit as the P-terminal bias voltage of the charging type sampling phase detector, and the bias circuit generates the N-terminal bias voltage of the discharge type sampling phase detector through its self-bias; The charging type sampling phase detector is used to compare the P-terminal bias voltage with the output of the multi-phase clock generation circuit. a phase difference between the clocks, and converting the phase difference into a first voltage; The discharge type sampling phase detector is used to compare the N-terminal bias voltage with the output of the multi-phase clock generation circuit. The phase difference between the clocks is converted into a second voltage.

4. A low-noise differential sampling phase-locked loop system with high linear sampling according to claim 3, characterized in that: The bias circuit includes a PMOS tube Mp1, a PMOS tube Mp2, an NMOS tube Mn1, an NMOS tube Mn2, a decoupling capacitor C P and decoupling capacitor C N ; The source of the PMOS tube Mp1 is connected to the power supply voltage, the gate of the PMOS tube Mp1 is connected to the ground potential, and the drain of the PMOS tube Mp1 is connected to the PMOS tube Mp2; The source of the NMOS tube Mn1 is connected to the power supply voltage, the gate of the NMOS tube Mn1 is connected to the ground potential, and the drain of the NMOS tube Mn1 is connected to the NMOS tube Mn2; The PMOS tube Mp2 is used to generate a bias current. The gate of the PMOS tube Mp2 is connected to a bias voltage VB generated by an external bandgap reference circuit, and is connected to the gate of the PMOS tube Mp4 to generate a charging current. The NMOS tube Mn2 is used to generate a bias voltage. The drain of the NMOS tube Mn2 is connected to the drain of the PMOS tube Mp2. The gate and drain of the NMOS tube Mn2 are short-circuited into a diode connection to generate a gate bias voltage of the NMOS tube Mn4. Decoupling capacitor C P , decoupling capacitor C N The second end of the decoupling capacitor C P , decoupling capacitor C N The first ends are respectively connected to the gates of the PMOS tube Mp2 and the NMOS tube Mn2, and are used to stabilize the bias voltage VB and the bias voltage IBN and filter out the noise of the PMOS tube Mp2 and the NMOS tube Mn2 respectively.

5. The low-noise differential sampling phase-locked loop system with high linear sampling according to claim 3, characterized in that: The charging type sampling phase detector comprises: a PMOS tube Mp3, a PMOS tube Mp4, an NMOS tube Mn5, a capacitor C S,P , switch S 1P ; The source of the PMOS tube Mp3 is connected to the power supply voltage, the drain of the PMOS tube Mp3 is connected to the source of the PMOS tube Mp4, and the gate of the PMOS tube Mp3 is connected to the P-terminal reference voltage REFP; The gate of the PMOS tube Mp4 is connected to the bias voltage VB generated by the external bandgap reference circuit. The drain of the NMOS tube Mn5 is connected to the drain of the PMOS tube Mp4, the gate of the NMOS tube Mn5 is connected to the P-terminal reference voltage REFP, and the source of the NMOS tube Mn5 is connected to the ground potential; Capacitor C S,P The second end of the capacitor C S,P The first end is connected through the switch S 1P The drain of the current source tube Mp4 and the output sampling voltage V S,P .

6. A low noise differential sampling phase locked loop system with high linear sampling according to claim 3, characterized in that: The discharge type sampling phase detector comprises: NMOS tube Mn3, NMOS tube Mn4, PMOS tube Mp5, capacitor C S,N and switch S 1N ; The source of the NMOS tube Mn3 is connected to the ground potential, the drain of the NMOS tube Mn3 is connected to the source of the NMOS tube Mn4, and the gate of the NMOS tube Mn3 is connected to the P-terminal reference voltage REFN; The gate and drain of the NMOS tube Mn2 are short-circuited into a diode connection to generate a gate bias voltage of the NMOS tube Mn4; The source of the PMOS tube Mp5 is connected to the power supply voltage, the drain of the PMOS tube Mp5 is connected to the drain of the NMOS tube Mn4, and the gate of the PMOS tube Mp5 is connected to the P-end reference voltage REFN; Capacitor C S,N The second end of the capacitor C S,N The first end is connected through the switch S 1N Connect the drain of NMOS tube Mn4 and the output sampling voltage V S,N .

7. A low noise differential sampling phase locked loop system with high linear sampling according to claim 1, characterized in that: The voltage shifter comprises: a first voltage shift circuit and a first holder, a second voltage shift circuit and a second holder; The first voltage shift circuit outputs the multi-phase clock generation circuit according to the Clocks are generated in different configurations Three voltage offsets, VDD is the power supply voltage; The first keeper is outputted by the multi-phase clock generating circuit. When the clock is high, the first voltage and Either offset voltage is passed to the holding capacitor; The second voltage shift circuit outputs the multi-phase clock generation circuit according to the Different clock configurations can generate Three voltage offsets, VDD represents the power supply voltage; The second keeper is outputted by the multi-phase clock generating circuit. When the clock is high, the second voltage and Either offset voltage is passed to the holding capacitor.

8. The low-noise differential sampling phase-locked loop system with high linear sampling according to claim 7, characterized in that: The first voltage shift circuit and the first keeper are a P-terminal two-bit voltage shift circuit and a keeper; The second voltage shift circuit and the second keeper are an N-terminal two-bit voltage shift circuit and a keeper; The P-terminal two-bit voltage shift circuit and keeper include: NMOS tube Mn1, PMOS tube Mp1, NMOS tube Mn3, PMOS tube Mp3, capacitor C O1,P , capacitor C O2,P , switch S 2P and capacitor C H,P ; The N-terminal two-bit voltage offset circuit and the keeper include: NMOS tube Mn2, PMOS tube Mp2, NMOS tube Mn4, PMOS tube Mp4, capacitor C O1,N , capacitor C O2,N , switch S 2N and capacitor C H,N ; Capacitor C O1,P , capacitor C O2,P The first end is connected to the sampling voltage V S,P , capacitor C O1,P The second end of the capacitor C is connected to the source of the NMOS tube Mn1 and the drain of the PMOS tube Mp1. O2,P The second end of the capacitor C is connected to the source of the NMOS tube Mn3 and the drain of the PMOS tube Mp3 respectively; O1,N , capacitor C O2,N The first end is connected to the sampling voltage V S,N , capacitor C O1,N The second end of the capacitor C is connected to the source of the NMOS tube Mn2 and the drain of the PMOS tube Mp2. O2,N The second end of the capacitor C is connected to the source of the NMOS tube Mn4 and the drain of the PMOS tube Mp4 respectively; H,P , capacitor C H,N The second end of the capacitor C is connected to the ground potential. H,P The first end is connected to the output holding voltage V H,P , capacitor C H,N The first end is connected to the output holding voltage V H,N .

9. A low-noise differential sampling phase-locked loop method with high linear sampling, based on a low-noise differential sampling phase-locked loop system with high linear sampling according to any one of claims 1 to 8, characterized in that: Low noise differential sampling phase-locked loop methods include: The single-ended reference signal is converted into a differential reference signal and input into a differential sampling phase detector; One of the three-phase non-overlapping clocks generated by the multi-phase clock generation circuit is used as a sampling clock of the differential sampling phase detector; The voltage shifter provides an offset voltage for the differential sampling phase detector; Two of the three-phase non-overlapping clocks generated by the multi-phase clock generation circuit serve as the offset control clock and the holding clock of the voltage shifter.

10. A low noise differential sampling phase locked loop method with high linear sampling according to claim 9, characterized in that: The low noise differential sampling phase locked loop method also includes: When the rising edge of the P-end reference clock and the falling edge of the N-end reference clock generated by the multi-phase clock generation circuit arrive, the differential sampling phase detector starts sampling, and the PMOS tube Mp4 starts to supply the capacitor C S,P Charging, NMOS tube Mn4 starts to supply capacitor C S,N Discharge, P terminal sampling node voltage V S,P Starts to rise, N-terminal sampling node voltage V S,N Start to descend; As the sampling clock of the differential sampling phase detector When the falling edge arrives, the sampling ends and the voltage V S,P and the N-terminal sampling node voltage V S,N Keep; Offset-controlled clock as a voltage shifter When the rising edge arrives, the charge is injected into the capacitor C O1,P , capacitor C O1,N , capacitor C O2,P , capacitor C O2,N , P terminal sampling node voltage V S,P Generate an upward voltage step, N-terminal sampling node voltage V S,N Produces a downward voltage step; Holding Clock as Voltage Shifter When the rising edge arrives, the P terminal sampling node voltage V S,P Transferred to the holding capacitor C H,P , N-terminal sampling node voltage V S,N Transferred to the holding capacitor C H,N ; As the sampling clock of the differential sampling phase detector When the rising edge arrives, the P terminal sampling node voltage V S,P and the N-terminal sampling node voltage V S,N Hold to start resetting.

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