Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and aims to enable channel regions in an N-type ring gate transistor and a P-type ring gate transistor which are distributed at intervals along the thickness direction of a semiconductor substrate to have different electrical conduction characteristics and improve the yield of the semiconductor device. The semiconductor device comprises a first semiconductor substrate, an N-type gate-all-around transistor, a P-type gate-all-around transistor, a bonding isolation layer and an insulating layer. The bonding isolation layer is arranged between the first gate stack structure and the second gate stack structure. In the first channel region and the second channel region, the upper one is bonded and interconnected over the lower one through a bonding isolation layer. The insulating layer is arranged between a first source / drain region included in the N-type ring gate transistor and a second source / drain region included in the P-type ring gate transistor. The insulating layer is adjacent to the bonding isolation layer. Wherein the first channel region and the second channel region are different in material and / or crystal orientation, and the first channel region and the second channel region are self-aligned.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] The three-dimensional stacked complementary field effect transistor device (CFET) includes vertically stacked N-type transistors and P-type transistors to improve the integration density of CMOS devices. In addition, the ring-gate transistor has advantages such as higher gate control capability compared to the planar transistor and the fin field effect transistor. Therefore, when the N-type transistor and the P-type transistor included in the CFET device are both ring-gate transistors, the working performance of the CMOS device can be improved.

[0003] In some application scenarios, the N-type gate-all-around transistor and the P-type gate-all-around transistor in the CFET device are required to have different channel conduction characteristics to meet the corresponding working requirements. However, the existing manufacturing method is difficult to realize the manufacturing of the above CFET device, resulting in the actual working performance of the existing CFET device including the N-type gate-all-around transistor and the P-type gate-all-around transistor is not good, and the integration is difficult. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to enable the channel regions in the N-type ring-gate transistor and the P-type ring-gate transistor spaced apart along the thickness direction of the semiconductor substrate to have different electrical conduction characteristics, thereby improving the applicability of the semiconductor device in different application scenarios and improving the yield of the semiconductor device.

[0005] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a semiconductor device, which includes: a first semiconductor substrate, an N-type ring gate transistor, a P-type ring gate transistor, a bonding isolation layer and an insulating layer. Along the thickness direction of the first semiconductor substrate, the N-type ring gate transistor and the P-type ring gate transistor are arranged on the first semiconductor substrate at intervals. The bonding isolation layer is arranged between the first gate stack structure included in the N-type ring gate transistor and the second gate stack structure included in the P-type ring gate transistor. In the first channel region included in the N-type ring gate transistor and the second channel region included in the P-type ring gate transistor, the one located above is bonded and interconnected above the one located below through the bonding isolation layer. The insulating layer is arranged between the first source / drain region included in the N-type ring gate transistor and the second source / drain region included in the P-type ring gate transistor. The insulating layer and the bonding isolation layer are adjacent. Among them, the materials and / or crystal orientations of the first channel region and the second channel region are different, and the first channel region and the second channel region are self-aligned.

[0006] In the case of adopting the above technical solution, in the semiconductor device provided by the present invention, the N-type ring gate transistor and the P-type ring gate transistor are spaced and distributed along the thickness direction of the semiconductor substrate. At this time, the N-type ring gate transistor and the P-type ring gate transistor can form a three-dimensional stacked complementary transistor device, which is conducive to improving the integration of the semiconductor device and realizing the miniaturization of the semiconductor device. In addition, because different semiconductor materials have different carrier conduction characteristics, when the materials of the first channel region included in the above-mentioned N-type ring gate transistor and the second channel region included in the P-type ring gate transistor are different, it is conducive to making the first channel region and the second channel region have different electrical conduction characteristics. Channel regions with different crystal orientations also have different carrier conduction characteristics (such as the channel region with a

[100] crystal orientation is conducive to the transmission of electrons, while the channel region with a

[110] crystal orientation is conducive to the transmission of holes). Therefore, when the crystal orientations of the first channel region included in the above-mentioned N-type ring gate transistor and the second channel region included in the P-type ring gate transistor are different, it is conducive to making the first channel region and the second channel region have different electrical conduction characteristics. It can be seen that the materials and / or crystal orientations of the first channel region and the second channel region can be set respectively according to the requirements of different application scenarios, so that both the N-type ring-gate transistor and the P-type ring-gate transistor have driving performance that meets the corresponding working requirements, thereby improving the applicability of semiconductor devices in different application scenarios.

[0007] In addition, the above-mentioned bonding isolation layer is arranged between the first gate stack structure included in the N-type ring gate transistor and the second gate stack structure included in the P-type ring gate transistor, which can not only reduce the leakage and interference between the N-type ring gate transistor and the P-type ring gate transistor. Moreover, in the first channel region included in the N-type ring gate transistor and the second channel region included in the P-type ring gate transistor, the one located above is bonded and interconnected above the one located below through the bonding isolation layer. At the same time, the insulating layer is arranged between the first source / drain region included in the N-type ring gate transistor and the second source / drain region included in the P-type ring gate transistor. Based on this, in the actual manufacturing process, in the first stack used to manufacture the first channel region and the second stack used to manufacture the second channel region, the one located above is bonded and interconnected above the one located below through the bonding isolation layer before forming the first source / drain region and the second source / drain region. At this time, the lower transistor has not yet been formed, and the N-type ring gate transistor and the P-type ring gate transistor are not subject to the restrictions of the low temperature process, which is conducive to improving the yield of the N-type ring gate transistor and the P-type ring gate transistor. After bonding and forming the fin structure, the first source / drain region and the second source / drain region, as well as the insulating layer between the two, can be formed respectively by source / drain etching, which not only realizes the different materials and / or crystal orientations of the first channel region and the second channel region by bonding, but also solves the problem that the upper one of the N-type ring-gate transistor and the P-type ring-gate transistor in the existing sequential integration method is limited by the low-temperature process and has poor performance, thereby improving the working performance and yield of the semiconductor device. In addition, the self-alignment of the first channel region and the second channel region improves the integration while also helping to reduce the difficulty of the subsequent interconnection process.

[0008] In one example, the carrier mobility of the material of the second channel region is greater than the carrier mobility of the material of the first channel region.

[0009] In one example, the crystal orientation of the first channel region is

[100] , and the crystal orientation of the second channel region is

[110] .

[0010] In one example, the material of the first channel region or the second channel region includes silicon, silicon germanium or germanium, wherein the germanium content in the material of the second channel region is greater than the germanium content in the material of the first channel region.

[0011] In one example, the bonding isolation layer includes at least two bonding isolation sub-layers stacked along the thickness direction of the first semiconductor substrate, and the material of at least one bonding isolation sub-layer is different from the materials of the remaining bonding isolation sub-layers.

[0012] In one example, the thickness of the bonding isolation layer is greater than or equal to 20 nm and less than or equal to 70 nm.

[0013] In a second aspect, the present invention provides a method for manufacturing a semiconductor device, which comprises: first, providing a first semiconductor substrate. Next, forming an N-type ring gate transistor, a P-type ring gate transistor, a bonding isolation layer and an insulating layer on the first semiconductor substrate. Among them, the N-type ring gate transistor and the P-type ring gate transistor are arranged on the first semiconductor substrate at intervals along the thickness direction of the first semiconductor substrate. The bonding isolation layer is arranged between the first gate stack structure included in the N-type ring gate transistor and the second gate stack structure included in the P-type ring gate transistor. In the first channel region included in the N-type ring gate transistor and the second channel region included in the P-type ring gate transistor, the one located above is bonded and interconnected above the one located below through the bonding isolation layer. The insulating layer is arranged between the first source / drain region included in the N-type ring gate transistor and the second source / drain region included in the P-type ring gate transistor. The insulating layer and the bonding isolation layer are adjacent. The materials and / or crystal orientations of the first channel region and the second channel region are different, and the first channel region and the second channel region are self-aligned.

[0014] In one example, an N-type all-around gate transistor, a P-type all-around gate transistor, a bonding isolation layer and an insulating layer are formed on a first semiconductor substrate, including: forming a fin structure on the first semiconductor substrate. Along the thickness direction of the first semiconductor substrate, the fin structure includes a first stack and a second stack arranged at intervals, and a bonding isolation layer located between the first stack and the second stack. The first stack includes a first sacrificial layer and a first channel layer alternately stacked, and the film layers at the top layer and the bottom layer in the first stack are both first sacrificial layers. The second stack includes a second sacrificial layer and a second channel layer alternately stacked, and the film layers at the top layer and the bottom layer in the second stack are both second sacrificial layers. The materials of the first sacrificial layer and the second sacrificial layer are different from the materials of the first channel layer and the second channel layer, respectively. Next, a first mask structure is formed across the fin structure. Next, the portion of the fin structure exposed outside the first mask structure is removed. Next, along the length direction of the fin structure, a first source / drain region is formed on both sides of the remaining first stack. Next, an insulating layer is formed. Next, along the length direction of the fin structure, a second source / drain region is formed on both sides of the remaining second stack. Next, at least a portion of the first mask structure is removed; and the remaining first sacrificial layer and the remaining second sacrificial layer are removed, so that the remaining first channel layer forms a first channel region, and the remaining second channel layer forms a second channel region. Next, a first gate stack structure is formed around the periphery of the first channel region, and a second gate stack structure is formed around the periphery of the second channel region.

[0015] In one example, a fin structure is formed on a first semiconductor substrate, including: providing a second semiconductor substrate. Next, on one of the first semiconductor substrate and the second semiconductor substrate, a first stacked layer arranged in an entirety and a first bonding interconnection layer located on the first stacked layer are formed; and on the other of the first semiconductor substrate and the second semiconductor substrate, a second stacked layer arranged in an entirety and a second bonding interconnection layer located on the second stacked layer are formed. The bonding isolation layer includes a first bonding interconnection layer and a second bonding interconnection layer. Next, the first stacked layer and the second stacked layer are bonded and interconnected together through the first bonding interconnection layer and the second bonding interconnection layer. Next, the second semiconductor substrate is removed. Next, a second mask structure is formed on a partial area of ​​one of the first stacked layer and the second stacked layer located above. Next, under the protection of the second mask structure, at least the first stacked layer, the second stacked layer and the bonding isolation layer are selectively etched to form a fin structure on the semiconductor substrate.

[0016] In one example, the first sacrificial layer and the second sacrificial layer are made of the same material.

[0017] In one example, the material of the first sacrificial layer and / or the second sacrificial layer includes germanium silicon or germanium, the material of the second channel layer includes germanium silicon, and the germanium content in the materials of the first sacrificial layer and the second sacrificial layer is at least 20% higher than the germanium content in the material of the second channel layer.

[0018] In one example, the second mask structure includes a first mask layer, a second mask layer and a third mask layer sequentially arranged along a thickness direction of the semiconductor substrate.

[0019] The material of the third mask layer is different from the material of the upper one of the first and second stacks, the material of the first mask layer is different from the material of the lower one of the first and second stacks, and the material of the second mask layer is different from the material of the bonding isolation layer.

[0020] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0022] Figure 1 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 1 ;

[0023] Figure 2A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 ;

[0024] Figure 3 Part (1) and part (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 3 and hint Figure 4 ;

[0025] Figure 4 Part (1) and part (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 5 and hint Figure 6 ;

[0026] Figure 5 Part (1) and part (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 7 and hint Figure 8 ;

[0027] Figure 6 Part (1) and part (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 9 and hint Figure 10 ;

[0028] Figure 7 Part (1) and part (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 10 A hint Figure 10 two;

[0029] Figure 8 Part (1) and part (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 10 Sanhe hint Figure 10 Four;

[0030] Fig. 9 Part (1) and part (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 10 Five and the hint Figure 10 six;

[0031] Fig.10 Part (1) and part (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 10 Seven and hint Figure 10 eight;

[0032] Fig.11Part (1) and part (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 10 Jiuhe hint Figure 2 ten;

[0033] Fig.12 Part (1) and part (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 2 Eleven and hint Figure 2 twelve;

[0034] Fig.13 Part (1) and part (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 2 Thirteen and hint Figure 2 fourteen;

[0035] Fig.14 Part (1) and part (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 2 Fifteen and hint Figure 2 sixteen;

[0036] Fig.15 Part (1) and part (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 2 Seventeen and hint Figure 2 eighteen;

[0037] Fig.16 Part (1) and part (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 2 Nineteen and hint Figure 3 ten;

[0038] Fig.17 Part (1) and part (2) are schematic diagrams of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 3 Eleven and hint Figure 3 twelve.

[0039] Figure numerals: 11 is a first semiconductor substrate, 12 is an N-type all-around gate transistor, 13 is a P-type all-around gate transistor, 14 is a first gate stack structure, 15 is a second gate stack structure, 16 is a bonding isolation layer, 17 is a first channel region, 18 is a second channel region, 19 is a first source / drain region, 20 is a second source / drain region, 21 is an insulating layer, 22 is a bonding isolation sublayer, 23 is a shallow trench isolation structure, 24 is a gate sidewall, 25 is an inner sidewall, 26 is Interlayer dielectric layer, 27 is a fin structure, 28 is a first stack, 29 is a second stack, 30 is a first sacrificial layer, 31 is a first channel layer, 32 is a second sacrificial layer, 33 is a second channel layer, 34 is a first mask structure, 35 is a sacrificial gate, 36 is a second semiconductor substrate, 37 is a first bonding interconnect layer, 38 is a second bonding interconnect layer, 39 is a second mask structure, 40 is a first mask layer, 41 is a second mask layer, and 42 is a third mask layer. DETAILED DESCRIPTION

[0040] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0041] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for a clearer expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0042] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0043] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0044] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0045] The three-dimensional stacked complementary field effect transistor device (CFET) includes vertically stacked N-type transistors and P-type transistors to improve the integration density of CMOS devices. In addition, the ring-gate transistor has advantages such as higher gate control capability compared to the planar transistor and the fin field effect transistor. Therefore, when the N-type transistor and the P-type transistor included in the CFET device are both ring-gate transistors, the working performance of the CMOS device can be improved.

[0046] In some application scenarios, the N-type ring-gate transistor and the P-type ring-gate transistor in the CFET device are required to have different channel conduction characteristics to meet the corresponding working requirements. For example: because the channel carriers of the N-type ring-gate transistor in the CFET device are electrons and the channel carriers of the P-type ring-gate transistor are holes, when the ring-gate transistor including the

[100] crystal orientation channel is applied to the above-mentioned CFET device, the above-mentioned ring-gate transistor is only beneficial to improve the electron mobility of the N-type ring-gate transistor, but is not conducive to the hole mobility of the P-type ring-gate transistor, resulting in poor working performance of the CFET device with the above-mentioned ring-gate transistor as the application structure. At this time, the crystal orientation of the channel region included in the P-type ring-gate transistor can be set to the

[110] crystal orientation, while the crystal orientation of the channel region included in the N-type ring-gate transistor is still the

[100] crystal orientation, so that the CFET device has higher working performance. For another example, the carrier mobility of the channel region material included in the P-type ring-gate transistor can be improved (such as using germanium silicon or germanium material with a higher germanium content than the channel region included in the N-type ring-gate transistor to manufacture the channel region included in the P-type ring-gate transistor) so that the P-type ring-gate transistor has higher working performance, while the N-type ring-gate transistor still uses conventional silicon or materials with lower carrier mobility such as germanium silicon with a lower germanium content to manufacture its own channel region.

[0047] However, it is difficult to manufacture the above CFET devices using existing manufacturing methods, resulting in poor actual working performance of existing CFET devices including N-type gate-all-around transistors and P-type gate-all-around transistors, and greater difficulty in integration. Specifically, the existing manufacturing methods for three-dimensional stacked complementary transistors mainly include the following two integration schemes:

[0048] The first method: using a monolithic method to manufacture a three-dimensional stacked complementary transistor. Specifically, taking the case where both the N-type transistor and the P-type transistor are ring-gate transistors, and the P-type transistor is located above the N-type transistor as an example, the process of manufacturing a three-dimensional stacked complementary transistor using an existing manufacturing method is described: First, a fin structure is formed on a semiconductor substrate. The fin structure includes at least two stacked layers. Each stacked layer includes a sacrificial layer, and a channel layer located on the sacrificial layer, and the materials of the sacrificial layer and the channel layer are both semiconductor materials. Next, a sacrificial gate and sidewalls are formed across part of the fin structure; and the sacrificial gate and sidewalls are used as masks to selectively etch the fin structure to remove the portion of the fin structure exposed outside the sacrificial gate and sidewalls. Then, a first semiconductor material for manufacturing the source region and drain region included in the N-type transistor is formed on the semiconductor substrate. At this time, since the remaining parts of the sacrificial layer and the channel layer corresponding to the N-type transistor and the P-type transistor are exposed after being etched, the remaining parts of these sacrificial layers and the channel layer can be used as seed layers for the epitaxial growth of the first semiconductor material. Therefore, the first semiconductor material is formed not only on both sides of the remaining parts of the sacrificial layer and the channel layer corresponding to the N-type transistor after being etched, but also on both sides of the remaining parts of the sacrificial layer and the channel layer corresponding to the P-type transistor after being etched. Next, it is necessary to remove the first semiconductor material located on both sides of the remaining parts of the sacrificial layer and the channel layer corresponding to the P-type transistor after being etched, and the remaining parts of the first semiconductor material form the source region and the drain region included in the N-type transistor. Then, an epitaxial isolation layer is formed covering the surface of the source region and the drain region of the N-type transistor away from the substrate; and the source region and the drain region of the P-type transistor are formed on the epitaxial isolation layer by an epitaxial growth process. Finally, the sacrificial gate and the part of the sacrificial layer located in the gate formation area are removed; and a gate stack structure surrounding the periphery of the channel area is formed to obtain a three-dimensional stacked complementary transistor.

[0049] The second method is to use a sequential method to manufacture a three-dimensional stacked complementary transistor. This method is to form the bottom transistor according to the manufacturing process of conventional semiconductor devices, and after forming the corresponding contact electrodes of the bottom transistor, use wafer-to-wafer bonding technology to cover a semiconductor layer on the top of the bottom transistor by wafer transfer. Then, the top transistor is integrated based on the semiconductor layer, and the top gate and bottom gate are connected to obtain a three-dimensional stacked complementary transistor.

[0050] From the manufacturing process of the first method mentioned above, it can be seen that the at least two stacked layers included in the fin structure are on the same semiconductor substrate and are formed sequentially through processes such as epitaxy. When the materials of the channel regions of the N-type ring-gate transistor and the P-type ring-gate transistor are different, the at least two stacked layers include at least three semiconductor materials, and there are lattice differences between the semiconductor layers of different materials. In addition, due to the limitation of the critical thickness of epitaxy, the material types of the high-mobility channel region in the first method are limited, and the formation of channels in other crystal directions is difficult. In the second method of manufacturing three-dimensional stacked complementary transistors, the channel regions of the N-type ring-gate transistor and the P-type ring-gate transistor are not self-aligned, resulting in greater difficulty in subsequent processes, and the upper one of the N-type ring-gate transistor and the P-type ring-gate transistor needs to be manufactured under a low-temperature process, otherwise it will affect the yield of the lower one, and the low-temperature process is not conducive to improving the working performance of the three-dimensional stacked complementary transistor.

[0051] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor device and a method for manufacturing the same. Among them, in the semiconductor device provided by the embodiment of the present invention, in the first channel region included in the N-type ring gate transistor and the second channel region included in the P-type ring gate transistor, the one located above is bonded and interconnected above the one located below through a bonding isolation layer. At this time, not only can the materials and / or crystal orientations of the first channel region and the second channel region be different by bonding, but also the problem that the one located above in the existing sequential integration method is limited by the low temperature process and has poor performance can be solved, thereby improving the working performance and yield of the semiconductor device. In addition, the above-mentioned first channel region and the second channel region are self-aligned, which not only improves the integration level, but also helps to reduce the difficulty of subsequent interconnection processes.

[0052] Specifically, the first aspect is Fig.17As shown in parts (1) and (2) of the present invention, the semiconductor device provided by the embodiment of the present invention includes: a first semiconductor substrate 11, an N-type all-around gate transistor 12, a P-type all-around gate transistor 13, a bonding isolation layer 16 and an insulating layer 21. Along the thickness direction of the first semiconductor substrate 11, the N-type all-around gate transistor 12 and the P-type all-around gate transistor 13 are arranged on the first semiconductor substrate 11 at intervals. The bonding isolation layer 16 is arranged between the first gate stack structure 14 included in the N-type all-around gate transistor 12 and the second gate stack structure 15 included in the P-type all-around gate transistor 13. In the first channel region 17 included in the N-type all-around gate transistor 12 and the second channel region 18 included in the P-type all-around gate transistor 13, the one located above is bonded and interconnected above the one located below through the bonding isolation layer 16. The insulating layer 21 is arranged between the first source / drain region 19 included in the N-type all-around gate transistor 12 and the second source / drain region 20 included in the P-type all-around gate transistor 13. The insulating layer 21 is adjacent to the bonding isolation layer 16. The first channel region 17 and the second channel region 18 have different materials and / or crystal orientations, and the first channel region 17 and the second channel region 18 are self-aligned.

[0053] When the above technical solution is adopted, Fig.17 As shown in parts (1) and (2) of the present invention, in the semiconductor device provided by the embodiment of the present invention, the N-type ring-gate transistor 12 and the P-type ring-gate transistor 13 are spaced apart in the thickness direction of the semiconductor substrate. At this time, the N-type ring-gate transistor 12 and the P-type ring-gate transistor 13 can form a three-dimensional stacked complementary transistor device, so as to improve the integration of the semiconductor device and facilitate the miniaturization of the semiconductor device. In addition, because different semiconductor materials have different carrier conduction characteristics, when the materials of the first channel region 17 included in the N-type ring-gate transistor 12 and the second channel region 18 included in the P-type ring-gate transistor 13 are different, it is beneficial to make the first channel region 17 and the second channel region 18 have different electrical conduction characteristics. Channel regions with different crystal orientations also have different carrier conduction characteristics (e.g., channel regions with a

[100] crystal orientation are conducive to the transmission of electrons, while channel regions with a

[110] crystal orientation are conducive to the transmission of holes). Therefore, when the crystal orientations of the first channel region 17 included in the N-type ring-gate transistor 12 and the second channel region 18 included in the P-type ring-gate transistor 13 are different, it is beneficial for the first channel region 17 and the second channel region 18 to have different electrical conduction characteristics. It can be seen that the materials and / or crystal orientations of the first channel region 17 and the second channel region 18 can be set according to the requirements of different application scenarios, so that both the N-type ring-gate transistor 12 and the P-type ring-gate transistor 13 have driving performance that meets the corresponding working requirements, thereby improving the applicability of semiconductor devices in different application scenarios.

[0054] In addition, if Figures 1 to 17As shown in parts (1) and (2) of the figure, the above-mentioned bonding isolation layer 16 is arranged between the first gate stack structure 14 included in the N-type ring-gate transistor 12 and the second gate stack structure 15 included in the P-type ring-gate transistor 13, which can not only reduce the leakage and interference between the N-type ring-gate transistor 12 and the P-type ring-gate transistor 13. Moreover, in the first channel region 17 included in the N-type ring-gate transistor 12 and the second channel region 18 included in the P-type ring-gate transistor 13, the one located above is bonded and interconnected above the one located below through the bonding isolation layer 16. At the same time, the insulating layer 21 is arranged between the first source / drain region 19 included in the N-type ring-gate transistor 12 and the second source / drain region 20 included in the P-type ring-gate transistor 13. Based on this, in the actual manufacturing process, in the first stack 28 for manufacturing the first channel region 17 and the second stack 29 for manufacturing the second channel region 18, the one located on the upper side is bonded and interconnected to the upper side of the one located on the lower side through the bonding isolation layer 16 before forming the first source / drain region 19 and the second source / drain region 20. At this time, the lower transistor has not been formed yet, and the N-type ring-gate transistor 12 and the P-type ring-gate transistor 13 do not need to be restricted by the low-temperature process, which is beneficial to improving the yield of the N-type ring-gate transistor 12 and the P-type ring-gate transistor 13. After bonding and forming the fin structure 27, the first source / drain region 19 and the second source / drain region 20, as well as the insulating layer 21 located therebetween, can be formed respectively by source / drain etching, which not only enables the first channel region 17 and the second channel region 18 to have different materials and / or crystal orientations by bonding, but also solves the problem that the upper one of the N-type ring-gate transistor 12 and the P-type ring-gate transistor 13 in the existing sequential integration method is limited by the low-temperature process and has poor performance, thereby improving the working performance and yield of the semiconductor device. In addition, the first channel region 17 and the second channel region 18 are self-aligned, which improves the integration while also helping to reduce the difficulty of the subsequent interconnection process.

[0055] In actual application, the embodiment of the present invention does not specifically limit the material and structure of the semiconductor substrate, as long as it can be applied to the semiconductor device provided in the embodiment of the present invention. For example, the semiconductor substrate can be a substrate made of any semiconductor material such as a silicon substrate, a silicon-on-insulator substrate, a germanium silicon substrate or a germanium substrate.

[0056] For N-type ring-gate transistors and P-type ring-gate transistors, in terms of the formation position, such as Fig.17 As shown in part (1) of FIG. 1 , along the thickness direction of the semiconductor substrate, the P-type gate-all-around transistor 13 may be disposed above the N-type gate-all-around transistor 12; or Fig.17 As shown in part (2) of FIG. 1 , the N-type gate-all-around transistor 12 may be arranged above the P-type gate-all-around transistor 13 .

[0057] It is understandable that the spacing between the N-type gate-all-around transistor and the P-type gate-all-around transistor along the thickness direction of the semiconductor substrate will affect the thickness of the bonding isolation layer and the insulating layer. The thickness of the bonding isolation layer will affect the degree of improvement of the leakage and interference between the first gate stack structure and the second gate stack structure, and the thickness of the insulating layer will affect the isolation effect between the first source / drain region and the second source / drain region. Therefore, the spacing between the N-type gate-all-around transistor and the P-type gate-all-around transistor can be determined according to the requirements for leakage and bonding between the N-type gate-all-around transistor and the P-type gate-all-around transistor in the actual application scenario, and no specific limitation is made here.

[0058] Exemplarily, along the thickness direction of the semiconductor substrate, the spacing between the N-type ring gate transistor and the P-type ring gate transistor can be greater than or equal to 20nm and less than or equal to 70nm. At this time, the thickness of the above-mentioned bonding isolation layer and / or insulating layer can also be greater than or equal to 20nm and less than or equal to 70nm. In this case, while ensuring that the bonding isolation layer and the insulating layer have a large thickness to reduce the risk of leakage, it is also possible to prevent the bonding between the N-type ring gate transistor and the P-type ring gate transistor from being affected by the large thickness of the bonding interconnect layer, thereby ensuring that the semiconductor device has a high structural reliability.

[0059] From a structural perspective, Fig.17 As shown in parts (1) and (2) of the invention, the N-type ring-gate transistor 12 includes a first source / drain region 19, a first channel region 17 and a first gate stack structure 14. The first channel region 17 is located between the first source / drain regions 19, and the first channel region 17 is in contact with the first source / drain region 19 at both ends along the length direction. Secondly, the first channel region 17 may include only one layer of nanostructure, or may include multiple layers of nanostructures spaced apart along the thickness direction of the semiconductor substrate. The first gate stack structure 14 surrounds the periphery of each layer of nanostructure included in the first channel region 17. Specifically, the first gate stack structure 14 may be formed in a gate dielectric layer on the periphery of the first channel region 17, and a gate located on the gate dielectric layer.

[0060] like Fig.17 As shown in parts (1) and (2) of the present invention, the above-mentioned P-type ring-gate transistor 13 includes a second source / drain region 20, a second channel region 18 and a second gate stack structure 15. The second channel region 18 is located between the second source / drain regions 20, and the two ends of the second channel region 18 along the length direction are respectively in contact with the second source / drain region 20. Secondly, the second channel region 18 may include only one layer of nanostructure, or may include multiple layers of nanostructures spaced apart along the thickness direction of the semiconductor substrate. The second gate stack structure 15 surrounds the periphery of each layer of nanostructure included in the second channel region 18. Specifically, the second gate stack structure 15 can be formed in a gate dielectric layer on the periphery of the second channel region 18, and a gate located on the gate dielectric layer.

[0061] In terms of materials, the materials of the first source / drain region, the first channel region, the second source / drain region, and the second channel region may include any semiconductor material such as silicon, silicon germanium, or germanium. The materials of the first channel region and the second channel region may be the same or different. The materials of the first channel region and the second channel region may be determined according to the crystal orientation of the first channel region and the second channel region. When the crystal orientations of the first channel region and the second channel region are the same, the materials of the first channel region and the second channel region are different. When the crystal orientations of the first channel region and the second channel region are different, the materials of the first channel region and the second channel region may be the same or different.

[0062] Specifically, when the materials of the first channel region and the second channel region are different, the carrier mobility of the material of the second channel region may be greater than the carrier mobility of the material of the first channel region. In this case, the driving performance of the P-type ring-gate transistor can be improved, and the working performance of the semiconductor device can be improved. As for the specific types of materials of the first channel region and the second channel region, they can be set according to actual needs.

[0063] Exemplarily, the material of the first channel region or the second channel region may include silicon, silicon germanium or germanium. The germanium content in the material of the second channel region is greater than the germanium content in the material of the first channel region. The difference in the germanium content in the materials of the first channel region and the second channel region may be determined according to actual needs and the actual manufacturing process, and is not specifically limited here. For example, the germanium content in the material of the second channel region may be at least 10% higher than the germanium content in the material of the first channel region.

[0064] Of course, when the materials of the first channel region and the second channel region are different, the carrier mobility of the material of the second channel region may also be less than or equal to the carrier mobility of the material of the first channel region.

[0065] In addition, when the crystal orientations of the first channel region and the second channel region are different, the crystal orientation of the first channel region may be a

[100] crystal orientation, and the crystal orientation of the second channel region may be a

[110] crystal orientation. In this case, since the channel region with a

[100] crystal orientation is conducive to the transmission of electrons, and the channel region with a

[110] crystal orientation is conducive to the transmission of holes, the crystal orientation of the first channel region included in the N-type ring-gate transistor is set to the

[100] crystal orientation, which is conducive to the transmission of electrons and ensures that the N-type ring-gate transistor has higher driving performance. Similarly, the crystal orientation of the second channel region included in the P-type ring-gate transistor is set to the

[110] crystal orientation, which is conducive to the transmission of holes and ensures that the P-type ring-gate transistor has higher driving performance.

[0066] Of course, when the first channel region and the second channel region have different crystal orientations, the first channel region may also be in a crystal orientation other than the

[100] orientation, and the second channel region may also be in a crystal orientation other than the

[110] orientation.

[0067] For the above bonding isolation layer, the bonding isolation layer is disposed between the first gate stack structure included in the N-type all-around gate transistor and the second gate stack structure included in the P-type all-around gate transistor. Fig.17 As shown in parts (1) and (2), in the first channel region 17 included in the N-type ring gate transistor 12 and the second channel region 18 included in the P-type ring gate transistor 13, the one located above is bonded and interconnected above the one located below through the bonding isolation layer 16.

[0068] Specifically, the bonding isolation layer may be a single-layer structure made of a single insulating material, for example, the material of the bonding isolation layer may be SiO2, SiCO, SiCON, Y2O3 or HfO2.

[0069] Or, if Fig.17 As shown in parts (1) and (2) of the figure, the bonding isolation layer 16 may also include at least two bonding isolation sublayers 22 stacked along the thickness direction of the first semiconductor substrate 11, and the material of at least one bonding isolation sublayer 22 is different from the material of the remaining bonding isolation sublayers 22. Specifically, the number of bonding isolation sublayers 22 included in the bonding isolation layer 16, the material types of different bonding isolation sublayers 22 in the bonding isolation layer 16, and the distribution of bonding isolation sublayers 22 with different materials can be set according to actual needs and are not specifically limited here.

[0070] For the above-mentioned insulating layer, the insulating layer is arranged between the first source / drain region included in the N-type ring gate transistor and the second source / drain region included in the P-type ring gate transistor, and is used to isolate the first source / drain region from the second source / drain region. The insulating layer is adjacent to the bonding isolation layer, that is, the side wall of the insulating layer is in contact with the side wall of the bonding isolation layer. The material of the insulating layer may include any insulating material such as silicon oxide, silicon nitride or silicon oxynitride. The thickness of the insulating layer can be referred to the above text and will not be repeated here.

[0071] In some cases, such as Figure 8 (1) and (2) of Fig.17 As shown in parts (1) and (2) of FIG. 1 , the semiconductor device may further include a shallow trench isolation structure 23. The shallow trench isolation structure 23 is disposed on the first semiconductor substrate 11 to isolate different active regions on the first semiconductor substrate 11 to prevent leakage.

[0072] In some cases, such as Fig.17As shown in parts (1) and (2), the semiconductor device may further include a gate sidewall 24, which is disposed at least on both sides of the first gate stack structure 14 and the second gate stack structure 15 along their own length direction to isolate the first gate stack structure 14 and the second gate stack structure 15 from other adjacent conductive structures to prevent leakage or interference.

[0073] In some cases, such as Fig.17 As shown in parts (1) and (2) in the figure, the N-type ring gate transistor 12 and / or the P-type ring gate transistor 13 may further include an inner side wall 25. The inner side wall 25 is arranged between the first gate stack structure 14 and the first source / drain region 19, and / or the inner side wall 25 is arranged between the second gate stack structure 15 and the second source / drain region 20, and is used to limit the length of the first gate stack structure 14 and / or the second gate stack structure 15, so as to improve the yield of the semiconductor device. Among them, only the N-type ring gate transistor may include the inner side wall, while the P-type ring gate transistor may not include the inner side wall. Alternatively, the P-type ring gate transistor may include the inner side wall, while the N-type ring gate transistor may not include the above-mentioned inner side wall. Alternatively, as Fig.17 As shown in parts (1) and (2) of the figure, both the N-type gate-all-around transistor 12 and the P-type gate-all-around transistor 13 include the inner sidewall 25. In this case, in the actual manufacturing process, the inner sidewall 25 included in the N-type gate-all-around transistor 12 and the P-type gate-all-around transistor 13 can be integrally formed to improve the manufacturing efficiency of the semiconductor device and help reduce the manufacturing cost of the semiconductor device. Alternatively, the inner sidewall 25 included in the N-type gate-all-around transistor 12 and the P-type gate-all-around transistor 13 can also be formed separately in different operation steps.

[0074] In some cases, such as Fig.17 As shown in parts (1) and (2) of the present invention, the semiconductor device may further include an interlayer dielectric layer 26 disposed on the first semiconductor substrate 11. The top of the interlayer dielectric layer 26 is flush with the top of the upper one of the first gate stack structure 14 and the second gate stack structure 15, so as to protect the first source / drain region 19 and the second source / drain region 20 from being affected by operations such as etching or cleaning, thereby improving the yield of the semiconductor device.

[0075] In terms of materials, the materials of the shallow trench isolation structure, gate sidewalls, inner sidewalls and interlayer dielectric layer can be set according to the actual manufacturing process and actual needs, and are not specifically limited here. Exemplarily, the materials of the shallow trench isolation structure, gate sidewalls, inner sidewalls and interlayer dielectric layer can include any insulating material such as silicon oxide or silicon nitride.

[0076] In a second aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device. Figures 1 to 17The manufacturing process is described by a cross-sectional view or a stereoscopic view of the operation shown. Specifically, the manufacturing method of the semiconductor device includes the following steps:

[0077] Firstly, a first semiconductor substrate is provided.

[0078] Next, if Fig.17 As shown in parts (1) and (2) of the invention, an N-type gate-all-around transistor 12, a P-type gate-all-around transistor 13, a bonding isolation layer 16 and an insulating layer 21 are formed on a first semiconductor substrate 11. The N-type gate-all-around transistor 12 and the P-type gate-all-around transistor 13 are arranged on the first semiconductor substrate 11 at intervals along the thickness direction of the first semiconductor substrate 11. The bonding isolation layer 16 is arranged between the first gate stack structure 14 included in the N-type gate-all-around transistor 12 and the second gate stack structure 15 included in the P-type gate-all-around transistor 13. In the first channel region 17 included in the N-type gate-all-around transistor 12 and the second channel region 18 included in the P-type gate-all-around transistor 13, the one located above is bonded and interconnected above the one located below through the bonding isolation layer 16. The insulating layer 21 is arranged between the first source / drain region 19 included in the N-type gate-all-around transistor 12 and the second source / drain region 20 included in the P-type gate-all-around transistor 13. The insulating layer 21 is adjacent to the bonding isolation layer 16. The first channel region 17 and the second channel region 18 have different materials and / or crystal orientations, and the first channel region 17 and the second channel region 18 are self-aligned.

[0079] It can be understood that the structure of the semiconductor device formed by the manufacturing method provided in the second aspect of the embodiment of the present invention is the same as the structure of the semiconductor device provided in the first aspect described above. Therefore, the specific structure and materials of the N-type ring-gate transistor and the P-type ring-gate transistor in the semiconductor device formed by the manufacturing method provided in the second aspect, the specific structure and materials of the bonding isolation layer, and the materials of the insulating layer, etc., can be referred to the previous text and will not be repeated here.

[0080] Exemplarily, the forming of an N-type all-around gate transistor, a P-type all-around gate transistor, a bonding isolation layer and an insulating layer on the first semiconductor substrate may include the following steps:

[0081] like Figure 7As shown in parts (1) and (2) of the figure, a fin structure 27 is formed on the first semiconductor substrate 11. Along the thickness direction of the first semiconductor substrate 11, the fin structure 27 includes a first stack 28 and a second stack 29 arranged at intervals, and a bonding isolation layer 16 located between the first stack 28 and the second stack 29. The first stack 28 includes a first sacrificial layer 30 and a first channel layer 31 alternately stacked, and the film layer at the top layer and the film layer at the bottom layer in the first stack 28 are both the first sacrificial layer 30. The second stack 29 includes a second sacrificial layer 32 and a second channel layer 33 alternately stacked, and the film layer at the top layer and the film layer at the bottom layer in the second stack 29 are both the second sacrificial layer 32. The materials of the first sacrificial layer 30 and the second sacrificial layer 32 are different from the materials of the first channel layer 31 and the second channel layer 33, respectively.

[0082] Specifically, the first channel layer in the first stack is used to manufacture the nanostructure included in the first channel region, and the second channel layer in the second stack is used to manufacture the nanostructure included in the second channel region. Therefore, the positional relationship between the first stack and the second stack in the fin structure can be determined according to the positional relationship between the N-type ring-gate transistor and the P-type ring-gate transistor in the semiconductor substrate. Figure 7 (1) of the above, and Fig.17 As shown in part (1) of FIG. 2 , along the thickness direction of the semiconductor substrate, when the N-type gate-all-around transistor 12 is located below the P-type gate-all-around transistor 13, the first stack 28 in the fin structure 27 is located below the second stack 29. Figure 7 (2) of the above, and Fig.17 As shown in part (2) of FIG. 1 , when the P-type gate-all-around transistor 13 is located below the N-type gate-all-around transistor 12, the second stack 29 in the fin structure 27 is located below the first stack 28. In addition, the number of layers and the material of the first channel layer 31 in the first stack 28 are respectively the same as the number of layers and the material of the nanostructure in the first channel region 17, and the number of layers and the material of the second channel layer 33 in the second stack 29 are respectively the same as the number of layers and the material of the nanostructure in the second channel region 18.

[0083] As for the above-mentioned first sacrificial layer and second sacrificial layer, the materials of the first sacrificial layer and the second sacrificial layer are different from the materials of the first channel layer and the second channel layer, respectively, so as to facilitate the subsequent selective etching of the first sacrificial layer and the second sacrificial layer relative to the first channel layer and the second channel layer, respectively, so that the layers of nanostructures included in the first channel region and the layers of nanostructures included in the second channel region are suspended. Specifically, the materials of the first sacrificial layer and the second sacrificial layer can be the same or different. Among them, when the materials of the first sacrificial layer and the second sacrificial layer are the same, the manufacturing efficiency of the semiconductor device can be improved by etching the first sacrificial layer and the second sacrificial layer. At the same time, the types of different semiconductor materials in the fin structure can also be reduced, which is conducive to reducing the critical thickness limit of each film layer in the first stack and the second stack in the epitaxial type, and improving the yield of the semiconductor device.

[0084] Exemplarily, the material of the first sacrificial layer and / or the second sacrificial layer includes germanium silicon or germanium, the material of the second channel layer includes germanium silicon, and the germanium content in the materials of the first sacrificial layer and the second sacrificial layer is at least 20% higher than the germanium content in the material of the second channel layer. 0.8 Ge 0.2 The material of the first sacrificial layer and / or the second sacrificial layer may be Si 0.5 Ge 0.5 、Si 0.4 Ge 0.6 、Si 0.3 Ge 0.7 、Si 0.2 Ge 0.8 or Si 0.1 Ge 0.9 wait.

[0085] In the actual manufacturing process, a second semiconductor substrate may be provided first. The second semiconductor substrate may be a substrate made of any semiconductor material such as silicon, silicon germanium or germanium. Figure 1 and Figure 2 As shown, epitaxy and deposition processes can be used to form a first stacked layer 28 disposed as a whole layer on one of the first semiconductor substrate 11 and the second semiconductor substrate 36, and a first bonding interconnection layer 37 located on the first stacked layer 28; Figure 1 and Figure 2 As shown, a second stacked layer 29 arranged in an entirety and a second bonding interconnection layer 38 located on the second stacked layer 29 are formed on the other of the first semiconductor substrate 11 and the second semiconductor substrate 36. The bonding isolation layer 16 includes a first bonding interconnection layer 37 and a second bonding interconnection layer 38. Specifically, as Figure 1 and Fig.17As shown in part (1) of FIG. 1 , if the N-type all-around gate transistor 12 is located below the P-type all-around gate transistor 13, it is necessary to form a first stack 28 and a first bonding interconnection layer 37 on the first semiconductor substrate 11, and to form a second stack 29 and a second bonding interconnection layer 38 on the second semiconductor substrate 36. Figure 2 and Fig.17 As shown in part (2) of the figure, if the P-type ring-gate transistor 13 is located below the N-type ring-gate transistor 12, it is necessary to form a second stack 29 and a second bonding interconnect layer 38 on the first semiconductor substrate 11, and to form a first stack 28 and a first bonding interconnect layer 37 on the second semiconductor substrate 36. The structure and material of the first bonding interconnect layer 37 and the second bonding interconnect layer 38 can be determined with reference to the structure and material of the bonding isolation layer 16 described above. For example: when the bonding isolation layer 16 is a single-layer structure, the materials of the first bonding interconnect layer 37 and the second bonding interconnect layer 38 are the same. For another example: when the bonding isolation layer includes two bonding isolation sublayers 22 with different materials, the first bonding interconnect layer 37 and the second bonding interconnect layer 38 can respectively correspond to the corresponding bonding isolation sublayers 22. Next, as Figure 3 As shown in parts (1) and (2) of FIG. 1 , a bonding process is used to bond the first stack 28 and the second stack 29 together through the first bonding interconnection layer 37 and the second bonding interconnection layer 38. Specifically, the specific process parameters of the bonding process can be determined according to actual needs. Optionally, a low temperature bonding process can be used to achieve the bonding interconnection of the first bonding interconnection layer 37 and the second bonding interconnection layer 38. Next, as Figure 4 As shown in parts (1) and (2) of the method, the second semiconductor substrate can be removed by dry etching and / or wet etching. Specifically, the second semiconductor substrate can be removed by only a single process (such as only chemical mechanical polishing, dry etching or wet etching). Alternatively, the thickness of the second semiconductor substrate can be first reduced by a certain value (such as 1 μm to 10 μm) by chemical mechanical polishing and / or dry etching, and then the remaining second semiconductor substrate can be removed by a wet etching process with a high selectivity. Such a setting can not only achieve rapid removal of the second semiconductor substrate, but also ensure that the first stack 28 and the second stack 29 have a high formation quality, thereby preventing the second semiconductor substrate from remaining after the operation. Next, as Figure 5 As shown in parts (1) and (2) of FIG. 1 , a second mask structure 39 may be formed on a portion of one of the first stack 28 and the second stack 29 located above by using processes such as deposition and photolithography. The second mask structure 39 may be a single-layer structure, and the material of the second mask structure 39 has a certain etching selectivity ratio to the materials of the first stack 28, the second stack 29, and the bonding isolation layer 16. Alternatively, as Figure 5As shown in parts (1) and (2) of FIG. 3 , the second mask structure 39 includes a first mask layer 40, a second mask layer 41, and a third mask layer 42, which are sequentially arranged along the thickness direction of the semiconductor substrate. The material of the third mask layer 42 is different from the material of the upper one of the first stack 28 and the second stack 29, so that the selective etching of the upper one of the first stack 28 and the second stack 29 can be achieved under the protection of the third mask layer 42; the material of the first mask layer 40 is different from the material of the lower one of the first stack 28 and the second stack 29, so that the selective etching of the lower one of the first stack 28 and the second stack 29 can be achieved under the protection of the first mask layer 40; the material of the second mask layer 41 is different from the material of the bonding isolation layer 16, so that the selective etching of the bonding isolation layer 16 can be achieved under the protection of the second mask layer 41. For example, the first mask layer 40 and the third mask layer 42 may be dielectric layers (such as silicon oxide or silicon nitride), and the second mask layer 41 may be a dielectric layer (such as silicon nitride or silicon oxynitride) or a semiconductor layer (such as amorphous silicon). Figure 6 As shown in parts (1) and (2) of FIG. 3 , under the protection of the second mask structure 39, a dry etching or wet etching process can be used to selectively etch at least the first stack 28, the second stack 29 and the bonding isolation layer 16 to form a fin structure 27 on the semiconductor substrate. In the case where the manufactured semiconductor device does not include a shallow trench isolation structure, the first stack, the second stack and the bonding isolation layer can be selectively etched. Figure 6 As shown in parts (1) and (2) of FIG. 1 , when the manufactured semiconductor device further includes a shallow trench isolation structure 23, it is necessary to selectively etch the first stack 28, the second stack 29, the bonding isolation layer 16 and a portion of the first semiconductor substrate 11 to form a fin; Figure 7 As shown in parts (1) and (2) in the figure, a shallow trench isolation structure 23 is then formed on the first semiconductor substrate 11 by using processes such as deposition and etching. The top of the shallow trench isolation structure 23 is less than or equal to the bottom height of the first sacrificial layer 30 and the second sacrificial layer 32 located at the bottom layer; the portion of the fin exposed outside the shallow trench isolation structure 23 is a fin-shaped structure 27.

[0086] Next, if Figure 8 As shown in parts (1) and (2) of FIG. 1 , a first mask structure 34 spanning the fin structure 27 may be formed by using processes such as deposition and etching.

[0087] In actual application, the embodiment of the present invention does not specifically limit the material and structure of the first mask structure, as long as it can be applied to the manufacturing method provided by the embodiment of the present invention. For example: the first mask structure may include a sacrificial gate. For another example: Figure 8As shown in parts (1) and (2) of FIG. 1 , the first mask structure may include a sacrificial gate 35 and gate spacers 24 at least located on both sides of the sacrificial gate 35 along its own length direction.

[0088] Next, if Fig. 9 As shown in parts (1) and (2) in the above, a dry etching process or a wet etching process may be used to remove the portion of the fin structure exposed outside the first mask structure 34 .

[0089] Next, if Fig.12 As shown in part (1) of FIG. 1 , epitaxy and etching processes can be used to form first source / drain regions 19 on both sides of the remaining first stack along the length direction of the fin structure.

[0090] Next, if Fig.13 As shown in part (1) of FIG. 1 , the insulating layer 21 may be formed by a deposition process or the like.

[0091] Next, if Fig.14 As shown in part (1) of FIG. 1 , epitaxy and etching processes can be used to form second source / drain regions 20 on both sides of the remaining second stack along the length direction of the fin structure.

[0092] It should be noted that the above description takes the case where the N-type gate-all-around transistor is located below the P-type gate-all-around transistor along the thickness direction of the semiconductor substrate as an example to describe the process of manufacturing the first source / drain region, the insulating layer, and the second source / drain region, but it does not mean that the N-type gate-all-around transistor in the semiconductor device formed by the manufacturing method provided in the embodiment of the present invention can only be located below the P-type gate-all-around transistor. In actual application, Fig.17 As shown in part (2) of FIG. 1 , the N-type gate-all-around transistor 12 may also be located above the P-type gate-all-around transistor 13. In this case, Figure 12 to Figure 14 As shown in part (2) of FIG. 1 , it is necessary to first form the second source / drain region 20 , then form an insulating layer 21 on the second source / drain region 20 , and then form the first source / drain region 19 on the insulating layer 21 .

[0093] In addition, after removing the portion of the fin structure exposed outside the first mask structure and before forming the first source / drain region, the insulating layer and the second source / drain region, as shown in FIG. Fig.10 As shown in parts (1) and (2) of FIG. 1 , a wet etching or dry etching process may be used to remove the edge portions of the remaining first sacrificial layer 30 and / or the second sacrificial layer 32 along the length direction of the fin structure to form a notch. Fig.11 As shown in parts (1) and (2) of FIG. 1 , deposition and etching processes are used to fill the inner sidewall 25 in the recess. Of course, the formation of the inner sidewall 25 may not be performed.

[0094] In addition, after forming the first source / drain region, the insulating layer and the second source / drain region, before performing subsequent operations, such as Fig.15 As shown in parts (1) and (2) of FIG. 1 , deposition and chemical mechanical polishing processes can also be used to form an interlayer dielectric layer 26 on the first semiconductor substrate 11. The top of the interlayer dielectric layer 26 is flush with the top of the first mask structure 34.

[0095] Next, at least a portion of the first mask structure is removed by using a dry etching process or a wet etching process.

[0096] Specifically, whether to remove part or all of the first mask structure can be determined according to its specific structure, and is not specifically limited here. If the first mask structure only includes the sacrificial gate, the first mask structure needs to be completely removed. Fig.16 As shown in parts (1) and (2) of FIG. 3 , if the first mask structure includes the sacrificial gate 35 and the gate spacer 24 , only the sacrificial gate 35 included in the first mask structure needs to be removed.

[0097] Next, if Fig.16 As shown in parts (1) and (2), the remaining first sacrificial layer and the remaining second sacrificial layer are removed by dry etching or wet etching to form the first channel region 17 and the remaining second channel layer is formed into the second channel region 18.

[0098] Next, if Fig.17 As shown in parts (1) and (2), a process such as atomic layer deposition can be used to form a first gate stack structure 14 surrounding the periphery of the first channel region 17, and to form a second gate stack structure 15 surrounding the periphery of the second channel region 18. The specific structure and materials of the first gate stack structure 14 and the second gate stack structure 15 can be referred to above and will not be repeated here.

[0099] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0100] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0101] The embodiments of the present invention are described above. However, these embodiments are only for a clearer description and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: a first semiconductor substrate; An N-type gate-all-around transistor and a P-type gate-all-around transistor are arranged on the first semiconductor substrate at intervals along the thickness direction of the first semiconductor substrate; A bonding isolation layer is provided between the first gate stack structure included in the N-type gate-all-around transistor and the second gate stack structure included in the P-type gate-all-around transistor; in the first channel region included in the N-type gate-all-around transistor and the second channel region included in the P-type gate-all-around transistor, the one located above is bonded and interconnected above the one located below through the bonding isolation layer; and an insulating layer disposed between a first source / drain region included in the N-type all-around gate transistor and a second source / drain region included in the P-type all-around gate transistor; the insulating layer is adjacent to the bonding isolation layer; The first channel region and the second channel region have different materials and / or different crystal orientations, and the first channel region and the second channel region are self-aligned.

2. The semiconductor device according to claim 1, wherein: The carrier mobility of the material of the second channel region is greater than the carrier mobility of the material of the first channel region; And / or, the crystal orientation of the first channel region is [100], and the crystal orientation of the second channel region is [110].

3. The semiconductor device according to claim 1, wherein: The material of the first channel region or the second channel region includes silicon, silicon germanium or germanium; The germanium content in the material of the second channel region is greater than the germanium content in the material of the first channel region.

4. The semiconductor device according to claim 1, wherein: The bonding isolation layer includes at least two bonding isolation sub-layers stacked along the thickness direction of the first semiconductor substrate, and the material of at least one of the bonding isolation sub-layers is different from the materials of the remaining bonding isolation sub-layers.

5. The semiconductor device according to claim 1, wherein: The thickness of the bonding isolation layer is greater than or equal to 20 nm and less than or equal to 70 nm.

6. A method for manufacturing a semiconductor device, characterized in that: include: Providing a first semiconductor substrate; forming an N-type all-around gate transistor, a P-type all-around gate transistor, a bonding isolation layer and an insulating layer on the first semiconductor substrate; Among them, the N-type ring-gate transistor and the P-type ring-gate transistor are arranged on the first semiconductor substrate at intervals along the thickness direction of the first semiconductor substrate; the bonding isolation layer is arranged between the first gate stack structure included in the N-type ring-gate transistor and the second gate stack structure included in the P-type ring-gate transistor; in the first channel region included in the N-type ring-gate transistor and the second channel region included in the P-type ring-gate transistor, the one located above is bonded and interconnected above the one located below through the bonding isolation layer; the insulating layer is arranged between the first source / drain region included in the N-type ring-gate transistor and the second source / drain region included in the P-type ring-gate transistor; the insulating layer and the bonding isolation layer are adjacent; the materials and / or crystal orientations of the first channel region and the second channel region are different, and the first channel region and the second channel region are self-aligned.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The forming of an N-type all-around gate transistor, a P-type all-around gate transistor, a bonding isolation layer and an insulating layer on the first semiconductor substrate includes: A fin structure is formed on the first semiconductor substrate; along the thickness direction of the first semiconductor substrate, the fin structure includes a first stack and a second stack arranged at intervals, and the bonding isolation layer located between the first stack and the second stack; the first stack includes a first sacrificial layer and a first channel layer alternately stacked, and the film layer located at the top layer and the film layer located at the bottom layer in the first stack are both the first sacrificial layer; the second stack includes a second sacrificial layer and a second channel layer alternately stacked, and the film layer located at the top layer and the film layer located at the bottom layer in the second stack are both the second sacrificial layer; the materials of the first sacrificial layer and the second sacrificial layer are different from the materials of the first channel layer and the second channel layer respectively; forming a first mask structure spanning over the fin structure; removing a portion of the fin structure exposed outside the first mask structure; forming the first source / drain regions on both sides of the remaining first stacked layers along the length direction of the fin structure; forming the insulating layer; forming the second source / drain regions on both sides of the remaining second stacked layers along the length direction of the fin-shaped structure; removing at least a portion of the first mask structure; and removing the remaining first sacrificial layer and the remaining second sacrificial layer, so that the remaining first channel layer forms the first channel region, and the remaining second channel layer forms the second channel region; The first gate stack structure is formed around the periphery of the first channel region, and the second gate stack structure is formed around the periphery of the second channel region.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The forming of a fin structure on the first semiconductor substrate comprises: Providing a second semiconductor substrate; On one of the first semiconductor substrate and the second semiconductor substrate, the first stacked layer is formed as a whole layer, and a first bonding interconnection layer is located on the first stacked layer; and on the other of the first semiconductor substrate and the second semiconductor substrate, the second stacked layer is formed as a whole layer, and a second bonding interconnection layer is located on the second stacked layer; the bonding isolation layer includes the first bonding interconnection layer and the second bonding interconnection layer; Bonding and interconnecting the first stacked layer and the second stacked layer together through the first bonding and interconnecting layer and the second bonding and interconnecting layer; removing the second semiconductor substrate; forming a second mask structure on a portion of an upper region of the first stack and the second stack; Under the protection of the second mask structure, at least the first stack, the second stack and the bonding isolation layer are selectively etched to form the fin structure on the semiconductor substrate.

9. The method for manufacturing a semiconductor device according to claim 7, wherein: The first sacrificial layer and the second sacrificial layer are made of the same material; And / or, the material of the first sacrificial layer and / or the second sacrificial layer includes silicon germanium or germanium, the material of the second channel layer includes silicon germanium, and the germanium content in the materials of the first sacrificial layer and the second sacrificial layer is at least 20% higher than the germanium content in the material of the second channel layer.

10. The method for manufacturing a semiconductor device according to claim 8, wherein: The second mask structure comprises a first mask layer, a second mask layer and a third mask layer which are sequentially arranged along the thickness direction of the semiconductor substrate; Among them, the material of the third mask layer is different from the material of the upper one of the first and second stacks, the material of the first mask layer is different from the material of the lower one of the first and second stacks, and the material of the second mask layer is different from the material of the bonding isolation layer.

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