Silicon-on-insulator wafer with cavity and alignment method of silicon-on-insulator wafer
By forming alignment marks and cavity on the insulating substrate and determining the cavity position using alignment marks, the problem of difficulty in alignment of cavity after bonding is solved, the structural accuracy and yield of the product are improved, and it has high practicality.
Patent Information
- Application Number
- CN202411644860.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-18
- Publication Date
- 2025-02-28
AI Technical Summary
After bonding, the cavity of the silicon wafer on the insulating substrate is covered, making it difficult for the pattern of the wafer surface to align with the covered cavity, affecting the yield and quality of the product.
By forming an alignment mark on the marking surface of the insulating substrate and forming a cavity on the polishing surface, the alignment mark is still exposed after the cavity is covered by the bonded wafer, and the alignment mark is used to determine the position of the cavity to achieve alignment.
It improves the accuracy and yield of the product structure, avoids the impact on the subsequent processing of the SOI wafer surface, does not occupy the effective area of the wafer front, and has high practicality.
Smart Images
Figure CN119545902A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of micro-electromechanical systems, and in particular to a silicon wafer on an insulating substrate with a cavity and an alignment method thereof. Background Art
[0002] With the maturity of bonding technology, silicon on insulating substrate (SOI) wafers are widely used in micro-electromechanical products. SOI wafers with cavities reserved on the substrate are gradually being used in industrial production due to their advantages of improving device performance, simplifying manufacturing processes and expanding application areas. However, after bonding, the cavity on the front side of the substrate is covered, which easily makes it difficult to align the pattern formed on the surface of another wafer covering the substrate surface with the covered cavity.
[0003] At present, alignment marks are often formed on the surface of the substrate, and after bonding is completed, the corresponding position of the other wafer covering the substrate is etched. After the alignment marks are exposed, the wafer is patterned using the alignment marks as a reference, thereby achieving alignment of the two layers of patterns. However, after the steps are etched on the surface of the wafer, the morphology of the wafer surface is affected, which is not conducive to subsequent deposition and etching, and can easily lead to a decrease in product yield. Therefore, this method is not suitable for industrial production. Summary of the invention
[0004] The object of the present invention is to provide a silicon wafer on an insulating substrate with a cavity and a higher yield and an alignment method thereof.
[0005] In order to achieve the above object, the present invention provides the following technical solutions:
[0006] A silicon wafer on an insulating substrate having a cavity, comprising:
[0007] A substrate having a polishing surface and a marking surface opposite to the polishing surface, wherein a cavity is formed on the polishing surface and an alignment mark is formed on the marking surface;
[0008] The bonding wafer comprises a bonding surface and a pattern surface opposite to the bonding surface, wherein the bonding surface is connected to the polishing surface of the substrate.
[0009] Optionally, the substrate is a single-sided polished sheet, and the surface roughness of the marking surface of the substrate is greater than the surface roughness of the polishing surface, a smooth area is formed on the marking surface, the alignment mark is formed in the smooth area, and the surface roughness of the smooth area is less than or equal to 1.2μm.
[0010] Optionally, a corrosion groove sunken into the marking surface is formed on the marking surface, the side of the corrosion groove close to the polishing surface is the smooth area, the depth of the corrosion groove is greater than or equal to 20μm, the alignment mark is a groove embedded in the smooth area, and the depth of the alignment mark is greater than or equal to 1μm.
[0011] Optionally, a reference mark corresponding to the alignment mark is formed on the pattern surface of the bonded wafer.
[0012] Optionally, the bonding wafer includes a stacked single crystal layer and an insulating layer, a side of the single crystal layer away from the insulating layer is the pattern surface, and a side of the insulating layer away from the single crystal layer is the bonding surface.
[0013] Optionally, the alignment mark is provided at multiple locations.
[0014] In a second aspect, the present invention further provides a method for aligning a silicon wafer on an insulating substrate, characterized in that it comprises:
[0015] providing the substrate;
[0016] forming the alignment mark on the mark surface of the substrate, and forming the cavity on the polished surface of the substrate, so that the relative position between the cavity and the alignment mark is determined;
[0017] The bonding wafer is provided, and the bonding surface of the bonding wafer is connected to the polishing surface of the substrate.
[0018] Optionally, forming the alignment mark on the mark surface of the substrate includes:
[0019] Partially polishing a preset position of the marking surface of the substrate to form a smooth area;
[0020] The alignment mark is formed in the smooth area.
[0021] Optionally, locally polishing a preset position of the marking surface of the substrate to form the smooth area comprises:
[0022] forming a mask covering the marking surface of the substrate, and forming a through hole at a portion of the mask corresponding to the preset position of the marking surface;
[0023] The marking surface of the substrate is subjected to etching polishing by means of a polishing liquid to form an etching groove at the preset position, and the side of the etching groove close to the polishing surface is the smooth area.
[0024] Optionally, the alignment method further comprises:
[0025] Taking the alignment mark as a reference, a reference mark is formed on the pattern surface of the bonded wafer connected to the substrate, and taking the reference mark as a reference, a preset pattern is formed on the pattern surface of the bonded wafer;
[0026] or
[0027] Taking the alignment mark as a reference, a preset pattern is formed on the pattern surface of the bonding wafer connected to the substrate.
[0028] According to the first aspect of the present invention, a cavity and an alignment mark are respectively formed on the relative polishing surface and the marking surface of the substrate, so that the alignment mark is still exposed after the cavity is covered by the bonded wafer. Since the relative position between the cavity and the alignment mark is determined, it is convenient to determine the position of the covered cavity through the alignment mark exposed to the outside, thereby improving the accuracy of the product structure and helping to improve the yield of the product. Since the alignment mark is formed on the back of the wafer, it will not affect the subsequent processing of the SOI wafer surface, which helps to improve the product quality. The alignment mark is formed on the back of the wafer and does not occupy the effective area of the front of the wafer, which helps to improve the compactness of the structure, facilitates the product structure design, and has high practicality.
[0029] Furthermore, using a single-sided polished wafer as a substrate has low cost and is applicable to existing machines. Since the surface roughness of the mark surface of the wafer of a single-sided polished wafer is usually around 3 μm, it is difficult to directly form a regular alignment mark on the back of the wafer, and the alignment mark is also difficult to identify after it is formed. Local polishing is performed on the mark surface of the wafer to form a smooth area with a small surface roughness, which facilitates the formation and identification of the alignment mark, and does not affect the substrate's applicability to existing operating machines, such as conveying equipment and suction equipment, and has high practicality.
[0030] According to the second aspect of the present invention, alignment marks and cavities with determined relative positions are formed by double-sided exposure, and after the bonded wafer covers the cavity, the position of the cavity is determined using the alignment marks as a reference, which helps to improve the structural accuracy of the product and improve the yield of the product.
[0031] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 Schematic diagram of the structural change of a silicon wafer on an insulating substrate in Embodiment 1 of the present invention;
[0033] Figure 2 This is a flow chart of a method for aligning a silicon wafer on an insulating substrate shown in Embodiment 1 of the present invention.
[0034] Legend: 1-substrate, 11-polished surface, 111-cavity, 12-marking surface, 121-etching groove, 122-smooth area, 123-alignment mark, 2-bonded wafer, 21-single crystal layer, 211-pattern surface, 2111-reference mark, 22-insulating layer, 221-bonding surface. DETAILED DESCRIPTION
[0035] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0036] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0037] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0038] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
[0039] See also Figure 1 The silicon wafer on insulating substrate with cavity protected by the present invention comprises a stacked substrate 1 and a bonding wafer 2. The substrate 1 has a polishing surface 11 and a marking surface 12 opposite to the polishing surface 11, a cavity 111 is formed on the polishing surface 11, and an alignment mark 123 is formed on the marking surface 12. The bonding wafer 2 has a bonding surface 221 and a graphic surface 211 opposite to the bonding surface 221, and the bonding surface 221 is connected to the polishing surface 11 of the substrate 1.
[0040] A cavity 111 and an alignment mark 123 are formed on the polishing surface 11 and the marking surface 12 relative to the substrate 1, respectively, so that the alignment mark 123 is still exposed after the cavity 111 is covered by the bonding wafer 2. Since the relative position between the cavity 111 and the alignment mark 123 is determined, it is convenient to determine the position of the covered cavity 111 through the alignment mark 123 exposed to the outside, thereby improving the accuracy of the product structure and helping to improve the yield of the product. Since the alignment mark 123 is formed on the back of the wafer, it will not affect the subsequent processing of the SOI wafer surface, which helps to improve the product quality. The alignment mark 123 is formed on the back of the wafer and does not occupy the effective area of the front of the wafer, which helps to improve the compactness of the structure, facilitates the product structure design, and has high practicality.
[0041] In some embodiments, the substrate 1 is a single-sided polished wafer, and the surface roughness of the marking surface 12 of the substrate 1 is greater than the surface roughness of the polishing surface 11, a smooth area 122 is formed on the marking surface 12, and the alignment mark 123 is formed in the smooth area 122, and the surface roughness of the smooth area 122 is less than or equal to 1.2μm, for example, it can be any value among 1.2μm, 1.0μm, 0.9μm, 0.8μm, 0.7μm and 0.6μm. Using a single-sided polished wafer as the substrate 1 is low in cost and suitable for existing machines. Since the surface roughness of the marking surface 12 of the wafer of the single-sided polished wafer is usually around 3μm, it is difficult to directly form a regular alignment mark 123 on the back of the wafer, and it is also difficult to identify the alignment mark 123 after it is formed. Local polishing is performed on the mark surface 12 of the wafer to form a smooth area 122 with a small surface roughness, which is convenient for forming and identifying the alignment mark 123 and does not affect the suitability of the substrate 1 for existing operating machines and auxiliary equipment, such as conveying equipment and suction equipment, etc., and has high practicality.
[0042] In some embodiments, a corrosion groove 121 is formed on the marking surface 12, and the side of the corrosion groove 121 close to the polishing surface 11 is a smooth area 122. The groove with a smooth bottom is formed by partial polishing, so as to form a relatively smooth smooth area 122.
[0043] In some embodiments, the depth of the corrosion groove 121 is greater than or equal to 20 μm, for example, it can be any value among 20 μm, 22 μm, 24 μm, 26 μm, 28 μm and 30 μm, so as to reduce the surface roughness of the smooth area 122 .
[0044] In some embodiments, the alignment mark 123 is a groove embedded in the smooth area 122 , and the depth of the alignment mark 123 is greater than or equal to 1 μm, for example, any value of 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm and 3.5 μm, so as to facilitate identification of the alignment mark 123 .
[0045] In some embodiments, the pattern surface 211 of the bonded wafer 2 is formed with a reference mark 2111 corresponding to the alignment mark 123, which is convenient for use as a reference when patterning the pattern surface 211, thereby improving alignment accuracy and reducing operating costs.
[0046] In some embodiments, the bonding wafer 2 includes a stacked single crystal layer 21 and an insulating layer 22 , the side of the single crystal layer 21 away from the insulating layer 22 is a pattern surface 211 , and the side of the insulating layer 22 away from the single crystal layer 21 is a bonding surface 221 .
[0047] In some embodiments, the alignment marks 123 are provided at multiple locations to facilitate alignment and calibration.
[0048] See also Figure 2 The present invention also applies for a method for aligning a silicon wafer on a protective insulating substrate, which is characterized by comprising:
[0049] S1. Provide a substrate 1.
[0050] S2. An alignment mark 123 is formed on the mark surface 12 of the substrate 1, and a cavity 111 is formed on the polishing surface 11 of the substrate 1, so that the relative position between the cavity 111 and the alignment mark 123 is determined.
[0051] S3 . Provide a bonding wafer 2 , and connect the bonding surface 221 of the bonding wafer 2 to the polishing surface 11 of the substrate 1 .
[0052] After forming the alignment mark 123, the cavity 111 is formed by double-sided alignment exposure, so that the relative position between the alignment mark 123 and the cavity 111 is determined. After the bonded wafer 2 covers the cavity 111, the alignment mark 123 is used as a reference to help determine the position of the cavity 111, thereby improving the structural accuracy of the product and helping to improve the yield of the product. In this embodiment, two alignment marks 123 are formed to facilitate alignment calibration.
[0053] In some embodiments, forming the alignment mark 123 on the mark surface 12 of the substrate 1 in step S2 includes:
[0054] S210 , locally polishing a preset position of the marking surface 12 of the substrate 1 to form a smooth area 122 .
[0055] S220 , forming an alignment mark 123 in the smooth area 122 .
[0056] First, the smooth area 122 with a flat surface is partially polished, and then the alignment mark 123 is formed on the smooth area 122, so that the formation and identification of the alignment mark 123 are facilitated.
[0057] In some embodiments, step S210 includes:
[0058] S211 , forming a mask covering the marking surface 12 of the substrate 1 , and forming a through hole at a portion of the mask corresponding to a preset position of the marking surface 12 .
[0059] S212 , etching and polishing are performed on the marking surface 12 of the substrate 1 using a polishing liquid to form an etching groove 121 at a preset position, and the side of the etching groove 121 close to the polishing surface 11 is a smooth area 122 .
[0060] Forming the smooth area 122 by using a mask and a polishing liquid helps ensure the accuracy of the position and shape of the smooth area 122, and helps to improve the uniformity of the product.
[0061] In some embodiments, the alignment method further comprises:
[0062] S401, using the alignment mark 123 as a reference, forming a reference mark 2111 on the pattern surface 211 of the bonding wafer 2 connected to the substrate 1, and using the reference mark 2111 as a reference, forming a preset pattern on the pattern surface 211 of the bonding wafer 2;
[0063] or
[0064] S402 , taking the alignment mark 123 as a reference, forming a preset pattern on the pattern surface 211 of the bonding wafer 2 connected to the substrate 1 .
[0065] The alignment mark 123 formed on the mark surface 12 of the substrate 1 is registered and copied to the pattern surface 211 of the bonded wafer 2, which is convenient for the subsequent alignment of the photolithography machine, helps to improve the accuracy of the positioning, and further improves the product yield.
[0066] Embodiment 1:
[0067] See also Figure 2 The alignment method of a silicon SOI wafer on an insulating substrate 1 having a cavity 111 shown in a preferred embodiment of the present application includes:
[0068] S1. Provide a substrate 1.
[0069] S2. An alignment mark 123 is formed on the mark surface 12 of the substrate 1, and a cavity 111 is formed on the polishing surface 11 of the substrate 1, so that the relative position between the cavity 111 and the alignment mark 123 is determined.
[0070] S3 . Provide a bonding wafer 2 , and connect the bonding surface 221 of the bonding wafer 2 to the polishing surface 11 of the substrate 1 .
[0071] See also Figure 1 In step S1, the substrate 1 is a single-sided polished silicon wafer, and the polished smooth polished surface 11 and the marking surface 12 opposite to the polished surface 11 are obtained. The marking surface 12 is not polished and has a surface roughness of about 3 μm.
[0072] Step S2 includes:
[0073] S210 , locally polishing a preset position of the marking surface 12 of the substrate 1 to form a smooth area 122 .
[0074] S220 , forming an alignment mark 123 in the smooth area 122 .
[0075] S230 , forming a cavity 111 on the polished surface 11 of the substrate 1 .
[0076] In this embodiment, an alignment mark 123 is etched on the mark surface 12, and a cavity 111 is etched on the polishing surface 11 opposite to the mark surface 12 by double-sided exposure with the alignment mark 123 as a reference. In this embodiment, the etching depth of the alignment mark 123 is 1 μm.
[0077] Step S210 includes:
[0078] S211 , forming a mask covering the marking surface 12 of the substrate 1 , and forming a through hole at a portion of the mask corresponding to a preset position of the marking surface 12 .
[0079] S212 , etching and polishing are performed on the marking surface 12 of the substrate 1 using a polishing liquid to form an etching groove 121 at a preset position, and the side of the etching groove 121 close to the polishing surface 11 is a smooth area 122 .
[0080] The mask shields and protects other areas of the marking surface 12 of the substrate 1, ensuring that the etching groove 121 is formed at the position corresponding to the through hole of the mask. In this embodiment, the depth of the etching groove 121 is 21 μm, and the surface roughness of the obtained smooth area 122 is 1 μm.
[0081] In step S3, the diameter of the bonded wafer 2 is the same as that of the substrate 1, and includes a stacked single crystal layer 21 and an insulating layer 22. The single crystal layer 21 is a silicon wafer, and its side away from the insulating layer 22 is a pattern surface 211. The insulating layer 22 is a silicon dioxide layer formed on the surface of the silicon wafer, and its side away from the single crystal layer 21 is a bonding surface 221. The bonded wafer 2 and the substrate 1 are subjected to the steps of surface cleaning and activation, alignment and bonding at room temperature, and high temperature annealing, so that the bonding surface 221 of the insulating layer 22 is connected to the polished surface 11 of the substrate 1, forming an SOI wafer with a cavity 111. After bonding, the bonded wafer 2 and the substrate 1 are tightly attached. Figure 1 In order to distinguish the bonding surface 221 from the polishing surface 11, a gap is provided between the two.
[0082] In this embodiment, step S4 is further included, and step S4 includes:
[0083] S401 , using the alignment mark 123 as a reference, forming a reference mark 2111 on the pattern surface 211 of the bonded wafer 2 connected to the substrate 1 , and using the reference mark 2111 as a reference, forming a preset pattern on the pattern surface 211 of the bonded wafer 2 .
[0084] The alignment mark 123 is copied and transferred to the pattern surface 211 of the bonding wafer 2 to form a reference mark 2111, which facilitates alignment during subsequent processing on the pattern surface 211 and helps to improve alignment accuracy and reduce operating costs.
[0085] The beneficial effects of the present invention are as follows: by providing a structure of an SOI wafer with a cavity 111 and an alignment method, a method for positioning the cavity 111 of the SOI wafer and aligning the subsequent operations is provided, which is applicable to existing production equipment and does not occupy the effective area of the wafer surface and does not affect the subsequent processing of the wafer. It is easy to operate and has high precision, which helps to improve the product yield and has high practicality.
[0086] Embodiment 2:
[0087] The difference between this embodiment and the first embodiment is that step S4 in this embodiment includes:
[0088] S402 , taking the alignment mark 123 as a reference, forming a preset pattern on the pattern surface 211 of the bonding wafer 2 connected to the substrate 1 .
[0089] Embodiment three:
[0090] The only difference between this embodiment and the first embodiment is that in this embodiment, the substrate 1 is a double-polished wafer, step S210 is not included, and in step S220, an alignment mark 123 is directly formed at a preset position.
[0091] Embodiment 4:
[0092] The only difference between this embodiment and the first embodiment is that in step S4 of this embodiment, only a reference mark 2111 is formed, and no preset pattern is formed.
[0093] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0094] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.
Claims
1. A silicon wafer on an insulating substrate having a cavity, characterized in that: include: A substrate (1) having a polishing surface (11) and a marking surface (12) opposite to the polishing surface (11), wherein a cavity (111) is formed on the polishing surface (11), and an alignment mark (123) is formed on the marking surface (12); A bonding wafer (2) comprises a bonding surface (221) and a patterned surface (211) opposite to the bonding surface (221), wherein the bonding surface (221) is connected to the polishing surface (11) of the substrate (1).
2. The silicon wafer on insulating substrate as claimed in claim 1, characterized in that: The substrate (1) is a single-sided polished sheet, and the surface roughness of the marking surface (12) of the substrate (1) is greater than the surface roughness of the polishing surface (11), a smooth area (122) is formed on the marking surface (12), the alignment mark (123) is formed in the smooth area (122), and the surface roughness of the smooth area (122) is less than or equal to 1.2 μm.
3. The silicon wafer on insulating substrate as claimed in claim 2, characterized in that: The marking surface (12) is formed with an etching groove (121) sunken in the marking surface (12); the side of the etching groove (121) close to the polishing surface (11) is the smooth area (122); the depth of the etching groove (121) is greater than or equal to 20 μm; the alignment mark (123) is a groove embedded in the smooth area (122); and the depth of the alignment mark (123) is greater than or equal to 1 μm.
4. The silicon wafer on insulating substrate as claimed in claim 1, characterized in that: The pattern surface (211) of the bonding wafer (2) is formed with a reference mark (2111) corresponding to the alignment mark (123).
5. The silicon wafer on insulating substrate as claimed in claim 1, characterized in that: The bonding wafer (2) comprises a stacked single crystal layer (21) and an insulating layer (22); the side of the single crystal layer (21) away from the insulating layer (22) is the patterned surface (211); and the side of the insulating layer (22) away from the single crystal layer (21) is the bonding surface (221).
6. The silicon wafer on insulating substrate according to any one of claims 1 to 5, characterized in that: The alignment mark (123) is arranged at multiple locations.
7. A method for aligning a silicon wafer on an insulating substrate as claimed in any one of claims 1 to 6, characterized in that: include: Providing the substrate (1); forming the alignment mark (123) on the mark surface (12) of the substrate (1), and forming the cavity (111) on the polishing surface (11) of the substrate (1), so that the relative position between the cavity (111) and the alignment mark (123) is determined; The bonding wafer (2) is provided, and the bonding surface (221) of the bonding wafer (2) is connected to the polishing surface (11) of the substrate (1).
8. The alignment method according to claim 7, characterized in that: The step of forming the alignment mark (123) on the mark surface (12) of the substrate (1) comprises: Locally polishing a preset position of the marking surface (12) of the substrate (1) to form a smooth area (122); The alignment mark (123) is formed in the smooth area (122).
9. The alignment method according to claim 8, characterized in that: Partially polishing a preset position of the marking surface (12) of the substrate (1) to form the smooth area (122) comprises: A mask is formed to cover the marking surface (12) of the substrate (1), and a through hole is formed on a portion of the mask corresponding to the preset position of the marking surface (12); The marking surface (12) of the substrate (1) is etched and polished by means of a polishing liquid to form an etched groove (121) at the preset position, and the side of the etched groove (121) close to the polished surface (11) is the smooth area (122).
10. The alignment method according to claim 7, characterized in that: Also includes: Taking the alignment mark (123) as a reference, a reference mark (2111) is formed on the pattern surface (211) of the bonding wafer (2) connected to the substrate (1), and taking the reference mark (2111) as a reference, a preset pattern is formed on the pattern surface (211) of the bonding wafer (2); or Taking the alignment mark (123) as a reference, a preset pattern is formed on the pattern surface (211) of the bonding wafer (2) connected to the substrate (1).